TWI697002B - Level shift circuit and display panel - Google Patents

Level shift circuit and display panel Download PDF

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TWI697002B
TWI697002B TW108110907A TW108110907A TWI697002B TW I697002 B TWI697002 B TW I697002B TW 108110907 A TW108110907 A TW 108110907A TW 108110907 A TW108110907 A TW 108110907A TW I697002 B TWI697002 B TW I697002B
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voltage
coupled
level shift
shift circuit
circuit
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TW202036577A (en
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李旭騏
賴韋霖
陳怡然
趙伯頴
莊錦棠
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友達光電股份有限公司
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Priority to CN201910993696.5A priority patent/CN110706635B/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A level shift circuit is provided. The level shifting circuit receives a low voltage input signal to provide a high voltage output signal. The bias generation device includes a plurality of voltage-dividing transistors and a plurality of capacitors. The voltage-dividing transistors are coupled in series between a system high voltage and a system low voltage, and there is a voltage-dividing node between the two adjacent voltage-dividing transistors. The voltage-dividing nodes provides a plurality of internal biases, wherein the voltage-dividing nodes are couple to the capacitors. The input stage circuit is coupled to the system low voltage for receiving the low voltage input signal. The cross-coupled stage circuit is coupled to the system high voltage. A plurality of buck units are coupled in series between the input stage circuit and the cross-coupled stage circuit and coupled to the voltage-dividing nodes to receive the internal bias voltages. The first output shifter is coupled to the cross-coupled stage circuit and one of the voltage-dividing nodes to output a high voltage output signal according to the system high voltage and a first internal bias among the internal bias voltages. A display panel including the level shifting circuit is also provided.

Description

位準移位電路與顯示面板Level shift circuit and display panel

本發明是有關於一種電壓位準移位技術，且特別是有關於一種位準移位電路與顯示面板。The invention relates to a voltage level shift technology, and in particular to a level shift circuit and a display panel.

位準移位電路是現有電子裝置中一種常見的電路。位準移位電路會將輸入的低電壓信號轉換成高電壓信號輸出。位準移位電路可以高壓製程MOS電晶體或是低壓製程(Low-Voltage CMOS Process)MOS電晶體實現。高壓製程MOS電晶體可承受高電壓，然而晶片面積加大與漏電流提高使得系統成本大幅提升。位準移位電路若以低壓製程MOS電晶體實現，與數位電路可整合於同一系統，晶片成本也可降低。位準移位電路的輸入信號會在高低電壓之間切換，而這種電壓遽變容易導致低耐壓但面積小的電晶體效能降低或損壞，連帶造成輸出的高電壓信號不夠穩定。另外，位準移位電路需要額外的偏壓。一般的技術是通過導電墊片（pad）來外接偏壓，然而這些導電墊片跟外接電流源可能會讓成本上升以及功耗增加。The level shift circuit is a common circuit in existing electronic devices. The level shift circuit converts the input low voltage signal into a high voltage signal output. The level shift circuit can be implemented by a high-voltage process MOS transistor or a low-voltage process (Low-Voltage CMOS Process) MOS transistor. High-voltage manufacturing MOS transistors can withstand high voltages. However, the increase in chip area and the increase in leakage current have greatly increased the system cost. If the level shift circuit is implemented by a low-voltage MOS transistor, it can be integrated with the digital circuit in the same system, and the chip cost can also be reduced. The input signal of the level shift circuit will switch between high and low voltage, and this voltage change is easy to cause the performance of the transistor with low voltage but small area to be reduced or damaged, and the resulting high voltage signal is not stable enough. In addition, the level shift circuit requires additional bias. The general technique is to use a conductive pad to externally bias. However, these conductive pads and an external current source may increase costs and increase power consumption.

如果位準移位電路是要應用在某些電子裝置時，可能還會要求位準移位電路的面積要微小化並且具有低漏電流。例如運用在微發光二極體（micro-LED）顯示面板上。因此如何提出一種具有電路面積微小化與低漏電流的位準移位電路，並確保低壓製程MOS電晶體穩定運作，成為一個重要的課題。If the level shift circuit is to be applied to some electronic devices, it may also require the area of the level shift circuit to be miniaturized and have low leakage current. For example, it is used in micro-LED display panels. Therefore, how to propose a level shift circuit with miniaturized circuit area and low leakage current, and to ensure the stable operation of MOS transistors in a low-voltage manufacturing process, has become an important issue.

本發明提供一種位準移位電路與顯示面板，位準移位電路可以應用於顯示面板，具有電路面積微小化、低漏電流、全幅輸出、信號低雜訊以及運作穩定的優點。The invention provides a level shift circuit and a display panel. The level shift circuit can be applied to a display panel, and has the advantages of miniaturized circuit area, low leakage current, full-scale output, low signal noise and stable operation.

本發明的實施例提供一種位準移位電路。位準移位電路接收低電壓輸入信號以提供高電壓輸出信號。位準移位電路包括偏壓產生裝置、輸入級電路、交叉耦合級電路、多個降壓單元與第一輸出移位器。偏壓產生裝置包括多個分壓電晶體與多個電容，這些分壓電晶體以串聯的形式耦接於系統高電壓與系統低電壓之間，且相鄰的這些分壓電晶體之間具有分壓節點以提供多個內部偏壓，其中這些分壓節點耦接這些電容。輸入級電路耦接系統低電壓，用以接收低電壓輸入信號。交叉耦合級電路耦接系統高電壓。這些降壓單元以串聯的形式耦接於輸入級電路與交叉耦合級電路之間，且分別耦接這些分壓節點以接收這些內部偏壓。第一輸出移位器耦接交叉耦合級電路與這些分壓節點的其中之一以根據系統高電壓與這些內部偏壓中的第一內部偏壓輸出高電壓輸出信號。Embodiments of the present invention provide a level shift circuit. The level shift circuit receives a low voltage input signal to provide a high voltage output signal. The level shift circuit includes a bias voltage generating device, an input stage circuit, a cross-coupling stage circuit, a plurality of step-down units and a first output shifter. The bias voltage generating device includes a plurality of partial piezoelectric crystals and a plurality of capacitors. These partial piezoelectric crystals are coupled in series between a high system voltage and a low system voltage, and there are The voltage-dividing node provides multiple internal bias voltages, wherein the voltage-dividing nodes are coupled to the capacitors. The input stage circuit is coupled to the low voltage of the system for receiving low voltage input signals. The cross-coupling stage circuit is coupled to the system high voltage. The buck units are coupled in series between the input stage circuit and the cross-coupling stage circuit, and are respectively coupled to the voltage dividing nodes to receive the internal bias voltages. The first output shifter is coupled to the cross-coupling stage circuit and one of the voltage dividing nodes to output a high voltage output signal according to the system high voltage and the first internal bias voltage among the internal bias voltages.

在本發明的一實施例中，上述的位準移位電路還包括第二輸出移位器。第二輸出移位器耦接輸入級電路與這些分壓節點的其中另一以根據系統低電壓與這些內部偏壓中的第二內部偏壓輸出低電壓輸出信號。In an embodiment of the invention, the above-mentioned level shift circuit further includes a second output shifter. The second output shifter is coupled to the input stage circuit and the other of the voltage-dividing nodes to output a low-voltage output signal according to the system low voltage and the second internal bias of the internal bias voltages.

在本發明的一實施例中，在上述的位準移位電路中，每一個分壓節點所耦接的電容的耐壓值大於或等於對應的分壓電晶體的耐壓值。In an embodiment of the present invention, in the above-mentioned level shift circuit, the withstand voltage value of the capacitor coupled to each voltage division node is greater than or equal to the corresponding withstand voltage value of the piezoelectric divider crystal.

在本發明的一實施例中，在上述的位準移位電路中，這些電容的電容值落在0.1pF至1pF的範圍內。In an embodiment of the invention, in the above-mentioned level shift circuit, the capacitance of these capacitors falls within the range of 0.1 pF to 1 pF.

在本發明的一實施例中，在上述的位準移位電路中，每一個電容與對應的分壓電晶體並聯。In an embodiment of the invention, in the above-mentioned level shift circuit, each capacitor is connected in parallel with the corresponding piezoelectric divider crystal.

在本發明的一實施例中，在上述的位準移位電路中，這些電容一端耦接對應的分壓節點且另一端接地。In an embodiment of the invention, in the above-mentioned level shift circuit, one end of these capacitors is coupled to the corresponding voltage dividing node and the other end is grounded.

在本發明的一實施例中，在上述的位準移位電路中，每一個降壓單元為互補式電晶體對，包括：第一PMOS電晶體與第一NMOS電晶體以及第二PMOS電晶體與第二NMOS電晶體。第一PMOS電晶體的汲極耦接至第一NMOS電晶體的汲極。第二PMOS電晶體與第二NMOS電晶體與第一PMOS電晶體與第一NMOS電晶體呈對稱配置，第二PMOS電晶體的汲極耦接至第二NMOS電晶體的汲極，且第一PMOS電晶體、第一NMOS電晶體、第二PMOS電晶體與第二NMOS電晶體的閘極都耦接至相同的分壓節點。In an embodiment of the present invention, in the above level shift circuit, each step-down unit is a complementary transistor pair, including: a first PMOS transistor, a first NMOS transistor, and a second PMOS transistor With the second NMOS transistor. The drain of the first PMOS transistor is coupled to the drain of the first NMOS transistor. The second PMOS transistor and the second NMOS transistor and the first PMOS transistor and the first NMOS transistor are arranged symmetrically, the drain of the second PMOS transistor is coupled to the drain of the second NMOS transistor, and the first The gates of the PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor are all coupled to the same voltage dividing node.

在本發明的一實施例中，在上述的位準移位電路中，位準移位電路中的電晶體都是由低壓製程產生的MOS電晶體，其中所述之低壓製程可為0.18mm（微米） CMOS製程。In an embodiment of the invention, in the above-mentioned level shift circuit, the transistors in the level shift circuit are all MOS transistors produced by a low-voltage process, wherein the low-voltage process may be 0.18 mm ( Micron) CMOS process.

在本發明的一實施例中，在上述的位準移位電路中，交叉耦合級電路包括二個PMOS電晶體，二個PMOS電晶體的源極耦接系統高電壓，二個PMOS電晶體的閘極耦接彼此的汲極，以及二個PMOS電晶體的汲極耦接這些降壓單元中的第一個降壓單元。In an embodiment of the invention, in the above-mentioned level shift circuit, the cross-coupling stage circuit includes two PMOS transistors, the sources of the two PMOS transistors are coupled to the system high voltage, and the two PMOS transistors The gates are coupled to the drains of each other, and the drains of the two PMOS transistors are coupled to the first of the buck units.

在本發明的一實施例中，在上述的位準移位電路中，第一輸出移位器接收交叉耦合級電路中的二個PMOS電晶體的汲極的電壓，且耦接於系統高電壓和具有第一內部偏壓的分壓節點之間。In an embodiment of the invention, in the above-mentioned level shift circuit, the first output shifter receives the voltages of the drains of the two PMOS transistors in the cross-coupling stage circuit, and is coupled to the system high voltage Between the voltage divider node with the first internal bias.

在本發明的一實施例中，在上述的位準移位電路中，輸入級電路包括二個NMOS電晶體，二個NMOS電晶體的汲極耦接這些降壓單元中的最後一個降壓單元，二個NMOS電晶體的源極耦接系統低電壓，以及二個NMOS電晶體其中之一的閘極接收低電壓輸入信號，二個NMOS電晶體其中另一的閘極接收低電壓輸入信號的反相信號。In an embodiment of the present invention, in the above-mentioned level shift circuit, the input stage circuit includes two NMOS transistors, and the drains of the two NMOS transistors are coupled to the last of the buck units , The source of the two NMOS transistors is coupled to the system low voltage, and the gate of one of the two NMOS transistors receives the low voltage input signal, and the gate of the other NMOS transistor receives the low voltage input signal Inverted signal.

本發明的實施例提供一種顯示面板，包括上述的位準移位電路。閘極驅動器接收由位準移位電路提供的高電壓輸出信號且提供多個閘極信號。多個畫素耦接多條掃描線以接收對應的閘極信號。An embodiment of the present invention provides a display panel including the above-mentioned level shift circuit. The gate driver receives the high voltage output signal provided by the level shift circuit and provides a plurality of gate signals. Multiple pixels are coupled to multiple scan lines to receive corresponding gate signals.

基於上述，本發明的實施例的位準移位電路可以提供在多個分壓節點提供不同的內部偏壓，通過設置電容降低內部偏壓的電壓變化，可以提供一種穩定輸出全擺幅的高電壓輸出信號。位準移位電路還通過多個降壓單元保護位準移位電路中的電晶體，避免電晶體受到過大的跨壓造成操作異常。上述的位準移位電路可以應用在顯示面板的電路設計中。Based on the above, the level shift circuit of the embodiment of the present invention can provide different internal bias voltages at multiple voltage-dividing nodes. By setting capacitors to reduce the voltage variation of the internal bias voltages, it can provide a stable output full swing high Voltage output signal. The level shifting circuit also protects the transistor in the level shifting circuit through a plurality of voltage-reducing units to prevent the transistor from being operated abnormally due to excessive voltage across. The above-mentioned level shift circuit can be applied to the circuit design of the display panel.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

圖1是依照本發明的一實施例的一種顯示面板的示意圖。請參照圖1，在本實施例中，顯示面板10包括位準移位電路100、閘極驅動器200、多條掃描線SL以及多個畫素PX。位準移位電路100接收低電壓輸入信號VIN以提供輸出信號VOUT給閘極驅動器200。輸出信號VOUT可以包括多個具有不同位準範圍的電壓信號，例如高電壓輸出信號與低電壓輸出信號，本發明對於輸出信號VOUT並不限制。閘極驅動器200接收輸出信號VOUT並提供多個閘極信號GS。這些畫素PX成陣列排列且分別耦接掃描線SL與資料線（圖中未顯示）。這些畫素PX會通過掃描線SL接收閘極信號GS以及通過資料線接收畫素電壓。FIG. 1 is a schematic diagram of a display panel according to an embodiment of the invention. Referring to FIG. 1, in this embodiment, the display panel 10 includes a level shift circuit 100, a gate driver 200, a plurality of scan lines SL, and a plurality of pixels PX. The level shift circuit 100 receives the low voltage input signal VIN to provide the output signal VOUT to the gate driver 200. The output signal VOUT may include a plurality of voltage signals having different level ranges, such as a high-voltage output signal and a low-voltage output signal. The present invention is not limited to the output signal VOUT. The gate driver 200 receives the output signal VOUT and provides a plurality of gate signals GS. These pixels PX are arranged in an array and are respectively coupled to the scanning line SL and the data line (not shown in the figure). These pixels PX receive the gate signal GS through the scan line SL and the pixel voltage through the data line.

在本實施例中，顯示面板10可以是micro-LED顯示面板或是液晶顯示面板，本發明並不限制。In this embodiment, the display panel 10 may be a micro-LED display panel or a liquid crystal display panel, and the present invention is not limited.

圖2是依照本發明的一實施例的一種位準移位電路的電路示意圖。請搭配圖1參考圖2，在本實施例中，位準移位電路100包括偏壓產生裝置110、輸入級電路120、交叉耦合級電路130、多個降壓單元142～148、第一輸出移位器150與第二輸出移位器160。偏壓產生裝置110包括多個分壓電晶體112與多個電容114。這些分壓電晶體112以串聯的形式耦接於系統高電壓VDD與系統低電壓VSS之間，且相鄰的分壓電晶體112之間具有分壓節點N以提供多個內部偏壓V1～V4，其中這些分壓節點N分別耦接電容114。2 is a circuit schematic diagram of a level shift circuit according to an embodiment of the invention. Please refer to FIG. 2 in conjunction with FIG. 1. In this embodiment, the level shift circuit 100 includes a bias voltage generating device 110, an input stage circuit 120, a cross-coupling stage circuit 130, a plurality of step-down units 142 to 148, and a first output The shifter 150 and the second output shifter 160. The bias voltage generating device 110 includes a plurality of partial piezoelectric crystals 112 and a plurality of capacitors 114. These partial piezoelectric crystals 112 are coupled in series between the system high voltage VDD and the system low voltage VSS, and there are voltage dividing nodes N between adjacent partial piezoelectric crystals 112 to provide a plurality of internal bias voltages V1~ V4, wherein the voltage dividing nodes N are respectively coupled to the capacitor 114.

在圖2中，這些串聯的分壓電晶體112可以將系統高電壓VDD分壓。由上而下，4個分壓節點N上的內部偏壓分別是內部偏壓V1（以下又稱為第一內部偏壓）、內部偏壓V3、內部偏壓V4與內部偏壓V2（以下又稱為第二內部偏壓）。圖2的電路架構僅作為示例，本發明不限制分壓電晶體、電容或分壓節點的數目。In FIG. 2, these series-connected piezoelectric crystals 112 can divide the system high voltage VDD. From top to bottom, the internal bias voltages on the four voltage-dividing nodes N are internal bias voltage V1 (hereinafter also referred to as first internal bias voltage), internal bias voltage V3, internal bias voltage V4, and internal bias voltage V2 (hereinafter Also known as the second internal bias). The circuit architecture of FIG. 2 is only an example, and the present invention does not limit the number of piezoelectric divider, capacitor, or voltage divider nodes.

輸入級電路120耦接系統低電壓VSS，用以接收低電壓輸入信號VIN，交叉耦合級電路130耦接系統高電壓VDD。這些降壓單元142～148以串聯的形式耦接於輸入級電路120與交叉耦合級電路130之間，並且分別耦接分壓節點N以接收內部偏壓V1～V4。第一輸出移位器150耦接交叉耦合級電路130與其中一個分壓節點N。在圖2的實施例中，第一輸出移位器150耦接具有第一內部偏壓V1的分壓節點N以根據系統高電壓VDD與第一內部偏壓V1輸出高電壓輸出信號VOH。第二輸出移位器160耦接輸入級電路120與具有第二內部偏壓V2的分壓節點N以根據系統低電壓VSS與第二內部偏壓V2輸出低電壓輸出信號VOL。在此，系統低電壓VSS小於第二內部偏壓V2，第二內部偏壓V2小於第一內部偏壓V1，以及第一內部偏壓V1小於系統高電壓VDD。The input stage circuit 120 is coupled to the system low voltage VSS to receive the low voltage input signal VIN, and the cross-coupling stage circuit 130 is coupled to the system high voltage VDD. The voltage reducing units 142 to 148 are coupled in series between the input stage circuit 120 and the cross-coupling stage circuit 130, and are respectively coupled to the voltage dividing node N to receive the internal bias voltages V1 to V4. The first output shifter 150 is coupled to the cross-coupling stage circuit 130 and one of the voltage dividing nodes N. In the embodiment of FIG. 2, the first output shifter 150 is coupled to a voltage dividing node N having a first internal bias voltage V1 to output a high voltage output signal VOH according to the system high voltage VDD and the first internal bias voltage V1. The second output shifter 160 is coupled to the input stage circuit 120 and the voltage dividing node N having the second internal bias voltage V2 to output the low voltage output signal VOL according to the system low voltage VSS and the second internal bias voltage V2. Here, the system low voltage VSS is less than the second internal bias voltage V2, the second internal bias voltage V2 is smaller than the first internal bias voltage V1, and the first internal bias voltage V1 is smaller than the system high voltage VDD.

具體而言，接收低電壓輸入信號VIN後，位準移位電路100可以對應地輸出電壓位準相較於低電壓輸入信號VIN被平移過的高電壓輸出信號VOH。高電壓輸出信號VOH的電壓位準是低電壓輸入信號VIN往系統高電壓VDD平移後的結果。Specifically, after receiving the low voltage input signal VIN, the level shift circuit 100 can correspondingly output the high voltage output signal VOH through which the voltage level is shifted compared to the low voltage input signal VIN. The voltage level of the high-voltage output signal VOH is the result of the low-voltage input signal VIN shifting toward the system high voltage VDD.

相較於現有的技術，位準移位電路100只需要外接系統高電壓VDD與系統低電壓VSS就可以提供多個內部偏壓V1～V4給第一輸出移位器150或第二輸出移位器160，不需要外接其他偏壓電源，可以免去電路上外接偏壓所需要的導電墊片（pad），大幅節省電路面積以及提升電路效能。本發明的位準移位電路100還包括耦接分壓節點N的多個電容114。信號在高-低電壓位準切換的剎那，因為電壓的劇烈變化容易造成電壓信號或電流信號不穩定，產生所謂的尖波（spike）。耦接分壓節點N的電容114具有穩壓的功效，可以消除這種暫態波動，讓內部偏壓V1～V4穩定以提升位準移位電路100的準確度與可靠度。Compared with the prior art, the level shift circuit 100 only needs to be connected to the system high voltage VDD and the system low voltage VSS to provide a plurality of internal bias voltages V1 to V4 to shift the first output shifter 150 or the second output The device 160 does not need to be connected to other bias power supply, and can eliminate the conductive pads needed for the external bias voltage on the circuit, which greatly saves the circuit area and improves the circuit performance. The level shift circuit 100 of the present invention further includes a plurality of capacitors 114 coupled to the voltage dividing node N. The moment the signal switches between high and low voltage levels, because of the drastic changes in voltage, it is easy to cause the voltage signal or current signal to become unstable, resulting in a so-called spike. The capacitor 114 coupled to the voltage dividing node N has a voltage stabilizing effect, which can eliminate such transient fluctuations and stabilize the internal bias voltages V1 ˜ V4 to improve the accuracy and reliability of the level shift circuit 100.

下面更進一步說明本實施例的電路架構。The circuit architecture of this embodiment is further described below.

這些分壓電晶體112以PMOS電晶體為例，且每一個分壓電晶體112的閘極與汲極互接，且其汲極耦接至對應的分壓節點N。在本實施例中，每一個電容114與對應的分壓電晶體112並聯並耦接相同的分壓節點N。每一個分壓節點N所耦接的電容114的耐壓值會大於或等於對應的分壓電晶體112的耐壓值。舉例來說，分壓電晶體112能容忍的跨壓範圍是0V（伏特）～3.3V，電容114的電容值可以選擇落在0.1pF（皮法拉）至1pF的範圍內。分壓電晶體112可以0.18mm（微米）CMOS製程實現，本發明並不限制。These partial piezoelectric crystals 112 are exemplified by PMOS transistors, and the gate electrode and the drain electrode of each partial piezoelectric crystal 112 are interconnected, and the drain electrode thereof is coupled to the corresponding voltage dividing node N. In the present embodiment, each capacitor 114 is connected in parallel with the corresponding voltage-dividing crystal 112 and is coupled to the same voltage-dividing node N. The withstand voltage value of the capacitor 114 coupled to each voltage dividing node N will be greater than or equal to the corresponding withstand voltage value of the divided piezoelectric crystal 112. For example, the cross-voltage range that the partial piezoelectric crystal 112 can tolerate is 0V (volt) to 3.3V, and the capacitance value of the capacitor 114 can be selected to fall within the range of 0.1 pF (picofarad) to 1 pF. The piezoelectric divider 112 can be implemented in a 0.18 mm (micron) CMOS process, and the present invention is not limited.

輸入級電路120包括二個NMOS電晶體122與124，NMOS電晶體122與124的汲極耦接降壓單元148，即最後一個降壓單元，源極耦接系統低電壓VSS。NMOS電晶體122與124的其中之一的閘極（在此是NMOS電晶體124）會接收低電壓輸入信號VIN，其中另一的閘極（在此是NMOS電晶體122）接收低電壓輸入信號VIN的反相信號。在本實施例中，輸入級電路120還可以包括反相器INV以提供低電壓輸入信號VIN的反相信號。The input stage circuit 120 includes two NMOS transistors 122 and 124. The drains of the NMOS transistors 122 and 124 are coupled to the buck unit 148, that is, the last buck unit, and the source is coupled to the system low voltage VSS. One of the gates of the NMOS transistors 122 and 124 (in this case, the NMOS transistor 124) receives the low voltage input signal VIN, and the other gate (in this case, the NMOS transistor 122) receives the low voltage input signal. Inverted signal of VIN. In this embodiment, the input stage circuit 120 may further include an inverter INV to provide an inverted signal of the low voltage input signal VIN.

第二輸出移位器160耦接NMOS電晶體122與124的汲極（或者降壓單元148的輸出端）以切換低電壓輸出信號VOL的電壓位準。第二輸出移位器160耦接於具有第二內部偏壓V2的分壓節點N與系統低電壓VSS之間，其閘極接收NMOS電晶體122與124的汲極上的電壓（也是降壓單元148的輸出電壓）並輸出低電壓輸出信號VOL。低電壓輸出信號VOL的電壓位準會隨著低電壓輸入信號VIN的上升與下降而在系統低電壓VSS與第二內部偏壓V2之間切換。The second output shifter 160 is coupled to the drains of the NMOS transistors 122 and 124 (or the output of the buck unit 148) to switch the voltage level of the low voltage output signal VOL. The second output shifter 160 is coupled between the voltage dividing node N having the second internal bias voltage V2 and the system low voltage VSS, and its gate receives the voltage on the drains of the NMOS transistors 122 and 124 (also a buck unit) 148 output voltage) and output low voltage output signal VOL. The voltage level of the low voltage output signal VOL will switch between the system low voltage VSS and the second internal bias voltage V2 as the low voltage input signal VIN rises and falls.

交叉耦合級電路130包括二個PMOS電晶體132與134。PMOS電晶體132與134的源極都耦接系統高電壓 VDD，且閘極耦接彼此的汲極。PMOS電晶體132與134的汲極耦接降壓單元142（即第一個降壓單元）以及第一輸出移位器150。第一輸出移位器150耦接於系統高電壓VDD與具有第一內部偏壓V1的分壓節點N之間並且接收PMOS電晶體132與134的汲極端上的電壓（也是降壓單元142的輸入電壓）以切換高電壓輸出信號VOH的電壓位準。高電壓輸出信號VOH的電壓位準會隨著低電壓輸入信號VIN的上升與下降而在系統高電壓VDD與第一內部偏壓V1之間切換，以實現全幅輸出。 The cross-coupling stage circuit 130 includes two PMOS transistors 132 and 134. The sources of PMOS transistors 132 and 134 are coupled to the system high voltage VDD, and the gates are coupled to the drains of each other. The drains of the PMOS transistors 132 and 134 are coupled to the buck unit 142 (ie, the first buck unit) and the first output shifter 150. The first output shifter 150 is coupled between the system high voltage VDD and the voltage dividing node N having the first internal bias voltage V1 and receives the voltage on the drain terminals of the PMOS transistors 132 and 134 (also the voltage drop unit 142 Input voltage) to switch the voltage level of the high-voltage output signal VOH. The voltage level of the high-voltage output signal VOH will switch between the system high voltage VDD and the first internal bias voltage V1 as the low-voltage input signal VIN rises and falls to achieve full-scale output.

圖2中的降壓單元142～148以互補式金屬氧化物半導體電晶體對（Complementary Metal-Oxide-Semiconductor pair, CMOS pair)的方式實施，且降壓單元142～148的結構彼此相同。每一個降壓單元包括第一PMOS電晶體TP1、第一NMOS電晶體TN1以及成對稱配置的第二PMOS電晶體TP2與第二NMOS電晶體TN2。第一PMOS電晶體TP1與第一NMOS電晶體TN1串接，第二PMOS電晶體TP2與第二NMOS電晶體TN2串接，也就是說第一PMOS電晶體TP1的汲極耦接至第一NMOS電晶體TN1的汲極，第二PMOS電晶體TP2的汲極耦接至第二NMOS電晶體TN2的汲極。第一PMOS電晶體TP1、第一NMOS電晶體TN1、第二PMOS電晶體TP2與第二NMOS電晶體TN2的閘極都耦接到相同的分壓節點N。The buck units 142 to 148 in FIG. 2 are implemented in the form of complementary metal-oxide-semiconductor pairs (CMOS pairs), and the structures of the buck units 142 to 148 are the same as each other. Each step-down unit includes a first PMOS transistor TP1, a first NMOS transistor TN1, and a symmetrically configured second PMOS transistor TP2 and second NMOS transistor TN2. The first PMOS transistor TP1 is connected in series with the first NMOS transistor TN1, and the second PMOS transistor TP2 is connected in series with the second NMOS transistor TN2, that is to say the drain of the first PMOS transistor TP1 is coupled to the first NMOS The drain of the transistor TN1 and the drain of the second PMOS transistor TP2 are coupled to the drain of the second NMOS transistor TN2. The gates of the first PMOS transistor TP1, the first NMOS transistor TN1, the second PMOS transistor TP2 and the second NMOS transistor TN2 are coupled to the same voltage dividing node N.

詳細來說，降壓單元142的電晶體的閘極都耦接至第一個分壓節點N（圖2中由上往下的排列順序）以接收第一內部偏壓V1；降壓單元144的電晶體的閘極都耦接至第二個分壓節點N以接收第三內部偏壓V3；降壓單元146的電晶體的閘極都耦接至第三個分壓節點N以接收第四內部偏壓V4；降壓單元148的電晶體的閘極都耦接至第四個分壓節點N以接收第二內部偏壓V2。In detail, the gates of the transistors of the step-down unit 142 are coupled to the first voltage-dividing node N (the arrangement order from top to bottom in FIG. 2) to receive the first internal bias voltage V1; the step-down unit 144 The gates of the transistors are coupled to the second voltage dividing node N to receive the third internal bias voltage V3; the gates of the transistors of the voltage step-down unit 146 are coupled to the third voltage dividing node N to receive the third Four internal bias voltages V4; the gates of the transistors of the voltage step-down unit 148 are coupled to the fourth voltage dividing node N to receive the second internal bias voltage V2.

交叉耦合級電路130中的PMOS電晶體132耦接降壓單元142中的第一PMOS電晶體TP1，PMOS電晶體134耦接第二PMOS電晶體TP2。輸入級電路120的NMOS電晶體122會耦接降壓單元148中的第一NMOS電晶體TN1，NMOS電晶體124耦接降壓單元148中的第二NMOS電晶體TN2。The PMOS transistor 132 in the cross-coupling stage circuit 130 is coupled to the first PMOS transistor TP1 in the buck unit 142, and the PMOS transistor 134 is coupled to the second PMOS transistor TP2. The NMOS transistor 122 of the input stage circuit 120 is coupled to the first NMOS transistor TN1 in the buck unit 148, and the NMOS transistor 124 is coupled to the second NMOS transistor TN2 in the buck unit 148.

特別說明的是，在本實施例中，圖2的實施例的MOS電晶體可以都是低壓製程產生的MOS電晶體。如此一來，電路面積可以微小化並且易於與數位電路整合。這些疊接的降壓單元142～148可以將系統高電壓VDD與系統低電壓VSS分隔成若干電壓範圍，以避免位準移位電路100中的電晶體承受的跨壓過大而產生問題。In particular, in this embodiment, the MOS transistors in the embodiment of FIG. 2 may all be MOS transistors produced in a low-voltage manufacturing process. In this way, the circuit area can be miniaturized and easily integrated with digital circuits. These stacked buck units 142-148 can separate the system high voltage VDD and the system low voltage VSS into several voltage ranges to avoid problems caused by excessive voltage across the transistors in the level shift circuit 100.

圖3是依照本發明的一實施例的一種位準移位電路的輸出信號的波形圖，圖4是依照本發明的一實施例的第一內部偏壓的波形圖，圖5是依照本發明的一實施例的第二內部偏壓的波形圖。請同時參照圖2至圖5，降壓單元142～148中左邊的第一PMOS電晶體TP1和第一NMOS電晶體TN1的導通狀況會與右邊的第二PMOS電晶體TP2和第二NMOS電晶體TN2相反，因此第一輸出移位器150與第二輸出移位器160的兩邊閘極會接收不同的電壓位準以選擇輸出高位準信號還是低位準信號。舉例來說，系統高電壓VDD為15V，系統低電壓VSS為0V，偏壓產生裝置110所輸出的第一內部偏壓V1是12V，第三偏壓V3是9V，第四偏壓V4是6V，第二內部偏壓V2是3V。低電壓輸入信號VIN是在0V～3V的脈衝信號。3 is a waveform diagram of an output signal of a level shift circuit according to an embodiment of the invention, FIG. 4 is a waveform diagram of a first internal bias voltage according to an embodiment of the invention, and FIG. 5 is a waveform diagram according to the invention The waveform diagram of the second internal bias voltage according to an embodiment. Please refer to FIG. 2 to FIG. 5 at the same time, the conduction conditions of the left first PMOS transistor TP1 and the first NMOS transistor TN1 in the step-down units 142-148 will be the same as the right second PMOS transistor TP2 and the second NMOS transistor TN2 is opposite, so the gates on both sides of the first output shifter 150 and the second output shifter 160 receive different voltage levels to select whether to output a high level signal or a low level signal. For example, the system high voltage VDD is 15V, the system low voltage VSS is 0V, the first internal bias voltage V1 output by the bias voltage generating device 110 is 12V, the third bias voltage V3 is 9V, and the fourth bias voltage V4 is 6V , The second internal bias voltage V2 is 3V. The low voltage input signal VIN is a pulse signal between 0V and 3V.

當低電壓輸入信號VIN是0V時，第一輸出移位器150從PMOS電晶體132的汲極端接收12.1V，從PMOS電晶體134的汲極端接收15V，因此高電壓輸出信號VOH的電壓位準被上拉至系統高電壓VDD。另一方面，第二輸出移位器160從NMOS電晶體122的汲極端接收0V，從NMOS電晶體124的汲極端接收2.9V。低電壓輸出信號VOL的電壓位準被上拉至第二內部偏壓V2（3V）。When the low voltage input signal VIN is 0V, the first output shifter 150 receives 12.1V from the drain terminal of the PMOS transistor 132 and 15V from the drain terminal of the PMOS transistor 134, so the voltage level of the high voltage output signal VOH Pulled up to the system high voltage VDD. On the other hand, the second output shifter 160 receives 0V from the drain terminal of the NMOS transistor 122 and 2.9V from the drain terminal of the NMOS transistor 124. The voltage level of the low voltage output signal VOL is pulled up to the second internal bias voltage V2 (3V).

當低電壓輸入信號VIN是3V時，第一輸出移位器150從PMOS電晶體132的汲極端接收15V，從PMOS電晶體134的汲極端接收12.1V，因此高電壓輸出信號VOH的電壓位準被下拉至第一內部偏壓V1（12V）。另一方面，第二輸出移位器160從NMOS電晶體122的汲極端接收2.9V，從NMOS電晶體124的汲極端接收0V，低電壓輸出信號VOL的電壓位準被下拉至系統低電壓VSS。When the low voltage input signal VIN is 3V, the first output shifter 150 receives 15V from the drain terminal of the PMOS transistor 132 and 12.1V from the drain terminal of the PMOS transistor 134, so the voltage level of the high voltage output signal VOH It is pulled down to the first internal bias voltage V1 (12V). On the other hand, the second output shifter 160 receives 2.9V from the drain terminal of the NMOS transistor 122 and 0V from the drain terminal of the NMOS transistor 124. The voltage level of the low voltage output signal VOL is pulled down to the system low voltage VSS .

位準移位電路100可以輸出電壓位準平移後的高電壓輸出信號VOH以及跟低電壓輸入信號VIN具有相同位準的低電壓輸出信號VOL。圖3顯示高電壓輸出信號VOH與低電壓輸出信號VOL都具有全擺幅，而且電壓位準可以精準地在12V～15V或0V～3V之間切換。上升時間（rising time）與下降時間（falling time）也都十分短暫。The level shift circuit 100 can output the high-voltage output signal VOH after the voltage level shift and the low-voltage output signal VOL having the same level as the low-voltage input signal VIN. Figure 3 shows that both the high-voltage output signal VOH and the low-voltage output signal VOL have full swing, and the voltage level can be accurately switched between 12V~15V or 0V~3V. The rising time and falling time are also very short.

圖4與圖5分別顯示第一內部偏壓V1與第二內部偏壓V2隨時間的變化情形。從圖4與圖5可以發現在耦接電容114的條件下，即使低電壓輸入信號VIN的電壓位準從3V改變至0V，第一內部偏壓V1與第二內部偏壓V2的暫態電壓變化也不超過1V，顯著地降低分壓節點N上可能發生的尖波。4 and 5 show the changes of the first internal bias voltage V1 and the second internal bias voltage V2 with time, respectively. It can be found from FIGS. 4 and 5 that under the condition of the coupling capacitor 114, even if the voltage level of the low-voltage input signal VIN changes from 3V to 0V, the transient voltages of the first internal bias voltage V1 and the second internal bias voltage V2 The change does not exceed 1V, which significantly reduces the spikes that may occur on the voltage divider node N.

另外說明的是，在其他的實施例中，可以不需要第二輸出移位器160，或是可以輸出位準移位器（包括第一輸出移位器150或第二輸出移位器160）也可以耦接不同的分壓節點，本發明並不限制位準移位器一定要選用哪一個內部分壓，亦即本發明並不限制高電壓輸出信號VOH或低電壓輸出信號VOL的輸出電壓範圍。In addition, in other embodiments, the second output shifter 160 may not be required, or the level shifter (including the first output shifter 150 or the second output shifter 160) may be output It can also be coupled to different voltage-dividing nodes. The invention does not limit which internal voltage divider the level shifter must choose. That is, the invention does not limit the output voltage of the high-voltage output signal VOH or the low-voltage output signal VOL range.

圖6是依照本發明的另一實施例的一種位準移位電路的電路示意圖。位準移位電路600的架構大致與位準移位電路100相同，差別在於偏壓產生裝置610中的電容614配置方式與偏壓產生裝置110中的電容114不同。偏壓產生裝置110的電容114與分壓電晶體112並聯，以並聯的分壓電晶體112跟電容114作為一個分壓單元的話，這些分壓單元串連於系統高電壓VDD與系統低電壓VSS之間。換句話說，每個分壓節點N都會耦接兩個電容114以達到穩壓的效果。偏壓產生裝置610中的多個分壓電晶體112依舊是串連於系統高電壓VDD與系統低電壓VSS之間，但每個分壓節點N只有耦接一個電容614。電容614的一端耦接分壓節點N，另一端接地（或是系統低電壓VSS）。6 is a schematic circuit diagram of a level shift circuit according to another embodiment of the invention. The architecture of the level shift circuit 600 is roughly the same as the level shift circuit 100, the difference is that the configuration of the capacitor 614 in the bias voltage generating device 610 is different from the capacitor 114 in the bias voltage generating device 110. The capacitor 114 of the bias voltage generating device 110 is connected in parallel with the piezoelectric divider 112. If the parallel piezoelectric divider 112 and the capacitor 114 are used as a voltage dividing unit, these voltage dividing units are connected in series to the system high voltage VDD and the system low voltage VSS between. In other words, each voltage dividing node N is coupled to two capacitors 114 to achieve the effect of voltage regulation. The plurality of partial piezoelectric crystals 112 in the bias voltage generating device 610 are still connected in series between the system high voltage VDD and the system low voltage VSS, but each voltage dividing node N has only one capacitor 614 coupled thereto. One end of the capacitor 614 is coupled to the voltage dividing node N, and the other end is grounded (or the system low voltage VSS).

關於位準移位電路600的電路運作大致相同於位準移位電路100的電路運作，在此則不再贅述。The circuit operation of the level shift circuit 600 is substantially the same as the circuit operation of the level shift circuit 100, and it will not be repeated here.

綜上所述，本發明提供一種顯示面板與位準移位電路。位準移位電路可以接收低電壓輸入信號來提供電壓位準平移後的高電壓輸出信號。位準移位電路具有偏壓產生裝置可以根據系統高電壓在多個分壓節點上提供多個不同的內部偏壓，並且每個分壓節點耦接電容以達到穩壓的效果。位準移位電路還利用多個降壓單元來將系統高電壓區分為若干電壓範圍以達到逐步降壓的效果，並且避免電晶體因為跨壓過大而產生問題。位準移位電路還利用交叉偶合級電路來加快高電壓輸出信號的上升時間與下降時間。因此本發明的位準移位電路具有輸出穩定、適用於低壓製程、全擺幅輸出以及不需要外接其他偏壓電源的優點。本發明的顯示面板的驅動電路使用上述的位準移位電路，因此可以縮小晶片面積還能降低電路的漏電流。In summary, the present invention provides a display panel and a level shift circuit. The level shift circuit can receive a low voltage input signal to provide a high voltage output signal after the voltage level is shifted. The level shift circuit has a bias voltage generating device that can provide a plurality of different internal bias voltages on multiple voltage-dividing nodes according to the high voltage of the system, and each voltage-dividing node is coupled to a capacitor to achieve the effect of voltage regulation. The level shift circuit also uses multiple buck units to divide the high voltage of the system into several voltage ranges to achieve the step-down effect, and to avoid problems caused by the excessive voltage across the transistor. The level shift circuit also uses a cross-coupling stage circuit to speed up the rise time and fall time of the high voltage output signal. Therefore, the level shift circuit of the present invention has the advantages of stable output, suitable for low-voltage manufacturing process, full swing output, and no need to connect other bias power supply. The driving circuit of the display panel of the present invention uses the above-mentioned level shift circuit, so the chip area can be reduced and the leakage current of the circuit can be reduced.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10:顯示面板10: Display panel

100、600:電壓轉換電路100, 600: voltage conversion circuit

110、610:偏壓產生裝置110, 610: bias voltage generating device

112:分壓電晶體112: Split piezoelectric crystal

114、614:電容114, 614: capacitance

120:輸入級電路120: input stage circuit

122、124:NMOS電晶體122, 124: NMOS transistor

130:交叉耦合級電路130: Cross-coupling stage circuit

132、134:PMOS電晶體132, 134: PMOS transistor

142~148:降壓單元142~148: Buck unit

150:第一輸出移位器150: first output shifter

160:第二輸出移位器160: second output shifter

200:閘極驅動器200: Gate driver

GS:閘極信號GS: Gate signal

INV:反相器INV: inverter

N:分壓節點N: voltage division node

SL:掃描線SL: Scan line

PX:畫素PX: pixel

TP1:第一PMOS電晶體TP1: the first PMOS transistor

TN1:第一NMOS電晶體TN1: the first NMOS transistor

TP2:第二PMOS電晶體TP2: Second PMOS transistor

TN2:第二NMOS電晶體TN2: Second NMOS transistor

V1~V4:內部偏壓V1~V4: internal bias

VIN:低電壓輸入信號VIN: low voltage input signal

VDD:系統高電壓VDD: system high voltage

VSS:系統低電壓VSS: System low voltage

VOUT:輸出信號VOUT: output signal

VOH:高電壓輸出信號VOH: high voltage output signal

VOL:低電壓輸出信號VOL: Low voltage output signal

圖1是依照本發明的一實施例的一種顯示面板的示意圖。 圖2是依照本發明的一實施例的一種位準移位電路的電路示意圖。 圖3是依照本發明的一實施例的一種位準移位電路的輸出信號的波形圖。 圖4是依照本發明的一實施例的第一內部偏壓的波形圖。 圖5是依照本發明的一實施例的第二內部偏壓的波形圖。 圖6是依照本發明的另一實施例的一種位準移位電路的電路示意圖。 FIG. 1 is a schematic diagram of a display panel according to an embodiment of the invention. 2 is a circuit schematic diagram of a level shift circuit according to an embodiment of the invention. 3 is a waveform diagram of an output signal of a level shift circuit according to an embodiment of the invention. 4 is a waveform diagram of a first internal bias voltage according to an embodiment of the invention. 5 is a waveform diagram of a second internal bias voltage according to an embodiment of the invention. 6 is a schematic circuit diagram of a level shift circuit according to another embodiment of the invention.

100:電壓轉換電路 100: voltage conversion circuit

110:偏壓產生裝置 110: bias voltage generating device

112:分壓電晶體 112: Split piezoelectric crystal

114:電容 114: capacitance

120:輸入級電路 120: input stage circuit

122、124:NMOS電晶體 122, 124: NMOS transistor

130:交叉耦合級電路 130: Cross-coupling stage circuit

132、134:PMOS電晶體 132, 134: PMOS transistor

142~148:降壓單元 142~148: Buck unit

150:第一輸出移位器 150: first output shifter

160:第二輸出移位器 160: second output shifter

INV:反相器 INV: inverter

N:分壓節點 N: voltage division node

TP1:第一PMOS電晶體 TP1: the first PMOS transistor

TN1:第一NMOS電晶體 TN1: the first NMOS transistor

TP2:第二PMOS電晶體 TP2: Second PMOS transistor

TN2:第二NMOS電晶體 TN2: Second NMOS transistor

V1~V4:內部偏壓 V1~V4: internal bias

VIN:低電壓輸入信號 VIN: low voltage input signal

VDD:系統高電壓 VDD: system high voltage

VSS:系統低電壓 VSS: System low voltage

VOH:高電壓輸出信號 VOH: high voltage output signal

VOL:低電壓輸出信號 VOL: Low voltage output signal

Claims (12)

一種位準移位電路，接收一低電壓輸入信號以提供一高電壓輸出信號，該位準移位電路包括：一偏壓產生裝置，包括多個分壓電晶體與多個電容，該些分壓電晶體以串聯的形式耦接於一系統高電壓與一系統低電壓之間，且相鄰的該些分壓電晶體之間具有一分壓節點以提供多個內部偏壓，其中該些分壓節點耦接該些電容；一輸入級電路，耦接該系統低電壓，用以接收該低電壓輸入信號；一交叉耦合級電路，耦接該系統高電壓；多個降壓單元，以串聯的形式耦接於該輸入級電路與該交叉耦合級電路之間，且分別耦接該些分壓節點以接收該些內部偏壓；以及一第一輸出移位器，耦接該交叉耦合級電路與該些分壓節點的其中之一以根據該系統高電壓與該些內部偏壓中的一第一內部偏壓輸出該高電壓輸出信號。 A level shift circuit receives a low voltage input signal to provide a high voltage output signal. The level shift circuit includes: a bias voltage generating device, including a plurality of piezoelectric crystals and a plurality of capacitors The piezoelectric crystals are coupled in series between a system high voltage and a system low voltage, and there is a voltage dividing node between the adjacent piezoelectric partial crystals to provide a plurality of internal bias voltages, among which The voltage divider node is coupled to the capacitors; an input stage circuit is coupled to the system low voltage to receive the low voltage input signal; a cross-coupling stage circuit is coupled to the system high voltage; a plurality of buck units are used to Serially coupled between the input stage circuit and the cross-coupling stage circuit, and respectively coupled to the voltage-dividing nodes to receive the internal bias voltages; and a first output shifter to couple the cross-coupling One of the stage circuit and the voltage dividing nodes outputs the high voltage output signal according to a first internal bias voltage of the system high voltage and the internal bias voltages. 如申請專利範圍第1項所述的位準移位電路，還包括：一第二輸出移位器，耦接該輸入級電路與該些分壓節點的其中另一以根據該系統低電壓與該些內部偏壓中的一第二內部偏壓輸出一低電壓輸出信號。 The level shift circuit as described in item 1 of the patent application scope further includes: a second output shifter, coupled to the input stage circuit and the other of the voltage-dividing nodes, according to the system low voltage and A second internal bias voltage among the internal bias voltages outputs a low voltage output signal. 如申請專利範圍第1項所述的位準移位電路，其中，每一個該分壓節點所耦接的該電容的耐壓值大於或等於對應的分壓電晶體的耐壓值。 The level shifting circuit as described in item 1 of the patent application range, wherein the withstand voltage value of the capacitor coupled to each of the voltage dividing nodes is greater than or equal to the corresponding withstand voltage value of the divided piezoelectric crystal. 如申請專利範圍第1項所述的位準移位電路，其中該些電容的電容值落在0.1pF至1pF的範圍內。 The level shift circuit as described in item 1 of the patent application scope, wherein the capacitance of these capacitors falls within the range of 0.1 pF to 1 pF. 如申請專利範圍第1項所述的位準移位電路，其中每一個該電容與對應的分壓電晶體並聯。 The level shift circuit as described in item 1 of the patent application scope, wherein each of the capacitors is connected in parallel with the corresponding piezoelectric piezoelectric crystal. 如申請專利範圍第1項所述的位準移位電路，其中該些電容一端耦接對應的分壓節點且另一端接地。 The level shift circuit as described in Item 1 of the patent application scope, wherein one end of the capacitors is coupled to the corresponding voltage dividing node and the other end is grounded. 如申請專利範圍第1項所述的位準移位電路，其中每一個該降壓單元為互補式電晶體對，包括：一第一PMOS電晶體與一第一NMOS電晶體，該第一PMOS電晶體的汲極耦接至該第一NMOS電晶體的汲極；以及一第二PMOS電晶體與一第二NMOS電晶體，與該第一PMOS電晶體與該第一NMOS電晶體呈對稱配置，該第二PMOS電晶體的汲極耦接至該第二NMOS電晶體的汲極，且該第一PMOS電晶體、該第一NMOS電晶體、該第二PMOS電晶體與該第二NMOS電晶體的閘極都耦接至對應的該分壓節點。 The level shift circuit as described in item 1 of the patent application scope, wherein each of the step-down units is a complementary transistor pair, including: a first PMOS transistor and a first NMOS transistor, the first PMOS The drain of the transistor is coupled to the drain of the first NMOS transistor; and a second PMOS transistor and a second NMOS transistor are arranged symmetrically with the first PMOS transistor and the first NMOS transistor , The drain of the second PMOS transistor is coupled to the drain of the second NMOS transistor, and the first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor The gates of the crystal are coupled to the corresponding voltage dividing nodes. 如申請專利範圍第7項所述的位準移位電路，其中該位準移位電路中的電晶體都是由低壓製程產生的MOS電晶體，其中所述低壓製程為0.18μm CMOS製程。 The level shift circuit as described in item 7 of the patent application scope, wherein the transistors in the level shift circuit are all MOS transistors produced by a low voltage process, wherein the low voltage process is a 0.18 μm CMOS process. 如申請專利範圍第1項所述的位準移位電路，其中該交叉耦合級電路包括二個PMOS電晶體，該二個PMOS電晶體的源極耦接該系統高電壓，該二個PMOS電晶體的閘極耦接彼此的汲極，以及該二個PMOS電晶體的汲極耦接該些降壓單元中的第一個降壓單元。 The level shift circuit as described in item 1 of the patent application scope, wherein the cross-coupling stage circuit includes two PMOS transistors, the sources of the two PMOS transistors are coupled to the high voltage of the system, and the two PMOS transistors The gates of the crystals are coupled to the drains of each other, and the drains of the two PMOS transistors are coupled to the first buck unit of the buck units. 如申請專利範圍第9項所述的位準移位電路，其中該第一輸出移位器接收該交叉耦合級電路中的該二個PMOS電晶體的汲極的電壓，且耦接於該系統高電壓和具有該第一內部偏壓的該分壓節點之間。 The level shift circuit as described in item 9 of the patent application range, wherein the first output shifter receives the voltage of the drains of the two PMOS transistors in the cross-coupling stage circuit and is coupled to the system Between the high voltage and the voltage dividing node with the first internal bias. 如申請專利範圍第1項所述的位準移位電路，其中該輸入級電路包括二個NMOS電晶體，該二個NMOS電晶體的汲極耦接該些降壓單元中的最後一個降壓單元，該二個NMOS電晶體的源極耦接該系統低電壓，以及該二個NMOS電晶體其中之一的閘極接收該低電壓輸入信號，該二個NMOS電晶體其中另一的閘極接收該低電壓輸入信號的反相信號。 The level shift circuit as described in item 1 of the patent application scope, wherein the input stage circuit includes two NMOS transistors, and the drains of the two NMOS transistors are coupled to the last step-down of the step-down units Unit, the sources of the two NMOS transistors are coupled to the system low voltage, and the gate of one of the two NMOS transistors receives the low voltage input signal, and the gate of the other of the two NMOS transistors Receive the inverted signal of this low voltage input signal. 一種顯示面板，包括：一位準移位電路，接收一低電壓輸入信號以提供一高電壓輸出信號，該位準移位電路包括：一偏壓產生裝置，包括多個分壓電晶體與多個電容，該些分壓電晶體以串聯的形式耦接於一系統高電壓與一系統低電壓之間，且相鄰的該些分壓電晶體之間具有一分壓節點以提供多個內部偏壓，其中該些分壓節點耦接該些電容； 一輸入級電路，耦接該系統低電壓，用以接收該低電壓輸入信號；一交叉耦合級電路，耦接該系統高電壓；多個降壓單元，以串聯的形式耦接於該輸入級電路與該交叉耦合級電路之間，且分別耦接該些分壓節點以接收該些內部偏壓；以及一第一輸出移位器，耦接該交叉耦合級電路與該些分壓節點的其中之一以根據該系統高電壓與該些內部偏壓中的一第一內部偏壓輸出該高電壓輸出信號；一閘極驅動器，接收該高電壓輸出信號且提供多個閘極信號；多條掃描線；以及多個畫素，耦接該些掃描線以接收對應的閘極信號。 A display panel includes: a level shift circuit that receives a low voltage input signal to provide a high voltage output signal. The level shift circuit includes: a bias voltage generating device including a plurality of piezoelectric crystals and multiple Capacitors, the partial piezoelectric crystals are coupled in series between a system high voltage and a system low voltage, and there is a voltage dividing node between adjacent partial piezoelectric crystals to provide multiple internal Bias voltage, wherein the voltage dividing nodes are coupled to the capacitors; An input stage circuit, coupled to the system low voltage, for receiving the low voltage input signal; a cross-coupling stage circuit, coupled to the system high voltage; multiple buck units, coupled in series to the input stage Between the circuit and the cross-coupling stage circuit, and are respectively coupled to the voltage-dividing nodes to receive the internal bias voltages; and a first output shifter, coupling the cross-coupling stage circuit and the voltage-dividing nodes One of them is to output the high voltage output signal according to the system high voltage and a first internal bias voltage among the internal bias voltages; a gate driver receives the high voltage output signal and provides a plurality of gate signals; A scan line; and a plurality of pixels, coupled to the scan lines to receive corresponding gate signals.
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