TWI692116B

TWI692116B - Light-emitting element

Info

Publication number: TWI692116B
Application number: TW106144622A
Authority: TW
Inventors: 蔡佳珍; 郭得山; 李奇霖; 卓亨穎; 歐震; 陳俊揚
Original assignee: 晶元光電股份有限公司
Priority date: 2017-12-19
Filing date: 2017-12-19
Publication date: 2020-04-21
Also published as: CN109935671B; TW201929258A; CN109935671A

Abstract

A light-emitting device, includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; an active layer formed between the second and the third semiconductor layers; an exposed region, passing through the third semiconductor layer and the active layer to expose a first surface of the first semiconductor layer and a second surface of the second semiconductor layer; and a first electrode, formed in the exposed region and contacting the first surface and the second surface; wherein the first semiconductor layer and the second semiconductor layer have different resistances.

Description

發光元件Light emitting element

本發明係關於一種發光裝置，更詳言之，係關於一種具有高亮度之發光元件。The present invention relates to a light-emitting device, and more specifically, to a light-emitting element with high brightness.

發光二極體(light-emitting diode, LED)為P型半導體與N型半導體所組成之光電元件，透過P-N接面上載子的結合放出光線，加上具有體積小、低耗電量、壽命長、反應速度快等優點，廣泛地使用於光學顯示裝置、交通號誌、資料儲存裝置、通訊裝置、照明裝置與醫療器材等。Light-emitting diode (LED) is a photoelectric element composed of P-type semiconductor and N-type semiconductor. It emits light through the combination of carriers on the PN junction, plus it has small size, low power consumption and long life. , Fast response and other advantages, widely used in optical display devices, traffic signs, data storage devices, communication devices, lighting devices and medical equipment.

一種發光元件，包含：一第一半導體層；一第二半導體層，位於第一半導體層上；一第三半導體層，位於該第二半導體層上；一活性層，位於第二半導體層及第三半導體層之間；一暴露區，穿過第三半導體層及活性層，暴露出第一半導體層之一第表面以及第二半導體層之一第二表面；以及一第一電極，位於暴露區中，且接觸第一表面及第二表面；其中，第一半導體層與第二半導體層具有不同阻值。A light emitting device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; an active layer on the second semiconductor layer and the first Between three semiconductor layers; an exposed area, passing through the third semiconductor layer and the active layer, exposing a first surface of the first semiconductor layer and a second surface of the second semiconductor layer; and a first electrode, located in the exposed area , And contact the first surface and the second surface; wherein, the first semiconductor layer and the second semiconductor layer have different resistance values.

申請案之實施例會被詳細地描述，並且繪製於圖式中，相同或類似的部分會以相同的號碼在各圖式以及說明出現。The embodiments of the application will be described in detail and drawn in the drawings, and the same or similar parts will appear in the drawings and descriptions with the same numbers.

第1A圖為本申請案第一實施例中所揭示之一發光元件1之上視圖的變化例A。第1B圖為沿第1A圖中變化例A的B-B’截面之側視圖，第1C圖為第1B圖中區域R之局部放大圖。FIG. 1A is a variation A of a top view of a light-emitting element 1 disclosed in the first embodiment of the present application. Fig. 1B is a side view along the B-B' cross-section of Modification A in Fig. 1A, and Fig. 1C is a partial enlarged view of the region R in Fig. 1B.

參照第1A至1C圖，第一實施例中變化例A之發光元件1包含一基板10，以及一半導體結構20位於基板10的上表面10a上。半導體結構20由基板10之上表面10a依序包含一第一半導體層201、一第二半導體層202、一活性層204以及一第三半導體層203。在半導體結構20中，包含一暴露區28，自第三半導體層203之上表面203a向下延伸，穿過第三半導體層203以及活性層204，暴露出第一半導體層201的上表面TS1和側表面LS1，以及第二半導體層202的上表面TS2、上部側表面LS2和下部側表面LS2’，其中由截面之側視觀之，第一半導體層201之上表面TS1具有一寬度W1；此外，第一半導體層201的側表面LS1和第二半導體層202的下部側表面LS2’相連接，第一半導體層201的上表面TS1和第二半導體層202的上表面TS2實質上平行。Referring to FIGS. 1A to 1C, the light-emitting element 1 of Variation A in the first embodiment includes a substrate 10, and a semiconductor structure 20 is located on the upper surface 10a of the substrate 10. The semiconductor structure 20 includes a first semiconductor layer 201, a second semiconductor layer 202, an active layer 204, and a third semiconductor layer 203 in sequence from the upper surface 10a of the substrate 10. The semiconductor structure 20 includes an exposed region 28 extending downward from the upper surface 203a of the third semiconductor layer 203, passing through the third semiconductor layer 203 and the active layer 204, exposing the upper surface TS1 of the first semiconductor layer 201 and The side surface LS1, and the upper surface TS2, upper side surface LS2, and lower side surface LS2' of the second semiconductor layer 202, wherein the top surface TS1 of the first semiconductor layer 201 has a width W1 as viewed from the side of the cross section; The side surface LS1 of the first semiconductor layer 201 and the lower side surface LS2' of the second semiconductor layer 202 are connected, and the upper surface TS1 of the first semiconductor layer 201 and the upper surface TS2 of the second semiconductor layer 202 are substantially parallel.

於本申請案一實施例中，暴露區28可藉由多次蝕刻製程所形成，例如，在第一次蝕刻製程中，先自第三半導體層203之上表面203a選定一部份區域，向下移除其下方的第三半導體層203、活性層204以及第二半導體層202，一直到第二半導體層202之一深度，暴露出第二半導體層202之上表面TS2以及上部側表面LS2。於一實施例中，蝕刻深度由上表面203a算起介於0.8-1.5 μm。接著，在第二次蝕刻製程中，自第二半導體層202之上表面TS2選定一部份區域，向下移除其下方的第二半導體層202以及第一半導體層201，一直到第一半導體層201之一深度，暴露出第一半導體層201之上表面TS1和側表面LS1，以及第二半導體層202的下部側表面LS2’。於一實施例中，蝕刻深度由第二半導體層202之上表面TS2算起介於0.2-1 μm。於本實施例中，第一半導體層201之上表面TS1比第一半導體層201和第二半導體層202之介面更接近於基板10。In an embodiment of the present application, the exposed region 28 may be formed by multiple etching processes. For example, in the first etching process, a part of the area is selected from the upper surface 203a of the third semiconductor layer 203, toward The third semiconductor layer 203, the active layer 204, and the second semiconductor layer 202 underneath are removed to a depth of the second semiconductor layer 202, exposing the upper surface TS2 and the upper side surface LS2 of the second semiconductor layer 202. In one embodiment, the etching depth is from 0.8 to 1.5 μm from the upper surface 203a. Next, in the second etching process, a part of the area is selected from the upper surface TS2 of the second semiconductor layer 202, and the second semiconductor layer 202 and the first semiconductor layer 201 below it are removed downwards until the first semiconductor One depth of the layer 201 exposes the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201 and the lower side surface LS2' of the second semiconductor layer 202. In one embodiment, the etching depth is between 0.2-1 μm from the top surface TS2 of the second semiconductor layer 202. In this embodiment, the upper surface TS1 of the first semiconductor layer 201 is closer to the substrate 10 than the interface between the first semiconductor layer 201 and the second semiconductor layer 202.

於本申請案之一實施例中，基板10包括絕緣基板或導電基板，當基板10為導電基板時，基板10和其上之半導體結構20之間會存在ㄧ絕緣區域，以避免兩者之間漏電流產生。絕緣基板包含用以成長氮化銦鎵(InGaN)之藍寶石(Al₂ O₃ )晶圓；導電基板包含用以成長磷化鋁鎵銦(AlGaInP)之砷化鎵(GaAs)晶圓，或用以成長氮化銦鎵(InGaN)之氮化鎵(GaN)晶圓、矽(Si)晶圓或碳化矽(SiC)晶圓。在基板10欲形成半導體結構20之上表面10a可包含一圖案化結構101，藉此提高半導體結構20之磊晶品質，或提高發光元件1之光摘出效率。In an embodiment of the present application, the substrate 10 includes an insulating substrate or a conductive substrate. When the substrate 10 is a conductive substrate, there will be an insulating region between the substrate 10 and the semiconductor structure 20 thereon to avoid the gap between the two Leakage current is generated. The insulating substrate includes a sapphire (Al ₂ O ₃ ) wafer for growing indium gallium nitride (InGaN); the conductive substrate includes a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or To grow InGaN gallium nitride (GaN) wafers, silicon (Si) wafers or silicon carbide (SiC) wafers. The upper surface 10a of the semiconductor structure 20 to be formed on the substrate 10 may include a patterned structure 101, thereby improving the epitaxial quality of the semiconductor structure 20 or improving the light extraction efficiency of the light emitting element 1.

於本申請案之一實施例中，在基板10與第一半導體層201之間更可包含其他半導體層，例如，包含一緩衝結構(圖未示)。緩衝結構可減緩基板10與半導體結構20之間晶格常數的不匹配，或幫助應力釋放，以改善磊晶品質。In one embodiment of the present application, another semiconductor layer may be included between the substrate 10 and the first semiconductor layer 201, for example, including a buffer structure (not shown). The buffer structure can alleviate the mismatch in lattice constant between the substrate 10 and the semiconductor structure 20, or help stress relief to improve epitaxial quality.

於基板10上形成半導體結構20包含緩衝結構之方法包含沉積法。沉積包含磊晶(Epitaxy)、物理氣相沉積法(PVD)。磊晶包含分子束磊晶法(MBE)、有機金屬氣相磊晶(MOVPE)、氣相磊晶成長法(VPE)或液相磊晶成長法(LPE)；物理氣相沉積法包含蒸鍍(evaporator)或濺鍍(sputter)。The method of forming the semiconductor structure 20 including the buffer structure on the substrate 10 includes a deposition method. The deposition includes epitaxy and physical vapor deposition (PVD). Epitaxy includes molecular beam epitaxy (MBE), organometallic vapor phase epitaxy (MOVPE), vapor phase epitaxy (VPE) or liquid phase epitaxy (LPE); physical vapor deposition includes vapor deposition (evaporator) or sputtering.

於本申請案中，半導體結構20中的第一半導體層201、第二半導體層202、活性層204或第三半導體層203可為單一層或包含複數子層。半導體結構20之材料包含Ⅲ-Ⅴ族半導體材料，例如Al_x In_y Ga_(1-x-y) N或Al_x In_y Ga_(1-x-y) P，其中0≦x，y≦1；(x+y)≦1。依據活性層204之材料，當半導體結構20材料為AlInGaP系列材料時，可發出波長介於610 nm及650 nm之間的紅光，波長介於530 nm及570 nm之間的綠光，當半導體結構10材料為InGaN系列材料時，可發出波長介於450 nm及490 nm之間的藍光，或是當半導體結構20材料為AlN、AlGaN、AlGaInN系列材料時，可發出波長介於400 nm及250 nm之間的藍紫光或不可見光的紫外光。Ⅲ-Ⅴ族半導體材料的選擇不在此限，亦可選擇上述以外的材料產生其他波段的非可見光，例如紅外光或遠紅外光。活性層204可為單異質結構(single heterostructure, SH )，雙異質結構(double heterostructure, DH)，雙側雙異質結構( double-side double heterostructure, DDH)，多層量子井結構(multi-quantum well, MQW)。活性層材料可為不摻雜摻雜物、摻雜p型摻雜物或摻雜n型摻雜物的半導體。In the present application, the first semiconductor layer 201, the second semiconductor layer 202, the active layer 204, or the third semiconductor layer 203 in the semiconductor structure 20 may be a single layer or include a plurality of sub-layers. The materials of the semiconductor structure 20 include group III-Ⅴ semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0≦x, y≦1; (x+ y)≦1. According to the material of the active layer 204, when the semiconductor structure 20 material is AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, and green light with a wavelength between 530 nm and 570 nm. When the structure 10 material is InGaN series material, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the semiconductor structure 20 material is AlN, AlGaN, AlGaInN series material, it can emit a wavelength between 400 nm and 250 Blue-violet light or invisible ultraviolet light between nm. The choice of III-Ⅴ semiconductor materials is not limited to this. Materials other than the above can also be selected to generate invisible light in other wavelength bands, such as infrared light or far infrared light. The active layer 204 may be a single heterostructure (single heterostructure, SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well structure (multi-quantum well, MQW). The active layer material may be a semiconductor undoped with dopants, doped with p-type dopants, or doped with n-type dopants.

第一及第二半導體層201及202具有相同之導電性、電性、極性或摻雜物，而第三半導體層203與第一及第二半導體層201、202具有不同之導電性、電性、極性或摻雜物。以本實施例為例，第三半導體層203為p型可提供電洞，第一及第二半導體層201及202為n型可提供電子，使得電子與電洞可於活性層204中複合以產生光線。於一實施例中，第二半導體層202厚度小於第一半導體層201厚度，例如，第二半導體層202厚度小於1 μm。其中，第一及第二半導體層201及202具有不同阻值，其材料與實施態樣將詳述如後。The first and second semiconductor layers 201 and 202 have the same conductivity, electrical property, polarity or dopant, and the third semiconductor layer 203 and the first and second semiconductor layers 201 and 202 have different conductivity and electrical properties , Polarity or dopant. Taking this embodiment as an example, the third semiconductor layer 203 is p-type to provide holes, and the first and second semiconductor layers 201 and 202 are n-type to provide electrons, so that electrons and holes can recombine in the active layer 204 to Generate light. In one embodiment, the thickness of the second semiconductor layer 202 is less than the thickness of the first semiconductor layer 201, for example, the thickness of the second semiconductor layer 202 is less than 1 μm. Among them, the first and second semiconductor layers 201 and 202 have different resistance values, and their materials and implementations will be described in detail later.

第一半導體層201之阻值可高於或低於第二半導層202。於一實施例中，第一及第二半導體層201及202包含相同材料及不同摻雜濃度的相同導電性摻雜物；在此，相同材料係指半導體中摻雜物以外的材料組成為相同。例如，第一半導體層201與第二半導層202分別為不同矽摻雜濃度的n型GaN。於一實施例中，第一半導體層201之阻值小於第二半導體層202，第一半導體層201為矽摻雜濃度2×10¹⁹ cm^-3 的n型GaN，第二半導體層202為矽摻雜濃度1.3×10¹⁹ cm^-3 的n型GaN；於另一實施例中，第一半導體層201之阻值大於第二半導體層202，第一半導體層201為矽摻雜濃度8×10¹⁸ cm^-3 的n型GaN，第二半導層202為矽摻雜濃度1.3×10¹⁹ cm^-3 的n型GaN。The resistance of the first semiconductor layer 201 can be higher or lower than that of the second semiconductor layer 202. In an embodiment, the first and second semiconductor layers 201 and 202 include the same material and the same conductive dopant at different doping concentrations; here, the same material refers to the same composition of materials other than the dopant in the semiconductor . For example, the first semiconductor layer 201 and the second semiconductor layer 202 are respectively n-type GaN with different silicon doping concentrations. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202, the first semiconductor layer 201 is n-type GaN with a silicon doping concentration of 2×10 ¹⁹ cm ^-3 , and the second semiconductor layer 202 is silicon N-type GaN with a doping concentration of 1.3×10 ¹⁹ cm ^-3 ; in another embodiment, the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202, and the first semiconductor layer 201 is a silicon doping concentration of 8×10 ¹⁸ cm ^-3 n-type GaN, the second semiconductor layer 202 is n-type GaN with a silicon doping concentration of 1.3×10 ¹⁹ cm ^-3 .

於另一實施例中，第一及第二半導體層201及202包含不同材料，例如，第一半導體層201為n型AlGaN，第二半導體層202為n型GaN；或是第一及第二半導體層201及202分別為不同鋁含量的n型AlGaN，其中，第一半導體層201之鋁含量高於第二半導體層201。於一實施例中，第一半導體層201之阻值小於第二半導體層202，例如，第一半導體層201為矽摻雜濃度a×10¹⁹ cm^-3 的n型Al_x Ga_1-x N，第二半導體層202為矽摻雜濃度b×10¹⁹ cm^-3 的n型Al_y Ga_1-y N，其中a＞b，10＞a＞0.5，且x＞y。此外，第一及第二半導體層201及202更可具有不同或相同的摻雜濃度的相同導電性摻雜物。於一實施例中，第一半導體層201之阻值小於第二半導體層202，例如，第一半導體層201為矽摻雜濃度2×10¹⁹ cm^-3 的n型AlGaN，第二半導體層202為矽摻雜濃度介於5×10¹⁸ cm^-3 至7×10¹⁸ cm^-3 的n型GaN。In another embodiment, the first and second semiconductor layers 201 and 202 include different materials, for example, the first semiconductor layer 201 is n-type AlGaN, and the second semiconductor layer 202 is n-type GaN; or the first and second The semiconductor layers 201 and 202 are respectively n-type AlGaN with different aluminum contents, wherein the aluminum content of the first semiconductor layer 201 is higher than that of the second semiconductor layer 201. In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. For example, the first semiconductor layer 201 is an n-type Al _x Ga _1-x N with a silicon doping concentration of a×10 ¹⁹ cm ^-3 The second semiconductor layer 202 is an n-type Al _y Ga _1-y N with a silicon doping concentration of b×10 ¹⁹ cm ⁻³ , where a>b, 10>a>0.5, and x>y. In addition, the first and second semiconductor layers 201 and 202 may further have the same conductive dopant with different or the same doping concentration. In an embodiment, the resistance value of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. For example, the first semiconductor layer 201 is n-type AlGaN with a silicon doping concentration of 2×10 ¹⁹ cm ^-3 , and the second semiconductor layer 202 It is n-type GaN with a silicon doping concentration ranging from 5×10 ¹⁸ cm ^-3 to 7×10 ¹⁸ cm ^-3 .

於另一實施例中，第一半導體層201可包含超晶格結構，例如為AlGaN/GaN兩子層之超晶格結構，或是在單一半導體材料中利用調變式摻雜所形成之半導體層。In another embodiment, the first semiconductor layer 201 may include a superlattice structure, for example, a superlattice structure of two sublayers of AlGaN/GaN, or a semiconductor formed by modulation doping in a single semiconductor material Floor.

一第一電極30，位於暴露區28中，同時接觸具有不同阻值的第一半導體層201和第二半導體層202。如第1B及1C圖所示，第一電極30接觸第一半導體層201之上表面TS1和側表面LS1，以及第二半導體層202之上表面TS2和下部側表面LS2’，且第一電極30和上部側表面LS2之間具有一間隙。於本實施例中，第一電極30為一第一打線墊，於上視圖中具有寬度W_N ，且上表面TS1與第一電極30具有相似的圖案形狀。上表面TS1中包含與第一電極30接觸的第一接觸區域C₁ ，上表面TS2中包含與第一電極30接觸的第二接觸區域C₂ 。第一接觸區域C₁ 面積與第二接觸區域C₂ 面積不相等。於第一實施例的變化例A中，第一電極30之寬度W_N 大於上表面TS1之寬度W₁ ，第一接觸區域C₁ 面積等於上表面TS1面積，且第一接觸區域C₁ 面積大於第二接觸區域C₂ 面積。於一實施例中，第一半導體層201之阻值大於第二半導體層202，第一接觸區域C₁ 面積大於或等於第二接觸區域C₂ 面積。於一實施例中，第一半導體層201之阻值小於第二半導體層202，第一接觸區域C₁ 面積大於第二接觸區域C₂ 面積。A first electrode 30 is located in the exposed region 28 and simultaneously contacts the first semiconductor layer 201 and the second semiconductor layer 202 with different resistances. As shown in FIGS. 1B and 1C, the first electrode 30 contacts the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201, and the upper surface TS2 and the lower side surface LS2' of the second semiconductor layer 202, and the first electrode 30 There is a gap with the upper side surface LS2. In this embodiment, the first electrode 30 is a first wire bonding pad with a width W _N in the top view, and the top surface TS1 and the first electrode 30 have a similar pattern shape. The upper surface TS1 includes a first contact region C ₁ that contacts the first electrode 30, and the upper surface TS2 includes a second contact region C _{2 that} contacts the first electrode 30. The area of the first contact area C ₁ is not equal to the area of the second contact area C ₂ . In Variation A of the first embodiment, the width W _{N of the} first electrode 30 is greater than the width W ₁ of the upper surface TS1, the area of the first contact region C ₁ is equal to the area of the upper surface TS1, and the area of the first contact region C ₁ is greater than The area of the second contact area C ₂ . In an embodiment, the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202, and the area of the first contact region C ₁ is greater than or equal to the area of the second contact region C ₂ . In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202, and the area of the first contact region C ₁ is larger than the area of the second contact region C ₂ .

於本申請案另一實施例中，第一接觸區域C₁ 面積小於第二接觸區域C₂ 面積。於一實施例中，第一半導體層201之阻值大於第二半導體層202，第一接觸區域C₁ 面積小於第二接觸區域C₂ 面積。於一實施例中，第一半導體層201之阻值小於第二半導體層202，第一接觸區域C₁ 面積小於或等於第二接觸區域C₂ 面積。In another embodiment of the present application, the area of the first contact area C ₁ is smaller than the area of the second contact area C ₂ . In one embodiment, the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202, and the area of the first contact region C ₁ is smaller than the area of the second contact region C ₂ . In one embodiment, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202, and the area of the first contact region C ₁ is less than or equal to the area of the second contact region C ₂ .

第三半導體層203之上表面203a具有一電流阻擋層60，於一實施例中，電流阻擋層60包含一開口60a，暴露出部分上表面203a。電流阻擋層60可包含單層介電材料或是由複數組折射率不同之介電材料交互堆疊所組成介電材料疊層，其材料可包含但不限於氧化矽(SiO_X )、氮化矽(Si₃ N₄ )、氧化鋁(Al₂ O₃ )、氧化鈦(Ti_X O_Y )、五氧化二鉭(Ta₂ O₅ )、氧化鈮(Nb₂ O₅ )、氧化锆(ZrO₂ )或前述材料的组合。電流阻擋層60對於活性層204所發出的光線為透明。The upper surface 203a of the third semiconductor layer 203 has a current blocking layer 60. In one embodiment, the current blocking layer 60 includes an opening 60a exposing a portion of the upper surface 203a. The current blocking layer 60 may comprise a single layer of dielectric material or a stack of dielectric materials composed of alternating stacks of multiple dielectric materials with different refractive indices. The materials may include but are not limited to silicon oxide (SiO _X ) and silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (Ti _X O _Y ), tantalum pentoxide (Ta ₂ O ₅ ), niobium oxide (Nb ₂ O ₅ ), zirconium oxide (ZrO ₂ ) Or a combination of the aforementioned materials. The current blocking layer 60 is transparent to the light emitted by the active layer 204.

一透明導電層18覆蓋第三半導體層203之上表面203a，與第三半導體層203電性接觸，並同時覆蓋在電流阻擋層60上。透明導電層18可以是金屬或是透明導電材料，其中金屬可選自具有透光性的薄金屬層，透明導電材料對於活性層204所發出的光線為透明，包含銦錫氧化物(ITO)、氧化鋁鋅(AZO)、氧化鎵鋅(GZO)、或銦鋅氧化物(IZO)等材料。透明導電層18具有一開口18a，對應於電流阻擋層60之開口60a。於一實施例中，透明導電層18僅覆蓋第三半導體層203之上表面203a，與第三半導體層203電性接觸，但不覆蓋電流阻擋層60上，與透明導電層18與電流阻擋層60之間有一間隙。A transparent conductive layer 18 covers the upper surface 203a of the third semiconductor layer 203, is in electrical contact with the third semiconductor layer 203, and simultaneously covers the current blocking layer 60. The transparent conductive layer 18 may be a metal or a transparent conductive material, wherein the metal may be selected from a thin metal layer with light transmission, the transparent conductive material is transparent to the light emitted by the active layer 204, including indium tin oxide (ITO), Alumina zinc (AZO), gallium zinc oxide (GZO), or indium zinc oxide (IZO) and other materials. The transparent conductive layer 18 has an opening 18a corresponding to the opening 60a of the current blocking layer 60. In one embodiment, the transparent conductive layer 18 only covers the upper surface 203a of the third semiconductor layer 203 and is in electrical contact with the third semiconductor layer 203, but does not cover the current blocking layer 60, the transparent conductive layer 18 and the current blocking layer There is a gap between 60.

一第二電極40位於電流阻擋部60、透明導電層18以及第三半導體層203上，與透明導電層18以及第三半導體層203電性連接。第二電極40包含第二打線墊401以及由第二打線墊401所延伸出的第二延伸電極402。相較於第二延伸電極402，第一電極30之第一打線墊與第二電極40之第二打線墊401皆具有較寬的寬度，在後續製程中，可用以打線與外部電源或外部電子元件電性連接。第二電極40位於電流阻擋部60之對應位置上，第二電極40之外輪廓可等於或略小於電流阻擋部60之外輪廓。於本實施例中，第二打線墊401之位置對應於電流阻擋層60之開口60a及透明導電層18之開口18a上，並穿過這些開口，與第三半導體層203接觸。第一電極30與第二電極40之材料包含金屬，例如鉻(Cr)、鈦(Ti)、金(Au)、鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、銠(Rh)或鉑(Pt)等金屬或上述材料之合金或疊層。在第一電極30與第二電極40靠近半導體結構20之表面可選用具有較高反射率之金屬材料以形成一反射鏡來增進出光，在此所述具有較高的反射率係指對於活性層204所發出光線的波長具有80%以上的反射率。較高反射率之金屬材料包含例如鋁(Al)或銀(Ag)。A second electrode 40 is located on the current blocking portion 60, the transparent conductive layer 18 and the third semiconductor layer 203, and is electrically connected to the transparent conductive layer 18 and the third semiconductor layer 203. The second electrode 40 includes a second wire bonding pad 401 and a second extension electrode 402 extending from the second wire bonding pad 401. Compared to the second extension electrode 402, the first bonding pad of the first electrode 30 and the second bonding pad 401 of the second electrode 40 have a wider width, and can be used for bonding and external power supply or external electronics in the subsequent process The components are electrically connected. The second electrode 40 is located at a corresponding position of the current blocking portion 60. The outer contour of the second electrode 40 may be equal to or slightly smaller than the outer contour of the current blocking portion 60. In this embodiment, the position of the second bonding pad 401 corresponds to the opening 60a of the current blocking layer 60 and the opening 18a of the transparent conductive layer 18, and passes through these openings to contact the third semiconductor layer 203. The materials of the first electrode 30 and the second electrode 40 include metals such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), Metals such as rhodium (Rh) or platinum (Pt) or alloys or laminates of the above materials. On the surface of the first electrode 30 and the second electrode 40 close to the semiconductor structure 20, a metal material with higher reflectivity can be selected to form a mirror to enhance light extraction. Here, the higher reflectivity refers to the active layer The wavelength of the light emitted by 204 has a reflectivity of more than 80%. Metal materials with higher reflectivity include, for example, aluminum (Al) or silver (Ag).

於本申請案另一實施例中，發光元件1不具有電流阻擋層60，第二打線墊401經由透明導電層18之開口18a，與第三半導體層203接觸。In another embodiment of the present application, the light-emitting element 1 does not have the current blocking layer 60, and the second bonding pad 401 contacts the third semiconductor layer 203 through the opening 18a of the transparent conductive layer 18.

於本申請案另一實施例中，電流阻擋層60不具有開口60a，透明導電層18覆蓋電流阻擋層18之部份上表面與側壁，透明導電層18之開口18a暴露出第二打線墊401正下方電流阻擋層60的上表面，使第二打線墊401經由開口18a與電流阻擋層60接觸。第二打線墊401可接觸開口18a側壁之透明導電層18，或者第二打線墊401不接觸開口18a側壁之透明導電層18。In another embodiment of the present application, the current blocking layer 60 does not have an opening 60a, the transparent conductive layer 18 covers part of the upper surface and the side walls of the current blocking layer 18, and the opening 18a of the transparent conductive layer 18 exposes the second bonding pad 401 The upper surface of the current blocking layer 60 directly below makes the second bonding pad 401 contact the current blocking layer 60 via the opening 18a. The second bonding pad 401 may contact the transparent conductive layer 18 on the sidewall of the opening 18a, or the second bonding pad 401 may not contact the transparent conductive layer 18 on the sidewall of the opening 18a.

於本申請案另一實施例中，電流阻擋層60不具有開口60a，透明導電層18覆蓋電流阻擋層18之部份上表面與側壁，透明導電層18之開口18a暴露出位於第二打線墊401正下方電流阻擋層60的上表面及側壁，使第二打線墊401與電流阻擋層60接觸但不與透明導電層18接觸。In another embodiment of the present application, the current blocking layer 60 does not have an opening 60a, the transparent conductive layer 18 covers part of the upper surface and the side wall of the current blocking layer 18, and the opening 18a of the transparent conductive layer 18 is exposed on the second bonding pad The upper surface and the side wall of the current blocking layer 60 directly below 401 make the second bonding pad 401 contact the current blocking layer 60 but not the transparent conductive layer 18.

於本申請案另一實施例中，電流阻擋層60僅設置於第二打線墊401下，而第二延伸電極402下不具有電流阻擋部60。In another embodiment of the present application, the current blocking layer 60 is only disposed under the second bonding pad 401, and the current blocking portion 60 is not provided under the second extension electrode 402.

於本申請案另一實施例中，透明導電層18之開口18a可大於、小於或等於第二打線墊401的寬度。當透明導電層18之開口18a大於第二打線墊401的寬度時，第二打線墊401不接觸透明導電層18。In another embodiment of the present application, the opening 18a of the transparent conductive layer 18 may be greater than, less than, or equal to the width of the second bonding pad 401. When the opening 18 a of the transparent conductive layer 18 is larger than the width of the second bonding pad 401, the second bonding pad 401 does not contact the transparent conductive layer 18.

於本申請案另一實施例中，電流阻擋層60之開口60a可大於、小於或等於透明導電層18之開口18a。In another embodiment of the present application, the opening 60a of the current blocking layer 60 may be greater than, less than, or equal to the opening 18a of the transparent conductive layer 18.

一反射結構(圖未示)可選擇性地設置於基板10之下表面10b，以反射來自半導體結構20之光，增進發光元件1之出光效率。反射結構之材料可為金屬材料，包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)、銠(Rh)或上述材料之合金等。反射結構也可以是布拉格反射鏡(distributed Bragg reflector, DBR)，包含至少兩種以上折射率不同之可透光材料層堆疊而成。布拉格反射結構可為絕緣材料或導電材料，絕緣材料包含但不限於聚亞醯胺(PI)、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、氧化鎂(MgO)、Su8、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、氟碳聚合物(Fluorocarbon Polymer)、玻璃(Glass)、氧化鋁(Al₂ O₃ )、氧化鎂(MgO)、氧化矽(SiO_x )、氧化鈦(TiO₂ )、氧化鉭(Ta₂ O₅ )、氮化矽(SiN_x )、旋塗玻璃(SOG)或四乙氧基矽烷(TEOS)。導電材料包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO) 、氧化鎂(MgO)、砷化鋁鎵(AlGaAs)、氮化鎵(GaN)、磷化鎵(GaP)或氧化銦鋅(IZO)。反射結構也可以是由上述可透光材料層與金屬層所形成之全方向反射鏡(omnidirectional reflector, ODR)。A reflective structure (not shown) can be selectively disposed on the lower surface 10b of the substrate 10 to reflect the light from the semiconductor structure 20 and improve the light emitting efficiency of the light emitting element 1. The material of the reflective structure may be a metallic material, including but not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel ( Ni), platinum (Pt), tungsten (W), rhodium (Rh) or alloys of the above materials. The reflective structure may also be a distributed Bragg reflector (DBR), which is formed by stacking at least two layers of light-transmissive materials with different refractive indexes. The Bragg reflective structure may be an insulating material or a conductive material, and the insulating material includes but is not limited to polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), Su8 , Epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC ), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), glass (Glass), aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), silicon oxide (SiO _x ), titanium oxide ( TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), silicon nitride (SiN _x ), spin-on-glass (SOG) or tetraethoxysilane (TEOS). Conductive materials include but are not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide ( ZTO), Gallium Zinc Oxide (GZO), Zinc Oxide (ZnO), Magnesium Oxide (MgO), Aluminum Gallium Arsenide (AlGaAs), Gallium Nitride (GaN), Gallium Phosphide (GaP) or Indium Zinc Oxide (IZO) . The reflective structure may also be an omnidirectional reflector (ODR) formed by the light-transmitting material layer and the metal layer.

第1D圖繪示第一實施例中變化例B之發光元件1。第一實施例中變化例B之發光元件1與變化例A相似，差別在於，上表面TS1與第一電極30由上視觀之具有相同的寬度、圖案形狀，且上表面TS1的面積與第一電極30的底面積相同。第一電極30與半導體結構20的接觸面包含了第一半導體層201之上表面TS1和側表面LS1，以及第二半導體層202之下部側表面LS2’，而未接觸第二半導體層202之上表面TS2。FIG. 1D illustrates the light-emitting element 1 of Variation B in the first embodiment. The light-emitting element 1 of Variation B in the first embodiment is similar to Variation A, except that the upper surface TS1 and the first electrode 30 have the same width and pattern shape from the top view, and the area of the upper surface TS1 is the same as that of the first The bottom area of one electrode 30 is the same. The contact surface between the first electrode 30 and the semiconductor structure 20 includes the upper surface TS1 and the side surface LS1 of the first semiconductor layer 201, and the lower side surface LS2' of the second semiconductor layer 202 without contacting the second semiconductor layer 202 Surface TS2.

第2A圖為本申請案第二實施例中所揭示之一發光元件2之上視圖的變化例C及D。第2B圖為沿第2A圖中變化例C的B-B’截面之側視圖。第二實施例中之發光元件2與發光元件1相似，差別在於，變化例C中第一半導體層201之上表面TS1由上視觀之為一環狀圖案。相較於發光元件1，發光元件2中第一電極30與第二半導體層202所接觸的第二接觸區域C₂ 面積增加，而與第一半導體層201所接觸的第一接觸區域C₁ 面積減少。FIG. 2A is a variation C and D of a top view of a light-emitting element 2 disclosed in the second embodiment of the present application. FIG. 2B is a side view along the BB′ cross-section of Variation C in FIG. 2A. The light-emitting element 2 in the second embodiment is similar to the light-emitting element 1 except that the upper surface TS1 of the first semiconductor layer 201 in the modification C is a ring-shaped pattern when viewed from above. Increase compared to the light emitting element 1, the light emitting element 2 a first electrode 30 and the second semiconductor layer 202 in contact with the second contact region C ₂ area 201 and the first semiconductor layer in contact with the first contact area of regions C _{1 and} cut back.

變化例D與變化例C相似，差別在於，第一半導體層201之上表面TS1由上視觀之包含了複數個區域；意即，上表面TS1包含環狀圖案區域TS1a，以及一位於環狀圖案區域TS1a內的中間區域TS1b。Variation D is similar to Variation C, except that the upper surface TS1 of the first semiconductor layer 201 includes a plurality of regions from the top view; that is, the upper surface TS1 includes a ring-shaped pattern region TS1a and a ring-shaped region The middle area TS1b in the pattern area TS1a.

第3A圖為本申請案第三實施例中所揭示之一發光元件3之上視圖的變化例E及F。第3B圖為沿變化例E或變化例F的B-B’截面之側視圖。第三實施例中之發光元件3與發光元件1相似，差別在於，由上視觀之，變化例E及F中第一半導體層201之上表面TS1包含互相分離的兩區域TS1’，且此兩區域TS1’被部分的第一半導體層201與第二半導體層202所隔開。因此，於本實施例之上視圖中，兩區域TS1’之間為呈條狀的第二半導體層202之上表面TS2。條狀的第二半導體層202之上表面TS2可如變化例E所示，平行於發光元件3的任一邊緣11，或是如變化例F所示，傾斜於發光元件3的任一邊緣11。FIG. 3A is a variation E and F of a top view of a light-emitting element 3 disclosed in the third embodiment of the present application. Fig. 3B is a side view along the B-B' cross section of Modification E or Modification F. The light-emitting element 3 in the third embodiment is similar to the light-emitting element 1. The difference is that, from a top view, the upper surface TS1 of the first semiconductor layer 201 in Variations E and F includes two regions TS1' separated from each other, and this The two regions TS1' are separated by a portion of the first semiconductor layer 201 and the second semiconductor layer 202. Therefore, in the top view of this embodiment, the upper surface TS2 of the second semiconductor layer 202 in the shape of a strip is between the two regions TS1'. The upper surface TS2 of the strip-shaped second semiconductor layer 202 may be parallel to any edge 11 of the light emitting element 3 as shown in Modification E, or may be inclined to any edge 11 of the light emitting element 3 as shown in Modification F .

第4A圖為本申請案第四實施例中所揭示之一發光元件4之上視圖的變化例G至K。變化例G至K之發光元件4之差異在暴露區28，第一電極30以下的接觸面；暴露區28以外的各層結構皆相同。第4B圖為沿第4A圖中變化例G的B-B’截面之側視圖，第4C圖為沿變化例J的B-B’截面之側視圖。第三實施例中之發光元件3與發光元件1相似，差別在於，由上視觀之，變化例G至K中第一半導體層201之上表面TS1包含互相分離的複數區域TS1’，且此複數區域TS1’被複數條狀的第二半導體層202之上表面TS2所隔開。條狀的第二半導體層202之上表面TS2由上視觀之可如變化例G所示，平行或垂直於發光元件4的側邊11並呈十字交叉狀。FIG. 4A is a variation G to K of a top view of a light-emitting element 4 disclosed in the fourth embodiment of the present application. The difference between the light-emitting elements 4 of the modified examples G to K is the exposed area 28, the contact surface below the first electrode 30; the structure of each layer except the exposed area 28 is the same. Fig. 4B is a side view along the B-B' cross section of the modification G in Fig. 4A, and Fig. 4C is a side view along the B-B' cross section of the modification J. The light-emitting element 3 in the third embodiment is similar to the light-emitting element 1. The difference is that, from a top view, the upper surface TS1 of the first semiconductor layer 201 in the modified examples G to K includes plural regions TS1' separated from each other, and this The plurality of regions TS1' are separated by the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202. The top surface TS2 of the strip-shaped second semiconductor layer 202 is viewed from above, as shown in the modification G, parallel or perpendicular to the side 11 of the light emitting element 4 and in a cross shape.

於本實施例之變化例H中，複數條狀的第二半導體層202之上表面TS2由上視觀之，呈十字交叉並傾斜於發光元件3的側邊11。In Variation H of the present embodiment, the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is viewed from above and crosses and inclines to the side 11 of the light emitting element 3.

於本實施例之變化例I中，複數區域TS1’之數量比變化例H多，複數條狀的第二半導體層202之上表面TS2由上視觀之，呈一「米」字狀，上表面TS1的複數區域TS1’呈放射狀排列。In Variation I of this embodiment, the number of complex regions TS1' is greater than Variation H. The upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is viewed from above, in the shape of a "meter", The plural areas TS1' of the surface TS1 are arranged radially.

於本實施例之變化例J中，複數條狀的第二半導體層202之上表面TS2由上視觀之，呈水平條狀排列，上表面TS1的複數區域TS1’也呈彼此水平條狀排列。於另一變化例中，複數區域TS1’也可呈彼此垂直條狀排列，或是呈彼此平行且傾斜於側邊11的條狀排列。In Variation J of this embodiment, the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is arranged in a horizontal stripe as viewed from above, and the plurality of regions TS1' of the upper surface TS1 are also arranged in a horizontal stripe with each other . In another variation, the plurality of regions TS1' may also be arranged in stripes perpendicular to each other, or in stripes arranged parallel to each other and inclined to the side 11.

於本實施例之變化例K中，複數條狀的第二半導體層202之上表面TS2由上視觀之，呈一柵狀排列，使各第一半導體層201之上表面TS1的複數區域TS1’呈陣列狀排列。In Variation K of this embodiment, the upper surface TS2 of the plurality of strip-shaped second semiconductor layers 202 is arranged in a grid from a top view, so that the plurality of regions TS1 on the upper surface TS1 of each first semiconductor layer 201 'Arranged in an array.

將不同的第一半導體層201及第二半導體層202搭配上述各變化例A-K之發光元件進行實驗，分別與一對照發光元件(圖未示)作參考比較基礎，其中對照發光元件的第一電極僅接觸一單一n型半導體層，各組實驗的較佳結果詳列如表1。在編號1的實驗組中，第一半導體層201為矽摻雜濃度2×10¹⁹ cm^-3 的n型GaN，第二半導體層202為矽摻雜濃度1.3×10¹⁹ cm^-3 的n型GaN，此時第一半導體層201之阻值小於第二半導體層202。搭配變化例A-K之各發光元件及對照發光元件在電流密度為0.5-1.5 A/mm² 操作下，相較對照發光元件的表現，搭配變化例E之發光元件具有較高的光電轉換效率 (Wall Plug Efficiency, WPE) ，WPE較對照發光元件提升1.47%-1.69%。在編號2的實驗組中，第一半導體層201為矽摻雜濃度8×10¹⁸ cm^-3 的n型GaN，第二半導體層202為矽摻雜濃度1.3×10¹⁹ cm^-3 的n型GaN，此時第一半導體層201之阻值大於第二半導體層202。各變化例之發光元件及對照發光元件在電流密度為0.5-1.5 A/mm² 操作下，相較對照發光元件的表現，搭配變化例A之發光元件具有較高的WPE，WPE較對照發光元件提升1.2%；而搭配變化例K之發光元件具有較低的正向電壓(forward voltage, Vf)，Vf較對照發光元件降低0.021-0.037V。在編號3的實驗組中，當第一半導體層201為矽摻雜濃度2×10¹⁹ cm^-3 的n型AlGaN，第二半導體層202為矽摻雜濃度7×10¹⁸ cm^-3 的n型GaN，此時第一半導體層201之阻值小於第二半導體層202。各變化例之發光元件及對照發光元件在電流密度為0.5-1.5 A/mm² 操作下，相較對照發光元件的表現，搭配變化例B之發光元件具有較高的WPE，WPE較對照發光元件提升0.26%-0.41%；而搭配變化例F之發光元件具有較低的Vf，Vf較對照發光元件降低0.002-0.031V。【表一】

Experiments were conducted with different first semiconductor layer 201 and second semiconductor layer 202 in combination with the light-emitting elements of the above-mentioned variations AK, and were compared with a control light-emitting element (not shown), in which the first electrode of the control light-emitting element Only a single n-type semiconductor layer was contacted. The best results of each set of experiments are listed in Table 1. In the experimental group No. 1, the first semiconductor layer 201 is n-type GaN with a silicon doping concentration of 2×10 ¹⁹ cm ^-3 , and the second semiconductor layer 202 is an n-type silicon with a doping concentration of 1.3×10 ¹⁹ cm ^-3 For GaN, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202. Compared with the performance of the comparative light-emitting element, the light-emitting elements of the AK and the control light-emitting element with the variation of AK under the current density of 0.5-1.5 A/mm ² have higher photoelectric conversion efficiency (Wall Plug Efficiency, WPE), WPE increased by 1.47%-1.69% compared to the control light-emitting element. In the experiment group No. 2, the first semiconductor layer 201 is n-type GaN with a silicon doping concentration of 8×10 ¹⁸ cm ^-3 , and the second semiconductor layer 202 is an n-type with a silicon doping concentration of 1.3×10 ¹⁹ cm ^-3 For GaN, the resistance of the first semiconductor layer 201 is greater than that of the second semiconductor layer 202. The light-emitting element and the control light-emitting element of each modification under the operation of the current density of 0.5-1.5 A/mm ² , compared with the performance of the control light-emitting element, the light-emitting element with the modification A has a higher WPE, WPE than the control light-emitting element Increased by 1.2%; and the light-emitting device with variation K has a lower forward voltage (Vf), and Vf is reduced by 0.021-0.037V compared to the control light-emitting device. In the experiment group No. 3, when the first semiconductor layer 201 is n-type AlGaN with a silicon doping concentration of 2×10 ¹⁹ cm ^-3 , the second semiconductor layer 202 is an n-type silicon doping concentration of 7×10 ¹⁸ cm ^-3 Type GaN, the resistance of the first semiconductor layer 201 is smaller than that of the second semiconductor layer 202 at this time. The light-emitting element and the control light-emitting element of each modification under the operation of the current density of 0.5-1.5 A/mm ² , compared with the performance of the control light-emitting element, the light-emitting element with modification B has a higher WPE, WPE than the control light-emitting element Increased by 0.26%-0.41%; and the light-emitting device with Variation F has a lower Vf, which is 0.002-0.031V lower than the control light-emitting device. 【Table I】

第5A圖為本申請案第五實施例中所揭示之一發光元件5之上視圖。第5B圖為沿第5A圖中B-B’截面之側視圖。發光元件5與發光元件1在暴露區28以外之結構相似，因此不再贅述。差別在於，發光元件5之暴露區28設置於發光元件5之一短邊12，並沿一長邊13延伸；且暴露區28上設置了第一電極30，包含第一打線墊301及由第一打線墊301所延伸出的第一延伸電極302。如前述實施例中，除了藉由蝕刻方法在第一打線墊301對應位置的暴露區28內形成第一半導體層201之上表面TS1，更可同時在第一延伸電極302對應位置的暴露區28內也形成上表面TS1。如第5A及5B圖所示，在長邊13方向上的暴露區28內，第一半導體層201之上表面TS1包含複數個分開的區域TS1’，複數區域TS1’沿第一延伸電極302排列。第一延伸電極301與半導體結構20的接觸區域包含第一半導體層201上表面TS1的複數區域TS1’、第一半導體層201的側表面LS1、第二半導體層之上表面TS2以及下部側表面LS2’。FIG. 5A is a top view of a light-emitting element 5 disclosed in the fifth embodiment of the present application. Fig. 5B is a side view taken along the B-B' section in Fig. 5A. The structure of the light-emitting element 5 and the light-emitting element 1 outside the exposed area 28 is similar, and thus will not be described again. The difference is that the exposed area 28 of the light emitting element 5 is disposed on a short side 12 of the light emitting element 5 and extends along a long side 13; and the exposed area 28 is provided with a first electrode 30 including a first wire bonding pad 301 and a A first extended electrode 302 extended from a dozen wire pads 301. As in the previous embodiment, in addition to forming the upper surface TS1 of the first semiconductor layer 201 in the exposed area 28 of the corresponding position of the first bonding pad 301 by the etching method, the exposed area 28 of the corresponding position of the first extended electrode 302 can also be simultaneously The upper surface TS1 is also formed inside. As shown in FIGS. 5A and 5B, in the exposed region 28 in the long side 13 direction, the upper surface TS1 of the first semiconductor layer 201 includes a plurality of divided regions TS1′, and the plurality of regions TS1′ are arranged along the first extension electrode 302 . The contact area between the first extension electrode 301 and the semiconductor structure 20 includes a plurality of regions TS1' of the upper surface TS1 of the first semiconductor layer 201, the side surface LS1 of the first semiconductor layer 201, the upper surface TS2 of the second semiconductor layer, and the lower side surface LS2 '.

本實施例不限於此，暴露區28可設置於半導體結構20內的任何區域，第一電極30可包含一或多個第一延伸電極301，第一半導體層201之上表面TS1可設置於第一打線墊301下方及/或第一延伸電極301下方。This embodiment is not limited to this. The exposed region 28 may be provided in any area within the semiconductor structure 20, the first electrode 30 may include one or more first extension electrodes 301, and the upper surface TS1 of the first semiconductor layer 201 may be provided in the first Below a dozen wire pads 301 and/or below the first extension electrode 301.

如前述實施例中的各發光元件，利用不同阻值的第一半導體層201及第二半導體層202與不同圖案形狀的上表面TS1與TS2之搭配，使第一電極30與不同阻值的第一半導體層201及第二半導體層202間具有不同的接觸面積和接觸形狀，同時，第一電極30與第一半導體層201及第二半導體層202間具有不同的接觸電阻。藉由調整第一電極30與第一半導體層201及第二半導體層202間的接觸方式，使得發光元件具有較低的正向電壓(forward voltage, Vf)。例如，當第一電極30與第一半導體層201及第二半導體層202中具有較低阻值者之間有較大接觸面積時，第一電極30與整體半導體結構20具有較低接觸阻值。As in the light-emitting devices in the foregoing embodiments, the first semiconductor layer 201 and the second semiconductor layer 202 with different resistance values are used in combination with the upper surfaces TS1 and TS2 with different pattern shapes, so that the first electrode 30 and the first The first semiconductor layer 201 and the second semiconductor layer 202 have different contact areas and contact shapes, and at the same time, the first electrode 30 and the first semiconductor layer 201 and the second semiconductor layer 202 have different contact resistances. By adjusting the contact mode between the first electrode 30 and the first semiconductor layer 201 and the second semiconductor layer 202, the light emitting device has a lower forward voltage (forward voltage, Vf). For example, when the first electrode 30 has a larger contact area between the first semiconductor layer 201 and the second semiconductor layer 202 having a lower resistance value, the first electrode 30 and the overall semiconductor structure 20 have a lower contact resistance value .

第6圖為本申請案一實施例中所揭示之一發光裝置6之示意圖。將前述實施例中的發光元件1-5任一安裝於封裝基板51 之第一墊片511、第二墊片512上。第一墊片511、第二墊片512之間藉由一包含絕緣材料之絕緣部53做電性絕緣。倒裝晶片安裝係將與焊墊形成面相對之成長基板側向上設為主要的光取出面。為了增加發光裝置之光取出效率，可於發光元件1之周圍設置一反射結構54。FIG. 6 is a schematic diagram of a light-emitting device 6 disclosed in an embodiment of the application. Any one of the light emitting elements 1-5 in the foregoing embodiment is mounted on the first pad 511 and the second pad 512 of the package substrate 51. The first gasket 511 and the second gasket 512 are electrically insulated by an insulating portion 53 including an insulating material. In flip chip mounting, the side of the growth substrate opposite to the pad forming surface is set as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device, a reflective structure 54 may be provided around the light emitting element 1.

第7圖係為依本發明一實施例之發光裝置7之示意圖。發光裝置7為一球泡燈包括一燈罩602、一反射鏡604、一發光模組610、一燈座612、一散熱片614、一連接部616以及一電連接元件618。發光模組610包含一承載部606，以及複數個發光單元608位於承載部606上，其中複數個發光單元608可為前述實施例中的發光元件1-5任一或發光裝置6。FIG. 7 is a schematic diagram of a light-emitting device 7 according to an embodiment of the invention. The light-emitting device 7 is a bulb lamp including a lamp cover 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616, and an electrical connection element 618. The light emitting module 610 includes a carrying portion 606, and a plurality of light emitting units 608 are located on the carrying portion 606, wherein the plurality of light emitting units 608 may be any of the light emitting elements 1-5 or the light emitting device 6 in the foregoing embodiment.

惟上述實施例僅為例示性說明本申請案之原理及其功效，而非用於限制本申請案。任何本申請案所屬技術領域中具有通常知識者均可在不違背本申請案之技術原理及精神的情況下，對上述實施例進行修改及變化。因此本申請案之權利保護範圍如後述之申請專利範圍所列。However, the above-mentioned embodiments are only illustrative for explaining the principle and effect of the present application, not for limiting the present application. Anyone with general knowledge in the technical field to which this application belongs can modify and change the above embodiments without violating the technical principles and spirit of this application. Therefore, the scope of protection of the rights in this application is listed in the scope of patent applications mentioned later.

1、2、3、4、5‧‧‧發光元件6、7‧‧‧發光裝置10‧‧‧基板10a‧‧‧上表面10b‧‧‧下表面101‧‧‧圖案化結構11‧‧‧側邊12‧‧‧短邊13‧‧‧長邊18‧‧‧透明導電層18a‧‧‧透明導電層之開口20‧‧‧半導體結構201‧‧‧第一半導體層202‧‧‧第二半導體層203‧‧‧第三半導體層204‧‧‧活性層30‧‧‧第一電極301‧‧‧第一打線墊302‧‧‧第一延伸電極40‧‧‧第二電極401‧‧‧第二打線墊402‧‧‧第二延伸電極51‧‧‧封裝基板511‧‧‧第一墊片512‧‧‧第二墊片53‧‧‧絕緣部54‧‧‧反射結構60‧‧‧電流阻擋層60a‧‧‧電流阻擋層之開口602‧‧‧燈罩604‧‧‧反射鏡606‧‧‧承載部608‧‧‧發光單元610‧‧‧發光模組612‧‧‧燈座614‧‧‧散熱片616‧‧‧連接部618‧‧‧電連接元件C₁‧‧‧第一接觸區域C₂‧‧‧第二接觸區域TS1‧‧‧第一半導體層之上表面TS1’‧‧‧複數區域TS2‧‧‧第二半導體層之上表面LS1‧‧‧側表面LS2‧‧‧上部側表面LS2’‧‧‧下部側表面W₁‧‧‧上表面TS1之寬度W_N‧‧‧ 第一電極之寬度1, 2, 3, 4, 5‧‧‧‧Lighting element 6, 7‧‧‧Lighting device 10‧‧‧Substrate 10a‧‧‧Upper surface 10b‧‧‧Lower surface 101‧‧‧Patterned structure 11‧‧‧ Side 12‧‧‧Short side 13‧‧‧Long side 18‧‧‧Transparent conductive layer 18a‧‧‧Opening of transparent conductive layer 20‧‧‧Semiconductor structure 201‧‧‧First semiconductor layer 202‧‧‧Second Semiconductor layer 203‧‧‧third semiconductor layer 204‧‧‧active layer 30‧‧‧first electrode 301‧‧‧first wire bonding pad 302‧‧‧first extension electrode 40‧‧‧second electrode 401‧‧‧ Second wire bonding pad 402‧‧‧Second extension electrode 51‧‧‧Package substrate 511‧‧‧First pad 512‧‧‧Second pad 53‧‧‧Insulation part 54‧‧‧Reflective structure 60‧‧‧ Current blocking layer 60a ‧‧‧ opening of current blocking layer 602 ‧ ‧ ‧ lamp cover 604 ‧ ‧ ‧ reflector 606 ‧ ‧ ‧ bearing part 608 ‧ ‧ ‧ light unit 610 ‧ ‧ ‧ light module 612 ‧ ‧ ‧ lamp holder 614 ‧ ‧‧ Heat sink 616‧‧‧Connecting part 618‧‧‧Electrical connection element C ₁ ‧‧‧ First contact area C ₂ ‧‧‧ Second contact area TS1‧‧‧Top surface of the first semiconductor layer TS1′‧‧ ‧ Complex area TS2‧‧‧ Upper surface LS1 of the second semiconductor layer ‧‧‧ Side surface LS2‧‧‧Upper side surface LS2′‧‧‧Lower side surface W ₁ ‧‧‧Width of upper surface TS1 W _N ‧‧‧ The width of the first electrode

﹝圖1A至圖1D﹞為本申請案一實施例之發光元件1。 ﹝圖2A至圖2B﹞為本申請案另一實施例之發光元件2。 ﹝圖3A至圖3B﹞為本申請案另一實施例之發光元件3。 ﹝圖4A至圖4C﹞為本申請案另一實施例之發光元件4。 ﹝圖5A至圖5B﹞為本申請案另一實施例之發光元件5。 ﹝圖6﹞為本申請案一實施例之發光裝置6。 ﹝圖7﹞為本申請案另一實施例之發光裝置7。﹝ FIGS. 1A to 1D ﹞ is a light-emitting element 1 according to an embodiment of the present application. ﹝ 2A to 2B ﹞ is a light-emitting element 2 of another embodiment of the present application. ﹝ FIGS. 3A to 3B ﹞ is a light-emitting element 3 according to another embodiment of the present application. ﹝ FIGS. 4A to 4C ﹞ are light-emitting elements 4 according to another embodiment of the present application. ﹝ 5A to 5B ﹞ is a light-emitting element 5 of another embodiment of the present application. ﹝Figure 6﹞ is a light-emitting device 6 according to an embodiment of the application. ﹝Figure 7﹞ is a light-emitting device 7 according to another embodiment of the application.

1‧‧‧發光元件 1‧‧‧Lighting element

10‧‧‧基板 10‧‧‧ substrate

10a‧‧‧上表面 10a‧‧‧upper surface

10b‧‧‧下表面 10b‧‧‧Lower surface

101‧‧‧圖案化結構 101‧‧‧patterned structure

18‧‧‧透明導電層 18‧‧‧Transparent conductive layer

18a‧‧‧透明導電層之開口 18a‧‧‧Opening of transparent conductive layer

20‧‧‧半導體結構 20‧‧‧Semiconductor structure

201‧‧‧第一半導體層 201‧‧‧First semiconductor layer

202‧‧‧第二半導體層 202‧‧‧Second semiconductor layer

203‧‧‧第三半導體層 203‧‧‧third semiconductor layer

204‧‧‧活性層 204‧‧‧active layer

30‧‧‧第一電極 30‧‧‧First electrode

40‧‧‧第二電極 40‧‧‧Second electrode

401‧‧‧第二打線墊 401‧‧‧ Second playing pad

402‧‧‧第二延伸電極 402‧‧‧Second extension electrode

60‧‧‧電流阻擋層 60‧‧‧Current blocking layer

60a‧‧‧電流阻擋層之開口 60a‧‧‧Opening of current blocking layer

W₁‧‧‧上表面TS1之寬度 W ₁ ‧‧‧ Upper surface TS1 width

W_N‧‧‧第一電極之寬度 W _N ‧‧‧ The width of the first electrode

Claims

一種發光元件，包含：一第一半導體層；一第二半導體層，位於該第一半導體層上；一第三半導體層，位於該第二半導體層上；一活性層，位於該第二半導體層及該第三半導體層之間；一暴露區，穿過該第三半導體層及該活性層，暴露出該第一半導體層之一第一表面以及該第二半導體層之一第二表面，其中該第一表面包含一第一側表面以及一第一上表面；以及一第一電極，位於該暴露區中，且接觸該第一側表面、該第一上表面及該第二表面；其中，該第一半導體層與該第二半導體層具有不同阻值。 A light-emitting device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; an active layer on the second semiconductor layer And the third semiconductor layer; an exposed region, through the third semiconductor layer and the active layer, exposing a first surface of the first semiconductor layer and a second surface of the second semiconductor layer, wherein The first surface includes a first side surface and a first upper surface; and a first electrode is located in the exposed area and contacts the first side surface, the first upper surface, and the second surface; wherein, The first semiconductor layer and the second semiconductor layer have different resistances.

如申請專利範圍第1項所述的發光元件，其中該第一半導體層與該第二半導體層具有不同摻雜濃度的相同導電性摻雜物。 The light-emitting element according to item 1 of the patent application range, wherein the first semiconductor layer and the second semiconductor layer have the same conductive dopant with different doping concentrations.

如申請專利範圍第2項所述的發光元件，其中該第一半導體層與該第二半導體層包含相同材料。 The light-emitting element as described in item 2 of the patent application range, wherein the first semiconductor layer and the second semiconductor layer contain the same material.

如申請專利範圍第1項所述的發光元件，其中該第一半導體層與該第二半導體層包含不同材料。 The light-emitting element as described in item 1 of the patent application range, wherein the first semiconductor layer and the second semiconductor layer include different materials.

如申請專利範圍第1項所述的發光元件，其中該第一半導體層之厚度大於該第二半導體層之厚度。 The light-emitting element as described in item 1 of the patent application range, wherein the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer.

如申請專利範圍第1項所述的發光元件，其中：該第一上表面包含一第一接觸區域，與該第一電極接觸；以及該第二表面包含一第二側表面以及一第二上表面，其中該第二上表面包含一第二接觸區域，與該第一電極接觸。 The light-emitting element according to item 1 of the patent application scope, wherein: the first upper surface includes a first contact area, which is in contact with the first electrode; and The second surface includes a second side surface and a second upper surface, wherein the second upper surface includes a second contact area, which is in contact with the first electrode.

如申請專利範圍第6項所述的發光元件，其中該第一接觸區域及/或該第二接觸區域由上視觀之包含一圖案，及/或該第一接觸區域之面積與該第二接觸區域之面積不同。 The light-emitting element according to item 6 of the patent application scope, wherein the first contact area and/or the second contact area include a pattern from above, and/or the area of the first contact area and the second The area of the contact area is different.

如申請專利範圍第7項所述的發光元件，其中該圖案包含一條狀、一環狀、或幾何形狀。 The light-emitting element as described in item 7 of the patent application range, wherein the pattern includes a strip, a ring, or a geometric shape.

如申請專利範圍第6項所述的發光元件，其中該第一接觸區域由上視觀之包含複數個第一圖案，且該複數個第一圖案被該第二接觸區域所隔開。 The light-emitting element as described in item 6 of the patent application range, wherein the first contact area includes a plurality of first patterns as viewed from above, and the plurality of first patterns are separated by the second contact area.

如申請專利範圍第1項所述的發光元件，其中，該第一電極與該第一半導體層中及第二半導體層中具有較低阻值者之間有較大接觸面積。 The light-emitting element according to item 1 of the patent application scope, wherein the first electrode has a larger contact area between the first semiconductor layer and the second semiconductor layer having a lower resistance value.