下文中，將參照圖示詳細地描述本發明之示例性實施例，已使得本發明領域技術人員能夠充分地理解本發明之精神。本發明並不限於以下之實施例，而是可以以其他形式實施。在本說明書中，有一些相同的符號，其表示具有相同或是類似之結構、功能、原理的元件，且為業界具有一般知識能力者可以依據本說明書之教導而推知。為說明書之簡潔度考量，相同之符號的元件將不再重述。Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings, so that those skilled in the art of the present invention can fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some same symbols, which indicate elements with the same or similar structure, function, and principle, and those with general knowledge in the industry can infer it based on the teaching of this specification. For the sake of simplicity in the description, the elements with the same symbols will not be repeated.
圖1A顯示本申請案一實施例發光元件1之上視圖。圖2A至圖2H顯示本申請案一實施例發光元件1製造方法中各階段之上視圖；圖3A至圖3F顯示發光元件1製造方法中各階段之截面圖。發光元件1之製造方法詳述如下。首先，參照圖2A，在基板10上方形成半導體疊層12，以及在半導體疊層12上形成下部保護層23a。接著，參照圖2B，在半導體疊層12上形成及透明導電層18。圖3A顯示圖2A及圖2B之步驟完成後，沿A-A’線段之截面圖。基板10可以是一晶圓片，與形成於其上的半導體疊層12構成一半導體晶圓。半導體晶圓在後續切割製程後分離成複數個發光元件1，以下的實施例圖示及說明將以單一個發光元件1做代表。FIG. 1A shows a top view of a light-emitting element 1 according to an embodiment of the present application. FIGS. 2A to 2H show top views of various stages in the manufacturing method of the light-emitting device 1 according to an embodiment of the present application; FIGS. 3A to 3F show cross-sectional views of various stages in the manufacturing method of the light-emitting device 1. The method of manufacturing the light-emitting element 1 is described in detail below. First, referring to FIG. 2A, a semiconductor stack 12 is formed over the substrate 10, and a lower protective layer 23a is formed on the semiconductor stack 12. Next, referring to FIG. 2B, a transparent conductive layer 18 is formed on the semiconductor stack 12. Fig. 3A shows a cross-sectional view along the line A-A' after the steps of Fig. 2A and Fig. 2B are completed. The substrate 10 may be a wafer, and the semiconductor stack 12 formed thereon constitutes a semiconductor wafer. The semiconductor wafer is separated into a plurality of light-emitting elements 1 after the subsequent dicing process. The following embodiment illustrations and descriptions will use a single light-emitting element 1 as a representative.
基板10可以是一成長基板，包括用於生長磷化鎵銦(AlGaInP)的砷化鎵(GaAs)基板、及磷化鎵(GaP)基板，或用於生長氮化銦鎵(InGaN)或氮化鋁鎵(AlGaN)的藍寶石(Al2
O3
)基板，氮化鎵(GaN)基板，碳化矽(SiC)基板、及氮化鋁(AlN)基板。基板10包含一上表面10a。基板10可以是一圖案化基板，即，基板10在其上表面10a上具有圖案化結構(圖未示)。於一實施例中，從半導體疊層12發射的光可以被基板10的圖案化結構所折射，從而提高發光元件的亮度。此外，圖案化結構減緩或抑制了基板10與半導體疊層12之間因晶格不匹配而導致的錯位，從而改善半導體疊層12的磊晶品質。The substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) substrate used to grow indium gallium phosphide (AlGaInP), and a gallium phosphide (GaP) substrate, or used to grow indium gallium nitride (InGaN) or nitrogen. Aluminum gallium (AlGaN) sapphire (Al 2 O 3 ) substrates, gallium nitride (GaN) substrates, silicon carbide (SiC) substrates, and aluminum nitride (AlN) substrates. The substrate 10 includes an upper surface 10a. The substrate 10 may be a patterned substrate, that is, the substrate 10 has a patterned structure on its upper surface 10a (not shown). In one embodiment, the light emitted from the semiconductor stack 12 may be refracted by the patterned structure of the substrate 10, thereby improving the brightness of the light-emitting element. In addition, the patterned structure slows down or suppresses the misalignment between the substrate 10 and the semiconductor stack 12 caused by lattice mismatch, thereby improving the epitaxial quality of the semiconductor stack 12.
在本申請案的一實施例中，在基板10上形成半導體疊層12的方法包含有機金屬化學氣相沉積(MOCVD)、分子束磊晶法(MBE)、氫化物氣相磊晶(HVPE)或離子鍍，例如濺鍍或蒸鍍等。In an embodiment of the present application, the method for forming the semiconductor stack 12 on the substrate 10 includes metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE). Or ion plating, such as sputtering or evaporation.
依序在基板10上形成一緩衝結構(圖未示)、第一半導體層121、活性層123和第二半導體層122。緩衝結構、第一半導體層121、活性層123和第二半導體層122構成半導體疊層12。緩衝結構可減小上述的晶格不匹配並抑制錯位，從而改善磊晶品質。緩衝層的材料包括GaN、AlGaN或AlN。在一實施例中，緩衝結構包括多個子層(圖未示)。子層包括相同材料或不同材料。在一實施例中，緩衝結構包括兩個子層，其中第一子層的生長方式為濺鍍，第二子層的生長方式為MOCVD。在一實施例中，緩衝層另包含第三子層。其中第三子層的生長方式為MOCVD，第二子層的生長溫度高於或低於第三子層的生長溫度。於一實施例中，第一、第二及第三子層包括相同的材料，例如AlN，或不同材料，例如AN、GaN、AlGaN。在本申請案的一實施例中，第一半導體層121和第二半導體層122，例如為包覆層(cladding layer)或侷限層(confinement layer)，具有不同的導電型態、電性、極性或用於提供電子或電洞的摻雜元素。例如，第一半導體層121是n型半導體，以及第二半導體層122是p型半導體。活性層123形成於第一半導體層121與第二半導體層122之間。電子與電洞在電流驅動下在活性層123中結合，將電能轉換成光能以發光。可藉由改變半導體疊層12中一個或多個層別的物理特性和化學組成，來調整發光元件1或半導體疊層12所發出的光之波長。A buffer structure (not shown), a first semiconductor layer 121, an active layer 123 and a second semiconductor layer 122 are sequentially formed on the substrate 10. The buffer structure, the first semiconductor layer 121, the active layer 123 and the second semiconductor layer 122 constitute the semiconductor stack 12. The buffer structure can reduce the above-mentioned lattice mismatch and inhibit dislocation, thereby improving the quality of epitaxial crystals. The material of the buffer layer includes GaN, AlGaN or AlN. In one embodiment, the buffer structure includes a plurality of sub-layers (not shown). The sub-layers include the same material or different materials. In an embodiment, the buffer structure includes two sub-layers, wherein the growth method of the first sub-layer is sputtering, and the growth method of the second sub-layer is MOCVD. In one embodiment, the buffer layer further includes a third sub-layer. The growth method of the third sub-layer is MOCVD, and the growth temperature of the second sub-layer is higher or lower than the growth temperature of the third sub-layer. In one embodiment, the first, second, and third sublayers include the same material, such as AlN, or different materials, such as AN, GaN, and AlGaN. In an embodiment of the present application, the first semiconductor layer 121 and the second semiconductor layer 122, for example, a cladding layer or a confinement layer, have different conductivity types, electrical properties, and polarities. Or doping elements used to provide electrons or holes. For example, the first semiconductor layer 121 is an n-type semiconductor, and the second semiconductor layer 122 is a p-type semiconductor. The active layer 123 is formed between the first semiconductor layer 121 and the second semiconductor layer 122. The electrons and holes are combined in the active layer 123 under the current drive to convert electrical energy into light energy to emit light. The wavelength of the light emitted by the light-emitting element 1 or the semiconductor stack 12 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 12.
半導體疊層12的材料包括Alx
Iny
Ga(1-x-y)
N或Alx
Iny
Ga(1-x-y)
P的III-V族半導體材料，其中0≤x，y≤1；x+y≤1。根據活性層的材料，當半導體疊層12的材料是AlInGaP系列時，可以發出波長介於610nm和650nm之間的紅光或波長介於550nm和570nm之間的黃光。當半導體疊層12的材料是InGaN系列時，可以發出波長介於400nm和490nm之間的藍光或深藍光或波長介於490nm和550nm之間的綠光。當半導體疊層12的材料是AlGaN系列時，可以發出波長介於400nm和250nm之間的UV光。活性層123可以是單異質結構(single heterostructure; SH)、雙異質結構(double heterostructure; DH)、雙面雙異質結構(double-side double heterostructure; DDH)、多重量子井(multi-quantum well; MQW)。活性層123的材料可以是i型、p型或n型半導體。The material of the semiconductor stack 12 includes a III-V semiconductor material of Al x In y Ga (1-xy) N or Al x In y Ga (1-xy) P, where 0≤x, y≤1; x+y ≤1. According to the material of the active layer, when the material of the semiconductor stack 12 is AlInGaP series, it can emit red light with a wavelength between 610 nm and 650 nm or yellow light with a wavelength between 550 nm and 570 nm. When the material of the semiconductor stack 12 is the InGaN series, it can emit blue or deep blue light with a wavelength between 400 nm and 490 nm or green light with a wavelength between 490 nm and 550 nm. When the material of the semiconductor stack 12 is AlGaN series, UV light with a wavelength between 400 nm and 250 nm can be emitted. The active layer 123 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). ). The material of the active layer 123 may be an i-type, p-type, or n-type semiconductor.
接著，實施一暴露區28形成步驟。參見圖3A，在此步驟中，由第二半導體層122的上表面往下移除部分的活性層123及第一半導體層121，露出第一半導體層121的上表面121a，形成暴露區28。參見圖2A，相對於暴露區28，其他區域的半導體疊層12形成一高台MS。於本實施例中，暴露區28包含位於半導體疊層12之周圍環繞半導體疊層12的環繞區域以及分佈在半導體疊層12內的內部區域。各暴露區28包含由半導體疊層12側表面所形成的側壁以及由第一半導體層121的上表面121a所形成的底部。然後，於一實施例中，再進一步移除位於半導體疊層12的周圍，環繞區域外的部分第一半導體層121，露出基板上表面10a，形成走道區ISO。走道區ISO分隔並定義出複數個發光單元1，並做為後續切割製程中預備分割線(圖未示)的所在位置。於一實施例中，如圖2A所示，高台MS的輪廓呈波浪狀、鋸齒狀、方波狀或其他非直線的圖案，藉由高台MS輪廓的圖案設計可提高發光元件1的光取出效率。Next, a step of forming the exposed region 28 is performed. Referring to FIG. 3A, in this step, a portion of the active layer 123 and the first semiconductor layer 121 are removed from the upper surface of the second semiconductor layer 122 to expose the upper surface 121a of the first semiconductor layer 121 to form an exposed area 28. Referring to FIG. 2A, with respect to the exposed region 28, the semiconductor stack 12 in other regions forms a plateau MS. In this embodiment, the exposed area 28 includes a surrounding area surrounding the semiconductor stack 12 and an inner area distributed in the semiconductor stack 12. Each exposed region 28 includes a sidewall formed by the side surface of the semiconductor stack 12 and a bottom formed by the upper surface 121 a of the first semiconductor layer 121. Then, in one embodiment, the part of the first semiconductor layer 121 located around the semiconductor stack 12 and outside the surrounding area is further removed to expose the upper surface 10a of the substrate to form the walkway area ISO. The aisle area ISO separates and defines a plurality of light-emitting units 1, and is used as the location of the preparatory dividing line (not shown) in the subsequent cutting process. In one embodiment, as shown in FIG. 2A, the contour of the plateau MS is wavy, zigzag, square wave or other non-linear patterns, and the light extraction efficiency of the light-emitting element 1 can be improved by the pattern design of the contour of the plateau MS .
接著，同樣參照圖2A及圖3A，形成下部保護層23a在暴露區28上。下部保護層23a覆蓋暴露區28的底部、側壁以及部分的第二半導體層122。下部保護層23a相對於半導體疊層12所發出的光線為透明，其材料為非導電材料，包含有機材料或無機材料。其中有機材料包含Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、聚醯亞胺(Polyimide)或氟碳聚合物(Fluorocarbon Polymer)。無機材料包含例如矽膠(Silicone)、玻璃(Glass)或是介電材料，介電材料例如為氧化矽(SiNx
)、氮化矽(SiNx
)、氧氮化矽(SiOx
Ny
)、氧化鈮(Nb2
O5
)、氧化鉿(HfO2
)、氧化鈦(TiOx
)、氟化鎂(MgF2
)、氧化鋁(Al2
O3
)等。下部保護層23a的形成方式包含原子沉積法(Atomic Layer Deposition, ALD)、濺鍍(sputtering)、蒸鍍(evaporation)及旋塗(spin-coating)等方式。於另一實施例中，在半導體疊層12的周圍，下部保護層23a更覆蓋第一半導體層121的側壁。Next, referring also to FIGS. 2A and 3A, a lower protective layer 23a is formed on the exposed region 28. The lower protective layer 23a covers the bottom, sidewalls and part of the second semiconductor layer 122 of the exposed region 28. The lower protective layer 23a is transparent to the light emitted by the semiconductor stack 12, and its material is a non-conductive material, including organic or inorganic materials. Among them, organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethacrylic acid Methyl ester (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide or fluorocarbon polymer . The inorganic material includes, for example, silicone (Silicone), glass (Glass) or a dielectric material, a dielectric material such as silicon oxide (SiN x), silicon nitride (SiN x), silicon oxynitride (SiO x N y), Niobium oxide (Nb 2 O 5 ), hafnium oxide (HfO 2 ), titanium oxide (TiO x ), magnesium fluoride (MgF 2 ), aluminum oxide (Al 2 O 3 ), etc. The formation method of the lower protective layer 23a includes Atomic Layer Deposition (ALD), sputtering, evaporation, and spin-coating. In another embodiment, around the semiconductor stack 12, the lower protection layer 23a further covers the sidewall of the first semiconductor layer 121.
為了清楚顯示發光元件1製造方法中各階段之上視圖，圖2B至圖2H僅繪示高台MS、當下步驟所形成的層別，或是更繪示當下步驟之前一步驟所形成的層別。In order to clearly show the top views of each stage in the manufacturing method of the light-emitting element 1, FIGS. 2B to 2H only show the high stage MS, the layer formed in the current step, or more show the layer formed in the step before the current step.
在下部保護層23a形成後，參照圖2B及圖3A，實施一透明導電層18形成步驟。圖2B僅繪示高台MS及透明導電層18。透明導電層18覆蓋第二半導體層122之上表面，並與第二半導體層122電性接觸，包含開口180對應形成在暴露區28上。透明導電層18可以是金屬或是透明導電材料，其中金屬可選自具有透光性的薄金屬層，透明導電材料對於活性層123所發出的光線為透明，包含石墨烯、銦錫氧化物(ITO)、氧化鋁鋅(AZO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)或銦鋅氧化物(IZO)等材料。於一實施例中，透明導電層18覆蓋部分的下部保護層23a。於另一實施例中。透明導電層18不覆蓋下部保護層23a。於另一實施例中，可以先形成透明導電層18，再形成下部保護層23a。After the lower protective layer 23a is formed, referring to FIG. 2B and FIG. 3A, a step of forming the transparent conductive layer 18 is performed. FIG. 2B only shows the plateau MS and the transparent conductive layer 18. The transparent conductive layer 18 covers the upper surface of the second semiconductor layer 122 and is in electrical contact with the second semiconductor layer 122, and includes an opening 180 correspondingly formed on the exposed region 28. The transparent conductive layer 18 can be a metal or a transparent conductive material, where the metal can be selected from a thin metal layer with translucency. The transparent conductive material is transparent to the light emitted by the active layer 123, and includes graphene, indium tin oxide ( Materials such as ITO), aluminum oxide zinc (AZO), gallium zinc oxide (GZO), zinc oxide (ZnO) or indium zinc oxide (IZO). In one embodiment, the transparent conductive layer 18 covers a portion of the lower protective layer 23a. In another embodiment. The transparent conductive layer 18 does not cover the lower protective layer 23a. In another embodiment, the transparent conductive layer 18 may be formed first, and then the lower protective layer 23a may be formed.
接著，參照圖2C、圖3B及圖3C，實施一第一反射結構50形成步驟。圖3B顯示圖2A至圖2C之步驟完成後，沿A-A’線段之截面圖。圖2C僅繪示高台MS及第一反射結構50。先在第二半導體層122的上表面形成第一反射結構50，然後以顯影蝕刻等製程，在第一反射結構50中形成相互分離的開孔501及502。開孔501的位置對應於暴露區28及透明導電層開孔180，開孔502分佈在第二半導體層122上，並暴露其下方的透明導電層18。Next, referring to FIG. 2C, FIG. 3B, and FIG. 3C, a step of forming a first reflective structure 50 is performed. Fig. 3B shows a cross-sectional view along the line A-A' after the steps of Fig. 2A to Fig. 2C are completed. FIG. 2C only shows the high station MS and the first reflective structure 50. First, the first reflective structure 50 is formed on the upper surface of the second semiconductor layer 122, and then the openings 501 and 502 separated from each other are formed in the first reflective structure 50 by a process such as development and etching. The position of the opening 501 corresponds to the exposed area 28 and the transparent conductive layer opening 180. The openings 502 are distributed on the second semiconductor layer 122 and expose the transparent conductive layer 18 underneath.
於一實施例中，第6A圖顯示第一反射結構50的一截面局部放大圖，第一反射結構50由一對或複數對不同折射率的材料交互堆疊所形成。於本實施例中，如第5A圖所示，第一反射結構50包含一組材料疊層，例如為介電材料，由第一子層50a及第二子層50b交互堆疊所組成。一第一子層50a及一第二子層50b組成一介電材料對。第一子層50a相較於第二子層50b具有較高的折射率，於一實施例中，第一子層50a相較於第二子層50b具有較小的厚度。介電材料包括例如氧化矽、氮化矽、氧氮化矽、氧化鈮、氧化鉿、氧化鈦、氟化鎂、氧化鋁等。藉由不同折射率材料的選擇搭配其厚度設計堆疊成材料疊層構成第一反射結構50，對特定波長範圍的光線提供反射功能，例如為一分佈式布拉格反射器(DBR, distributed Bragg reflector)。In one embodiment, FIG. 6A shows a partial enlarged view of a cross-section of the first reflective structure 50. The first reflective structure 50 is formed by alternately stacking a pair or a plurality of pairs of materials with different refractive indexes. In this embodiment, as shown in FIG. 5A, the first reflective structure 50 includes a set of material stacks, such as a dielectric material, which is composed of a first sub-layer 50a and a second sub-layer 50b alternately stacked. A first sub-layer 50a and a second sub-layer 50b form a pair of dielectric materials. The first sublayer 50a has a higher refractive index than the second sublayer 50b. In one embodiment, the first sublayer 50a has a smaller thickness than the second sublayer 50b. The dielectric material includes, for example, silicon oxide, silicon nitride, silicon oxynitride, niobium oxide, hafnium oxide, titanium oxide, magnesium fluoride, aluminum oxide, and the like. The first reflective structure 50 is formed by stacking materials with different refractive index materials and thickness design to form a stack of materials, which provides a reflection function for light in a specific wavelength range, such as a distributed Bragg reflector (DBR).
於一實施例中，第一反射結構50更可包含第一子層50a及第二子層50b以外的其他層。例如，第一反射結構50更包含一底層(圖未示)位於第一子層50a(及/或第二子層50b)與半導體疊層12之間。也就是說，先於半導體疊層12上形成底層，接著再形成第一子層50a及第二子層50b。底層為非導電材料，包含有機材料或無機材料，其中無機材料可以是介電材料。底層的厚度大於第一子層50a及第二子層50b的厚度。於一實施例中，底層之形成方式與第一子層50a及第二子層50b不同，例如，底層之形成方式為化學汽相沉積(Chemical Vapor Deposition, CVD)，更佳地，藉由電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)來形成。第一子層50a及第二子層50b之形成方式為濺鍍。In one embodiment, the first reflective structure 50 may further include other layers than the first sublayer 50a and the second sublayer 50b. For example, the first reflective structure 50 further includes a bottom layer (not shown) between the first sublayer 50a (and/or the second sublayer 50b) and the semiconductor stack 12. That is, the bottom layer is formed on the semiconductor stack 12 first, and then the first sublayer 50a and the second sublayer 50b are formed. The bottom layer is a non-conductive material, including organic material or inorganic material, where the inorganic material can be a dielectric material. The thickness of the bottom layer is greater than the thickness of the first sublayer 50a and the second sublayer 50b. In one embodiment, the formation method of the bottom layer is different from the first sub-layer 50a and the second sub-layer 50b. For example, the formation method of the bottom layer is Chemical Vapor Deposition (CVD). It is formed by plasma enhanced chemical vapor deposition (PECVD). The first sub-layer 50a and the second sub-layer 50b are formed by sputtering.
於另一實施例中，如第6B圖所示，第一反射結構50包含複數組材料疊層，第一組材料疊層由第一子層50a及第二子層50b交互堆疊所組成，第二組材料疊層由第三子層50c及第四子層50d交互堆疊所組成。於一實施例中，第二組材料疊層例如為介電材料，由一第三子層50c及一第四子層50d組成一介電材料對。第三子層50c相較於第四子層50d具有較高的折射率，於一實施例中，第三子層50c相較於第四子層50d具有較小的厚度。第三子層50c與第一子層50a具有不同厚度，第三子層50c與第一子層50a可以是相同材料或不同材料。第四子層50d與第二子層50b具有不同厚度，第四子層50d與第二子層50b可以是相同材料或不同材料。In another embodiment, as shown in FIG. 6B, the first reflective structure 50 includes a plurality of stacks of materials. The first set of material stacks is composed of a first sub-layer 50a and a second sub-layer 50b alternately stacked. The two sets of material stacks consist of alternate stacking of the third sub-layer 50c and the fourth sub-layer 50d. In one embodiment, the second set of material stacks are, for example, dielectric materials, and a third sub-layer 50c and a fourth sub-layer 50d form a dielectric material pair. The third sub-layer 50c has a higher refractive index than the fourth sub-layer 50d. In one embodiment, the third sub-layer 50c has a smaller thickness than the fourth sub-layer 50d. The third sublayer 50c and the first sublayer 50a have different thicknesses, and the third sublayer 50c and the first sublayer 50a may be the same material or different materials. The fourth sublayer 50d and the second sublayer 50b have different thicknesses, and the fourth sublayer 50d and the second sublayer 50b may be the same material or different materials.
於另一實施例中，第一反射結構50更可包含一上層(圖未示)位於第一子層50a(及/或第二子層50b)上，相對第二半導體層122之另一側。也就是說，先於半導體疊層12上形成第一子層50a及第二子層50b，接著再形成上層。上層為非導電材料，包含有機材料或無機材料，其中無機材料可以是介電材料。上層的厚度大於第一子層50a及第二子層50b的厚度。於一實施例中，上層之形成方式與第一子層50a及第二子層50b不同，例如，上層之形成方式為化學汽相沉積，更佳地，藉由電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)來形成。第一子層50a及第二子層50b之形成方式為濺鍍。In another embodiment, the first reflective structure 50 may further include an upper layer (not shown) on the first sub-layer 50a (and/or the second sub-layer 50b) opposite to the other side of the second semiconductor layer 122 . That is, the first sublayer 50a and the second sublayer 50b are formed on the semiconductor stack 12 first, and then the upper layer is formed. The upper layer is a non-conductive material, including organic material or inorganic material, where the inorganic material can be a dielectric material. The thickness of the upper layer is greater than the thicknesses of the first sublayer 50a and the second sublayer 50b. In one embodiment, the method of forming the upper layer is different from that of the first sublayer 50a and the second sublayer 50b. For example, the method of forming the upper layer is chemical vapor deposition, and more preferably, plasma-assisted chemical vapor deposition ( plasma enhanced chemical vapor deposition, PECVD). The first sub-layer 50a and the second sub-layer 50b are formed by sputtering.
於另一實施例中，第一反射結構50包含複數組材料疊層與底層及/或上層。於另一實施例中，於形成第一反射結構50之前，藉由原子沉積法於基板10及半導體疊層20之一表面上形成一緻密層(圖未示)以直接披覆半導體疊層12之表面。於一實施例中，介由緻密層可更緻密的覆蓋填補半導體疊層12之表面缺陷，避免水氣的侵入。緻密層的材料包含無機材料，例如氧化矽、氧化鋁、氧化鉿、氧化鉭、氧化鋯、氧化釔、氧化鑭、氧化鉭、氮化矽、氮化鋁或氮氧化矽。於本實施例中，緻密層與半導體疊層12相接之介面包含金屬元素及氧，其中金屬元素包含鋁、鉿、鉭、鋯、釔、鑭或鉭。緻密層包含一厚度介於50 Å~2000 Å之間，較佳介於100 Å ~1500 Å之間。In another embodiment, the first reflective structure 50 includes a plurality of material stacks and a bottom layer and/or an upper layer. In another embodiment, before forming the first reflective structure 50, a uniform dense layer (not shown) is formed on one surface of the substrate 10 and the semiconductor stack 20 by atomic deposition to directly cover the semiconductor stack 12的面。 The surface. In one embodiment, the dense layer can more densely cover and fill the surface defects of the semiconductor stack 12 to avoid the intrusion of moisture. The material of the dense layer includes inorganic materials, such as silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, yttrium oxide, lanthanum oxide, tantalum oxide, silicon nitride, aluminum nitride, or silicon oxynitride. In this embodiment, the interface between the dense layer and the semiconductor stack 12 includes metal elements and oxygen, where the metal elements include aluminum, hafnium, tantalum, zirconium, yttrium, lanthanum, or tantalum. The dense layer includes a thickness between 50 Å and 2000 Å, preferably between 100 Å and 1500 Å.
於一實施例中，第一反射結構50的厚度介於0.3 μm至 6 μm。於一實施例中，第一反射結構50的側壁，例如開口501、502的側壁與透明導電層18的內夾角介於5度至80度。In one embodiment, the thickness of the first reflective structure 50 is between 0.3 μm and 6 μm. In one embodiment, the inner angle between the sidewalls of the first reflective structure 50, such as the sidewalls of the openings 501 and 502, and the transparent conductive layer 18 is between 5 degrees and 80 degrees.
於一實施例中，第一反射結構50在相鄰開口501之間不具有開口502。In one embodiment, the first reflective structure 50 does not have an opening 502 between adjacent openings 501.
於另一實施例中，第一反射結構50並非如圖2C具有複數個開口501、502，而是以複數個分開的島狀(圖未示)分佈於第二半導體層122上。In another embodiment, the first reflective structure 50 does not have a plurality of openings 501 and 502 as shown in FIG. 2C, but is distributed on the second semiconductor layer 122 in the shape of a plurality of separated islands (not shown).
接著，參照圖2D及圖3C，實施一第二反射結構36形成步驟。圖3C顯示圖2A至圖2D之步驟完成後，沿A-A’線段之截面圖。圖2D僅繪示高台MS及第二反射結構36。第二反射結構36對應形成於透明導電層18及第一反射結構50 上，其經由第一反射結構50的開口502與透明導電層18及第二半導體層122電性連接，且包含複數個開口360對應於第一反射結構50的開口501，形成在暴露區28上。第二反射結構36包含一金屬結構，可包含單層金屬或是由複數層金屬所形成之疊層。於一實施例中，第二反射結構36包含阻障層(圖未示)及反射層(圖未示)，阻障層形成並覆蓋於反射層上，阻障層可以防止反射層之金屬元素的遷移、擴散或氧化。反射層的材料包含對於半導體疊層12 所發射的光線具有高反射率的金屬材料，例如銀(Ag)、金(Au)、鋁(Al)、鈦(Ti)、鉻(Cr)、銅(Cu)、鎳(Ni)、鉑(Pt)、釕(Ru)或上述材料之合金或疊層。阻障層的材料包括鉻(Cr)、鉑(Pt)、鈦(Ti)、鎢(W)、鋅(Zn) 或上述材料之合金或疊層。於一實施例中，當阻障層為金屬疊層時，阻障層係由兩層或兩層以上的金屬交替堆疊而形成，例如Cr/Pt，Cr/Ti，Cr/TiW，Cr/W，Cr/Zn，Ti/Pt，Ti/W，Ti/TiW，Ti/Zn，Pt/TiW，Pt/W，Pt/Zn，TiW/W，TiW/Zn，或W/Zn等。於另一實施例中(圖未示)，第一反射結構50包含複數個島狀分佈於第二半導體層122上，第二反射結構36經由島狀之間的間隙與透明導電層18及第二半導體層122電性連接。Next, referring to FIGS. 2D and 3C, a step of forming a second reflective structure 36 is performed. Fig. 3C shows a cross-sectional view along the line A-A' after the steps in Fig. 2A to Fig. 2D are completed. FIG. 2D only shows the high station MS and the second reflective structure 36. The second reflective structure 36 is correspondingly formed on the transparent conductive layer 18 and the first reflective structure 50, and is electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122 through the opening 502 of the first reflective structure 50, and includes a plurality of openings 360 corresponds to the opening 501 of the first reflective structure 50 and is formed on the exposed area 28. The second reflective structure 36 includes a metal structure, which may include a single layer of metal or a stack of multiple layers of metal. In one embodiment, the second reflective structure 36 includes a barrier layer (not shown) and a reflective layer (not shown). The barrier layer is formed and covers the reflective layer. The barrier layer can prevent metal elements in the reflective layer. The migration, diffusion or oxidation of particles. The material of the reflective layer includes a metal material with high reflectivity for the light emitted by the semiconductor stack 12, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper ( Cu), nickel (Ni), platinum (Pt), ruthenium (Ru) or alloys or laminates of the above materials. The material of the barrier layer includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or laminates of the above materials. In one embodiment, when the barrier layer is a metal stack, the barrier layer is formed by alternately stacking two or more layers of metal, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr/W , Cr/Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc. In another embodiment (not shown), the first reflective structure 50 includes a plurality of islands distributed on the second semiconductor layer 122, and the second reflective structure 36 is connected to the transparent conductive layer 18 and the first semiconductor layer through the gaps between the islands. The two semiconductor layers 122 are electrically connected.
接著，參照圖2E及圖3D，實施一上部保護層23b形成步驟。圖3D顯示圖2A至圖2E之步驟完成後，沿A-A’線段之截面圖。圖2E僅繪示高台MS、第二反射結構36及上部保護層23b。上部保護層23b形成在第二反射結構36上，覆蓋部分第二反射結構36之上表面，並且覆蓋下部保護層23a。在暴露區28以及暴露區28附近，上部保護層23b與下部保護層23a相疊且連接。Next, referring to FIGS. 2E and 3D, a step of forming the upper protective layer 23b is performed. Fig. 3D shows a cross-sectional view along the line A-A' after the steps of Fig. 2A to Fig. 2E are completed. FIG. 2E only shows the plateau MS, the second reflective structure 36 and the upper protective layer 23b. The upper protective layer 23b is formed on the second reflective structure 36, covers part of the upper surface of the second reflective structure 36, and covers the lower protective layer 23a. In the exposed area 28 and the vicinity of the exposed area 28, the upper protective layer 23b and the lower protective layer 23a overlap and are connected.
上部保護層23b包含開口230、231以及232。參照圖2E，複數個開口230間隔地設置於上部保護層23b的周圍，露出半導體疊層12周圍暴露區28的底部，也就是第一半導體層上表面121a，其功能及對應截面結構將詳述如後。複數個開口231設置於半導體疊層12內部的暴露區28，露出暴露區28的底部的第一半導體層上表面121a。開口232露出第二反射結構36，於本實施例中僅繪示單一個開口232，然而本發明不限於此，上部保護層23b可包含複數個開口232分別暴露第二反射結構36。於一實施例中，先形成一絕緣材料覆蓋第二反射結構36及暴露區28，接著再利用顯影蝕刻等方式形成開口230、231及232，以形成上部保護層23b。在形成開口230、231的同時，也移除了開口230、231正下方的下部保護層23a。上部保護層23b與下部保護層23a構成一第一保護層23，上部保護層23b與下部保護層23a可為相同材料或不同材料。也就是說，第一保護層23具有複數個開口230間隔地設置於其周圍，露出第一半導體層上表面121a，以及複數個開口231設置於半導體疊層12內部的暴露區28，露出第一半導體層上表面121a。上部保護層23b相對於半導體疊層12所發出的光線為透明，其材料為非導電材料，包含有機材料或無機材料。其中有機材料包含Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醯亞胺(Polyimide)、聚醚醯亞胺(Polyetherimide)或氟碳聚合物(Fluorocarbon Polymer)。無機材料包含矽膠(Silicone)、玻璃(Glass)或是介電材料。介電材料例如為氧化矽(SiNx
)、氮化矽(SiNx
)、氧氮化矽(SiOx
Ny
)、氧化鈮(Nb2
O5
)、氧化鉿(HfO2
)、氧化鈦(TiOx
)、氟化鎂(MgF2
)、氧化鋁(Al2
O3
)等。下部保護層23a的形成方式包含原子沉積法(Atomic Layer Deposition, ALD)、濺鍍(sputtering)、蒸鍍(evaporation)及旋塗(spin-coating)等方式。由於第一保護層23覆蓋暴露區28的側壁，也就是半導體疊層12的側壁，可以保護半導體疊層12，避免在後續製程中可能破壞半導體疊層12。於另一實施例中，在半導體疊層12的周圍，上部保護層23b更覆蓋第一半導體層121的側壁。The upper protective layer 23b includes openings 230, 231, and 232. 2E, a plurality of openings 230 are arranged at intervals around the upper protective layer 23b, exposing the bottom of the exposed area 28 around the semiconductor stack 12, that is, the upper surface 121a of the first semiconductor layer. The function and corresponding cross-sectional structure will be described in detail As after. A plurality of openings 231 are provided in the exposed area 28 inside the semiconductor stack 12 to expose the upper surface 121 a of the first semiconductor layer at the bottom of the exposed area 28. The opening 232 exposes the second reflective structure 36. In this embodiment, only a single opening 232 is shown. However, the present invention is not limited to this. The upper protective layer 23b may include a plurality of openings 232 to respectively expose the second reflective structure 36. In one embodiment, an insulating material is first formed to cover the second reflective structure 36 and the exposed area 28, and then the openings 230, 231, and 232 are formed by developing and etching to form the upper protective layer 23b. While forming the openings 230 and 231, the lower protective layer 23a directly under the openings 230 and 231 is also removed. The upper protective layer 23b and the lower protective layer 23a constitute a first protective layer 23, and the upper protective layer 23b and the lower protective layer 23a may be the same material or different materials. That is, the first protection layer 23 has a plurality of openings 230 arranged around it at intervals, exposing the upper surface 121a of the first semiconductor layer, and a plurality of openings 231 are arranged in the exposed area 28 inside the semiconductor stack 12, exposing the first The upper surface of the semiconductor layer 121a. The upper protective layer 23b is transparent to the light emitted by the semiconductor stack 12, and its material is a non-conductive material, including organic materials or inorganic materials. Among them, organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethacrylic acid Methyl ester (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyimide, polyetherimide or fluorocarbon polymer . Inorganic materials include silicone, glass or dielectric materials. Dielectric material, for example, silicon oxide (SiN x), silicon nitride (SiN x), silicon oxynitride (SiO x N y), niobium oxide (Nb 2 O 5), hafnium oxide (HfO 2), titanium oxide ( TiO x ), magnesium fluoride (MgF 2 ), alumina (Al 2 O 3 ), etc. The formation method of the lower protective layer 23a includes Atomic Layer Deposition (ALD), sputtering, evaporation, and spin-coating. Since the first protection layer 23 covers the sidewalls of the exposed region 28, that is, the sidewalls of the semiconductor stack 12, it can protect the semiconductor stack 12 and avoid possible damage to the semiconductor stack 12 in the subsequent manufacturing process. In another embodiment, around the semiconductor stack 12, the upper protective layer 23b further covers the sidewall of the first semiconductor layer 121.
接著，參照圖2F及圖3E，實施一電極形成步驟。圖3E顯示圖2A至圖2F之步驟完成後，沿A-A’線段之截面圖。圖2F僅繪示高台MS、上部保護層23b及電極。電極包含第一電極20以及第二電極30，其中第一電極20覆蓋上部保護層23b，經由上部保護層23b的開口230及231，接觸暴露區28底部的第一半導體層121並與其形成電性連接。第二電極30與第一電極20相互分離，形成在上部保護層23b的開口232中，接觸第二反射結構36並與第二半導體層122電性連接。電極包含金屬材料，例如鋁(Al)、鉻(Cr)、鉑(Pt)、鈦(Ti)、鎢(W)、鋅(Zn) 或上述材料之合金或疊層。Next, referring to FIG. 2F and FIG. 3E, an electrode forming step is performed. Fig. 3E shows a cross-sectional view along the line A-A' after the steps of Fig. 2A to Fig. 2F are completed. FIG. 2F only shows the plateau MS, the upper protective layer 23b and the electrodes. The electrodes include a first electrode 20 and a second electrode 30. The first electrode 20 covers the upper protective layer 23b, and contacts the first semiconductor layer 121 at the bottom of the exposed region 28 through the openings 230 and 231 of the upper protective layer 23b and forms electrical conductivity therewith. connect. The second electrode 30 and the first electrode 20 are separated from each other, are formed in the opening 232 of the upper protective layer 23 b, contact the second reflective structure 36 and are electrically connected to the second semiconductor layer 122. The electrode includes a metal material, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or laminates of the foregoing materials.
接著，參照圖2G，實施一第二保護層形成步驟。參照圖2H，實施一焊墊形成步驟。圖3F顯示圖2A至圖2G之步驟完成後，沿A-A’線段之截面圖。圖2G僅繪示高台MS、第一電極20、第二電極30及第二保護層25。Next, referring to FIG. 2G, a second protective layer forming step is performed. Referring to FIG. 2H, a pad formation step is performed. Fig. 3F shows a cross-sectional view along the line A-A' after the steps of Fig. 2A to Fig. 2G are completed. FIG. 2G only shows the plateau MS, the first electrode 20, the second electrode 30, and the second protective layer 25.
第二保護層25形成在第一電極20、第二電極30以及暴露區28上，並延伸覆蓋第一半導體層121的側壁及走道區ISO。第二保護層25包含開口251以及252，其中，開口251露出第一電極20，開口251露出第二電極30。於本實施例中僅繪示單一個開口251及單一個開口252，然而本發明不限於此，上部保護層23b可包含複數個開口251及開口252。第二保護層25的材料包括為非導電材料，包含有機材料或無機材料。其中有機材料包含Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、聚醯亞胺(Polyimide)或氟碳聚合物(Fluorocarbon Polymer)。無機材料包含矽膠(Silicone)、玻璃(Glass)或是介電材料，介電材料例如為氧化矽(SiNx
)、氮化矽(SiNx
)、氧氮化矽(SiOx
Ny
)、氧化鈮(Nb2
O5
)、氧化鉿(HfO2
)、氧化鈦(TiOx
)、氟化鎂(MgF2
)、氧化鋁(Al2
O3
)等。於一實施例中，第二保護層25由一對或複數對不同折射率的材料交互堆疊所形成，藉由不同折射率材料的選擇搭配其厚度設計，第二保護層25形成一反射結構，對特定波長範圍的光線提供反射功能，例如為一分佈式布拉格反射器。於一實施例中，類似於第一反射結構50，第二保護層25包含一組或複數組材料疊層，與底層及/或上層。於一實施例中，具有分佈式布拉格反射器的第二保護層25覆蓋半導體疊層12位於走道區ISO的側壁，有利於走道區ISO附近的光摘出，增進發光元件1的亮度。於一實施例中，具有分佈式布拉格反射器的第二保護層25包含m對介電材料對，第一反射結構50包含n對介電材料對，其中m大於n。於一實施例中，第二保護層的厚度大於第一反射結構50的厚度。The second protection layer 25 is formed on the first electrode 20, the second electrode 30, and the exposed area 28, and extends to cover the sidewall of the first semiconductor layer 121 and the passage area ISO. The second protection layer 25 includes openings 251 and 252, wherein the opening 251 exposes the first electrode 20, and the opening 251 exposes the second electrode 30. In this embodiment, only a single opening 251 and a single opening 252 are shown, but the present invention is not limited to this, and the upper protective layer 23b may include a plurality of openings 251 and openings 252. The material of the second protective layer 25 includes non-conductive materials, including organic materials or inorganic materials. Among them, organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethacrylic acid Methyl ester (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide or fluorocarbon polymer . The inorganic material comprises silicone (Silicone), glass (Glass) or a dielectric material, a dielectric material such as silicon oxide (SiN x), silicon nitride (SiN x), silicon oxynitride (SiO x N y), oxide Niobium (Nb 2 O 5 ), hafnium oxide (HfO 2 ), titanium oxide (TiO x ), magnesium fluoride (MgF 2 ), aluminum oxide (Al 2 O 3 ), etc. In one embodiment, the second protective layer 25 is formed by alternately stacking a pair or a plurality of pairs of materials with different refractive indexes. Through the selection of different refractive index materials and the thickness design, the second protective layer 25 forms a reflective structure. It provides a reflection function for light in a specific wavelength range, such as a distributed Bragg reflector. In one embodiment, similar to the first reflective structure 50, the second protective layer 25 includes a stack or multiple stacks of materials, and a bottom layer and/or an upper layer. In one embodiment, the second protective layer 25 with the distributed Bragg reflector covers the sidewall of the semiconductor stack 12 located in the walkway area ISO, which facilitates the extraction of light near the walkway area ISO and improves the brightness of the light emitting element 1. In one embodiment, the second protective layer 25 with a distributed Bragg reflector includes m pairs of dielectric materials, and the first reflective structure 50 includes n pairs of dielectric materials, where m is greater than n. In one embodiment, the thickness of the second protective layer is greater than the thickness of the first reflective structure 50.
於一實施例中，第二保護層25的厚度可爲1 μm 至6 μm。若第二保護層25的厚度小於1 μm，較薄的厚度可能會使得第二保護層25 的絕緣性和抗濕性變弱，降低發光元件1的可靠度。於一實施例中，第二保護層25的厚度大於上部保護層23b的厚度。In one embodiment, the thickness of the second protection layer 25 may be 1 μm to 6 μm. If the thickness of the second protective layer 25 is less than 1 μm, the thinner thickness may weaken the insulation and moisture resistance of the second protective layer 25 and reduce the reliability of the light-emitting element 1. In one embodiment, the thickness of the second protective layer 25 is greater than the thickness of the upper protective layer 23b.
接著，參照圖2H，在開口251及252內分別形成第一焊墊80a及第二焊墊80b。圖2H僅繪示高台MS、第一電極20、第二電極30、第二保護層25及焊墊。第一焊墊80a與第一電極20相接，和第一半導體層121形成電性連接。第二焊墊80b與第二電極30相接，和第二半導體層122形成電性連接。第一焊墊80a及第二焊墊80b包含金屬材料，例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)等金屬或上述材料之疊層或合金。第一焊墊80a及第二焊墊80b可由單個層或是多個層所組成。例如，第一焊墊80a及第二焊墊80b可包括Ti/Au、Ti/Pt/Au、Cr/Au、Cr/Pt/Au、Ni/Au、Ni/Pt/Au或Cr/Al/Cr/Ni/Au。在後續切割(dicing)製程完成並形成獨立的發光元件1後，第一焊墊80a及第二焊墊80b以覆晶的方式和一載板(圖未示)上的電路接合，以達到和外部電子元件或外部電源的連接。於另一實施例中，第一焊墊80a及/或第二焊墊80b更可覆蓋於第二保護層25上。於另一實施例中，第一焊墊80a及/或第二焊墊80b可避開暴露區28分佈在半導體疊層12內的內部區域，以避免因高低差造成焊墊與半導體疊層12之間各層介面可能產生的剝離。第一焊墊80a及第二焊墊80b之表面有對應第一反射結構50之開口502形成的複數個凹部(圖未示)，介由該些凹部，於後續封裝製程中，可提升焊墊與載板之間的接合力，以提升製程良率。Next, referring to FIG. 2H, a first pad 80a and a second pad 80b are formed in the openings 251 and 252, respectively. FIG. 2H only shows the plateau MS, the first electrode 20, the second electrode 30, the second protective layer 25 and the bonding pad. The first bonding pad 80 a is connected to the first electrode 20 and forms an electrical connection with the first semiconductor layer 121. The second bonding pad 80 b is connected to the second electrode 30 and forms an electrical connection with the second semiconductor layer 122. The first pad 80a and the second pad 80b include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn) , Nickel (Ni), platinum (Pt) and other metals or laminates or alloys of the above materials. The first bonding pad 80a and the second bonding pad 80b may be composed of a single layer or multiple layers. For example, the first bonding pad 80a and the second bonding pad 80b may include Ti/Au, Ti/Pt/Au, Cr/Au, Cr/Pt/Au, Ni/Au, Ni/Pt/Au, or Cr/Al/Cr /Ni/Au. After the subsequent dicing process is completed and the independent light-emitting element 1 is formed, the first bonding pad 80a and the second bonding pad 80b are connected to a circuit on a carrier board (not shown) in a flip chip manner to achieve harmony Connection of external electronic components or external power supply. In another embodiment, the first solder pad 80a and/or the second solder pad 80b may further cover the second protective layer 25. In another embodiment, the first bonding pad 80a and/or the second bonding pad 80b can avoid the exposed area 28 and are distributed in the internal area of the semiconductor stack 12 to avoid the difference in height between the bonding pad and the semiconductor stack 12 The possible peeling of the interface between each layer. The surfaces of the first solder pad 80a and the second solder pad 80b have a plurality of recesses (not shown) formed corresponding to the opening 502 of the first reflective structure 50. Through these recesses, the solder pad can be lifted in the subsequent packaging process The bonding force between the carrier and the substrate to improve the process yield.
最後，沿著走道區ISO，也就是各發光元件1的周圍，將半導體晶圓分割形成複數個發光元件1。於一實施例中，如圖3F所示，用雷射27照射基板10的下表面，雷射27聚焦於基板10內部，使基板10內部形成變質區(圖未示)，再自變質區沿著基板10的晶面形成裂痕將各發光元件1分割開來。惟本實施例的切割方式並不限於此，任何其他適用於將晶圓切割成發光元件的方法，亦可適用。Finally, along the aisle area ISO, that is, around each light-emitting element 1, the semiconductor wafer is divided to form a plurality of light-emitting elements 1. In one embodiment, as shown in FIG. 3F, a laser 27 is used to irradiate the lower surface of the substrate 10, and the laser 27 is focused on the inside of the substrate 10 to form a metamorphic zone (not shown) inside the substrate 10. Cracks are formed on the crystal plane of the substrate 10 to separate the light-emitting elements 1. However, the cutting method of this embodiment is not limited to this, and any other method suitable for cutting the wafer into light-emitting elements is also applicable.
於一實施例中，圖4A至圖4C顯示發光元件1製造方法中於圖2A至圖2E之步驟中沿A-A”之部份截面圖。圖4A顯示形成下部保護層23a、透明導電層18與第一反射結構50材料層於半導體疊層12上。其中，下部保護層23a在暴露區28上的厚度為t1。接著，參照圖4B，以蝕刻的方式在第一反射結構50材料層中形成開口501及502，移除暴露區28上方的第一反射結構50材料層。其中，蝕刻包含乾蝕刻，例如為感應耦合核電漿(inductively coupled plasma，ICP)蝕刻。於一實施例中，蝕刻包含乾蝕刻搭配濕蝕刻。在蝕刻第一反射結構50材料層以形成開口502時，由於透明導電層18覆蓋第二半導體層122，所以第二半導體層122不會因蝕刻而造成損傷。在蝕刻第一反射結構50材料層以形成開口501以及移除暴露區28上方的第一反射結構50材料層時，由於下部保護層23a覆蓋暴露區28，所以暴露區28底部的第一半導體層121不會因蝕刻而造成損傷。蝕刻第一反射結構50之步驟完成後，位於暴露區28的下部保護層23a具有厚度t1’。其中厚度t1’大於 100 Å且厚度t1’小於厚度t1。藉由下部保護層23a覆蓋暴露區28以保護第一半導體層121，可以確保第一反射結構50的開口501可被完全打開，暴露區28上方不殘留其材料層，又可確保第一半導體層121不受損傷。於另一實施中，並非所有暴露區28上的第一反射結構50材料層被移除，而是僅位於半導體疊層12內部區域的暴露區28上的第一反射結構50材料層被移除。In one embodiment, FIGS. 4A to 4C show partial cross-sectional views along AA" in the steps of FIGS. 2A to 2E in the manufacturing method of the light-emitting element 1. FIG. 4A shows the formation of the lower protective layer 23a, the transparent conductive layer 18, and The material layer of the first reflective structure 50 is on the semiconductor stack 12. The thickness of the lower protective layer 23a on the exposed area 28 is t1. Next, referring to FIG. 4B, the material layer of the first reflective structure 50 is formed in an etching manner The openings 501 and 502 are used to remove the material layer of the first reflective structure 50 above the exposed region 28. The etching includes dry etching, such as inductively coupled plasma (ICP) etching. In one embodiment, etching includes Dry etching and wet etching. When etching the material layer of the first reflective structure 50 to form the opening 502, since the transparent conductive layer 18 covers the second semiconductor layer 122, the second semiconductor layer 122 will not be damaged by the etching. When a reflective structure 50 material layer is used to form the opening 501 and the first reflective structure 50 material layer above the exposed area 28 is removed, since the lower protective layer 23a covers the exposed area 28, the first semiconductor layer 121 at the bottom of the exposed area 28 will not Damage caused by etching. After the step of etching the first reflective structure 50 is completed, the lower protective layer 23a located in the exposed area 28 has a thickness t1'. The thickness t1' is greater than 100 Å and the thickness t1' is less than the thickness t1. By the lower protection The layer 23a covers the exposed area 28 to protect the first semiconductor layer 121, which can ensure that the opening 501 of the first reflective structure 50 can be fully opened, and no material layer remains on the exposed area 28, and can ensure that the first semiconductor layer 121 is not damaged. In another implementation, not all the material layers of the first reflective structure 50 on the exposed regions 28 are removed, but only the material layers of the first reflective structure 50 on the exposed regions 28 of the inner region of the semiconductor stack 12 are removed. remove.
接著，參照圖4C，依序形成第二反射結構36、上部保護層23b以及上部保護層的開口231、232及230(未繪示於圖4C)。上部保護層23b與下部保護層23a構成第一保護層23。在暴露區28以及暴露區28附近的第二半導體層122上，上部保護層23b疊加在下部保護層23a，並與其相接。在形成開口230、231的同時，也移除了開口230、231正下方的下部保護層23a。也就是說，第一保護層23具有複數個開口230間隔地設置於其周圍，露出第一半導體層上表面121a，以及複數個開口231設置於半導體疊層12內部的暴露區28，露出第一半導體層上表面121a。在暴露區28底部上方的第一保護層23之厚度(即，位於暴露區28的下部保護層23a的厚度t1’與上部保護層23b的厚度之總和)為T，在第二半導體層122上的第一保護層23之厚度(即，位於此處的下部保護層23a厚度與上部保護層23b厚度之總和)為T’， T小於T’。於一實施例中，T與T’之差值大於2000 Å。於另一實施例中，T與T’之差值大於3000 Å。於一實施例中，位於暴露區28的下部保護層23a的厚度t1’，小於位於第二半導體層122上表面的下部保護層23a的厚度t1。接著，依照前述圖2F至圖2H中的步驟，完成發光元件1。Next, referring to FIG. 4C, the second reflective structure 36, the upper protective layer 23b, and the openings 231, 232, and 230 of the upper protective layer are sequentially formed (not shown in FIG. 4C). The upper protective layer 23b and the lower protective layer 23a constitute the first protective layer 23. On the exposed region 28 and the second semiconductor layer 122 near the exposed region 28, the upper protective layer 23b is superimposed on the lower protective layer 23a and is in contact with it. While the openings 230 and 231 are formed, the lower protective layer 23a directly under the openings 230 and 231 is also removed. That is, the first protection layer 23 has a plurality of openings 230 arranged at intervals around it, exposing the upper surface 121a of the first semiconductor layer, and a plurality of openings 231 are arranged in the exposed area 28 inside the semiconductor stack 12, exposing the first The upper surface 121a of the semiconductor layer. The thickness of the first protective layer 23 above the bottom of the exposed region 28 (ie, the sum of the thickness t1' of the lower protective layer 23a and the thickness of the upper protective layer 23b located in the exposed region 28) is T, on the second semiconductor layer 122 The thickness of the first protective layer 23 (that is, the sum of the thickness of the lower protective layer 23a and the thickness of the upper protective layer 23b located here) is T', and T is less than T'. In one embodiment, the difference between T and T'is greater than 2000 Å. In another embodiment, the difference between T and T'is greater than 3000 Å. In one embodiment, the thickness t1' of the lower protective layer 23a located in the exposed region 28 is smaller than the thickness t1 of the lower protective layer 23a located on the upper surface of the second semiconductor layer 122. Next, according to the steps in FIGS. 2F to 2H described above, the light-emitting element 1 is completed.
圖5A及圖5B分別顯示圖2A至圖2F之步驟完成後，沿B-B’線段及C-C’線段之截面圖。參照圖2F及圖5A，第一電極20接觸第一保護層23的開口230所暴露出的第一半導體疊層上表面121a。參照圖2F及圖5B，在沒有開口230的地方，第一保護層23覆蓋半導體疊層12周圍的暴露區28，使第一電極20不接觸第一半導體疊層上表面121a。如此一來，在半導體疊層12周圍，第一電極20經由間隔設置的開口230，間隔地接觸第一半導體疊層上表面121a，使電流在半導體疊層12的周圍均勻擴散。Figures 5A and 5B respectively show cross-sectional views along the line B-B' and the line C-C' after the steps of Figure 2A to Figure 2F are completed. 2F and 5A, the first electrode 20 contacts the upper surface 121a of the first semiconductor stack exposed by the opening 230 of the first protection layer 23. 2F and 5B, where there is no opening 230, the first protective layer 23 covers the exposed area 28 around the semiconductor stack 12 so that the first electrode 20 does not contact the upper surface 121a of the first semiconductor stack. In this way, around the semiconductor stack 12, the first electrode 20 contacts the upper surface 121a of the first semiconductor stack at intervals through the openings 230 arranged at intervals, so that the current is uniformly diffused around the semiconductor stack 12.
圖1A顯示依本實施例製造方法所製作的發光元件1之上視圖，圖1B顯示圖1A中沿A-A’線段之截面圖，圖1C顯示圖1B中之局部放大圖。Fig. 1A shows a top view of a light-emitting device 1 manufactured according to the manufacturing method of this embodiment, Fig. 1B shows a cross-sectional view along the line A-A' in Fig. 1A, and Fig. 1C shows a partial enlarged view of Fig. 1B.
參照圖1A、圖1B及圖1C，發光元件1包含基板10、半導體疊層12位於基板上10、暴露區28位於半導體疊層12的周圍及內部區域，暴露出第一半導體層上表面121a、透明導電層18位於第二半導體層122上、第一反射結構50位於透明導電層18上，包含複數個開口502暴露出透明導電層18、第二反射結構36位於第一反射結構50上，經由第一反射結構開口502與透明導電層18及第二半導體層122電性連接。第二反射結構36與第一反射結構50形成一全方位反射鏡(omnidirectional reflector，ODR)，增進光的反射及發光元件1的亮度。第一保護層23覆蓋暴露區28，並延伸覆蓋部分該第二半導體層122的上表面。第一保護層23包含下部保護層23a及上部半導體層23b。其中，下部保護層23a接觸半導體疊層12，更詳言之，下部保護層23a接觸暴露區28側壁及部分底部，上部保護層23b自暴露區28延伸至覆蓋第二反射結構36，包含開口232暴露第二反射結構36。此外，第一保護層23包含開口231位於半導體疊層12內部區域的暴露區28，暴露出第一半導體層上表面121a。於一實施例中，第一保護層23更包含開口230位於半導體疊層12周圍的暴露區28，暴露出第一半導體層上表面121a。在暴露區28底部上方的第一保護層23之厚度為T，在第二半導體層122上的第一保護層23之厚度為T’， T小於T’。 於一實施例中，T與T’之差值大於2000 Å。於另一實施例中，T與T’之差值大於3000 Å。1A, 1B, and 1C, the light-emitting element 1 includes a substrate 10, a semiconductor stack 12 on the substrate 10, and an exposed area 28 located around and inside the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer, The transparent conductive layer 18 is located on the second semiconductor layer 122, the first reflective structure 50 is located on the transparent conductive layer 18, and includes a plurality of openings 502 exposing the transparent conductive layer 18, and the second reflective structure 36 is located on the first reflective structure 50 through The first reflective structure opening 502 is electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122. The second reflective structure 36 and the first reflective structure 50 form an omnidirectional reflector (ODR) to improve the reflection of light and the brightness of the light-emitting element 1. The first protection layer 23 covers the exposed area 28 and extends to cover part of the upper surface of the second semiconductor layer 122. The first protective layer 23 includes a lower protective layer 23a and an upper semiconductor layer 23b. Wherein, the lower protective layer 23a contacts the semiconductor stack 12. In more detail, the lower protective layer 23a contacts the sidewalls and part of the bottom of the exposed region 28, and the upper protective layer 23b extends from the exposed region 28 to cover the second reflective structure 36 and includes an opening 232 The second reflective structure 36 is exposed. In addition, the first protection layer 23 includes an exposed area 28 with an opening 231 located in the inner region of the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer. In one embodiment, the first protection layer 23 further includes an exposed area 28 with an opening 230 located around the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer. The thickness of the first protective layer 23 above the bottom of the exposed region 28 is T, and the thickness of the first protective layer 23 on the second semiconductor layer 122 is T', and T is less than T'. In one embodiment, the difference between T and T'is greater than 2000 Å. In another embodiment, the difference between T and T'is greater than 3000 Å.
第一電極20覆蓋第一保護層23上，經由第一保護層開口231及230與第一半導體層121電性連接。第二電極30與第一電極20相互分離，經由上部保護層開口232接觸第二反射結構36，與第二半導體層122電性連接。於一實施例中，第二電極30位於上部保護層開口232中。於另一實施例中，第二電極30位於上部保護層開口232中更延伸至上部保護層23b上。第二保護層25位於第一電極20與第二電極30上，包含開口251暴露第一電極20與開口252暴露第二電極30。如圖1B所示，第二保護層25更覆蓋半導體疊層12周圍的側壁及基板上表面10a。於一實施例中，第二保護層25包含分佈式布拉格反射結構，可以增加光在半導體疊層12周圍的反射，增進發光元件1亮度。第一焊墊80a位於開口251，並接觸第一電極20。第二焊墊80b位於開口252，並接觸第二電極30。The first electrode 20 covers the first protection layer 23 and is electrically connected to the first semiconductor layer 121 through the first protection layer openings 231 and 230. The second electrode 30 and the first electrode 20 are separated from each other, contact the second reflective structure 36 through the upper protective layer opening 232, and are electrically connected to the second semiconductor layer 122. In one embodiment, the second electrode 30 is located in the upper protective layer opening 232. In another embodiment, the second electrode 30 is located in the upper protective layer opening 232 and extends to the upper protective layer 23b. The second protection layer 25 is located on the first electrode 20 and the second electrode 30, and includes an opening 251 to expose the first electrode 20 and an opening 252 to expose the second electrode 30. As shown in FIG. 1B, the second protection layer 25 further covers the sidewalls around the semiconductor stack 12 and the upper surface 10a of the substrate. In one embodiment, the second protective layer 25 includes a distributed Bragg reflection structure, which can increase the reflection of light around the semiconductor stack 12 and improve the brightness of the light-emitting element 1. The first bonding pad 80 a is located in the opening 251 and contacts the first electrode 20. The second bonding pad 80 b is located in the opening 252 and contacts the second electrode 30.
圖1A顯示本申請案一實施例發光元件2之上視圖。圖7A至圖7I顯示本申請案一實施例發光元件2製造方法中各階段之上視圖；圖8A至圖8G顯示發光元件2製造方法中各階段之截面圖。發光元件2之製造方法詳述如下。發光元件2之部分製程及結構和發光元件1類似，類似的製程及結構請參考發光元件1之說明及圖式，不再贅述，後續將針對差異處詳細說明。首先，參照圖7A至圖7B及圖8A，其步驟如圖2A至圖2B及圖3A說明所述，故於此不再贅述。FIG. 1A shows a top view of a light-emitting element 2 according to an embodiment of the present application. FIGS. 7A to 7I show top views of various stages in the manufacturing method of the light-emitting device 2 according to an embodiment of the present application; FIGS. 8A to 8G show cross-sectional views of various stages in the manufacturing method of the light-emitting device 2. The manufacturing method of the light-emitting element 2 is described in detail below. Part of the manufacturing process and structure of the light-emitting element 2 is similar to that of the light-emitting element 1. For the similar manufacturing process and structure, please refer to the description and drawings of the light-emitting element 1, which will not be repeated here. The differences will be described in detail later. First, referring to FIG. 7A to FIG. 7B and FIG. 8A, the steps are described in FIGS. 2A to 2B and FIG. 3A, so they will not be repeated here.
接著，參照圖7C及圖8B，實施一蝕刻停止層26形成步驟。圖8B顯示圖7A至圖7C之步驟完成後，沿A-A’線段之截面圖。圖7C僅繪示高台MS、透明導電層18及蝕刻停止層26。先在透明導電層18的上表面形成蝕刻停止材料層(未圖示)，然後以顯影蝕刻或掀離(lift-off)等製程，在透明導電層18的上表面形成蝕刻停止層26。蝕刻停止層26為複數個彼此分離的島狀結構。Next, referring to FIGS. 7C and 8B, an etching stop layer 26 formation step is performed. Fig. 8B shows a cross-sectional view along the line A-A' after the steps of Figs. 7A to 7C are completed. FIG. 7C only shows the plateau MS, the transparent conductive layer 18 and the etch stop layer 26. First, an etching stop material layer (not shown) is formed on the upper surface of the transparent conductive layer 18, and then the etching stop layer 26 is formed on the upper surface of the transparent conductive layer 18 by a process such as development etching or lift-off. The etch stop layer 26 is a plurality of island-shaped structures separated from each other.
於一實施例中，蝕刻停止層26包含一金屬，金屬材料包含對發光元件2發出的光有高反射率的反射金屬，例如銀(Ag)、金(Au)、鋁(Al)、鈦(Ti)、鉻(Cr)、銅(Cu)、鎳(Ni)、鉑(Pt)、釕(Ru)或上述材料之合金或疊層。In one embodiment, the etching stop layer 26 includes a metal, and the metal material includes a reflective metal with high reflectivity to the light emitted by the light-emitting element 2, such as silver (Ag), gold (Au), aluminum (Al), and titanium ( Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru) or alloys or laminates of the above materials.
於一實施例中，蝕刻停止層26包含屏障層(圖未示)及接觸層(圖未示)，接觸層位於透明導電層18及屏障層之間，屏障層可以防止接觸層之金屬元素的遷移、擴散或氧化。接觸層的材料包含對於半導體疊層12 所發射的光線具有高反射率的金屬材料，例如銀(Ag)、金(Au)、鋁(Al)、鈦(Ti)、鉻(Cr)、銅(Cu)、鎳(Ni)、鉑(Pt)、釕(Ru)或上述材料之合金或疊層。屏障層的材料包括鉻(Cr)、鉑(Pt)、鈦(Ti)、鎢(W)、鋅(Zn) 或上述材料之合金或疊層。於一實施例中，當屏障層為金屬疊層時，屏障層係由兩層或兩層以上的金屬交替堆疊而形成，例如Cr/Pt，Cr/Ti，Cr/TiW，Cr/W，Cr/Zn，Ti/Pt，Ti/W，Ti/TiW，Ti/Zn，Pt/TiW，Pt/W，Pt/Zn，TiW/W，TiW/Zn，或W/Zn等。In one embodiment, the etch stop layer 26 includes a barrier layer (not shown) and a contact layer (not shown). The contact layer is located between the transparent conductive layer 18 and the barrier layer. The barrier layer can prevent the metal elements of the contact layer from deteriorating. Migration, diffusion or oxidation. The material of the contact layer includes a metal material with high reflectivity for the light emitted by the semiconductor stack 12, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper ( Cu), nickel (Ni), platinum (Pt), ruthenium (Ru) or alloys or laminates of the above materials. The material of the barrier layer includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or laminates of the above materials. In one embodiment, when the barrier layer is a metal laminate, the barrier layer is formed by alternately stacking two or more layers of metal, such as Cr/Pt, Cr/Ti, Cr/TiW, Cr/W, Cr /Zn, Ti/Pt, Ti/W, Ti/TiW, Ti/Zn, Pt/TiW, Pt/W, Pt/Zn, TiW/W, TiW/Zn, or W/Zn, etc.
接著，參照圖7D及圖8C，實施一第一反射結構50形成步驟。圖8C顯示圖7A至圖7D之步驟完成後，沿A-A’線段之截面圖。圖7D僅繪示高台MS及第一反射結構50。先在第二半導體層122的上表面形成一反射材料層，然後以顯影蝕刻等製程，在反射材料層中形成相互分離的開孔501及502後以形成第一反射結構50。開孔501的位置對應於暴露區28及透明導電層開孔180，開孔502分佈在第二半導體層122上，並暴露其下方的蝕刻停止層26。第一反射結構50的材料、疊層、厚度及形成方法等，如圖6A至圖6B說明所述，故於此不再贅述。Next, referring to FIGS. 7D and 8C, a step of forming a first reflective structure 50 is performed. Fig. 8C shows a cross-sectional view along the line A-A' after the steps of Figs. 7A to 7D are completed. FIG. 7D only shows the high station MS and the first reflective structure 50. First, a reflective material layer is formed on the upper surface of the second semiconductor layer 122, and then by a process such as development and etching, the openings 501 and 502 separated from each other are formed in the reflective material layer to form the first reflective structure 50. The position of the opening 501 corresponds to the exposed area 28 and the transparent conductive layer opening 180. The openings 502 are distributed on the second semiconductor layer 122 and expose the etching stop layer 26 below it. The material, stack, thickness, and forming method of the first reflective structure 50 are as described in the description of FIGS. 6A to 6B, so they will not be repeated here.
於一實施例中，蝕刻停止層26包含被開孔502暴露的中央部分及與第一反射結構50重疊的邊緣部分，在顯影蝕刻第一反射結構50時，可能會過蝕刻至蝕刻停止層26的中央部分，而使得蝕刻停止層26的中央部分之厚度小於蝕刻停止層26的邊緣部分。In one embodiment, the etching stop layer 26 includes a central part exposed by the opening 502 and an edge part overlapping with the first reflective structure 50. When the first reflective structure 50 is developed and etched, the etching stop layer 26 may be over-etched. The thickness of the central part of the etching stop layer 26 is smaller than the edge part of the etching stop layer 26.
接著，參照圖7E及圖8D，實施一第二反射結構36形成步驟。圖8D顯示圖7A至圖7E之步驟完成後，沿A-A’線段之截面圖。圖7E僅繪示高台MS及第二反射結構36。第二反射結構36對應形成於透明導電層18、蝕刻停止層26及第一反射結構50 上，其經由第一反射結構50的開口502與蝕刻停止層26、透明導電層18及第二半導體層122電性連接，且包含複數個開口360對應於第一反射結構50的開口501，形成在暴露區28上。第二反射結構36包含一金屬結構，可包含單一金屬層或是由複數金屬層所形成之疊層。於一實施例中，第二半導體層122於基板10上之投影面積與第二反射結構36於基板10上之投影面積的比例為100%~120%。藉由調整第二反射結構36的面積使其接近於第二半導體層122於基板10上之投影面積，以提升第二反射結構36的反射面積，提高發光元件的光摘出效率。第二反射結構36的材料、疊層、厚度及形成方法等，如圖2D及圖3C說明所述，故於此不再贅述。Next, referring to FIGS. 7E and 8D, a step of forming a second reflective structure 36 is performed. Fig. 8D shows a cross-sectional view along the line A-A' after the steps of Figs. 7A to 7E are completed. FIG. 7E only shows the high station MS and the second reflective structure 36. The second reflective structure 36 is correspondingly formed on the transparent conductive layer 18, the etch stop layer 26 and the first reflective structure 50, which passes through the opening 502 of the first reflective structure 50 and the etch stop layer 26, the transparent conductive layer 18 and the second semiconductor layer 122 is electrically connected, and includes a plurality of openings 360 corresponding to the openings 501 of the first reflective structure 50, and are formed on the exposed area 28. The second reflective structure 36 includes a metal structure, which may include a single metal layer or a stacked layer formed by a plurality of metal layers. In one embodiment, the ratio of the projected area of the second semiconductor layer 122 on the substrate 10 to the projected area of the second reflective structure 36 on the substrate 10 is 100%~120%. By adjusting the area of the second reflective structure 36 to be close to the projection area of the second semiconductor layer 122 on the substrate 10, the reflective area of the second reflective structure 36 is increased, and the light extraction efficiency of the light-emitting element is improved. The material, stack, thickness, and forming method of the second reflective structure 36 are as described in the description of FIG. 2D and FIG. 3C, so the details are not described herein again.
最後，參照圖7F至圖7I及圖8E至圖8G，其步驟如圖2E至圖2H及圖3D至3F說明所述，故於此不再贅述。Finally, referring to FIGS. 7F to 7I and FIGS. 8E to 8G, the steps are described in FIGS. 2E to 2H and FIGS. 3D to 3F, so they will not be repeated here.
於一實施例中，圖9A至圖9C顯示發光元件2製造方法中於圖7A至圖7F之步驟中沿A-A”之部份截面圖。圖9A顯示形成下部保護層23a、透明導電層18、蝕刻停止層26與第一反射結構50於半導體疊層12上。其中，部分第一反射結構50材料層形成於位於暴露區28的下部保護層23a上，下部保護層23a在暴露區28上的厚度為t1。接著，參照圖9B，以蝕刻的方式在第一反射結構50材料層形成開口501及502，並移除暴露區28上方的第一反射結構50材料層。其中，蝕刻包含乾蝕刻，例如為感應耦合核電漿(inductively coupled plasma，ICP)蝕刻。於一實施例中，蝕刻包含乾蝕刻搭配濕蝕刻。在蝕刻第一反射結構50材料層以形成開口502時，由於蝕刻停止層26覆蓋透明導電層18，所以透明導電層18不會因蝕刻而造成損傷。在蝕刻第一反射結構50材料層以形成開口501以及移除暴露區28上方的第一反射結構50時，由於下部保護層23a覆蓋暴露區28，所以暴露區28底部的第一半導體層121不會因蝕刻而造成損傷。蝕刻第一反射結構50之步驟完成後，位於暴露區28的下部保護層23a具有厚度t1’。其中厚度t1’大於 100 Å且厚度t1’小於厚度t1。藉由下部保護層23a覆蓋暴露區28以保護第一半導體層121，可以確保第一反射結構50的開口501可被完全打開，暴露區28上方不殘留其材料層，又可確保第一半導體層121不受損傷。於另一實施中，並非所有暴露區28上的第一反射結構50材料層被移除，而是僅位於半導體疊層12內部區域的暴露區28上的第一反射結構50被移除。參照圖9C，第一保護層23與其他層別的疊構關係及其位於不同位置的厚度差異，如圖4C說明所述，故於此不再贅述。In one embodiment, FIGS. 9A to 9C show partial cross-sectional views along AA" in the steps of FIGS. 7A to 7F in the manufacturing method of the light-emitting element 2. FIG. 9A shows the formation of the lower protective layer 23a, the transparent conductive layer 18, The etch stop layer 26 and the first reflective structure 50 are on the semiconductor stack 12. A part of the material layer of the first reflective structure 50 is formed on the lower protective layer 23a located in the exposed area 28, and the lower protective layer 23a is located on the exposed area 28. The thickness is t1. Next, referring to Fig. 9B, openings 501 and 502 are formed in the material layer of the first reflective structure 50 by etching, and the material layer of the first reflective structure 50 above the exposed region 28 is removed. The etching includes dry etching. For example, inductively coupled plasma (ICP) etching. In one embodiment, the etching includes dry etching and wet etching. When the material layer of the first reflective structure 50 is etched to form the opening 502, the etching stop layer 26 Covering the transparent conductive layer 18, so the transparent conductive layer 18 will not be damaged by etching. When the material layer of the first reflective structure 50 is etched to form the opening 501 and the first reflective structure 50 above the exposed area 28 is removed, due to the lower protection The layer 23a covers the exposed area 28, so the first semiconductor layer 121 at the bottom of the exposed area 28 will not be damaged by etching. After the step of etching the first reflective structure 50 is completed, the lower protective layer 23a located in the exposed area 28 has a thickness t1' The thickness t1' is greater than 100 Å and the thickness t1' is less than the thickness t1. By covering the exposed region 28 with the lower protective layer 23a to protect the first semiconductor layer 121, it can be ensured that the opening 501 of the first reflective structure 50 can be completely opened and exposed The material layer of the region 28 does not remain above, but also to ensure that the first semiconductor layer 121 is not damaged. In another implementation, not all the material layers of the first reflective structure 50 on the exposed region 28 are removed, but only located in the semiconductor layer. The first reflective structure 50 on the exposed area 28 in the inner area of the laminate 12 is removed. Referring to FIG. 9C, the stacking relationship between the first protective layer 23 and other layers and the difference in thickness at different positions are illustrated in FIG. 4C Said, so I will not repeat it here.
圖10A及圖10B分別顯示圖7A至圖7G之步驟完成後，圖7G沿B-B’線段及C-C’線段之截面圖。參照圖7G及圖10A至圖10B，第一電極20、第一保護層23及半導體疊層12的疊層位置關係，如圖2F及圖5A至圖5B說明所述，故於此不再贅述。Fig. 10A and Fig. 10B respectively show the cross-sectional views of Fig. 7G along the line B-B’ and the line C-C’ after the steps of Fig. 7A to Fig. 7G are completed. Referring to FIGS. 7G and 10A to 10B, the positional relationship between the first electrode 20, the first protective layer 23, and the semiconductor stack 12 is as described in FIGS. 2F and 5A to 5B, so it will not be repeated here. .
圖1A顯示依本實施例製造方法所製作的發光元件2之上視圖，圖1D顯示圖1A中沿A-A’線段之截面圖，圖1E顯示圖1D中之局部放大圖。Fig. 1A shows a top view of a light-emitting element 2 manufactured according to the manufacturing method of this embodiment, Fig. 1D shows a cross-sectional view along the line A-A' in Fig. 1A, and Fig. 1E shows a partial enlarged view of Fig. 1D.
參照圖1A、圖1D及圖1E，發光元件2包含基板10、半導體疊層12位於基板上10、暴露區28位於半導體疊層12的周圍及內部區域，暴露出第一半導體層上表面121a、透明導電層18位於第二半導體層122上、蝕刻停止層26位於透明導電層18上，包含複數個彼此分離的島狀結構、第一反射結構50位於透明導電層18及蝕刻停止層26上，包含複數個開口502暴露出蝕刻停止層26、第二反射結構36位於第一反射結構50上，經由第一反射結構開口502與蝕刻停止層26、透明導電層18及第二半導體層122電性連接。第二反射結構36與第一反射結構50形成一全方位反射鏡(omnidirectional reflector，ODR)，增進光的反射及發光元件1的亮度。然而，第一保護層23與其他層別的疊構關係及於不同位置的厚度關係，以及第一電極20、第二電極30、第一焊墊80a及第二焊墊80b與其他層別的疊構關係，已如圖1B及圖1C說明所述，故於此不再贅述。1A, 1D, and 1E, the light-emitting element 2 includes a substrate 10, a semiconductor stack 12 on the substrate 10, and an exposed area 28 located around and inside the semiconductor stack 12, exposing the upper surface 121a of the first semiconductor layer, The transparent conductive layer 18 is located on the second semiconductor layer 122, the etching stop layer 26 is located on the transparent conductive layer 18, and includes a plurality of island-shaped structures separated from each other. The first reflective structure 50 is located on the transparent conductive layer 18 and the etching stop layer 26, A plurality of openings 502 expose the etching stop layer 26, the second reflective structure 36 is located on the first reflective structure 50, and the first reflective structure opening 502 and the etching stop layer 26, the transparent conductive layer 18 and the second semiconductor layer 122 are electrically connected connect. The second reflective structure 36 and the first reflective structure 50 form an omnidirectional reflector (ODR) to improve the reflection of light and the brightness of the light-emitting element 1. However, the stacking relationship between the first protective layer 23 and other layers and the thickness relationship at different positions, and the relationship between the first electrode 20, the second electrode 30, the first pad 80a and the second pad 80b and other layers The stacking relationship has been described in FIG. 1B and FIG. 1C, so it will not be repeated here.
圖11係為依本發明一實施例之發光裝置3之示意圖。將前述實施例中的發光元件1、2以倒裝晶片之形式安裝於載板51 之第一墊片511、第二墊片512上。第一墊片511、第二墊片512之間藉由一包含絕緣材料之絕緣部53做電性絕緣。倒裝晶片安裝係將與焊墊形成面相對之基板10側向上，做為主要的出光面。為了增加發光裝置3之光摘出效率，可於發光元件1、2之周圍設置一反射結構54。FIG. 11 is a schematic diagram of a light-emitting device 3 according to an embodiment of the present invention. The light-emitting elements 1 and 2 in the foregoing embodiment are mounted on the first pad 511 and the second pad 512 of the carrier board 51 in the form of flip chip. The first gasket 511 and the second gasket 512 are electrically insulated by an insulating portion 53 including an insulating material. The flip-chip mounting system uses the side of the substrate 10 opposite to the bonding pad formation surface as the main light-emitting surface. In order to increase the light extraction efficiency of the light-emitting device 3, a reflective structure 54 can be provided around the light-emitting elements 1 and 2.
圖12係為依本發明一實施例之發光裝置4 之示意圖。發光裝置4 為包含一燈罩602、一反射鏡604、一發光模組610、一燈座612、一散熱片614、一連接部616 以及一電連接元件618。發光模組610 包含一承載部606，以及複數個發光單元608 位於承載部606 上，其中複數個發光單元608 可為前述實施例中的發光元件1、2 或發光裝置3。FIG. 12 is a schematic diagram of a light-emitting device 4 according to an embodiment of the present invention. The light-emitting device 4 includes a lampshade 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connection portion 616, and an electrical connection element 618. The light-emitting module 610 includes a supporting portion 606, and a plurality of light-emitting units 608 are located on the supporting portion 606, wherein the plurality of light-emitting units 608 can be the light-emitting elements 1, 2 or the light-emitting device 3 in the foregoing embodiment.
惟上述實施例僅為例示性說明本申請案之原理及其功效，而非用於限制本申請案。任何本申請案所屬技術領域中具有通常知識者均可在不違背本申請案之技術原理及精神的情況下，對上述實施例進行修改及變化。舉凡依本申請案申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本申請案之申請專利範圍內。However, the above-mentioned embodiments are only illustrative of the principle and effects of the application, and are not used to limit the application. Anyone with ordinary knowledge in the technical field to which this application belongs can modify and change the above-mentioned embodiments without violating the technical principles and spirit of this application. All the equivalent changes and modifications of the shape, structure, characteristics and spirit described in the scope of patent application of this application shall be included in the scope of patent application of this application.
