TWI686056B - Circuit structure of high-frequency and low-noise amplifier - Google Patents
Circuit structure of high-frequency and low-noise amplifier Download PDFInfo
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本發明涉及放大器領域，特別是指一種高頻低雜訊放大器電路結構。 The invention relates to the field of amplifiers, in particular to a high-frequency low-noise amplifier circuit structure.
低雜訊放大器作為無線電接收機的前置射頻信號放大器，需要在盡可能低地產生雜訊的前提下，對射頻信號進行放大，以降低後面各級模組產生的雜訊對信號的影響。 As a pre-RF signal amplifier for radio receivers, low-noise amplifiers need to amplify the RF signal under the premise of generating noise as low as possible to reduce the influence of noise generated by the modules at all levels on the signal.
如圖1所示，應用於衛星電視接收機的傳統低雜訊放大器通常由兩級級聯的場效電晶體放大器組成，以實現極低的雜訊係數、較高的信號增益以及良好的穩定性。其電路結構主要包括一級放大電路1’、二級放大電路2’、第一偏置電路3’和第二偏置電路4’，一級放大電路1’包括第一場效電晶體MN1’，二級放大電路2’包括第二場效電晶體MN2’，第一偏置電路3’包括第一電容C1’、第二電容C2’、第一電阻R1’、第二電阻R2’、第一四分之一波長濾波器F1’和第二四分之一波長濾波器F2’；第二偏置電路4’包括第三電容C3’、第四電容C4’、第四電阻R4’、第五電阻R5’、第三四分之一波長濾波器F3’和第四四分之一波長濾波器F4’；第一場效電晶體MN1’的閘極連接信號輸入端Input’和第一四分之一波長濾波器F1’的第一端，第一場效電晶體MN1’的源極接地，第一場效電晶體MN1’的汲極連接於第二四分之一波長濾波器F2’的第一端，第一場 效電晶體MN1’的汲極通過一第五電容C5’與第二場效電晶體MN2’的閘極相連，第五電容C5’兩端分別連接第一場效電晶體MN1’的汲極和第二場效電晶體MN2’的閘極；第一四分之一波長濾波器F1’的第二端連接第一電容C1’的第一端、第一電阻R1’的第一端和第三電阻R3’的第一端，第一電容C1’的第二端接地；第二四分之一波長濾波器F2’的第二端連接第二電容C2’的第一端、第二電阻R2’的第一端和第三電阻R3’的第二端，第二電容C2’第二端接地，第一電阻R1’的第二端和第二電阻R2’的第二端連接直流偏置電壓信號Bias’；第二場效電晶體MN2’的閘極連接第三四分之一波長濾波器F3’的第一端，第二場效電晶體MN2’的源極接地，第二場效電晶體MN2’的汲極連接於第四四分之一波長濾波器F4’的第一端，第二場效電晶體MN2’的汲極通過第六電容C6’與信號輸出端Output’相連，電容C6’兩端分別連接第二場效電晶體MN2’的汲極和信號輸出端Output’；第三四分之一波長濾波器F3’的第二端連接第三電容C3’的第一端、第四電阻R4’的第一端和第六電阻R6’的第一端，第三電容C3’的第二端接地；第四四分之一波長濾波器F4’的第二端連接第四電容C4’的第一端、第五電阻R5’的第一端和第六電阻R6’的第二端，第四電容C4’的第二端接地，第四電阻R4’的第二端和第五電阻R5’的第二端連接直流偏置電壓信號Bias’。 As shown in Figure 1, traditional low noise amplifiers used in satellite TV receivers are usually composed of two-stage cascaded field effect transistor amplifiers to achieve extremely low noise coefficients, high signal gain, and good stability Sex. The circuit structure mainly includes a first-stage amplifier circuit 1', a second-stage amplifier circuit 2', a first bias circuit 3'and a second bias circuit 4'. The first-stage amplifier circuit 1'includes a first field effect transistor MN1', two Stage amplifier circuit 2'includes a second field effect transistor MN2', the first bias circuit 3'includes a first capacitor C1', a second capacitor C2', a first resistor R1', a second resistor R2', a first four A quarter-wave filter F1' and a second quarter-wave filter F2'; the second bias circuit 4'includes a third capacitor C3', a fourth capacitor C4', a fourth resistor R4', a fifth resistor R5', the third quarter-wave filter F3' and the fourth quarter-wave filter F4'; the gate of the first field effect transistor MN1' is connected to the signal input terminal Input' and the first quarter The first end of a wavelength filter F1', the source of the first field effect transistor MN1' is grounded, the drain of the first field effect transistor MN1' is connected to the first end of the second quarter wave filter F2' One end, the first game The drain of the effect transistor MN1' is connected to the gate of the second field effect transistor MN2' through a fifth capacitor C5', and the two ends of the fifth capacitor C5' are respectively connected to the drain of the first field effect transistor MN1' and The gate of the second field effect transistor MN2'; the second end of the first quarter-wave filter F1' is connected to the first end of the first capacitor C1', the first end of the first resistor R1' and the third The first end of the resistor R3' and the second end of the first capacitor C1' are grounded; the second end of the second quarter-wave filter F2' is connected to the first end of the second capacitor C2' and the second resistor R2' The first terminal and the second terminal of the third resistor R3', the second terminal of the second capacitor C2' is grounded, and the second terminal of the first resistor R1' and the second terminal of the second resistor R2' are connected to a DC bias voltage signal Bias'; the gate of the second field effect transistor MN2' is connected to the first end of the third quarter-wave filter F3', the source of the second field effect transistor MN2' is grounded, and the second field effect transistor The drain of MN2' is connected to the first end of the fourth quarter-wave filter F4', the drain of the second field effect transistor MN2' is connected to the signal output terminal Output' through the sixth capacitor C6', and the capacitor C6 'Both ends are connected to the drain of the second field effect transistor MN2' and the signal output terminal Output'; the second end of the third quarter-wavelength filter F3' is connected to the first end and the third end of the third capacitor C3' The first end of the fourth resistor R4' and the first end of the sixth resistor R6', the second end of the third capacitor C3' is grounded; the second end of the fourth quarter-wave filter F4' is connected to the fourth capacitor C4 The first end of'the first end of the fifth resistor R5' and the second end of the sixth resistor R6', the second end of the fourth capacitor C4' is grounded, the second end of the fourth resistor R4' and the fifth resistor The second terminal of R5' is connected to the DC bias voltage signal Bias'.
傳統低雜訊放大器的電路原理是：在一級放大電路1’和第一偏置電路3’中，第二電阻R2’作為電流源給第一場效電晶體MN1’汲極提供偏置，同時第二電阻R2’與第二電容C2’組成RC低通濾波器，用於濾除來自於直流偏置電壓信號Bias’的雜訊；第一電阻R1’和第三電阻R3’通過電阻分壓而給第一場效電晶體MN1’的閘極提供直流偏置，同時第一電阻R1’與第一電容C1’組成RC低通濾波器，用於濾除來自於直流偏置電壓信號Bias’的雜訊；第一四分之一波長濾 波器F1’和第二四分之一波長濾波器F2’用於防止射頻洩露，提高信號增益。在二級放大電路2’和第二偏置電路4’中，第五電阻R5’作為電流源給第二場效電晶體MN2’的汲極提供偏置，同時第五電阻R5’與第四電容C4’組成RC低通濾波器，用於濾除來自於直流偏置電壓信號Bias’的雜訊；第四電阻R4’和第六電阻R6’通過電阻分壓而給第二場效電晶體MN2’的閘極提供直流偏置，同時第四電阻R4’與第三電容C3’組成RC低通濾波器，用於濾除來自於直流偏置電壓信號Bias’的雜訊；第三四分之一波長濾波器F3’和第四四分之一波長濾波器F4’用於防止射頻洩露，提高信號增益。 The circuit principle of the conventional low noise amplifier is that: in the first-stage amplifier circuit 1'and the first bias circuit 3', the second resistor R2' serves as a current source to bias the drain of the first field effect transistor MN1', and The second resistor R2' and the second capacitor C2' form an RC low-pass filter for filtering noise from the DC bias voltage signal Bias'; the first resistor R1' and the third resistor R3' are divided by the resistor The DC bias is provided to the gate of the first field effect transistor MN1', and at the same time, the first resistor R1' and the first capacitor C1' form an RC low-pass filter for filtering the DC bias voltage signal Bias' Noise; the first quarter wavelength filter The wave filter F1' and the second quarter-wave filter F2' are used to prevent radio frequency leakage and improve signal gain. In the second-stage amplifier circuit 2'and the second bias circuit 4', the fifth resistor R5' serves as a current source to provide a bias to the drain of the second field effect transistor MN2', and the fifth resistor R5' and the fourth Capacitor C4' forms an RC low-pass filter for filtering noise from the DC bias voltage signal Bias'; the fourth resistor R4' and the sixth resistor R6' divide the resistor to give the second field effect transistor The gate of MN2' provides DC bias, and the fourth resistor R4' and the third capacitor C3' form an RC low-pass filter for filtering noise from the DC bias voltage signal Bias'; the third quarter One wavelength filter F3' and the fourth quarter wavelength filter F4' are used to prevent radio frequency leakage and improve signal gain.
上述的傳統低雜訊放大器以其電路結構簡單、易於匹配、穩定性良好及雜訊係數低等優點，廣泛應用於射頻接收電路前端。但存在以下問題：每一級放大電路的增益較低，並且偏置電路的元件較多，整體電路佔用PCB板面積較大，即整體電路的布板面積大。 The traditional low noise amplifier mentioned above is widely used in the front end of the radio frequency receiving circuit due to its advantages of simple circuit structure, easy matching, good stability and low noise coefficient. However, there are the following problems: the gain of each stage of the amplifying circuit is low, and there are many components of the bias circuit, and the overall circuit occupies a large PCB area, that is, the overall circuit layout area is large.
基於傳統低雜訊放大器的缺點，中國專利公告號CN204272090U提出了一種高頻介面電路，在該高頻介面電路中，提供一種改進低雜訊放大器電路結構，將低雜訊放大器A’的負載複用於後級射頻電路RF’中，如圖2所示，該低雜訊放大器A’的負載為後級射頻電路RF’輸入端換衡器T’的初級線圈；換衡器T’初級線圈的第一端連接於低雜訊放大器A’的輸出端，換衡器T’初級線圈的第二端連接直流偏置電壓信號Bias’與隔直電容Cp’的第一端，隔直電容Cp’的第二端接地；現有的這種高頻介面電路，改善了電路板元器件數量、電路佔用PCB板面積以及電路製造成本，但低雜訊放大器A’只有一級放大，增益不夠大，不足以讓電路整體的雜訊係數達到充分小，造成雜訊性能差。 Based on the shortcomings of traditional low-noise amplifiers, Chinese Patent Announcement No. CN204272090U proposes a high-frequency interface circuit in which an improved low-noise amplifier circuit structure is provided, and the load of the low-noise amplifier A'is complex Used in the post-stage RF circuit RF', as shown in FIG. 2, the load of the low noise amplifier A'is the primary coil of the converter T'at the input end of the post-stage RF circuit RF'; the first coil of the converter T'primary coil One end is connected to the output end of the low noise amplifier A', the second end of the primary coil of the converter T'is connected to the first end of the DC bias voltage signal Bias' and the DC blocking capacitor Cp', the first end of the DC blocking capacitor Cp' The two terminals are grounded; the existing high-frequency interface circuit improves the number of circuit board components, the circuit occupies the PCB area and the circuit manufacturing cost, but the low noise amplifier A'only has one-stage amplification and the gain is not large enough to allow the circuit The overall noise factor is sufficiently small, resulting in poor noise performance.
本發明的目的在於提供一種高頻低雜訊放大器電路結構，其具有結構簡單，雜訊性能好的優點。 The purpose of the present invention is to provide a high-frequency low-noise amplifier circuit structure, which has the advantages of simple structure and good noise performance.
為了達成上述目的，本發明揭示一種高頻低雜訊放大器電路結構，包含：一信號輸入端；一射頻放大電路；一負載；以及一信號輸出端；所述射頻放大電路包括級聯的一一級放大電路和一二級放大電路；所述一級放大電路為單端放大電路，所述一級放大電路包括一第一場效電晶體和一第四電阻；所述二級放大電路為單端放大電路，所述二級放大電路包括一第二場效電晶體、一第一電阻、一第二電阻、一第三電阻以及一旁路電容；所述負載為一負載電感；所述第一場效電晶體的閘極連接所述信號輸入端和所述第一電阻的第一端，所述第一場效電晶體的源極接地，所述第一場效電晶體的汲極連接所述第四電阻的第一端和所述第二場效電晶體的閘極，所述第四電阻的第二端連接所述負載電感的第一端和所述信號輸出端，所述信號輸出端接入一直流偏置電壓信號；所述第一電阻的第二端連接所述第二電阻的第一端和所述第三電阻的第一端；所述第三電阻的第二端接地，所述第二電阻的第二端連接所述第二場效電晶體的源極和所述旁路電容的第一端，所述旁路電容的第二端接地；所述第二場效電晶體的汲極連接所述負載電感的第二端。所述第四電阻的第二端通過一濾波電阻和一第一濾波電容與所述負載電感的第一端和所述信號輸出端相連，所述濾波電阻的第一端連接所述負載電感的第一端和所述信號輸出端，所述濾波電阻的第二端連接所述第一濾波電容的第一端和所述第四電阻的第二端，所述第一濾波電容的第二端接地。所述第一電阻的第一端通過一四分之一濾波器和一第二濾波電容與所述第一場效電晶體的閘極和信號輸入端相連；所述四分之一濾波器的第一端連接所述第二濾波電容的第一端和所述第一 電阻的第一端，所述第二濾波電容的第二端接地，所述四分之一濾波器的第二端連接所述第一場效電晶體的閘極和所述信號輸入端。 In order to achieve the above object, the present invention discloses a high-frequency low-noise amplifier circuit structure, including: a signal input terminal; a radio frequency amplifier circuit; a load; and a signal output terminal; the radio frequency amplifier circuit includes a cascade Amplifier circuit and a two-stage amplifier circuit; the first-stage amplifier circuit is a single-ended amplifier circuit, the first-stage amplifier circuit includes a first field effect transistor and a fourth resistor; the second-stage amplifier circuit is a single-ended amplifier Circuit, the second-stage amplifier circuit includes a second field effect transistor, a first resistor, a second resistor, a third resistor and a bypass capacitor; the load is a load inductance; the first field effect The gate of the transistor is connected to the signal input terminal and the first terminal of the first resistor, the source of the first field effect transistor is grounded, and the drain of the first field effect transistor is connected to the first The first end of the four resistors and the gate of the second field effect transistor, the second end of the fourth resistor is connected to the first end of the load inductor and the signal output, and the signal output is connected Into a DC bias voltage signal; the second end of the first resistor is connected to the first end of the second resistor and the first end of the third resistor; the second end of the third resistor is grounded, so The second end of the second resistor is connected to the source of the second field effect transistor and the first end of the bypass capacitor, the second end of the bypass capacitor is grounded; the second field effect transistor The drain of is connected to the second end of the load inductor. The second end of the fourth resistor is connected to the first end of the load inductor and the signal output terminal through a filter resistor and a first filter capacitor, and the first end of the filter resistor is connected to the load inductor The first terminal and the signal output terminal, the second terminal of the filter resistor is connected to the first terminal of the first filter capacitor and the second terminal of the fourth resistor, the second terminal of the first filter capacitor Ground. The first terminal of the first resistor is connected to the gate and signal input terminal of the first field effect transistor through a quarter filter and a second filter capacitor; The first end is connected to the first end of the second filter capacitor and the first The first terminal of the resistor, the second terminal of the second filter capacitor is grounded, and the second terminal of the quarter filter is connected to the gate of the first field effect transistor and the signal input terminal.
又一種高頻低雜訊放大器電路結構，包含：一信號輸入端；一射頻放大電路；一負載；以及一信號輸出端，所述信號輸出端包括一第一信號輸出端和一第二信號輸出端；其中所述射頻放大電路包括級聯的一一級放大電路和一二級放大電路；所述一級放大電路為單端放大電路，所述一級放大電路包括一第一場效電晶體和一第四電阻；所述二級放大電路為單端放大電路，所述二級放大電路包括一第二場效電晶體、一第一電阻、一第二電阻、一第三電阻以及一旁路電容；所述負載為一射頻電路輸入端的輸入一換衡器的一初級線圈；輸入所述換衡器的一次級線圈的第一端和第二端分別連接所述第一信號輸出端和所述第二信號輸出端；所述第一場效電晶體的閘極連接所述信號輸入端和所述第一電阻的第一端，所述第一場效電晶體的源極接地，所述第一場效電晶體的汲極連接所述第四電阻的第一端和所述第二場效電晶體的閘極，所述第四電阻的第二端連接所述第二場效電晶體的汲極和輸入所述換衡器的所述初級線圈的第一端；所述第一電阻的第二端連接所述第二電阻的第一端和所述第三電阻的第一端；所述第三電阻的第二端接地，所述第二電阻的第二端連接所述第二場效電晶體的源極和所述旁路電容的第一端，所述旁路電容的第二端接地；輸入所述換衡器的所述初級線圈的第二端接入一直流偏置電壓信號，輸入所述換衡器的所述初級線圈的第二端連接一隔直電容的第一端，所述隔直電容的第二端接地。所述第四電阻的第二端通過一濾波電阻和一第一濾波電容與輸入所述換衡器的所述初級線圈的第一端和所述第二場效電晶體的汲極相連，所述濾波電阻的第一端連接輸入所述換衡器的所述初級線圈的第一端和所述第 二場效電晶體的汲極，所述濾波電阻的第二端連接所述第一濾波電容的第一端和所述第四電阻的第二端，所述第一濾波電容的第二端接地。所述第一電阻的第一端通過一四分之一濾波器和一第二濾波電容與所述第一場效電晶體的閘極和所述信號輸入端相連；所述四分之一濾波器的第一端連接所述第二濾波電容的第一端和所述第一電阻的第一端，所述第二濾波電容的第二端接地，所述四分之一濾波器的第二端連接所述第一場效電晶體的閘極和所述信號輸入端。所述換衡器全名為平衡-不平衡轉換器(balanced to unbalanced,Balun)。 Another high-frequency low-noise amplifier circuit structure includes: a signal input terminal; a radio frequency amplifier circuit; a load; and a signal output terminal, the signal output terminal includes a first signal output terminal and a second signal output End; wherein the RF amplifier circuit includes a cascade of a first-stage amplifier circuit and a second-stage amplifier circuit; the first-stage amplifier circuit is a single-ended amplifier circuit, the first-stage amplifier circuit includes a first field effect transistor and a A fourth resistor; the secondary amplifier circuit is a single-ended amplifier circuit, and the secondary amplifier circuit includes a second field effect transistor, a first resistor, a second resistor, a third resistor, and a bypass capacitor; The load is an input of a radio frequency circuit input a primary coil of a converter; the first end and the second end of the primary coil input to the converter are respectively connected to the first signal output and the second signal Output terminal; the gate of the first field effect transistor is connected to the signal input terminal and the first end of the first resistor, the source of the first field effect transistor is grounded, and the first field effect The drain of the transistor is connected to the first end of the fourth resistor and the gate of the second field effect transistor, and the second end of the fourth resistor is connected to the drain of the second field effect transistor and The first end of the primary coil input to the converter; the second end of the first resistor is connected to the first end of the second resistor and the first end of the third resistor; the third resistor The second terminal of the second resistor is grounded, the second terminal of the second resistor is connected to the source of the second field effect transistor and the first terminal of the bypass capacitor, and the second terminal of the bypass capacitor is grounded; The second end of the primary coil of the converter is connected to a DC bias voltage signal, and the second end of the primary coil input to the converter is connected to the first end of a DC blocking capacitor. The second end of the capacitor is grounded. The second end of the fourth resistor is connected to the first end of the primary coil input to the converter and the drain of the second field effect transistor through a filter resistor and a first filter capacitor. The first end of the filter resistor is connected to the first end of the primary coil input to the converter and the first The drain of the two field effect transistors, the second end of the filter resistor is connected to the first end of the first filter capacitor and the second end of the fourth resistor, and the second end of the first filter capacitor is grounded . The first end of the first resistor is connected to the gate of the first field effect transistor and the signal input through a quarter filter and a second filter capacitor; the quarter filter The first end of the filter is connected to the first end of the second filter capacitor and the first end of the first resistor, the second end of the second filter capacitor is grounded, and the second end of the quarter filter The terminal is connected to the gate of the first field effect transistor and the signal input terminal. The full name of the converter is a balanced-unbalanced converter (balanced to unbalanced, Balun).
再一種高頻低雜訊放大器電路結構，包含：一信號輸入端；一射頻放大電路；一負載；以及一信號輸出端，所述信號輸出端包括一第一信號輸出端和一第二信號輸出端；其中所述射頻放大電路包括級聯的一一級放大電路和一二級放大電路；所述一級放大電路為單端放大電路，所述一級放大電路包括一第一場效電晶體和一第四電阻；所述二級放大電路為差分放大電路，所述二級放大電路包括一第二場效電晶體、一第三場效電晶體、一第一電阻、一第二電阻、一第三電阻、一第五電阻、一第六電阻、一第七電阻、一諧振電感以及一旁路電容；所述負載為一負載電感；所述第一場效電晶體的閘極連接所述信號輸入端和所述第一電阻的第一端，所述第一場效電晶體的源極接地，所述第一場效電晶體的汲極連接所述第四電阻的第一端、所述第五電阻的第一端和所述第二場效電晶體的閘極；所述第一電阻的第二端連接所述第二電阻的第一端和所述第三電阻的第一端；所述第三電阻的第二端接地，所述第二電阻的第二端連接所述第二場效電晶體的源極和所述第三場效電晶體的源極，所述第四電阻的第二端連接所述第六電阻的第一端和所述第七電阻的第一端，所述第六電阻的第二端連接所述第一信號輸出端、所述負載電感的第一端和所述第二場 效電晶體的汲極，所述第七電阻的第二端連接所述第二信號輸出端、所述負載電感的第二端和所述第三場效電晶體的汲極，所述負載電感的中心抽頭接入一直流偏置電壓信號；所述第五電阻的第二端連接所述第三場效電晶體的閘極和所述諧振電感的第一端，所述諧振電感的第二端連接所述旁路電容的第一端，所述旁路電容的第二端接地。所述第四電阻的第二端通過一濾波電阻和一第一濾波電容與所述第六電阻的第一端和所述第七電阻的第一端相連，所述濾波電阻的第一端連接所述第六電阻的第一端和所述第七電阻的第一端，所述濾波電阻的第二端連接所述第一濾波電容的第一端和所述第四電阻的第二端，所述第一濾波電容的第二端接地。所述第一電阻的第一端通過一四分之一濾波器和一第二濾波電容與所述第一場效電晶體的閘極和所述信號輸入端相連；所述四分之一濾波器的第一端連接所述第二濾波電容的第一端和所述第一電阻的第一端，所述第二濾波電容的第二端接地，所述四分之一濾波器的第二端連接所述第一場效電晶體的閘極和所述信號輸入端。 Another high-frequency low-noise amplifier circuit structure includes: a signal input terminal; a radio frequency amplifier circuit; a load; and a signal output terminal, the signal output terminal includes a first signal output terminal and a second signal output End; wherein the RF amplifier circuit includes a cascade of a first-stage amplifier circuit and a second-stage amplifier circuit; the first-stage amplifier circuit is a single-ended amplifier circuit, the first-stage amplifier circuit includes a first field effect transistor and a Fourth resistor; the second-stage amplifier circuit is a differential amplifier circuit, the second-stage amplifier circuit includes a second field effect transistor, a third field effect transistor, a first resistor, a second resistor, a first Three resistors, a fifth resistor, a sixth resistor, a seventh resistor, a resonant inductor and a bypass capacitor; the load is a load inductor; the gate of the first field effect transistor is connected to the signal input And the first end of the first resistor, the source of the first field effect transistor is grounded, and the drain of the first field effect transistor is connected to the first end of the fourth resistor and the first The first end of the fifth resistor and the gate of the second field effect transistor; the second end of the first resistor is connected to the first end of the second resistor and the first end of the third resistor; The second end of the third resistor is grounded, the second end of the second resistor is connected to the source of the second field effect transistor and the source of the third field effect transistor, and the The second terminal is connected to the first terminal of the sixth resistor and the first terminal of the seventh resistor, and the second terminal of the sixth resistor is connected to the first signal output terminal and the first terminal of the load inductor And the second field A drain electrode of an effect transistor, a second end of the seventh resistor is connected to the second signal output terminal, a second end of the load inductor, and a drain electrode of the third field effect transistor, the load inductor Is connected to the DC bias voltage signal; the second end of the fifth resistor is connected to the gate of the third field effect transistor and the first end of the resonant inductor, the second end of the resonant inductor Is connected to the first end of the bypass capacitor, and the second end of the bypass capacitor is grounded. The second end of the fourth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor through a filter resistor and a first filter capacitor, and the first end of the filter resistor is connected A first terminal of the sixth resistor and a first terminal of the seventh resistor, a second terminal of the filter resistor are connected to a first terminal of the first filter capacitor and a second terminal of the fourth resistor, The second end of the first filter capacitor is grounded. The first end of the first resistor is connected to the gate of the first field effect transistor and the signal input through a quarter filter and a second filter capacitor; the quarter filter The first end of the filter is connected to the first end of the second filter capacitor and the first end of the first resistor, the second end of the second filter capacitor is grounded, and the second end of the quarter filter The terminal is connected to the gate of the first field effect transistor and the signal input terminal.
又再一種高頻低雜訊放大器電路結構，包含：一信號輸入端；一射頻放大電路；一負載；以及一信號輸出端，所述信號輸出端包括一第一信號輸出端和一第二信號輸出端；其中所述射頻放大電路包括級聯的一一級放大電路和一二級放大電路；所述一級放大電路為單端放大電路，所述一級放大電路包括一第一場效電晶體和一第四電阻；所述二級放大電路為差分放大電路，所述二級放大電路包括一第二場效電晶體、一第三場效電晶體、一第一電阻、一第二電阻、一第三電阻、一第五電阻、一第六電阻、一第七電阻、一諧振電感以及一旁路電容；所述負載為一射頻電路輸入端的輸入一換衡器的一初級線圈；輸入所述換衡器的一次級線圈的第一端和第二端分別連接所述第一信號輸 出端和所述第二信號輸出端；所述第一場效電晶體的閘極連接所述信號輸入端和所述第一電阻的第一端，所述第一場效電晶體的源極接地，所述第一場效電晶體的汲極連接所述第四電阻的第一端、所述第五電阻的第一端和所述第二場效電晶體的閘極；所述第一電阻的第二端連接所述第二電阻的第一端和所述第三電阻的第一端；所述第三電阻的第二端接地，所述第二電阻的第二端連接所述第二場效電晶體的源極和所述第三場效電晶體的源極，所述第四電阻的第二端連接所述第六電阻的第一端和所述第七電阻的第一端，所述第六電阻的第二端連接輸入所述換衡器的所述初級線圈的第一端和所述第二場效電晶體的汲極，所述第七電阻的第二端連接輸入所述換衡器的所述初級線圈的第二端和所述第三場效電晶體的汲極，輸入所述換衡器的所述初級線圈的中心抽頭接入一直流偏置電壓信號；所述第五電阻的第二端連接所述第三場效電晶體的閘極和所述諧振電感的第一端，所述諧振電感的第二端連接所述旁路電容的第一端，所述旁路電容的第二端接地。所述第四電阻的第二端通過一濾波電阻和一第一濾波電容與所述第六電阻的第一端和所述第七電阻的第一端相連，所述濾波電阻的第一端連接所述第六電阻的第一端和所述第七電阻的第一端，所述濾波電阻的第二端連接所述第一濾波電容的第一端和所述第四電阻的第二端，所述第一濾波電容的第二端接地。所述第一電阻的第一端通過一四分之一濾波器和一第二濾波電容與所述第一場效電晶體的閘極和所述信號輸入端相連；所述四分之一濾波器的第一端連接所述第二濾波電容的第一端和所述第一電阻的第一端，所述第二濾波電容的第二端接地，所述四分之一濾波器的第二端連接所述第一場效電晶體的閘極和所述信號輸入端。 Yet another high-frequency low-noise amplifier circuit structure includes: a signal input terminal; a radio frequency amplifier circuit; a load; and a signal output terminal, the signal output terminal includes a first signal output terminal and a second signal Output terminal; wherein the RF amplifier circuit includes a cascaded first-stage amplifier circuit and a second-stage amplifier circuit; the first-stage amplifier circuit is a single-ended amplifier circuit, and the first-stage amplifier circuit includes a first field effect transistor and A fourth resistor; the secondary amplifier circuit is a differential amplifier circuit, the secondary amplifier circuit includes a second field effect transistor, a third field effect transistor, a first resistor, a second resistor, a A third resistor, a fifth resistor, a sixth resistor, a seventh resistor, a resonant inductor, and a bypass capacitor; the load is a primary coil of an input of a radio frequency circuit, an input of a converter; the input of the converter The first end and the second end of the primary coil of the The output terminal and the second signal output terminal; the gate of the first field effect transistor is connected to the signal input terminal and the first end of the first resistor, and the source electrode of the first field effect transistor Grounding, the drain of the first field effect transistor is connected to the first end of the fourth resistor, the first end of the fifth resistance, and the gate of the second field effect transistor; the first The second end of the resistor is connected to the first end of the second resistor and the first end of the third resistor; the second end of the third resistor is grounded, and the second end of the second resistor is connected to the first The source of the second field effect transistor and the source of the third field effect transistor, the second end of the fourth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor , The second end of the sixth resistor is connected to the first end of the primary coil of the input converter and the drain of the second field effect transistor, and the second end of the seventh resistor is connected to the input The second end of the primary coil of the converter and the drain of the third field effect transistor are input to the center tap of the primary coil of the converter to be connected to a DC bias voltage signal; The second end of the fifth resistor is connected to the gate of the third field effect transistor and the first end of the resonant inductor, the second end of the resonant inductor is connected to the first end of the bypass capacitor, and the side The second end of the circuit capacitor is grounded. The second end of the fourth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor through a filter resistor and a first filter capacitor, and the first end of the filter resistor is connected A first terminal of the sixth resistor and a first terminal of the seventh resistor, a second terminal of the filter resistor are connected to a first terminal of the first filter capacitor and a second terminal of the fourth resistor, The second end of the first filter capacitor is grounded. The first end of the first resistor is connected to the gate of the first field effect transistor and the signal input through a quarter filter and a second filter capacitor; the quarter filter The first end of the filter is connected to the first end of the second filter capacitor and the first end of the first resistor, the second end of the second filter capacitor is grounded, and the second end of the quarter filter The terminal is connected to the gate of the first field effect transistor and the signal input terminal.
根據上述技術特徵可達成以下功效： According to the above technical features, the following effects can be achieved:
1.本發明的射頻放大電路包括級聯的一級放大電路和二級放大電路，可實現兩級放大以提高本發明的增益，從而降低與本發明的射頻放大電路輸出相連的後級電路模組的雜訊對本發明的射頻放大電路的雜訊性能的影響，實現了低雜訊特性。 1. The RF amplifier circuit of the present invention includes a cascaded first-stage amplifier circuit and a second-stage amplifier circuit, which can realize two-stage amplification to improve the gain of the present invention, thereby reducing the output of the subsequent stage circuit module connected to the RF amplifier circuit of the present invention The effect of noise on the noise performance of the RF amplifier circuit of the present invention achieves low noise characteristics.
2.本發明的射頻放大電路採用直流負反饋自偏壓結構，使得本發明的射頻放大電路具有更加穩定的直流工作狀態。 2. The radio frequency amplifier circuit of the present invention adopts a DC negative feedback self-bias voltage structure, so that the radio frequency amplifier circuit of the present invention has a more stable DC working state.
3.本發明的射頻放大電路具有交流負反饋環路，使得本發明的射頻放大電路具有更加穩定的增益。 3. The radio frequency amplifier circuit of the present invention has an AC negative feedback loop, so that the radio frequency amplifier circuit of the present invention has a more stable gain.
4.本發明的負載可以為一射頻電路輸入端的輸入換衡器的初級線圈，即本發明的負載與射頻電路輸入端的輸入換衡器複用，這樣本發明與射頻電路便是直接連接，使得本發明無需考慮本發明與射頻電路之間的阻抗匹配問題，這樣可以在沒有增加射頻電路的布板面積的同時，顯著減小本發明的布板面積，極大的降低了製造成本。 4. The load of the present invention may be the primary coil of the input converter of the input end of the radio frequency circuit, that is, the load of the present invention is multiplexed with the input converter of the input end of the radio frequency circuit, so that the present invention and the radio frequency circuit are directly connected, making the present invention There is no need to consider the impedance matching problem between the present invention and the radio frequency circuit, so that the layout area of the present invention can be significantly reduced without increasing the layout area of the radio frequency circuit, which greatly reduces the manufacturing cost.
先前技術 Prior art
(1’)‧‧‧一級放大電路 (1’)‧‧‧One-stage amplifier circuit
(2’)‧‧‧二級放大電路 (2’)‧‧‧two-stage amplifier circuit
(3’)‧‧‧第一偏置電路 (3’)‧‧‧First bias circuit
(4’)‧‧‧第二偏置電路 (4’)‧‧‧Second bias circuit
(Bias’)‧‧‧直流偏置電壓信號 (Bias’) ‧‧‧ DC bias voltage signal
(MN1’)‧‧‧第一場效電晶體 (MN1’)‧‧‧First Field Effect Transistor
(MN2’)‧‧‧第二場效電晶體 (MN2’)‧‧‧second field effect transistor
(A’)‧‧‧低雜訊放大器 (A’)‧‧‧low noise amplifier
(C1’)‧‧‧第一電容 (C1’)‧‧‧First capacitor
(C2’)‧‧‧第二電容 (C2’)‧‧‧Second capacitor
(C3’)‧‧‧第三電容 (C3’)‧‧‧third capacitor
(C4’)‧‧‧第四電容 (C4’)‧‧‧The fourth capacitor
(C5’)‧‧‧第五電容 (C5’) The fifth capacitor
(C6’)‧‧‧第六電容 (C6’) The sixth capacitor
(Cp’)‧‧‧隔直電容 (Cp’) ‧‧‧ DC blocking capacitor
(F1’)‧‧‧第一四分之一波長濾波器 (F1’) ‧‧‧ First quarter wavelength filter
(F2’)‧‧‧第二四分之一波長濾波器 (F2’) ‧‧‧ Second quarter wavelength filter
(F3’)‧‧‧第三四分之一波長濾波器 (F3’) ‧‧‧ Third quarter wavelength filter
(F4’)‧‧‧第四四分之一波長濾波器 (F4’) ‧‧‧ Fourth quarter wavelength filter
(Input’)‧‧‧信號輸入端 (Input’)‧‧‧signal input
(Output’)‧‧‧信號輸出端 (Output’)‧‧‧Signal output
(R1’)‧‧‧第一電阻 (R1’)‧‧‧ First resistance
(R2’)‧‧‧第二電阻 (R2’)‧‧‧second resistance
(R3’)‧‧‧第三電阻 (R3’) The third resistor
(R4’)‧‧‧第四電阻 (R4’) ‧‧‧ Fourth resistance
(R5’)‧‧‧第五電阻 (R5’) The fifth resistor
(R6’)‧‧‧第六電阻 (R6’) The sixth resistor
(RF’)‧‧‧後級射頻電路 (RF’)‧‧‧‧Frequency RF circuit
(T’)‧‧‧換衡器 (T’)‧‧‧Converter
本發明高頻低雜訊放大器電路結構 Circuit structure of high-frequency low-noise amplifier of the invention
(1)‧‧‧射頻放大電路 (1)‧‧‧RF amplifier circuit
(11)‧‧‧一級放大電路 (11)‧‧‧One-stage amplifier circuit
(12)‧‧‧二級放大電路 (12)‧‧‧Two-stage amplifier circuit
(2)‧‧‧負載 (2)‧‧‧load
(Bias)‧‧‧直流偏置電壓信號 (Bias)‧‧‧DC bias voltage signal
(C1)‧‧‧旁路電容 (C1)‧‧‧Bypass capacitor
(C2)‧‧‧第一濾波電容 (C2)‧‧‧First filter capacitor
(C3)‧‧‧第二濾波電容 (C3)‧‧‧Second filter capacitor
(Cp)‧‧‧隔直電容 (Cp) ‧‧‧ DC blocking capacitor
(FG)‧‧‧四分之一濾波器 (FG) ‧‧‧ quarter filter
(Input)‧‧‧信號輸入端 (Input)‧‧‧Signal input terminal
(L1)‧‧‧負載電感 (L1)‧‧‧load inductance
(L2)‧‧‧諧振電感 (L2)‧‧‧Resonant inductor
(MN1)‧‧‧第一場效電晶體 (MN1)‧‧‧First Field Effect Transistor
(MN2)‧‧‧第二場效電晶體 (MN2)‧‧‧second field effect transistor
(MN3)‧‧‧第三場效電晶體 (MN3) ‧‧‧ third field effect transistor
(Output)‧‧‧信號輸出端 (Output)‧‧‧Signal output
(Output1)‧‧‧第一信號輸出端 (Output1)‧‧‧First signal output
(Output2)‧‧‧第二信號輸出端 (Output2)‧‧‧Second signal output
(R0)‧‧‧濾波電阻 (R0)‧‧‧filter resistance
(R1)‧‧‧第一電阻 (R1)‧‧‧ First resistance
(R2)‧‧‧第二電阻 (R2)‧‧‧Second resistance
(R3)‧‧‧第三電阻 (R3)‧‧‧third resistance
(R4)‧‧‧第四電阻 (R4)‧‧‧ Fourth resistance
(R5)‧‧‧第五電阻 (R5)‧‧‧fifth resistance
(R6)‧‧‧第六電阻 (R6)‧‧‧Sixth resistance
(R7)‧‧‧第七電阻 (R7)‧‧‧The seventh resistor
(RF)‧‧‧射頻電路 (RF)‧‧‧RF circuit
(T)‧‧‧換衡器 (T)‧‧‧ Exchanger
[第一圖]係傳統的低雜訊放大器的電路示意圖。 [Figure 1] is a circuit schematic diagram of a conventional low noise amplifier.
[第二圖]係現有的一種高頻介面電路的電路示意圖。 [Second figure] It is a circuit schematic diagram of a conventional high-frequency interface circuit.
[第三圖]係本發明實施例一的電路示意圖。 [Third figure] It is a schematic circuit diagram of the first embodiment of the present invention.
[第四圖]係本發明實施例二的電路示意圖。 [Fourth figure] is a schematic circuit diagram of a second embodiment of the present invention.
[第五圖]係本發明實施例三的電路示意圖。 [Fifth figure] is a schematic circuit diagram of a third embodiment of the present invention.
[第六圖]係本發明實施例四的電路示意圖。 [Sixth figure] It is a schematic circuit diagram of the fourth embodiment of the present invention.
[第七圖]係本發明實施例五的電路示意圖。 [Seventh figure] It is a circuit schematic diagram of the fifth embodiment of the present invention.
[第八圖]係本發明實施例六的電路示意圖。 [Figure 8] is a schematic circuit diagram of Embodiment 6 of the present invention.
[第九圖]係本發明實施例七的電路示意圖。
[Figure 9] is a schematic circuit diagram of
[第十圖]係本發明實施例八的電路示意圖。 [Figure 10] is a schematic circuit diagram of Embodiment 8 of the present invention.
綜合上述技術特徵，本發明高頻低雜訊放大器電路結構的主要功效將可於下述實施例清楚呈現。 Based on the above technical features, the main functions of the circuit structure of the high-frequency low-noise amplifier of the present invention will be clearly shown in the following embodiments.
請先參閱第三圖，係揭示本發明實施例一，本發明的實施例一為一種高頻低雜訊放大器電路結構，包含一信號輸入端Input、一射頻放大電路1、負載2以及一信號輸出端Output；其中所述射頻放大電路1包括級聯的一一級放大電路11和一二級放大電路12；所述一級放大電路11為單端放大電路，所述一級放大電路11包括一第一場效電晶體MN1和一第四電阻R4；所述二級放大電路12為單端放大電路，所述二級放大電路12包括一第二場效電晶體MN2、一第一電阻R1、一第二電阻R2、一第三電阻R3以及一旁路電容C1；所述負載2為一負載電感L1；所述第一場效電晶體MN1的閘極連接所述信號輸入端Input和所述第一電阻R1的第一端，所述第一場效電晶體MN1的源極接地，所述第一場效電晶體MN1的汲極連接所述第四電阻R4的第一端和所述第二場效電晶體MN2的閘極，所述第四電阻R4的第二端連接所述負載電感L1的第一端和所述信號輸出端Output，所述信號輸出端Output接入一直流偏置電壓信號Bias；所述第一電阻R1的第二端連接所述第二電阻R2的第一端和所述第三電阻R3的第一端；所述第三電阻R3的第二端接地，所述第二電阻R2的第二端連接所述第二場效電晶體MN2的源極和所述旁路電容C1的第一端，所述旁路電容C1的第二端接地；所述第二場效電晶體MN2的汲極連接所述負載電感L1的第二端。 Please refer to the third figure to reveal the first embodiment of the present invention. The first embodiment of the present invention is a high-frequency and low-noise amplifier circuit structure, which includes a signal input terminal, an RF amplifier circuit 1, a load 2 and a signal The output terminal Output; wherein the RF amplifier circuit 1 includes a cascaded first-stage amplifier circuit 11 and a second-stage amplifier circuit 12; the first-stage amplifier circuit 11 is a single-ended amplifier circuit, the first-stage amplifier circuit 11 includes a first A field effect transistor MN1 and a fourth resistor R4; the secondary amplifier circuit 12 is a single-ended amplifier circuit, the secondary amplifier circuit 12 includes a second field effect transistor MN2, a first resistor R1, a A second resistor R2, a third resistor R3 and a bypass capacitor C1; the load 2 is a load inductance L1; the gate of the first field effect transistor MN1 is connected to the signal input terminal Input and the first The first end of the resistor R1, the source of the first field effect transistor MN1 is grounded, and the drain of the first field effect transistor MN1 is connected to the first end of the fourth resistor R4 and the second field The gate of the effect transistor MN2, the second end of the fourth resistor R4 is connected to the first end of the load inductor L1 and the signal output terminal Output, and the signal output terminal Output is connected to a DC bias voltage signal Bias; the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the first end of the third resistor R3; the second end of the third resistor R3 is grounded, the first The second end of the two resistors R2 is connected to the source of the second field effect transistor MN2 and the first end of the bypass capacitor C1, and the second end of the bypass capacitor C1 is grounded; the second field effect The drain of the transistor MN2 is connected to the second end of the load inductor L1.
在本發明實施例一中，初態時，即所述第一場效電晶體MN1和所述第二場效電晶體MN2無電流流過時，所述信號輸出端Output接入所述直流偏置電壓信號Bias，此時所述第一場效電晶體MN1的汲極電壓為所述直流偏置電壓信號Bias的電壓，而此時所述第二場效電晶體MN2的源極電壓為地電壓；由於所述第一場效電晶體MN1的汲極連接所述第二場效電晶體MN2的閘極，因此此時所述第二場效電晶體MN2的閘源電壓差為所述直流偏置電壓信號Bias的電壓值，所述第二場效電晶體MN2便導通；隨著所述第二場效電晶體MN2的通道電流流過，所述第二電阻R2與所述第三電阻R3分壓回饋至所述第一場效電晶體MN1的閘極，從而使得所述第一場效電晶體MN1導通，而隨著所述第一場效電晶體MN1的通道電流流過，所述第一場效電晶體MN1的汲極電壓降低，這樣所述第二場效電晶體MN2的閘極電壓下降，使得所述第二場效電晶體MN2的源極電壓下降，則經由所述第二電阻R2和所述第三電阻R3分壓回饋至所述第一場效電晶體MN1的閘極電壓下降，以使得所述第一場效電晶體MN1的閘極電壓維持一個定值，這樣所述射頻放大電路1便形成了穩定的直流負反饋自偏壓結構。在本發明實施例一中，所述負載電感L1與所述第四電阻R4組成一交流負反饋環路，所述交流負反饋環路的工作原理為：若所述第二場效電晶體MN2的閘極電壓信號上升，則經由所述負載電感L1與所述第四電阻R4採樣回饋至所述第二場效電晶體MN2閘極的電壓下降，以使得所述第二場效電晶體MN2的閘極電壓維持一個定值，從而使得所述射頻放大電路1具有穩定的信號增益。
In the first embodiment of the present invention, in the initial state, that is, when no current flows through the first field effect transistor MN1 and the second field effect transistor MN2, the signal output terminal Output is connected to the DC bias Voltage signal Bias, at this time the drain voltage of the first field effect transistor MN1 is the voltage of the DC bias voltage signal Bias, and at this time the source voltage of the second field effect transistor MN2 is the ground voltage ; Since the drain electrode of the first field effect transistor MN1 is connected to the gate electrode of the second field effect transistor MN2, the gate source voltage difference of the second field effect transistor MN2 at this time is the DC bias Set the voltage value of the voltage signal Bias, the second field effect transistor MN2 is turned on; as the channel current of the second field effect transistor MN2 flows, the second resistor R2 and the third resistor R3 The divided voltage is fed back to the gate of the first field effect transistor MN1, so that the first field effect transistor MN1 is turned on, and as the channel current of the first field effect transistor MN1 flows, the The drain voltage of the first field-effect transistor MN1 decreases, so that the gate voltage of the second field-effect transistor MN2 decreases, so that the source voltage of the second field-effect transistor MN2 decreases. The divided voltage of the second resistor R2 and the third resistor R3 is fed back to the gate voltage of the first field effect transistor MN1 to decrease, so that the gate voltage of the first field effect transistor MN1 maintains a fixed value, so The radio
在本發明實施例一中，所述射頻放大電路1採用兩級放大結構，因此所述射頻放大電路1具有較高的增益，可以減弱後級模組的雜訊對所述高頻低雜訊放大器電路結構的整體雜訊性能的影響。在本發明實施例一中，當所
述射頻放大電路1正常工作時，即所述第一場效電晶體MN1和所述第二場效電晶體MN2導通時，此時外部之一射頻信號輸入到所述信號輸入端Input，所述射頻信號便通過所述第一場效電晶體MN1放大後輸出至所述第二場效電晶體MN2的閘極，然後所述射頻信號再經所述第二場效電晶體MN2放大後由所述信號輸出端Output輸出。
In the first embodiment of the present invention, the radio
請參閱第四圖，係揭示本發明實施例二，本發明的實施例二與實施例一的區別在於：在實施例一中，所述第四電阻R4的第二端直接與所述負載電感L1的第一端和所述信號輸出端Output相連；而在實施例二中，所述第四電阻R4的第二端通過一濾波電阻R0和一第一濾波電容C2與所述負載電感L1的第一端和所述信號輸出端Output相連，其中所述濾波電阻R0的第一端連接所述負載電感L1的第一端和所述信號輸出端Output，所述濾波電阻R0的第二端連接所述第一濾波電容C2的第一端和所述第四電阻R4的第二端，所述第一濾波電容C2的第二端接地，所述濾波電阻R0和第一濾波電容C2形成一衰減網路而阻止所述射頻信號通過，防止由所述信號輸出端Output輸出的所述射頻信號再流入所述一級放大電路11中，而使得所述一級放大電路11的增益衰減；通過調節所述衰減網路的時間常數，可調節所述射頻放大電路1的增益。
Please refer to the fourth figure, which discloses the second embodiment of the present invention. The difference between the second embodiment of the present invention and the first embodiment is that in the first embodiment, the second end of the fourth resistor R4 directly contacts the load inductance The first terminal of L1 is connected to the signal output terminal Output; and in the second embodiment, the second terminal of the fourth resistor R4 is connected to the load inductor L1 through a filter resistor R0 and a first filter capacitor C2 The first terminal is connected to the signal output terminal Output, wherein the first terminal of the filter resistor R0 is connected to the first terminal of the load inductor L1 and the signal output terminal Output, and the second terminal of the filter resistor R0 is connected The first end of the first filter capacitor C2 and the second end of the fourth resistor R4, the second end of the first filter capacitor C2 is grounded, and the filter resistor R0 and the first filter capacitor C2 form an attenuation The network prevents the radio frequency signal from passing through, prevents the radio frequency signal output from the signal output terminal Output from flowing into the first-
請參閱第五圖，係揭示本發明實施例三，本發明的實施例三與實施例二的區別在於：在實施例二中，所述第一電阻R1的第一端直接與所述第一場效電晶體MN1的閘極和所述信號輸入端Input相連；而在實施例三中，所述第一電阻R1的第一端通過一四分之一濾波器FG和一第二濾波電容C3與所述第一場效電晶體MN1的閘極和所述信號輸入端Input相連；其中所述四分之一濾波器FG的第一端連接所述第二濾波電容C3的第一端和所述第一電阻R1的第一端， 所述第二濾波電容C3的第二端接地，所述四分之一濾波器FG的第二端連接所述第一場效電晶體MN1的閘極和所述信號輸入端Input；所述四分之一波長濾波器FG、所述第三電容C3以及所述第一電阻R1可構成一偏置濾波網路，所述偏置濾波網路可阻止從所述信號輸入端Input輸入的所述射頻信號輸入到所述第二場效電晶體MN2的源極，而使得所述二級放大電路12的增益衰減；另外所述第一電阻R1和所述第二濾波電容C3可組成低通濾波器，以濾除由所述二級放大電路12回饋回所述一級放大電路11的雜訊。 Please refer to the fifth figure, which discloses the third embodiment of the present invention. The difference between the third embodiment of the present invention and the second embodiment is that in the second embodiment, the first end of the first resistor R1 is directly connected to the first The gate of the field effect transistor MN1 is connected to the signal input terminal Input; and in the third embodiment, the first terminal of the first resistor R1 passes through a quarter filter FG and a second filter capacitor C3 Connected to the gate of the first field effect transistor MN1 and the signal input terminal Input; wherein the first end of the quarter filter FG is connected to the first end of the second filter capacitor C3 and the Describe the first end of the first resistor R1, The second end of the second filter capacitor C3 is grounded, and the second end of the quarter filter FG is connected to the gate of the first field effect transistor MN1 and the signal input terminal Input; The half-wavelength filter FG, the third capacitor C3, and the first resistor R1 may form an offset filter network, and the offset filter network may prevent the input from the signal input terminal Input The radio frequency signal is input to the source of the second field effect transistor MN2, so that the gain of the second amplifier circuit 12 is attenuated; in addition, the first resistor R1 and the second filter capacitor C3 may form a low-pass filter To filter out the noise fed back from the second-stage amplifier circuit 12 to the first-stage amplifier circuit 11.
請參閱第六圖，係揭示本發明實施例四，本發明的實施例四為一種高頻低雜訊放大器電路結構，包含一信號輸入端Input、一射頻放大電路1、一負載2以及一信號輸出端，所述信號輸出端包括一第一信號輸出端Output1和一第二信號輸出端Output2；其中所述射頻放大電路1包括級聯的一一級放大電路11和一二級放大電路12；所述一級放大電路11為單端放大電路，所述一級放大電路11包括一第一場效電晶體MN1和一第四電阻R4；所述二級放大電路12為單端放大電路，所述二級放大電路12包括一第二場效電晶體MN2、一第一電阻R1、一第二電阻R2、一第三電阻R3以及一旁路電容C1；所述負載2為一射頻電路RF輸入端的輸入一換衡器T的一初級線圈；輸入所述換衡器T的一次級線圈的第一端和第二端分別連接所述第一信號輸出端Output1和所述第二信號輸出端Output2；所述第一場效電晶體MN1的閘極連接所述信號輸入端Input和所述第一電阻R1的第一端，所述第一場效電晶體MN1的源極接地，所述第一場效電晶體MN1的汲極連接所述第四電阻R4的第一端和所述第二場效電晶體MN2的閘極，所述第四電阻R4的第二端連接所述第二場效電晶體MN2的汲極和輸入所述換衡器T的所述初級線圈的第一端；所述第一電阻R1的第二端連接所述第
二電阻R2的第一端和所述第三電阻R3的第一端；所述第三電阻R3的第二端接地，所述第二電阻R2的第二端連接所述第二場效電晶體MN2的源極和所述旁路電容C1的第一端，所述旁路電容C1的第二端接地；輸入所述換衡器T的所述初級線圈的第二端接入一直流偏置電壓信號Bias，輸入所述換衡器T的所述初級線圈的第二端連接一隔直電容Cp的第一端，所述隔直電容Cp的第二端接地。其中所述第四電阻R4的第二端可通過一濾波電阻R0和一第一濾波電容C2與輸入所述換衡器T的所述初級線圈的第一端和所述第二場效電晶體MN2的汲極相連，所述濾波電阻R0的第一端連接輸入所述換衡器T的所述初級線圈的第一端和所述第二場效電晶體MN2的汲極，所述濾波電阻R0的第二端連接所述第一濾波電容C2的第一端和所述第四電阻R4的第二端，所述第一濾波電容C2的第二端接地；所述第一電阻R1的第一端通過一四分之一濾波器FG和一第二濾波電容C3與所述第一場效電晶體MN1的閘極和所述信號輸入端Input相連；所述四分之一濾波器FG的第一端連接所述第二濾波電容C3的第一端和所述第一電阻R1的第一端，所述第二濾波電容C3的第二端接地，所述四分之一濾波器FG的第二端連接所述第一場效電晶體MN1的閘極和所述信號輸入端Input。
Please refer to the sixth figure, which discloses the fourth embodiment of the present invention. The fourth embodiment of the present invention is a high-frequency low-noise amplifier circuit structure, including a signal input terminal, an
在本發明實施例四中，初態時，即所述第一場效電晶體MN1和所述第二場效電晶體MN2無電流流過時，輸入所述換衡器T的所述初級線圈的第二端接入所述直流偏置電壓信號Bias，由於所述隔直電容Cp的作用，此時輸入所述換衡器T的所述初級線圈的第二端的電壓為所述直流偏置電壓信號Bias的電壓，使得所述第一場效電晶體MN1的汲極電壓為所述直流偏置電壓信號Bias的電壓，而此時所述第二場效電晶體MN2的源極電壓為地電壓；由於所述第一場效電晶體MN1的汲極連接所述第二場效電晶體MN2的閘極，因此此時所
述第二場效電晶體MN2的閘源電壓差為所述直流偏置電壓信號Bias的電壓值，所述第二場效電晶體MN2便導通；隨著所述第二場效電晶體MN2的通道電流流過，所述第二電阻R2與所述第三電阻R3分壓回饋至所述第一場效電晶體MN1的閘極，從而使得所述第一場效電晶體MN1導通；而隨著所述第一場效電晶體MN1的通道電流流過，所述第一場效電晶體MN1的汲極電壓降低，這樣所述第二場效電晶體MN2的閘極電壓下降，使得所述第二場效電晶體MN2的源極電壓下降，則經由所述第二電阻R2和所述第三電阻R3分壓回饋至所述第一場效電晶體MN1閘極的電壓下降，以使得所述第一場效電晶體MN1的閘極電壓維持一個定值，這樣所述射頻放大電路1便形成了穩定的直流負反饋自偏壓結構。在本發明實施例四中，輸入所述換衡器T的所述初級線圈與所述第四電阻R4組成一交流負反饋環路，所述交流負反饋環路的工作原理為：若所述第二場效電晶體MN2的閘極電壓信號上升，則經由輸入所述換衡器T的所述初級線圈與所述第四電阻R4採樣回饋至所述第二場效電晶體MN2閘極的電壓下降，以使得所述第二場效電晶體MN2的閘極電壓維持一個定值，從而使得所述射頻放大電路1具有穩定的信號增益。
In the fourth embodiment of the present invention, in the initial state, that is, when no current flows through the first field effect transistor MN1 and the second field effect transistor MN2, the first input of the primary coil of the converter T The two ends are connected to the DC bias voltage signal Bias. Due to the role of the DC blocking capacitor Cp, the voltage input to the second end of the primary coil of the converter T at this time is the DC bias voltage signal Bias Voltage, so that the drain voltage of the first field effect transistor MN1 is the voltage of the DC bias voltage signal Bias, while the source voltage of the second field effect transistor MN2 is the ground voltage; The drain of the first field effect transistor MN1 is connected to the gate of the second field effect transistor MN2.
The gate-source voltage difference of the second field effect transistor MN2 is the voltage value of the DC bias voltage signal Bias, and the second field effect transistor MN2 is turned on; as the second field effect transistor MN2 When the channel current flows, the second resistor R2 and the third resistor R3 are divided and fed back to the gate of the first field effect transistor MN1, so that the first field effect transistor MN1 is turned on; As the channel current of the first field effect transistor MN1 flows, the drain voltage of the first field effect transistor MN1 decreases, so that the gate voltage of the second field effect transistor MN2 decreases, making the When the source voltage of the second field effect transistor MN2 drops, the voltage returned to the gate of the first field effect transistor MN1 through the second resistor R2 and the third resistor R3 drops, so that The gate voltage of the first field effect transistor MN1 maintains a constant value, so that the radio
在本發明實施例四中，當所述射頻放大電路1正常工作時，即所述第一場效電晶體MN1和所述第二場效電晶體MN2導通時，此時外部之一射頻信號輸入到所述信號輸入端Input，所述射頻信號便通過所述第一場效電晶體MN1放大後輸出至所述第二場效電晶體MN2的閘極，然後所述射頻信號再經所述第二場效電晶體MN2放大後輸入至輸入所述換衡器T的所述初級線圈；由於所述隔直電容Cp的存在，對於所述射頻信號而言，輸入所述換衡器T的所述初級線圈第二端相當於接地，這樣輸入到輸入所述換衡器T的所述初級線圈的所
述射頻信號會使得所述初級線圈產生激勵電流，進而使得輸入所述換衡器T的所述次級線圈的兩端感應出一雙相射頻差分信號，所述雙相射頻差分信號從所述第一信號輸出端Output1和所述第二信號輸出端Output2輸入至所述射頻電路RF的後端電路中。
In the fourth embodiment of the present invention, when the radio
在實施例四中，所述高頻低雜訊放大器電路結構的所述負載2為所述射頻電路RF輸入端的輸入所述換衡器T的所述初級線圈，即所述高頻低雜訊放大器電路結構的所述負載2與所述射頻電路RF輸入端的輸入所述換衡器T的所述初級線圈複用，這樣所述射頻放大電路1輸出端阻抗可直接與輸入所述換衡器T進行匹配，無需再考慮為所述射頻放大電路1設計通用的50歐姆阻抗匹配電路。
In the fourth embodiment, the
請參閱第七圖，係揭示本發明實施例五，本發明的實施例五為一種高頻低雜訊放大器電路結構，包含一信號輸入端Input、一射頻放大電路1、一負載2以及一信號輸出端，所述信號輸出端包括一第一信號輸出端Output1和一第二信號輸出端Output2；其中所述射頻放大電路1包括級聯的一一級放大電路11和一二級放大電路12；所述一級放大電路11為單端放大電路，所述一級放大電路11包括一第一場效電晶體MN1和一第四電阻R4；所述二級放大電路12為差分放大電路，所述二級放大電路12包括一第二場效電晶體MN2、一第三場效電晶體MN3、一第一電阻R1、一第二電阻R2、一第三電阻R3、一第五電阻R5、一第六電阻R6、一第七電阻R7、一諧振電感L2以及一旁路電容C1；所述負載2為一負載電感L1；所述第一場效電晶體MN1的閘極連接所述信號輸入端Input和所述第一電阻R1的第一端，所述第一場效電晶體MN1的源極接地，所述第一場效電晶體MN1的汲極連接所述第四電阻R4的第一端、所述第五電阻R5
的第一端和所述第二場效電晶體MN2的閘極；所述第一電阻R1的第二端連接所述第二電阻R2的第一端和所述第三電阻R3的第一端；所述第三電阻R3的第二端接地，所述第二電阻R2的第二端連接所述第二場效電晶體MN2的源極和所述第三場效電晶體MN3的源極，所述第四電阻R4的第二端連接所述第六電阻R6的第一端和所述第七電阻R7的第一端所述，第六電阻R6的第二端連接所述第一信號輸出端Output1、所述負載電感L1的第一端和所述第二場效電晶體MN2的汲極，所述第七電阻R2的第二端連接所述第二信號輸出端Output2、所述負載電感L1的第二端和所述第三場效電晶體MN3的汲極，所述負載電感L1的中心抽頭接入一直流偏置電壓信號Bias；所述第五電阻R5的第二端連接所述第三場效電晶體MN3的閘極和所述諧振電感L2的第一端，所述諧振電感L2的第二端連接所述旁路電容C1的第一端，所述旁路電容C1的第二端接地。
Please refer to the seventh figure, which discloses the fifth embodiment of the present invention. The fifth embodiment of the present invention is a high-frequency low-noise amplifier circuit structure, including a signal input terminal, an
在本發明實施例五中，初態時，即所述第一場效電晶體MN1、所述第二場效電晶體MN2和所述第三場效電晶體MN3無電流流過時，所述負載電感L1的中心抽頭接入所述直流偏置電壓信號Bias，此時所述第一場效電晶體MN1的汲極電壓為所述直流偏置電壓信號Bias的電壓，而此時所述第二場效電晶體MN2和所述第三場效電晶體MN3的源極電壓為地電壓；由於所述第一場效電晶體MN1的汲極連接所述第二場效電晶體MN2的閘極和所述第三場效電晶體MN3的閘極，因此此時所述第二場效電晶體MN2的閘源電壓差為所述直流偏置電壓信號Bias的電壓值，所述第三場效電晶體MN3的閘源電壓差為所述直流偏置電壓信號Bias的電壓值，所述第二場效電晶體MN2和所述第三場效電晶體MN3便導通；隨著所述第二場效電晶體MN2和所述第三場效電晶體MN3的通道電流流過，所述第二電阻R2與所述第三電阻R3分壓回饋至所述第一場效電晶體
MN1的閘極，從而使得所述第一場效電晶體MN1導通，而隨著所述第一場效電晶體MN1的通道電流流過，所述第一場效電晶體MN1的汲極電壓降低，這樣所述第二場效電晶體MN2的閘極電壓和所述第三場效電晶體MN3的閘極電壓下降，使得所述第二場效電晶體MN2的源極電壓和所述第三場效電晶體MN3的源極電壓下降，則經由所述第二電阻R2和所述第三電阻R3分壓回饋至所述第一場效電晶體MN1閘極的電壓下降，以使得所述第一場效電晶體MN1閘極電壓維持一個定值，這樣所述射頻放大電路1便形成了穩定的直流負反饋自偏壓結構。在本發明實施例五中，所述負載電感L1、所述第四電阻R4、所述第六電阻R6與所述第七電阻R7組成一交流負反饋環路，所述交流負反饋環路的工作原理為：若所述第二場效電晶體MN2的閘極和所述第三場效電晶體MN3的閘極的等效交流電壓上升，則經由所述負載電感L1、所述第四電阻R4、所述第六電阻R6與所述第七電阻R7採樣回饋至所述第二場效電晶體MN2的閘極和所述第三場效電晶體MN3的閘極等效交流電壓下降，從而使得所述第二場效電晶體MN2和所述第三場效電晶體MN3的閘極等效交流電壓維持一個定值，使得所述射頻放大電路1具有穩定的信號增益。
In Embodiment 5 of the present invention, in the initial state, that is, when the first field effect transistor MN1, the second field effect transistor MN2, and the third field effect transistor MN3 have no current flowing, the load The center tap of the inductor L1 is connected to the DC bias voltage signal Bias, at this time the drain voltage of the first field effect transistor MN1 is the voltage of the DC bias voltage signal Bias, and at this time the second The source voltages of the field effect transistor MN2 and the third field effect transistor MN3 are ground voltages; since the drain of the first field effect transistor MN1 is connected to the gate of the second field effect transistor MN2 and The gate electrode of the third field effect transistor MN3, so at this time the gate source voltage difference of the second field effect transistor MN2 is the voltage value of the DC bias voltage signal Bias, the third field effect power The gate-source voltage difference of the crystal MN3 is the voltage value of the DC bias voltage signal Bias, and the second field effect transistor MN2 and the third field effect transistor MN3 are turned on; with the second field effect The channel current of the transistor MN2 and the third field effect transistor MN3 flows through, and the second resistor R2 and the third resistor R3 are divided and fed back to the first field effect transistor
The gate of MN1, so that the first field effect transistor MN1 is turned on, and as the channel current of the first field effect transistor MN1 flows, the drain voltage of the first field effect transistor MN1 decreases , So that the gate voltage of the second field effect transistor MN2 and the gate voltage of the third field effect transistor MN3 drop, so that the source voltage of the second field effect transistor MN2 and the third When the source voltage of the field effect transistor MN3 drops, the voltage feedback to the gate of the first field effect transistor MN1 drops through the second resistor R2 and the third resistor R3, so that the first The gate voltage of the field effect transistor MN1 maintains a fixed value, so that the RF amplifier circuit 1 forms a stable DC negative feedback self-bias voltage structure. In Embodiment 5 of the present invention, the load inductance L1, the fourth resistor R4, the sixth resistor R6 and the seventh resistor R7 form an AC negative feedback loop. The working principle is: if the equivalent AC voltage of the gate of the second field effect transistor MN2 and the gate of the third field effect transistor MN3 rises, then through the load inductance L1, the fourth resistance R4. The sixth resistor R6 and the seventh resistor R7 are sampled and fed back to the gate of the second field effect transistor MN2 and the gate of the third field effect transistor MN3. The gate equivalent AC voltage of the second field effect transistor MN2 and the third field effect transistor MN3 is maintained at a fixed value, so that the radio
在本發明實施例五中，所述射頻放大電路1採用兩級放大結構，因此所述射頻放大電路1具有較高的增益，可以減弱後級模組的雜訊對所述高頻低雜訊放大器電路結構的整體雜訊性能的影響，而且所述二級放大電路12為差分放大電路，具有更好的穩定性。在本發明實施例五中，當所述射頻放大電路1正常工作時，即所述第一場效電晶體MN1、所述第二場效電晶體MN2和所述第三場效電晶體MN3導通時，此時外部之一射頻信號輸入到所述信號輸入端Input，所述射頻信號通過所述第一場效電晶體MN1放大後分成兩路，分別輸出
至所述第二場效電晶體MN2的閘極和所述第三場效電晶體MN3的閘極進行放大而形成一射頻差分信號，所述射頻差分信號從所述第一信號輸出端Output1和所述第二信號輸出端Output2輸出。
In the fifth embodiment of the present invention, the
請參閱第八圖，係揭示本發明實施例六，本發明的實施例六與實施例五的區別在於：在實施例五中，所述第四電阻R4的第二端直接與所述第六電阻R6的第一端和所述第七電阻R7的第一端相連；在實施例六中，所述第四電阻R4的第二端通過一濾波電阻R0和一第一濾波電容C2與所述第六電阻R6的第一端和所述第七電阻R7的第一端相連，其中所述濾波電阻R0的第一端連接所述第六電阻R6的第一端和所述第七電阻R7的第一端，所述濾波電阻R0的第二端連接所述第一濾波電容C2的第一端和所述第四電阻R4的第二端，所述第一濾波電容C2的第二端接地，所述濾波電阻R0和所述第一濾波電容C2形成一衰減網路而阻止所述射頻信號通過，防止由所述信號輸出端Output輸出的所述射頻信號再流入所述一級放大電路11中，而使得所述一級放大電路11的增益衰減；通過調節所述衰減網路的時間常數，可調節所述射頻放大電路1的增益。 Please refer to the eighth figure, which discloses the sixth embodiment of the present invention. The difference between the sixth embodiment of the present invention and the fifth embodiment is that in the fifth embodiment, the second end of the fourth resistor R4 is directly connected to the sixth The first end of the resistor R6 is connected to the first end of the seventh resistor R7; in the sixth embodiment, the second end of the fourth resistor R4 is connected to the second resistor through a filter resistor R0 and a first filter capacitor C2 The first end of the sixth resistor R6 is connected to the first end of the seventh resistor R7, wherein the first end of the filter resistor R0 is connected to the first end of the sixth resistor R6 and the seventh resistor R7 At the first end, the second end of the filter resistor R0 is connected to the first end of the first filter capacitor C2 and the second end of the fourth resistor R4, and the second end of the first filter capacitor C2 is grounded, The filter resistor R0 and the first filter capacitor C2 form an attenuation network to prevent the radio frequency signal from passing, and prevent the radio frequency signal output by the signal output terminal Output from flowing into the first-stage amplifier circuit 11, The gain of the first-stage amplifier circuit 11 is attenuated; by adjusting the time constant of the attenuation network, the gain of the radio-frequency amplifier circuit 1 can be adjusted.
請參閱第九圖，係揭示本發明實施例七，本發明的實施例七與實施例六的區別在於：在實施例六中，所述第一電阻R1的第一端直接與所述第一場效電晶體MN1的閘極和所述信號輸入端Input相連；在實施例七中，所述第一電阻R1的第一端通過一四分之一濾波器FG和一第二濾波電容C3與所述第一場效電晶體MN1的閘極和所述信號輸入端Input相連；其中所述四分之一濾波器FG的第一端連接所述第二濾波電容C3的第一端和所述第一電阻R1的第一端，所述第二濾波電容C3的第二端接地，所述四分之一濾波器FG的第二端連接所述第一場效電晶體MN1的閘極和所述信號輸入端Input；所述四分之一波長濾波 器FG、所述第三電容C3以及所述第一電阻R1可構成一偏置濾波網路，所述偏置濾波網路可阻止所述信號輸入端Input輸入的所述射頻信號輸入到所述第二場效電晶體MN2的源極，而使得所述二級放大電路12的增益衰減；另外所述第一電阻R1和所述第二濾波電容C3可組成低通濾波器，以濾除由所述二級放大電路12回饋回所述一級放大電路11的雜訊。 Please refer to the ninth figure, which discloses the seventh embodiment of the present invention. The difference between the seventh embodiment of the present invention and the sixth embodiment is that in the sixth embodiment, the first end of the first resistor R1 is directly connected to the first The gate of the field effect transistor MN1 is connected to the signal input terminal Input; in the seventh embodiment, the first terminal of the first resistor R1 passes through a quarter filter FG and a second filter capacitor C3 The gate of the first field effect transistor MN1 is connected to the signal input terminal Input; wherein the first end of the quarter filter FG is connected to the first end of the second filter capacitor C3 and the The first end of the first resistor R1, the second end of the second filter capacitor C3 is grounded, and the second end of the quarter filter FG is connected to the gate of the first field effect transistor MN1 and all The signal input terminal Input; the quarter-wave filter The FG, the third capacitor C3, and the first resistor R1 may form an offset filter network, and the offset filter network may prevent the radio frequency signal input from the signal input terminal Input from being input to the The source of the second field effect transistor MN2 causes the gain of the second-stage amplifier circuit 12 to be attenuated; in addition, the first resistor R1 and the second filter capacitor C3 may form a low-pass filter to filter out The second-stage amplifier circuit 12 feeds back the noise of the first-stage amplifier circuit 11.
請參閱第十圖，係揭示本發明實施例八，本發明的實施例八為一種高頻低雜訊放大器電路結構，包含一信號輸入端Input、一射頻放大電路1、一負載2以及一信號輸出端，所述信號輸出端包括一第一信號輸出端Output1和所述第二信號輸出端Output2；其中所述射頻放大電路1包括級聯的一一級放大電路11和一二級放大電路12；所述一級放大電路11為單端放大電路，所述一級放大電路11包括一第一場效電晶體MN1和一第四電阻R4；所述二級放大電路12為差分放大電路，所述二級放大電路12包括一第二場效電晶體MN2、一第三場效電晶體MN3、一第一電阻R1、一第二電阻R2、一第三電阻R3、一第五電阻R5、一第六電阻R6、一第七電阻R7、一諧振電感L2以及一旁路電容C1；所述負載2為一射頻電路RF輸入端的輸入一換衡器T的一初級線圈；輸入所述換衡器T的一次級線圈的第一端和第二端分別連接所述第一信號輸出端Output1和所述第二信號輸出端Output2；所述第一場效電晶體MN1的閘極連接所述信號輸入端Input和所述第一電阻R1的第一端，所述第一場效電晶體MN1的源極接地，所述第一場效電晶體MN1的汲極連接所述第四電阻R4的第一端、所述第五電阻R5的第一端和所述第二場效電晶體MN2的閘極；所述第一電阻R1的第二端連接所述第二電阻R2的第一端和所述第三電阻R3的第一端；所述第三電阻R3的第二端接地，所述第二電阻R2的第二端連接所述第二場效電晶體MN2的源極和所述 第三場效電晶體MN3的源極，所述第四電阻R4的第二端連接所述第六電阻R6的第一端和所述第七電阻R7的第一端，所述第六電阻R6的第二端連接輸入所述換衡器T的所述初級線圈的第一端和所述第二場效電晶體MN2的汲極，所述第七電阻R7的第二端連接輸入所述換衡器T的所述初級線圈的第二端和所述第三場效電晶體MN3的汲極，輸入所述換衡器T的所述初級線圈的中心抽頭接入一直流偏置電壓信號Bias；所述第五電阻R5的第二端連接所述第三場效電晶體MN3的閘極和所述諧振電感L2的第一端，所述諧振電感L2的第二端連接所述旁路電容C1的第一端，所述旁路電容C1的第二端接地。其中所述第四電阻R4的第二端可通過一濾波電阻R0和一第一濾波電容C2與所述第六電阻R6的第一端和所述第七電阻R7的第一端相連，所述濾波電阻R0的第一端連接所述第六電阻R6的第一端和所述第七電阻R7的第一端，所述濾波電阻R0的第二端連接所述第一濾波電容C2的第一端和所述第四電阻R4的第二端，所述第一濾波電容C2的第二端接地。所述第一電阻R1的第一端可通過一四分之一濾波器FG和一第二濾波電容C3與所述第一場效電晶體MN1的閘極和所述信號輸入端Input相連；所述四分之一濾波器FG的第一端連接所述第二濾波電容C3的第一端和所述第一電阻R1的第一端，所述第二濾波電容C3的第二端接地，所述四分之一濾波器FG的第二端連接所述第一場效電晶體MN1的閘極和所述信號輸入端Input。 Please refer to the tenth figure, which discloses the eighth embodiment of the present invention. The eighth embodiment of the present invention is a high-frequency low-noise amplifier circuit structure, including a signal input terminal, an RF amplifier circuit 1, a load 2 and a signal An output terminal, the signal output terminal includes a first signal output terminal Output1 and the second signal output terminal Output2; wherein the RF amplifier circuit 1 includes a cascaded first-stage amplifier circuit 11 and a second-stage amplifier circuit 12 The first-stage amplifier circuit 11 is a single-ended amplifier circuit, and the first-stage amplifier circuit 11 includes a first field effect transistor MN1 and a fourth resistor R4; the second-stage amplifier circuit 12 is a differential amplifier circuit, the second Stage amplifier circuit 12 includes a second field effect transistor MN2, a third field effect transistor MN3, a first resistor R1, a second resistor R2, a third resistor R3, a fifth resistor R5, a sixth A resistor R6, a seventh resistor R7, a resonant inductor L2, and a bypass capacitor C1; the load 2 is a primary coil of an RF converter input to a converter T; a primary coil input to the converter T The first end and the second end are respectively connected to the first signal output terminal Output1 and the second signal output terminal Output2; the gate of the first field effect transistor MN1 is connected to the signal input terminal Input and the The first end of the first resistor R1, the source of the first field effect transistor MN1 is grounded, the drain of the first field effect transistor MN1 is connected to the first end of the fourth resistor R4, the first The first terminal of the fifth resistor R5 and the gate of the second field effect transistor MN2; the second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and the third resistor R3 The first end; the second end of the third resistor R3 is grounded, and the second end of the second resistor R2 is connected to the source of the second field effect transistor MN2 and the The source of the third field effect transistor MN3, the second end of the fourth resistor R4 is connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7, the sixth resistor R6 The second end of the input is connected to the first end of the primary coil of the converter T and the drain of the second field effect transistor MN2, and the second end of the seventh resistor R7 is connected to the input of the converter The second end of the primary coil of T and the drain of the third field effect transistor MN3 are input to the center tap of the primary coil of the converter T to receive a DC bias voltage signal Bias; The second end of the fifth resistor R5 is connected to the gate of the third field effect transistor MN3 and the first end of the resonant inductor L2, and the second end of the resonant inductor L2 is connected to the first terminal of the bypass capacitor C1 At one end, the second end of the bypass capacitor C1 is grounded. The second end of the fourth resistor R4 may be connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7 through a filter resistor R0 and a first filter capacitor C2. The first end of the filter resistor R0 is connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7, and the second end of the filter resistor R0 is connected to the first end of the first filter capacitor C2 And the second end of the fourth resistor R4, and the second end of the first filter capacitor C2 is grounded. The first terminal of the first resistor R1 may be connected to the gate of the first field effect transistor MN1 and the signal input terminal through a quarter filter FG and a second filter capacitor C3; The first end of the quarter filter FG is connected to the first end of the second filter capacitor C3 and the first end of the first resistor R1. The second end of the second filter capacitor C3 is grounded. The second end of the quarter filter FG is connected to the gate of the first field effect transistor MN1 and the signal input terminal Input.
在本發明實施例八中，初態時，即所述第一場效電晶體MN1、所述第二場效電晶體MN2和所述第三場效電晶體MN3無電流流過時，輸入所述換衡器T的所述初級線圈的中心抽頭接入一直流偏置電壓信號Bias，此時所述第一場效電晶體MN1的汲極電壓為所述直流偏置電壓信號Bias的電壓，而此時所
述第二場效電晶體MN2和所述第三場效電晶體MN3的源極電壓為地電壓；由於所述第一場效電晶體MN1的汲極連接所述第二場效電晶體MN2的閘極和所述第三場效電晶體MN3的閘極，因此此時所述第二場效電晶體MN2的閘源電壓差為所述直流偏置電壓信號Bias的電壓值，所述第三場效電晶體MN3的閘源電壓差為所述直流偏置電壓信號Bias的電壓值，所述第二場效電晶體MN2和所述第三場效電晶體MN3便導通；隨著所述第二場效電晶體MN2和所述第三場效電晶體MN3的通道電流流過，所述第二電阻R2與所述第三電阻R3分壓回饋至所述第一場效電晶體MN1的閘極，從而使得所述第一場效電晶體MN1導通，而隨著所述第一場效電晶體MN1的通道電流流過，所述第一場效電晶體MN1的汲極電壓降低，這樣所述第二場效電晶體MN2的閘極電壓和所述第三場效電晶體MN3的閘極電壓下降，使得所述第二場效電晶體MN2的源極電壓和所述第三場效電晶體MN3的源極電壓下降，則經由所述第二電阻R2和所述第三電阻R3分壓回饋至所述第一場效電晶體MN1閘極的電壓下降，以使得所述第一場效電晶體MN1閘極電壓維持一個定值，這樣所述射頻放大電路1便形成了穩定的直流負反饋自偏壓結構。在本發明實施例八中，輸入所述換衡器T的所述初級線圈、所述第四電阻R4、所述第六電阻R6與所述第七電阻R7組成一交流負反饋環路，所述交流負反饋環路的工作原理為：若所述第二場效電晶體MN2和所述第三場效電晶體MN3的閘極等效交流電壓上升，則經由輸入所述換衡器T的所述初級線圈、所述第四電阻R4、所述第六電阻R6與所述第七電阻R7採樣回饋至所述第二場效電晶體MN2和所述第三場效電晶體MN3的閘極等效交流電壓下降，從而使得所述第二場效電晶體MN2和所述第三場效電晶體MN3的閘極等效交流電壓維持一個定值，使得所述射頻放大電路1具有穩定的信號增益。
In the eighth embodiment of the present invention, in the initial state, that is, when no current flows through the first field effect transistor MN1, the second field effect transistor MN2, and the third field effect transistor MN3, the input The center tap of the primary coil of the converter T is connected to the DC bias voltage signal Bias, and at this time the drain voltage of the first field effect transistor MN1 is the voltage of the DC bias voltage signal Bias, and this Time
The source voltage of the second field effect transistor MN2 and the third field effect transistor MN3 is the ground voltage; since the drain of the first field effect transistor MN1 is connected to the second field effect transistor MN2 The gate electrode and the gate electrode of the third field effect transistor MN3, so at this time the gate source voltage difference of the second field effect transistor MN2 is the voltage value of the DC bias voltage signal Bias, the third The gate-source voltage difference of the field effect transistor MN3 is the voltage value of the DC bias voltage signal Bias, and the second field effect transistor MN2 and the third field effect transistor MN3 are turned on; The channel current of the second field effect transistor MN2 and the third field effect transistor MN3 flows, and the second resistor R2 and the third resistor R3 are divided and fed back to the gate of the first field effect transistor MN1 So that the first field effect transistor MN1 is turned on, and as the channel current of the first field effect transistor MN1 flows, the drain voltage of the first field effect transistor MN1 decreases. The gate voltage of the second field effect transistor MN2 and the gate voltage of the third field effect transistor MN3 drop, so that the source voltage of the second field effect transistor MN2 and the third field effect power When the source voltage of the crystal MN3 drops, the voltage returned to the gate of the first field effect transistor MN1 via the second resistor R2 and the third resistor R3 is divided, so that the first field effect The gate voltage of the transistor MN1 maintains a constant value, so that the
在本發明實施例八中，所述射頻放大電路1採用兩級放大結構，因此所述射頻放大電路1具有較高的增益，可以減弱後級模組的雜訊對所述高頻低雜訊放大器電路結構的整體雜訊性能的影響，而且所述二級放大電路12為差分放大電路，具有更好的穩定性。在本發明實施例八中，當所述射頻放大電路1正常工作時，即所述第一場效電晶體MN1、所述第二場效電晶體MN2和所述第三場效電晶體MN3導通時，此時外部之一射頻信號輸入到所述信號輸入端Input，所述射頻信號通過所述第一場效電晶體MN1放大後分成兩路，分別輸出至所述第二場效電晶體MN2的閘極和所述第三場效電晶體MN3的閘極進行放大而形成一射頻差分信號輸入至輸入所述換衡器T的所述初級線圈兩端，使得輸入所述換衡器T的所述初級線圈產生激勵電流，進而使得輸入所述換衡器T次級線圈的兩端感應出一雙相射頻差分信號，所述雙相射頻差分信號從所述第一信號輸出端Output1和所述第二信號輸出端Output2輸入至所述射頻電路RF的後端電路中。
In the eighth embodiment of the present invention, the
在本發明實施例八中，所述高頻低雜訊放大器電路結構的所述負載2為所述射頻電路RF輸入端的輸入所述換衡器T的所述初級線圈，即所述高頻低雜訊放大器電路結構的所述負載2與所述射頻電路RF輸入端的輸入所述換衡器T的所述初級線圈複用，這樣所述射頻放大電路1輸出端阻抗可直接與輸入所述換衡器T進行匹配，無需再考慮為所述射頻放大電路1設計通用的50歐姆阻抗匹配電路。
In the eighth embodiment of the present invention, the
綜合上述實施例之說明，當可充分瞭解本發明之操作、使用及本發明產生之功效，惟以上所述實施例僅係為本發明之較佳實施例，當不能以此 限定本發明實施之範圍，即依本發明申請專利範圍及發明說明內容所作簡單的等效變化與修飾，皆屬本發明涵蓋之範圍內。 Based on the description of the above embodiments, the operation, use and effects of the present invention can be fully understood. However, the above-mentioned embodiments are only preferred embodiments of the present invention. Limiting the scope of implementation of the present invention, that is, simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the description of the invention, are within the scope of the present invention.
(1)‧‧‧射頻放大電路 (1)‧‧‧RF amplifier circuit
(11)‧‧‧一級放大電路 (11)‧‧‧One-stage amplifier circuit
(12)‧‧‧二級放大電路 (12)‧‧‧Two-stage amplifier circuit
(2)‧‧‧負載 (2)‧‧‧load
(Bias)‧‧‧直流偏置電壓信號 (Bias)‧‧‧DC bias voltage signal
(C1)‧‧‧旁路電容 (C1)‧‧‧Bypass capacitor
(C2)‧‧‧第一濾波電容 (C2)‧‧‧First filter capacitor
(C3)‧‧‧第二濾波電容 (C3)‧‧‧Second filter capacitor
(Cp)‧‧‧隔直電容 (Cp) ‧‧‧ DC blocking capacitor
(FG)‧‧‧四分之一濾波器 (FG) ‧‧‧ quarter filter
(Input)‧‧‧信號輸入端 (Input)‧‧‧Signal input terminal
(MN1)‧‧‧第一場效電晶體 (MN1)‧‧‧First Field Effect Transistor
(MN2)‧‧‧第二場效電晶體 (MN2)‧‧‧second field effect transistor
(Output1)‧‧‧第一信號輸出端 (Output1)‧‧‧First signal output
(Output2)‧‧‧第二信號輸出端 (Output2)‧‧‧Second signal output
(R0)‧‧‧濾波電阻 (R0)‧‧‧filter resistance
(R1)‧‧‧第一電阻 (R1)‧‧‧ First resistance
(R2)‧‧‧第二電阻 (R2)‧‧‧Second resistance
(R3)‧‧‧第三電阻 (R3)‧‧‧third resistance
(R4)‧‧‧第四電阻 (R4)‧‧‧ Fourth resistance
(RF)‧‧‧射頻電路 (RF)‧‧‧RF circuit
(T)‧‧‧換衡器 (T)‧‧‧ Exchanger
Claims (12)
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387880A (en) * | 1993-10-20 | 1995-02-07 | Trw Inc. | Compact monolithic wide band HEMT low noise amplifiers with regulated self-bias |
| US7495514B2 (en) * | 2005-02-18 | 2009-02-24 | Himax Technologies Limited | Low noise amplifier |
| US8467739B2 (en) * | 2006-03-10 | 2013-06-18 | Sasidhar Vajha | Monolithic integrated transceiver |
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2019
- 2019-07-04 TW TW108123617A patent/TWI686056B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387880A (en) * | 1993-10-20 | 1995-02-07 | Trw Inc. | Compact monolithic wide band HEMT low noise amplifiers with regulated self-bias |
| US7495514B2 (en) * | 2005-02-18 | 2009-02-24 | Himax Technologies Limited | Low noise amplifier |
| US8467739B2 (en) * | 2006-03-10 | 2013-06-18 | Sasidhar Vajha | Monolithic integrated transceiver |
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