TWI684391B - 製造具有增加產量的半導體裝置模組的方法 - Google Patents
製造具有增加產量的半導體裝置模組的方法 Download PDFInfo
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- TWI684391B TWI684391B TW107125604A TW107125604A TWI684391B TW I684391 B TWI684391 B TW I684391B TW 107125604 A TW107125604 A TW 107125604A TW 107125604 A TW107125604 A TW 107125604A TW I684391 B TWI684391 B TW I684391B
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- semiconductor die
- pillars
- sacrificial material
- stack
- semiconductor
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Abstract
製造半導體裝置模組之方法可涉及在一犧牲材料中形成孔,且將一導電材料放置於該等孔中。可移除該犧牲材料以曝露該導電材料之柱。可在移除該犧牲材料之後,將一半導體晶粒堆疊放置於該等柱之至少兩者之間,該堆疊之該等半導體晶粒之一者包含一作用表面,該作用表面面向與該堆疊之該等半導體晶粒之另一者之另一作用表面之一方向相反之一方向。該等柱及該半導體晶粒堆疊可至少被橫向囊封於一囊封劑中。可在至少橫向囊封該等柱及該半導體晶粒堆疊之後,將該等半導體晶粒之該一者之接合墊電連接至對應柱。
Description
本發明大體上係關於半導體裝置模組及製造半導體裝置模組之方法。更明確言之,所揭示實施例係關於可增加產量、減少翹曲且改良可靠性之製造半導體裝置模組之方法。
在一些實施例中,製造半導體裝置模組之方法可涉及在一犧牲材料中形成孔且將一導電材料放置於該等孔中。可移除該犧牲材料以曝露該導電材料之柱。可在移除該犧牲材料之後將一半導體晶粒堆疊放置於該等柱之至少兩者之間,該堆疊之該等半導體晶粒之一者包含一作用表面,該作用表面面向與該堆疊之該等半導體晶粒之另一者之另一作用表面的一方向相反之一方向。該等柱及該半導體晶粒堆疊可至少橫向囊封於一囊封劑中。可在至少橫向囊封該等柱及該半導體晶粒堆疊之後將該等半導體晶粒之該一者之接合墊電連接至對應柱。
在其他實施例中,製造半導體裝置模組之方法可涉及在一犧牲材料中形成孔且在該等孔中形成一導電材料之柱。可移除該犧牲材料以曝露該導電材料之該等柱。可在移除該犧牲材料之後將半導體晶粒堆疊放置於各自組之對應柱之間,各堆疊包括具有彼此背離之作用表面的兩個半導體晶粒。該等柱及該等半導體晶粒堆疊可至少橫向囊封於一囊封劑中。可將至少該囊封劑之材料移除至一預定厚度。在將至少該囊封劑之材料移除至該預定厚度之後,可將各堆疊之該等半導體晶粒之一者的接合墊電連接至該各自組之該等對應柱。
在其他實施例中,半導體裝置模組可包含一重佈層及定位於該重佈層上之一第一半導體晶粒,該第一半導體晶粒之一第一作用表面面向該重佈層。一第二半導體晶粒可定位於該第一半導體晶粒上,該第二半導體晶粒之一第二作用表面背離該第一半導體晶粒。柱可經定位而橫向鄰近於該第一半導體晶粒及該第二半導體晶粒,該等柱自該重佈層延伸至至少與該第二作用表面共面之一位置。一第一囊封劑可至少橫向包圍該第一半導體晶粒、該第二半導體晶粒及該等柱。電連接件可在該第一囊封劑上方自該等柱橫向延伸至該第二半導體晶粒之該第二作用表面上之接合墊。一第二囊封劑可定位於該等電連接件上方。導電凸塊可在該重佈層之與該第一半導體晶粒相對之一側上連接至該重佈層。
在其他實施例中,系統可包含經組態以接收輸入且產生輸出之一處理器,及可操作地連接至該處理器之一半導體裝置模組。該半導體裝置模組可包含定位於重佈層上之一第一半導體晶粒,該第一半導體晶粒之一第一作用表面面向該重佈層。一第二半導體晶粒可定位於該第一半導體晶粒上,該第二半導體晶粒之一第二作用表面背離該第一半導體晶粒。柱可經定位而橫向鄰近於該第一半導體晶粒及該第二半導體晶粒,該等柱自該重佈層延伸至至少與該第二作用表面共面之一位置。一第一囊封劑可至少橫向包圍該第一半導體晶粒、該第二半導體晶粒及該等柱。電連接件可在該第一囊封劑上方自該等柱橫向延伸至該第二半導體晶粒之該第二作用表面上之接合墊。一第二囊封劑可定位於該等電連接件上方。導電凸塊可在該重佈層之與該第一半導體晶粒相對之一側上連接至該重佈層,該等導電凸塊將該半導體裝置模組可操作地連接至該處理器。
優先權主張 本申請案主張於2017年7月26日申請之名為「Methods of Making Semiconductor Device Modules With Increased Yield」之美國專利申請案序號15/660,442之申請日期的權利。
本發明中呈現之繪示並不意謂為任何特定半導體裝置、半導體裝置模組、其等之組件或製造一半導體裝置模組之一程序中之動作的實際視圖,而是僅為用以描述闡釋性實施例之理想化表示。因此,圖式不一定按比例繪製。
所揭示實施例大體上係關於可增加产量、減少翹曲且改良模組可靠性之製造半導體裝置模組之方法。更明確言之,本發明揭示製造半導體裝置模組之方法之實施例,其可涉及形成導電柱且隨後將其等曝露並連接至一半導體裝置。
參考圖1,其展示在製造一半導體裝置模組之一程序之一第一階段中之一第一中間產品100之一側視橫截面視圖。可藉由將一犧牲材料102暫時固定至一支撐基板104而形成第一中間產品100。犧牲材料102可具有例如一至少實質上均勻厚度T,如在垂直於犧牲材料102所暫時固定至之支撐基板104之一上表面106的一方向上量測。犧牲材料102可包含例如一介電材料。更明確言之,犧牲材料102可包含一光阻材料。作為一特定非限制性實例,犧牲材料102可包括一光敏材料,該光敏材料包含例如重氮萘醌及酚醛樹脂(例如,酚醛清漆樹脂)。
支撐基板104可經設計大小且經塑形以在結構上強化犧牲材料102。支撐基板104可包含例如具有足夠剛性之一材料以支撐上覆犧牲材料102。更明確言之,支撐基板104可包含例如一半導體材料或一陶瓷材料。作為一特定非限制性實例,支撐基板104可包含一玻璃材料。
犧牲材料102可藉由一暫時接合材料108固定至支撐基板104。暫時接合材料108可包含至少一第一材料110,第一材料110經組態以將犧牲材料102暫時固定至支撐基板104。第一材料110可包含例如聚合物材料。更明確言之,第一材料110可包含例如一黏著劑材料。作為一特定非限制性實例,第一材料110可包含例如一紫外光可固化或一熱可固化黏著劑材料。暫時接合材料108之第一材料110可***於犧牲材料102與支撐基板104之間。例如,第一材料110可與支撐基板104面向犧牲材料102之上表面106直接接觸。
在一些實施例中(諸如圖1中所示),暫時接合材料108進一步可包含一第二材料112,第二材料112經組態以暫時固定待在形成一半導體裝置模組之程序期間形成的另一導電材料結構。第二材料112可包含(例如)經組態以與一導電材料接合之一材料。更明確言之,第二材料112可包含(例如)氧化物、一無機材料、一金屬或金屬合金材料。作為特定非限制性實例,第二材料112可包含氧化矽、碳化物、鋁、鋁合金、銅、銅合金、金、金合金、銀、銀合金、錫或錫合金。第二材料112可係與犧牲材料102面向支撐基板104之一下表面114直接接觸。例如,第二材料112可***於第一材料110與犧牲材料102之間,如圖1中所示,或可被混合在整個第一材料110中。
可藉由(例如)將暫時接合材料108放置於支撐基板104之上表面106上並在預形成且已放置之暫時接合材料108上形成犧牲材料102來形成中間產品100。作為另一實例,可藉由在支撐基板104之上表面106上形成暫時接合材料108且使預形成量之犧牲材料102的下表面114與暫時接合材料108接觸來形成中間產品100。
中間產品100可係可縮放的。例如,中間產品100可起始用於形成一單一半導體裝置模組、一行中之多個半導體裝置模組或一陣列中之多個半導體裝置模組之一程序。
圖2係在製造半導體裝置模組之程序之一第二階段中之一第二中間產品116之一側視橫截面視圖。在第二階段期間,孔118可係形成於犧牲材料102中。孔118可自犧牲材料102之一上表面120延伸穿過犧牲材料102而至至少犧牲材料102之下表面114。孔118可係定位於預定位置中(例如,呈一預定圖案)。
各孔118之一高度H可係在(例如)約10微米與約200微米之間。更明確言之,各孔118之高度H可係在(例如)約50微米與約200微米之間。作為一特定非限制性實例,各孔118之高度H可係在(例如)約100微米與約200微米之間(例如,約150微米)。各孔118之一寬度W可係在(例如)約10微米與約90微米之間。更明確言之,各孔118之寬度W可係在(例如)約20微米與約50微米之間。
可藉由(例如)將一遮罩施覆至犧牲材料102之上表面120並藉由曝露於一預定波長的光(例如,紫外光)或藉由蝕刻而自未由遮罩覆蓋之犧牲材料102的曝露部分移除材料來形成孔118。作為額外實例,可藉由鑽孔(例如,雷射鑽孔)或經由曝露於一溶劑來形成孔118。
圖3係在製造半導體裝置模組之程序之一第三階段中之一第三中間產品122之一側視橫截面視圖。在第三階段期間,可將一導電材料124 (諸如(舉例而言)銅)放置於孔118中。例如,導電材料124可填充孔118,使得導電材料124可接觸暫時接合材料108,且導電材料124之一上表面126可與犧牲材料102之上表面120至少實質上齊平。
在其中暫時接合材料108包含第二材料112之實施例中,導電材料124可接觸至少暫時接合材料108之第二材料112且暫時固定至第二材料112。例如,導電材料124可與第二材料112接合。
可藉由例如電鍍、無電式鍍覆、濺鍍或其他程序而將導電材料124定位於孔118中。將導電材料124定位於孔118中可發生在已形成意欲存在於半導體裝置模組中之任何電連接之前,此可減小將導電材料124定位於孔118中之條件將削弱、損壞或斷開此等連接之可能性。因此,較大數量之所得半導體裝置模組可為可操作的,從而增加產量。
圖4係在製造半導體裝置模組之程序之一第四階段中之一第四中間產品128之一側視橫截面視圖。在第四階段期間,可移除犧牲材料102而曝露導電材料124之柱130。可藉由例如剝離、將犧牲材料102曝露於一溶劑、將犧牲材料102曝露於一預定波長之光(例如,紫外光)或將犧牲材料102曝露於熱而移除犧牲材料102。剩餘柱130可由暫時接合材料108固持於適當位置中。
圖5係在製造半導體裝置模組之程序之一第五階段中之一第五中間產品132之一側視橫截面視圖。在第五階段期間,可將半導體晶粒136及138之一堆疊134放置於柱130之至少兩者之間。例如,可將半導體晶粒136及138之一堆疊134放置於兩個各自組之柱130之各者之間。如圖5中所示,一給定半導體裝置模組可包含半導體晶粒136及138之多個堆疊134。例如,各半導體裝置模組最終可包含半導體晶粒136及138之兩個、四個、六個或八個堆疊134。
各堆疊134可包含至少兩個半導體晶粒136及138。例如,各堆疊134可包含定位成靠近支撐基板104之一第一半導體晶粒136,及定位於第一半導體晶粒136之與支撐基板104相對之一側上的一第二半導體晶粒138。第一半導體晶粒136之一第一作用表面140可面向支撐基板104且與暫時接合材料108接觸。第二半導體晶粒138之一第二作用表面142可面向與第一作用表面140面向之方向相反之一方向。例如,第二半導體晶粒138之第二作用表面142可定位於第二半導體晶粒138之與第一半導體晶粒136相對之一側上。可藉由將一接合材料145定位於第一半導體晶粒136與第二半導體晶粒138之間而將第一半導體晶粒136固定至第二半導體晶粒138。更明確言之,接合材料145可例如定位於第一半導體晶粒136之一第一非作用表面141與第二半導體晶粒138之一第二非作用表面143之間且與其等直接接觸。第一作用表面140及第二作用表面142之各者可包含經組態以形成電連接及操作連接的接合墊144。第一半導體晶粒136之第一作用表面140及第二半導體晶粒138之第二作用表面142可包含嵌入於其中之積體電路,該積體電路電連接至且可操作地連接至接合墊144。例如,第一半導體晶粒136、第二半導體晶粒138或第一半導體晶粒136及第二半導體晶粒138兩者可組態為一邏輯晶片或一記憶體晶片。
可使用例如此項技術中已知之一取置操作來執行對半導體晶粒136及138之堆疊134之放置。
圖6係在製造半導體裝置模組之程序之一第六階段中之一第六中間產品146之一側視橫截面視圖。在第六階段期間,可藉由例如包覆模製而將柱130及半導體晶粒136及138之堆疊134至少橫向囊封於一囊封劑148中。例如,囊封劑148可完全覆蓋至少第一半導體晶粒136之第一側表面150、第二半導體晶粒138之第二側表面152,及各柱130之側表面154。在一些實施例中,囊封劑148進一步可在第二半導體晶粒138之第二作用表面142、一或多個柱130之上表面126或兩者上方延伸。囊封劑148可包含例如一介電材料。更明確言之,囊封劑148可包含一經固化聚合物材料。囊封劑148可在結構上支撐半導體晶粒136及138之堆疊134及柱130,以及將其等固定於適當位置中。
圖7係在製造半導體裝置模組之程序之一第七階段中之一第七中間產品156之一側視橫截面視圖。在第七階段期間,可移除至少囊封劑148之材料以使囊封劑148與各第二半導體晶粒138之接合墊及各柱130之上表面126齊平。例如,可在至少實質上垂直於第二半導體晶粒138之第二作用表面142之一方向上移除囊封劑148之材料。在一些實施例中,可在第七階段期間移除柱130之一或多者的導電材料124以使各柱130之上表面126與第二半導體晶粒138之接合墊144齊平。在一些實施例中,可在第七階段期間移除接合墊144之一或多者之材料以使接合墊144與柱130之上表面126及囊封劑148齊平。例如,接合墊144之材料最初可自第二半導體晶粒138之第二作用表面142突出,且移除可使其等更靠近第二作用表面142或與第二作用表面142齊平。可藉由例如磨除(grinding away)相關材料而完成移除。
圖8係在製造半導體裝置模組之程序之一第八階段中之一第八中間產品158之一側視橫截面視圖。在第八階段期間,各第二半導體晶粒138之接合墊144可電連接至對應柱130。例如,可形成各自在囊封劑148之一中介部分上方自其對應柱130延伸至一各自接合墊144的電連接件160。可藉由例如放置或形成自柱130延伸至其等各自接合墊144之導電跡線而形成電連接件160。電連接件160可包含例如一金屬或金屬合金材料。
與將類似組態之半導體晶粒電連接至下層結構之習知方法相比,經由柱130及電連接件160電連接第二半導體晶粒138可更廉價且更可靠。例如,形成矽穿孔及形成線接合之各者花費更多時間且耗費更多資源而未產生顯著低於本文中揭示之方法的一故障率。因此,所揭示方法可節省時間且節約資源,同時維持或改良電連接之可靠性而增加產量。
在一些實施例中,一介電保護材料162 (其亦可特性化為一鈍化材料)可放置於至少電連接件160上方。例如,保護材料162可自定位於囊封劑148 (其定位成橫向鄰近於在最終將形成一給定半導體裝置模組之一周邊處的一柱130)上方、柱130及其相關聯電連接件160上方、第二半導體晶粒138之第二作用表面142上方、另一電連接件160及相關聯柱130上方的一位置延伸至囊封劑148之至少另一部分(其定位成橫向鄰近於另一柱130)。更明確言之,保護材料162可自定位於囊封劑148 (其定位成橫向鄰近於在最終將形成一給定半導體裝置模組之一周邊處的一柱130)上方、柱130及其相關聯電連接件160上方、待包含於半導體裝置模組中之半導體晶粒136及138之各堆疊134上方、另一電連接件160及相關聯柱130 (其在最終將形成給定半導體裝置模組之一相對周邊處)上方的一位置延伸至囊封劑148之至少另一部分(其定位成鄰近於在最終將形成給定半導體裝置模組之與保護材料162開始之處相對之一側上的另一柱130)。保護材料162可包含例如聚合物材料。
圖9係在製造半導體裝置模組之程序之一第九階段中之一第九中間產品164之一側視橫截面視圖。在第九階段期間,另一囊封劑166可定位於半導體晶粒136及138之堆疊134上方。例如,可將該另一囊封劑166放置於第八中間產品158 (參見圖8)之一整個曝露上部分上方,使得該另一囊封劑166可覆蓋第一囊封劑148、柱130及相關聯電連接件160、接合墊144及半導體晶粒136及138之堆疊134,以及選用保護材料162。在包含保護材料162之實施例中,該另一囊封劑166可與第一囊封劑148及保護材料162直接接觸。在缺乏保護材料162之實施例中,該另一囊封劑166可與第一囊封劑148、電連接件160及視情況柱130、接合墊144及第二半導體晶粒138之第二作用表面142之任何組合的部分直接接觸。該另一囊封劑166可包含例如一介電材料。更明確言之,該另一囊封劑166可包含例如一經固化聚合物材料。該另一囊封劑166與第一囊封劑148可為相同材料或一不同材料。
在放置另一囊封劑166之後,第九階段進一步可涉及自第一半導體晶粒136之第一作用表面140下方移除支撐基板104 (參見圖8)。例如,可削弱或移除暫時接合材料108 (參見圖8)且可使支撐基板104 (參見圖8)位移以將支撐基板104 (參見圖8)自第一半導體晶粒136之第一作用表面140及其他剩餘組件卸離。更明確言之,可藉由曝露於例如熱、光(例如,紫外光)或一溶劑而削弱或移除暫時接合材料108 (參見圖8),且可使支撐基板104 (參見圖8)橫向位移而將支撐基板104 (參見圖8)自第一半導體晶粒136之第一作用表面140及其他剩餘組件卸離。
另外,第九階段可涉及將另一支撐基板168在另一囊封劑166之與半導體晶粒136及138之堆疊134相對之一側上固定至該另一囊封劑166。例如,可在另一囊封劑166之與保護材料162相對之一側上將另一暫時接合材料170定位於該另一囊封劑166上方,且可將另一支撐基板168定位成與該另一暫時接合材料170接觸,以將該另一支撐基板168固定至該另一囊封劑166。另一支撐基板168及另一暫時接合材料170可選自先前結合第一支撐基板104及暫時接合材料108描述之材料,且可包含與用於第一支撐基板104及暫時接合材料108的實際材料相同之材料或不同之材料。接著,可倒轉由另一支撐基板168支撐之總成以進行進一步處理。
圖10係在製造半導體裝置模組之程序之一第十階段中之一第十中間產品172之一側視橫截面視圖。在第十階段期間,一重佈層174可被形成而鄰近於第一半導體晶粒136之第一作用表面140。重佈層174可經組態以將信號路由至堆疊134之半導體晶粒136及138,且自其等路由信號。例如,重佈層174可包含與第一半導體晶粒136之第一作用表面140上之接合墊144電連通的接觸件176,及與柱130電連通的其他接觸件178,此可藉由電連接件160來使接觸件178與第二半導體晶粒138之第二作用表面142上之接合墊144電連通。路由連接件180可自接觸件176及178延伸至經定位於重佈層174之與半導體晶粒136及138之堆疊134相對之一側上的接合墊182以用於輸出。可藉由將大量導電材料及介電材料選擇性地循序放置於圖9之倒轉總成上,或藉由添加一預形成之重佈層174來形成重佈層174,如此項技術中已知。
亦在第十階段期間,可將導電材料凸塊184放置於接合墊182上,以能夠將半導體晶粒136及138之堆疊134可操作地連接至另一裝置或結構(例如,較高層級封裝)。例如,凸塊184可組態為球、柱、支柱、圓柱(column)、立柱、金屬塊或經固定至接合墊182之其他大量導電材料。作為一特定非限制實例,凸塊184可包括焊料球之一球柵陣列。
圖11係由圖1至圖10之程序形成之半導體裝置模組186之一側視橫截面視圖。作為第十階段中之一最終動作,可藉由執行先前結合移除第一支撐基板104 (參見圖8)所描述之適用於另一支撐基板168及其相關聯另一暫時接合材料170的任何動作來移除另一支撐基板168 (參見圖10)。
所得半導體裝置模組186可包含一重佈層174,重佈層174包含在重佈層174之一第一側上經電連接至導電材料凸塊184的接合墊182,及重佈層之一第二相對側上的導電材料接觸件176及178。導電材料凸塊184可被固定至接合墊182。一第一組接觸件176可被固定至半導體裝置模組186中之半導體晶粒136及138之各堆疊134之一第一半導體晶粒136的接合墊144。一第二組接觸件178可被固定至柱130,柱130至少部分延伸穿過橫向包圍半導體晶粒136及138之堆疊134之一囊封劑148,柱130在至少實質上垂直於第一半導體晶粒136之一第一作用表面140之一方向上延伸。各自柱130可係經由在囊封劑148上方橫向延伸之電連接件160電連接至堆疊134之一第二半導體晶粒138的接合墊144。第二半導體晶粒138之一第二作用表面142可面向與第一作用表面140面向之一方向相反之一方向。電連接件160可係由一保護材料162覆蓋,保護材料162繼而可係由另一囊封劑166覆蓋。可藉由使凸塊184接觸對應接合墊且回焊凸塊184以形成一電連接來將半導體裝置模組186可操作地連接至另一裝置。
圖12係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第一階段中之一第一中間產品188之一側視橫截面視圖。在此實施例中,可在引入重佈層174之後添加半導體晶粒136及138之堆疊134,而非如圖5至圖10所示般在放置半導體晶粒136及138之堆疊134之後引入重佈層174。在第一階段期間,可將重佈層174固定至支撐基板104。例如,可將一預形成重佈層174放置成與支撐基板104上之暫時接合材料108接觸,或可藉由將導電材料(藉由施覆及圖案化金屬層)及介電材料(藉由施覆及圖案化以形成孔徑)選擇性地循序定位於支撐基板104上方之接合材料108上而在接合材料108上形成重佈層174。重佈層174可包含在重佈層174面向支撐基板104之一第一側上之預定位置中的接合墊182,及在重佈層174之一第二相對側上之預定位置中的接觸件176及178。路由連接件180可在接觸件176與178之間延伸且將接觸件176及178電連接至接合墊182。
圖13係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第二階段中之一第二中間產品190之一側視橫截面視圖。在第二階段期間,可將犧牲材料102在重佈層174之與支撐基板104相對之一側上定位於重佈層174上,此可藉由執行先前結合圖1描述之適用於圖13中所示之重佈層174的動作而完成。例如,犧牲材料102可覆蓋重佈層174之上表面且與接觸件176及178直接接觸。
圖14係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第三階段中之一第三中間產品192之一側視橫截面視圖。在第三階段期間,孔118可形成於犧牲材料102中。孔118可與經組態以連接至第二半導體晶粒138 (參見圖11)之接觸件178對準,使得形成孔118可曝露接觸件178。可藉由執行先前結合圖2描述之適用於圖14中所示之定位及組態的任何動作而完成形成孔118。
圖15係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第四階段中之一第四中間產品194之一側視橫截面視圖。在第四階段期間,可將導電材料124放置於孔118中。在將導電材料124放置於孔118中時,導電材料124可固定至在孔118之底部處曝露的接觸件178並且與其形成一電連接。可藉由執行先前結合圖3描述適用於圖15中所示之定位及組態的任何動作而將導電材料124放置於孔118中。
圖16係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第五階段中之一第五中間產品196之一側視橫截面視圖。在第五階段期間,可移除犧牲材料102而曝露導電材料124之柱130。移除犧牲材料102亦可曝露未由柱130覆蓋且橫向定位於柱130之組之間的重佈層174之接觸件176。可藉由執行先前結合圖4描述適用於圖16中所示之組態的任何動作而完成移除犧牲材料102。
圖17係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第六階段中之一第六中間產品198之一側視橫截面視圖。在第六階段期間,可將半導體晶粒136及138之堆疊134放置於重佈層174之接觸件176上的各自組之柱130之間。更明確言之,各堆疊134之第一半導體晶粒136之接合墊144可與重佈層174之對應接觸件176對準,可使接合墊144及接觸件176彼此接觸,且可藉由將接合墊144固定至接觸件176 (例如,藉由引入一焊料材料或藉由使接合墊144、接觸件176或兩者之一導電材料流動)而將第一半導體晶粒136機械連接且電連接至重佈層174。可藉由執行先前結合圖5描述之適用於圖17之結構及定位的任何動作而完成相對於重佈層174定位堆疊134。藉由在形成重佈層174之後放置半導體晶粒136及138之堆疊134 (例如,採取一「晶片最後」方法),方法可實現測試、組裝且使用僅已知含有可操作半導體晶粒136及138之該等堆疊134。此外,此等方法論可減小半導體晶粒136及138之電連接經歷損壞或失效之可能性,此係因為在引入堆疊134之前已發生較大比例之程序動作。
圖18係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第七階段中之一第七中間產品200之一側視橫截面視圖。在第七階段期間,半導體晶粒136及138之堆疊134以及柱130可至少橫向囊封於囊封劑148中。另外,可諸如(舉例而言)藉由研磨至一最終厚度而移除囊封劑148之一部分及視情況柱130之一或多者以及第二半導體晶粒138之接合墊144之一部分。可藉由執行先前結合圖6及圖7描述之適用於圖18之結構的任何動作而完成囊封及材料移除。
圖19係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第八階段中之一第八中間產品202之一側視橫截面視圖。在第八階段期間,可藉由形成在囊封劑148上方自給定柱130延伸至接合墊144的各自電連接件160而將柱130電連接至一對應堆疊134之第二半導體晶粒138之接合墊144。在一些實施例中,電連接件160可由一保護材料162覆蓋。可藉由執行先前結合圖8描述之適用於圖19之結構的任何動作而放置電連接件160且添加保護材料162。
圖20係在製造半導體裝置模組186 (參見圖11)之程序之另一實施例的一第九階段中之一第九中間產品204之一側視橫截面視圖。在第九階段期間,可將另一囊封劑166放置於選用保護材料162上方及電連接件160上方。可藉由執行先前結合圖9描述之適用於圖20之結構的任何動作而放置另一囊封劑166。為形成半導體裝置模組186 (參見圖11),可藉由執行先前結合圖9描述之適用於圖20之結構的任何動作而移除支撐基板104,且可藉由執行先前結合圖10描述之適用於圖20之結構的任何動作而將導電材料凸塊184放置於重佈層174之接合墊182上。
圖21係根據本發明之包含一半導體裝置模組206之一系統214之一示意性方塊圖。系統214包含一處理器208,處理器208與一或多個半導體裝置模組206 (例如,一或多個記憶體模組)、一或多個輸入裝置210及一或多個輸出裝置212電耦合。系統214可為一消費性電子裝置,諸如一桌上型電腦、一膝上型電腦、一平板電腦、一電子閱讀器、一智慧型電話或其他類型之連通裝置,以及併有一半導體裝置模組之任何類型之計算系統。半導體裝置模組206可包含一記憶體裝置(例如,第一半導體晶粒裝置136及第二半導體晶粒裝置138之一或多者),如上文論述。
根據本發明之半導體裝置模組可實現對其等併入至其中之系統的高度及寬度之更佳控制。另外,此等半導體裝置模組可減少程序變動。根據本發明之半導體裝置模組進一步可減少或消除形成矽穿孔及線接合以形成跨半導體裝置之電連接的必要性。此外,本文中描述之柱可增加處理量且維持矽穿孔及線接合之更佳信號品質。最終,模組可透過產生其等所需之處理及在將其等與一系統整合之前測試完整模組之能力兩者實現更佳品質控制。
作為一闡釋性總結,製造半導體裝置模組之方法可涉及在一犧牲材料中形成孔且將一導電材料放置於孔中。可移除犧牲材料以曝露導電材料之柱。可在移除犧牲材料之後將一半導體晶粒堆疊放置於該等柱之至少兩者之間,該堆疊之該等半導體晶粒之一者包含一作用表面,該作用表面面向與該堆疊之該等半導體晶粒之另一者之另一作用表面的一方向相反之一方向。柱及半導體晶粒堆疊可至少橫向囊封於一囊封劑中。可在至少橫向囊封柱及半導體晶粒堆疊之後將該等半導體晶粒之該一者之接合墊電連接至對應柱。
作為另一闡釋性總結,製造半導體裝置模組之方法可涉及在一犧牲材料中形成孔且在孔中形成一導電材料之柱。可移除犧牲材料以曝露導電材料之該等柱。可在移除該犧牲材料之後將半導體晶粒堆疊放置於各自組之對應柱之間,各堆疊包括具有彼此背離之作用表面的兩個半導體晶粒。柱及半導體晶粒堆疊可至少橫向囊封於一囊封劑中。可將至少囊封劑之材料移除至一預定厚度。可在將至少囊封劑之材料移除至預定厚度之後將各堆疊之半導體晶粒之一者的接合墊電連接至該各自組之對應柱。
作為又一闡釋性總結,半導體裝置模組可包含一重佈層及定位於重佈層上之一第一半導體晶粒,第一半導體晶粒之一第一作用表面面向重佈層。一第二半導體晶粒可定位於第一半導體晶粒上,第二半導體晶粒之一第二作用表面背離第一半導體晶粒。柱可定位成橫向鄰近於第一半導體晶粒及第二半導體晶粒,柱自該重佈層延伸至至少與第二作用表面共面之一位置。一第一囊封劑可至少橫向包圍第一半導體晶粒、第二半導體晶粒及柱。電連接件可在第一囊封劑上方自柱橫向延伸至第二半導體晶粒之第二作用表面上的接合墊。一第二囊封劑可定位於電連接件上方。導電凸塊可在重佈層之與第一半導體晶粒相對之一側上連接至重佈層。
作為又一闡釋性總結,系統可包含經組態以接收輸入且產生輸出之一處理器,及可操作地連接至處理器之一半導體裝置模組。半導體裝置模組可包含定位於重佈層上之一第一半導體晶粒,第一半導體晶粒之一第一作用表面面向重佈層。一第二半導體晶粒可定位於第一半導體晶粒上,第二半導體晶粒之一第二作用表面背離第一半導體晶粒。柱可定位成橫向鄰近於第一半導體晶粒及第二半導體晶粒,柱自重佈層延伸至至少與第二作用表面共面之一位置。一第一囊封劑可至少橫向包圍第一半導體晶粒、第二半導體晶粒及柱。電連接件可在第一囊封劑上方自柱橫向延伸至第二半導體晶粒之第二作用表面上的接合墊。一第二囊封劑可定位於電連接件上方。導電凸塊可在該重佈層之與第一半導體晶粒相對之一側上連接至重佈層,導電凸塊將半導體裝置模組可操作地連接至處理器。
雖然已結合圖描述某些闡釋性實施例,但一般技術者將認知且明白,本發明之範疇不限於本發明中所明確展示且描述之該等實施例。實情係,可對本發明中描述之實施例進行許多添加、刪除及修改而產生在本發明之範疇(諸如明確主張之範疇,包含合法等效物)內的實施例。另外,來自一項所揭示實施例之特徵可與另一所揭示實施例之特徵組合而仍在如發明人所預期的本發明之範疇內。
100‧‧‧第一中間產品102‧‧‧犧牲材料104‧‧‧第一支撐基板106‧‧‧支撐基板之上表面108‧‧‧暫時接合材料110‧‧‧第一材料112‧‧‧第二材料114‧‧‧犧牲材料之下表面116‧‧‧第二中間產品118‧‧‧孔120‧‧‧犧牲材料之上表面122‧‧‧第三中間產品124‧‧‧導電材料126‧‧‧導電材料之上表面/柱之上表面128‧‧‧第四中間產品130‧‧‧柱132‧‧‧第五中間產品134‧‧‧半導體晶粒堆疊136‧‧‧第一半導體晶粒/第一半導體晶粒装置138‧‧‧第二半導體晶粒/第二半導體晶粒装置140‧‧‧第一作用表面141‧‧‧第一非作用表面142‧‧‧第二作用表面143‧‧‧第二非作用表面144‧‧‧接合墊145‧‧‧接合材料146‧‧‧第六中間產品148‧‧‧第一囊封劑150‧‧‧第一側表面152‧‧‧第二側表面154‧‧‧柱之側表面156‧‧‧第七中間產品158‧‧‧第八中間產品160‧‧‧電連接件162‧‧‧保護材料164‧‧‧第九中間產品166‧‧‧囊封劑168‧‧‧支撐基板170‧‧‧暫時接合材料172‧‧‧第十中間產品174‧‧‧重佈層176‧‧‧接觸件178‧‧‧接觸件180‧‧‧路由連接件182‧‧‧接合墊184‧‧‧凸塊186‧‧‧半導體裝置模組188‧‧‧第一中間產品190‧‧‧第二中間產品192‧‧‧第三中間產品194‧‧‧第四中間產品196‧‧‧第五中間產品198‧‧‧第六中間產品200‧‧‧第七中間產品202‧‧‧第八中間產品204‧‧‧第九中間產品206‧‧‧半導體裝置模組208‧‧‧處理器210‧‧‧輸入裝置212‧‧‧輸出裝置214‧‧‧系統T‧‧‧犧牲材料之厚度
雖然本發明以特別地指出且清楚地主張特定實施例之申請專利範圍結束,但可容易在結合隨附圖式閱讀時自以下描述確定在本發明之範疇內之實施例的各種特徵及優點,其中: 圖1係在製造一半導體裝置模組之一程序之一第一階段中之一第一中間產品之一側視橫截面視圖; 圖2係在製造半導體裝置模組之程序之一第二階段中之一第二中間產品之一側視橫截面視圖; 圖3係在製造半導體裝置模組之程序之一第三階段中之一第三中間產品之一側視橫截面視圖; 圖4係在製造半導體裝置模組之程序之一第四階段中之一第四中間產品之一側視橫截面視圖; 圖5係在製造半導體裝置模組之程序之一第五階段中之一第五中間產品之一側視橫截面視圖; 圖6係在製造半導體裝置模組之程序之一第六階段中之一第六中間產品之一側視橫截面視圖; 圖7係在製造半導體裝置模組之程序之一第七階段中之一第七中間產品之一側視橫截面視圖; 圖8係在製造半導體裝置模組之程序之一第八階段中之一第八中間產品之一側視橫截面視圖; 圖9係在製造半導體裝置模組之程序之一第九階段中之一第九中間產品之一側視橫截面視圖; 圖10係在製造半導體裝置模組之程序之一第十階段中之一第十中間產品之一側視橫截面視圖; 圖11係由圖1至圖10之程序形成之半導體裝置模組之一側視橫截面視圖; 圖12係在製造如圖11中描繪之一半導體裝置模組之一程序之另一實施例的一第一階段中之一第一中間產品之一側視橫截面視圖; 圖13係在製造半導體裝置模組之程序之該另一實施例的一第二階段中之一第二中間產品之一側視橫截面視圖; 圖14係在製造半導體裝置模組之程序之該另一實施例的一第三階段中之一第三中間產品之一側視橫截面視圖; 圖15係在製造半導體裝置模組之程序之該另一實施例的一第四階段中之一第四中間產品之一側視橫截面視圖; 圖16係在製造半導體裝置模組之程序之該另一實施例的一第五階段中之一第五中間產品之一側視橫截面視圖; 圖17係在製造半導體裝置模組之程序之該另一實施例的一第六階段中之一第六中間產品之一側視橫截面視圖; 圖18係在製造半導體裝置模組之程序之該另一實施例的一第七階段中之一第七中間產品之一側視橫截面視圖; 圖19係在製造半導體裝置模組之程序之該另一實施例的一第八階段中之一第八中間產品之一側視橫截面視圖; 圖20係在製造半導體裝置模組之程序之該另一實施例的一第九階段中之一第九中間產品之一側視橫截面視圖;及 圖21係根據本發明之包含一半導體裝置模組之一系統之一示意性方塊圖。
100‧‧‧第一中間產品
102‧‧‧犧牲材料
104‧‧‧第一支撐基板
106‧‧‧支撐基板之上表面
108‧‧‧暫時接合材料
110‧‧‧第一材料
112‧‧‧第二材料
114‧‧‧犧牲材料之下表面
T‧‧‧犧牲材料之厚度
Claims (19)
- 一種製造一半導體裝置模組之方法,其包括:在一犧牲材料中形成孔;將一導電材料放置於該等孔中;移除該犧牲材料以曝露該導電材料之柱;在移除該犧牲材料之後,將一半導體晶粒堆疊放置於該等柱之至少兩者之間,該堆疊之該等半導體晶粒之一者包含一作用表面,該作用表面面向與該堆疊之該等半導體晶粒之另一者之另一作用表面之一方向相反之一方向;將該等柱及該半導體晶粒堆疊至少橫向囊封於一囊封劑中;在至少橫向囊封該等柱及該半導體晶粒堆疊之後,將該等半導體晶粒之該一者之接合墊電連接至對應柱;及將一保護材料放置在於該等接合墊與該等對應柱之間延伸的電連接件上方。
- 如請求項1之方法,進一步包括在將該等柱及該半導體晶粒堆疊至少橫向囊封於該囊封劑中之後,使一重佈層與該堆疊之該等半導體晶粒之另一者的接合墊電連通。
- 如請求項1或2之方法,其中在移除該犧牲材料之後將該半導體晶粒堆疊放置於該等對應柱之間包括:在將該等柱及該半導體晶粒堆疊至少橫向囊封於該囊封劑中之前,將該半導體晶粒堆疊放置於一重佈層上,且將 該堆疊之該等半導體晶粒之該另一者的接合墊與該重佈層的導體電連接。
- 如請求項1或2之方法,進一步包括在將該等接合墊電連接至該等對應柱之前,移除至少該囊封劑之材料以曝露該等接合墊。
- 如請求項1或2之方法,進一步包括將該保護材料囊封於另一囊封劑中。
- 如請求項1或2之方法,進一步包括在於該犧牲材料中形成該等孔之前,將該犧牲材料暫時固定至一支撐基板。
- 如請求項6之方法,其中將該犧牲材料暫時固定至該支撐基板包括:將該犧牲材料放置於一黏著劑材料上方,該黏著劑材料包括一金屬或金屬合金材料且係定位於該支撐基板上。
- 如請求項7之方法,其中將該導電材料放置於該等孔中包括:使該等導電材料與至少該金屬或金屬合金材料接觸。
- 如請求項6之方法,進一步包括在至少橫向囊封該等柱及該半導體晶粒堆疊之後,移除該支撐基板。
- 如請求項1或2之方法,進一步包括在於該犧牲材料中形成該等孔之 前,將該犧牲材料暫時固定至一重佈層。
- 如請求項10之方法,其中在該犧牲材料中形成該等孔包括:在該等孔內曝露該重佈層之電導體,且其中將該導電材料放置於該等孔中包括:將該導電材料電連接至該等孔中之該等電導體。
- 如請求項11之方法,其中移除該犧牲材料包括:曝露該重佈層之額外電導體,且其中將該半導體晶粒堆疊放置於該等對應柱之間包括:將該堆疊之該等半導體晶粒之該另一者的其他接合墊電連接至該等額外電導體。
- 如請求項6之方法,進一步包括在將該等半導體晶粒之該一者之該等接合墊電連接至該等對應柱之後,移除該支撐基板。
- 一種製造一半導體裝置模組之方法,其包括:在一犧牲材料中形成孔;在該等孔中形成一導電材料之柱;移除該犧牲材料以曝露該導電材料之該等柱;在移除該犧牲材料之後,將半導體晶粒堆疊放置於各自組之對應柱之間,各堆疊包括具有彼此背離之作用表面的兩個半導體晶粒;將該等柱及該等半導體晶粒堆疊至少橫向囊封於一囊封劑中;將至少該囊封劑之材料移除至一預定厚度;在將至少該囊封劑之材料移除至該預定厚度之後,將各堆疊之該等 半導體晶粒之一者的接合墊電連接至該各自組的該等對應柱;將一保護材料放置在於該等接合墊與該等對應柱之間延伸的電連接件上方。
- 如請求項14之方法,進一步包括在將該等柱及該等半導體晶粒堆疊至少橫向囊封於該囊封劑中之後,使一重佈層的導體與該等堆疊之至少兩者之該等半導體晶粒之另一者的接合墊電連通。
- 如請求項15之方法,其中在移除該犧牲材料之後將該等半導體晶粒堆疊放置於該等各自組之該等對應柱之間包括:在將該等柱及該等半導體晶粒堆疊至少橫向囊封於該囊封劑中之前,將至少兩個半導體晶粒堆疊放置於一重佈層上,且將該等堆疊之該至少兩者之該等半導體晶粒之該另一者的接合墊與該重佈層的該等導體電連接。
- 如請求項14或15之方法,進一步包括在於該犧牲材料中形成該等孔之前,將該犧牲材料暫時固定至一支撐基板。
- 如請求項14或15之方法,進一步包括在於該犧牲材料中形成該等孔之前,將該犧牲材料暫時固定至一重佈層。
- 如請求項18之方法,其中在該犧牲材料中形成該等孔包括:在該等孔內曝露該重佈層之電導體,且其中在該等孔中形成該導電材料之柱包括:將該等柱電連接至該等電導體。
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CN115206900B (zh) | 2023-10-24 |
US10325874B2 (en) | 2019-06-18 |
WO2019022975A1 (en) | 2019-01-31 |
US20190252342A1 (en) | 2019-08-15 |
CN110892515A (zh) | 2020-03-17 |
TW202021438A (zh) | 2020-06-01 |
TW201911985A (zh) | 2019-03-16 |
US10586780B2 (en) | 2020-03-10 |
US20190067233A1 (en) | 2019-02-28 |
US20190035755A1 (en) | 2019-01-31 |
CN115206900A (zh) | 2022-10-18 |
US10192843B1 (en) | 2019-01-29 |
TWI740352B (zh) | 2021-09-21 |
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