TWI684276B - 溝渠式功率電晶體及其製作方法 - Google Patents

溝渠式功率電晶體及其製作方法 Download PDF

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TWI684276B
TWI684276B TW108101122A TW108101122A TWI684276B TW I684276 B TWI684276 B TW I684276B TW 108101122 A TW108101122 A TW 108101122A TW 108101122 A TW108101122 A TW 108101122A TW I684276 B TWI684276 B TW I684276B
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trench
layer
gate
insulating layer
isolation
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TW108101122A
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TW202027269A (zh
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李柏賢
葉人豪
邱信諺
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力源半導體股份有限公司
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Priority to TW108101122A priority Critical patent/TWI684276B/zh
Priority to US16/567,075 priority patent/US10749006B2/en
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Publication of TW202027269A publication Critical patent/TW202027269A/zh

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Abstract

一種溝渠式功率電晶體，包含一半導體基體。該半導體基體包括至少一主動部，該至少一主動部具有一溝渠閘極結構，該溝渠閘極結構具有一自頂面向下延伸並界定出一閘極溝渠的圍壁、一由絕緣材料構成並延伸覆蓋該圍壁表面的第一隔離層、一由絕緣材料構成，填置於閘極溝渠並覆蓋第一隔離層的隔離單元、一位於該閘極溝渠的底部的屏蔽電極，及一位於該屏蔽電極上方的閘極電極。藉由隔離單元的結構設計，讓第四隔離層包覆閘極電極與屏蔽電極鄰近的周面，而可讓閘極電極與氮化物材料隔離，因此，可避免因閘極電極與氮化物接觸或是過於接近產生交互作用而影響元件特性的缺點。此外，本發明還提供製作該溝渠式功率電晶體的方法。

Description

溝渠式功率電晶體及其製作方法
本發明是有關於一種功率電晶體及其製作方法，特別是指一種溝渠式功率電晶體及其製作方法。
功率電晶體(Power MOSFET)可應用於數位電路或類比電路，因此，目前已是功率元件的主流而被廣泛應用於不同的電子元件。
功率電晶體依電流流通路徑可分為水平式及垂直式，其中，以垂直式功率電晶體而言，目前常見的則為溝渠式閘極金氧半場效電晶體(Trench Gate Power MOSFET，或UMOSFET)、V型溝槽金氧半場效電晶體(VMOSFET)，或垂直式雙擴散金氧半場效電晶體(VDMOSFET)。而再以溝渠式功率電晶體而言，由於其U型溝渠形狀可有效降低導通電阻(on-state resistance)並可改善電晶體的終端邊緣特性(edge termination characteristics)，也使溝渠式閘極金氧半場效電晶體成為高頻低壓功率元件的主流。
然而，溝渠式功率電晶體雖然可降低導通電阻，但是在阻斷模式(blocking mode)操作時，因為需承受所有流經漂移區(如N-type drift layer)的正向阻斷電壓(forward blocking voltage)，因此，為了可承受較高的正向阻斷電壓，就必須降低漂移區的摻雜濃度，但是降低漂移區的摻雜濃度又會提升元件的導通電阻，而不利於元件特性。此外，因為位於溝渠內的閘極電極的體積較大，因此，閘極-汲極電容(gate-to-drain capacitance C GD)也會較大，也會降低該溝渠式功率電晶體於高頻的靈敏度。
參閱圖1，美國專利第US5998833號公開一種可提升高頻特性以及崩潰電壓的功率電晶體。功率電晶體的每一個電晶體單元(unit cell)100包含一第一型摻雜，且具有高摻雜濃度(例如N +摻雜)的汲極層(drain layer)114、一第一型摻雜的漂移區(drift layer)112、一形成於該漂移區112，且為第二型摻雜(P-type)的井區(base layer)116、一高摻雜濃度的源極層(source layer)118、分別與該源極層118及汲極層114成歐姆接觸的源極電極128b及汲極電極130，及一溝渠結構。該溝渠結構具有相反的兩個側壁120a、一底面120b，一氧化物絕緣層125，該氧化物絕緣層125具有一介於該閘極電極127與溝渠源極電極128a之間的絕緣區125a、一閘極電極127，及一溝渠源極電極(trench-based source electrode)128a。其主要是利用溝渠源極電極128a取代部分的閘極電極，減小閘極-汲極電容(gate-to-drain capacitance C GD)，以降低元件於高頻操作時產生的干擾電流及閘極電荷，而得以在無須犧牲導通電阻的前提下，提升崩潰電壓，以及元件於高頻的切換速度。
因此，本發明的目的，即在於藉由溝渠內絕緣層的結構設計，提供另一種可提升元件的耐壓性並同時具有低導通電阻的溝渠式功率電晶體。
於是，本發明的溝渠式功率電晶體，包含一半導體基體。
該半導體基體包括一頂面，及至少一主動部。
該至少一主動部具有一溝渠閘極結構、一井區，及一源極。
該溝渠閘極結構具有一自該頂面向下延伸並界定出一閘極溝渠的圍壁、一由絕緣材料構成並延伸覆蓋該圍壁表面的第一隔離層、一由絕緣材料構成，填置於該閘極溝渠並覆蓋該第一隔離層的隔離單元、一位於該閘極溝渠的底部的屏蔽電極，及一位於該屏蔽電極上方的閘極電極。其中，該隔離單元具有一介於該頂面與該閘極溝渠的底部之間的上隔離區，及一介於該上隔離區與該閘極溝渠的底部之間的下隔離區，該下隔離區具有自該第一隔離層表面依序形成的一第二隔離層及一第三隔離層，該第二隔離層是氮化物，且該第二隔離層與該第三隔離層是由不同的絕緣材料構成，該屏蔽電極位於該下隔離區並被該第三隔離層包覆，該上隔離區具有一由絕緣材料構成，覆蓋該第一隔離層表面及該下隔離區表面，且構成材料與該第二隔離層不同的第四隔離層，該閘極電極位於該上隔離區，該閘極電極的周面被該第四隔離層包覆且頂面會自該閘極溝渠對外露出。
該井區自該頂面向下並延伸至該溝渠閘極結構。
該源極形成在該井區內，並延伸至該溝渠閘極結構。
此外，本發明的另一目的，在於提供一種溝渠式功率電晶體的製作方法。
於是，本發明該溝渠式功率電晶體的製作方法包含以下步驟。
步驟A，提供一半導體半成品，該半導體半成品包括一半導體基體、及多個自該半導體基體的頂面向下形成並定義出一閘極溝渠的圍壁。
步驟B，自該半導體基體的頂面及該等閘極溝渠的圍壁表面依序沉積一第一絕緣層、一氮化物層，以及一第二絕緣層，且該第一絕緣層與該第二絕緣層選自與該氮化物層不同的絕緣材料。
步驟C，於該等閘極溝渠填置多晶矽，接著蝕刻移除對應位於該頂面及該等閘極溝渠的圍壁表面露出的該第二絕緣層。
步驟D，蝕刻移除位於該等閘極溝渠內部分的多晶矽，再以熱氧化方式形成一層覆蓋該頂面並填置於該等閘極溝渠且覆蓋該多晶矽的第三絕緣層。
步驟E，蝕刻移除對應位於該頂面的該第三絕緣層讓該氮化物層露出，並移除部分填置於該等閘極溝渠的第三絕緣層至與該多晶矽之間具有一預定的厚度。
步驟F，蝕刻移除裸露出之氮化物層，令被該氮化物層遮覆的第一絕緣層露出。
步驟G，利用低壓化學氣相沉積，於溫度介於650℃~750℃的條件下，於該第一絕緣層、氮化物層、第二絕緣層、第三絕緣層及多晶矽露出的表面沉積形成一第四絕緣層。
步驟H，於該等閘極溝渠的第四絕緣層上沉積多晶矽，並將對應位於該頂面的第四絕緣層蝕刻移除。
步驟I，於該等閘極溝渠周圍利用離子佈植形成井區及源極，形成多個主動部，再形成一覆蓋該半導體基體的頂面及該等主動部的絕緣層，及一與該等主動部成歐姆接觸，用於將該等主動部對外電連接的導電單元。
本發明的功效在於：藉由製程及結構設計，利用在溫度介於650℃~750℃的條件下沉積形成該第四隔離層，並讓該四隔離層包覆該閘極電極與該屏蔽電極鄰近的周面，而可讓該閘極電極與氮化物材料隔離，避免因該閘極電極與氮化物接觸或是過於接近產生交互作用，造成溝渠閘極結構的誘發電荷而影響元件的特性。
在本發明被詳細描述之前，應當注意在以下的說明內容中，類似的元件是以相同的編號來表示。
參閱圖2，本發明溝渠式功率電晶體的一實施例，包含一基板2、一半導體基體3、一邊緣終端結構4、一絕緣層5，及一導電單元6。
該基板2具有一汲極電極21，及一與該汲極電極21成歐姆接觸，由半導體材料構成並具有高濃度的第一型摻雜的一汲極區22。
該半導體基體3覆蓋該汲極區22，具有一反向該基板2的頂面31、一自該汲極區22向上延伸，具有第一型摻雜，且摻雜濃度小於該汲極區22的漂移區32，及至少一個形成於該漂移區32的主動部3A。其中，該頂面31即為該漂移區32反向該汲極電極21的表面，且於圖2中是以2個主動部3A說明。要說明的是，第一型摻雜是第一導電型態摻雜，第二型摻雜則為與該第一導電型態摻雜的電性相反的第二導電型態摻雜。例如，該第一型摻雜為N型摻雜，該第二型摻雜則為P型摻雜，反之，則反。本發明的溝渠式功率電晶體可用於NMOS，亦可用在PMOS，並無特別限制。
每一個主動部3A包含一溝渠閘極結構33、一具有第二型摻雜的井區34，及一第一型摻雜的源極35。其中，該溝渠閘極結構33自該頂面31向下延伸而形成於該漂移區32，該井區34自該頂面31向下並延伸至該溝渠閘極結構33。該源極35形成在該井區34內，並延伸至該溝渠閘極結構33。
詳細的說，該溝渠閘極結構33具有一自該頂面31向下延伸並界定出一閘極溝渠的圍壁331、一延伸覆蓋該圍壁331表面的第一隔離層36、一填置於該閘極溝渠並覆蓋該第一隔離層36的隔離單元37、一位於該閘極溝渠的底部的屏蔽電極38，及一位於該屏蔽電極38上方的閘極電極39。
其中，該隔離單元37由絕緣材料構成，具有一位於該閘極溝渠332的底部的下隔離區37A，及一介於該下隔離區37A與該頂面31之間的上隔離區37B。
該下隔離區37A具有自該第一隔離層36表面依序形成的一第二隔離層371及一第三隔離層372，該第二隔離層371是由可保護該第一隔離層36並可避免該第一隔離層36氧化成長的氮化物構成。
該上隔離區37B具有一覆蓋該第一隔離層36表面及該下隔離區37A的該第二隔離層371及該第三隔離層372的表面，且由氧化物絕緣材料構成的第四隔離層373。於本實施例中，是以該第一隔離層371及該第三隔離層372是氧化矽，該第二隔離層是氮化矽，且該第四隔離層373是由溫度介於650℃~750℃的低壓化學氣相沉積方式沉積而得的氧化物(二氧化矽)，厚度約100~500 Å的材料構成為例說明。
要說明的是，該第一隔離層371及該第三隔離層372的氧化矽可以是經由不同製程方式所形成。例如，該第一隔離層371可以利用化學氣相沉積或熱氧化方式形成，結構較為緻密的氧化矽，而該第三隔離層372可以是經由熱氧化方式形成的氧化矽。由於該等膜層的製程方法為本技術領域所周知，因此不再多加贅述。
該屏蔽電極38位於該下隔離區37A並被該第三隔離層372包覆。該閘極電極39位於該上隔離區37B，其中，該閘極電極39的周面被該第四隔離層373包覆且頂面會自該閘極溝渠對外露出，該第三隔離層372於該屏蔽電極38與該閘極電極39之間具有一厚度T，且該厚度T介於2000~4000 Å。
該邊緣終端結構4環圍該等主動部3A，並位於該等主動部3A的最外圍。具有一自該頂面31向下延伸並界定出一終端溝渠的圍繞面41，一個填置於該終端溝渠並由絕緣材料構成的絕緣單元42，及一被該絕緣單元42包覆的導電部43。
絕緣單元42具有自該圍繞面41的表面依序形成的一第一阻絕層421、一第二阻絕層422，及一第三阻絕層423。其中，該第二阻絕層422是由可保護該第一阻絕層421且可避免該第一阻絕層421氧化成長的材料所構成，該第一阻絕層421與該第三阻絕層423可以選自相同或不同材料，且是由與該第二阻絕層422不同材料構成，該導電部44被該第三阻絕層423包覆。
於一些實施例中，該第一阻絕層421、第二阻絕層422，及第三阻絕層423是分別由氧化物、氮化物及氧化物所構成，於本實施例中該第一阻絕層421、第二阻絕層422，及第三阻絕層423是分別由氧化矽、氮化矽，及氧化矽為例說明。其中，該第一阻絕層421與該第三阻絕層423的氧化矽可以是經由不同製程方式所形成。例如，該第一阻絕層421可以利用化學氣相沉積或熱氧化方式形成，結構較為緻密的氧化矽，而該第三阻絕層423則可以是經由熱氧化方式形成的氧化矽。由於該等膜層的製程方法為本技術領域所周知，因此不再多加贅述。
於一些實施例中，該導電部43自鄰近該終端溝渠的底面向上延伸，且高度不小於該終端溝渠的深度的1/2。
該絕緣層5覆蓋該半導體基體3的頂面31，是由具有低介電常數的絕緣材料構成，例如磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)等。
該導電單元6設置於該絕緣層5上，經由三維佈線結構而可用於令該等主動部3A及該邊緣終端結構4對外電連接。具有多個穿過該絕緣層5與該源極35成歐姆接觸的源極導電插塞61、多個與該閘極電極39成歐姆接觸的閘極導電插塞(圖未示)、一與該導電部44成歐姆接觸的終端導電插塞62，及一形成於該絕緣層5表面，可用於分別將該等源極導電插塞61、閘極導電插塞，及終端導電插塞62電連接的導電層63。
要說明的是，氮化物雖然可於蝕刻以及熱製程的過程保護氧化矽，使其不受到後續製程的破壞及影響，而影響該閘極溝渠結構33與漂移區32之間的界面特性。然而，氮化物卻也同時會與該閘極電極39產生交互作用，而影響元件的特性，因此，本發明的溝渠式功率電晶體藉由該隔離單元37的結構設計，讓該第四隔離層373包覆該閘極電極39並令該第四隔離層373進一步界於該閘極電極39與該屏蔽電極38之間，讓該閘極電極39與氮化物材料有效隔離，避免因該閘極電極39與該第二絕緣層432接觸或是過於接近，造成氮化物與閘極電極39間交互作用產生誘發電荷，而降低該溝渠式功率電晶的操作效能及可靠度的問題。
此外，本發明該功率電晶體因可具有較高的耐壓性，因此，可提升漂移區的摻雜濃度，進而可降低導通電阻，而進一步降低元件操作的功耗。
茲將前述該實施例的製作方法配合參閱圖3~圖8，說明如下。
首先進行步驟91，提供一半導體半成品。
該步驟91是利用一般半導體磊晶及離子佈植製程方式形成具有第一型摻雜的該汲極區22及該漂移區32。接著，自該漂移區32的頂面31向下蝕刻形成多個閘極溝渠及位於該等閘極溝渠最外圍的終端溝渠。
然後，進行步驟92，於該頂面31、該等閘極溝渠的圍壁331及該終端溝渠的圍繞面41的表面沉積形成絕緣層。
詳細的說，該步驟92是自該頂面31、該等閘極溝渠的圍壁331及該終端溝渠的圍繞面41的表面依序沉積一第一絕緣層201、一氮化物層202，以及一第二絕緣層203。
要說明的是，該等溝渠的深度及該等絕緣材料的厚度是依據所欲製得的功率元件的耐壓性而有不同，而因為絕緣材料(例如半導體常用的高介電絕緣材料，如氮化矽(Si 3N 4)、氧化鋁(Al 2O 3)、氧化釔(Y 2O 3)、氧化鈦(TiO 2)、氧化鉿(HfO 2)、氧化鋯(ZrO 2)等，或是氧化矽(SiO 2))的選擇，以及溝渠的深度與絕緣材料的厚度與功率元件耐壓性之間的關係為本技術領域者所周知，因此，不再多加說明。於本實施例中，該第一絕緣層201及該第二絕緣層203均是以氧化矽為例說明，該等閘極溝渠及該終端溝渠的深度約為2~6um，該第一絕緣層201的厚度約為100 Å、該氮化物層202的厚度約為250~500 Å，且該第二絕緣層203的厚度約為1000~6000 Å。
然後，進行步驟93，於溝渠中填置多晶矽204，並蝕刻移除部分的該第二絕緣層203。
詳細的說，該步驟93是於該閘極溝渠及該終端溝渠填置多晶矽204，接著蝕刻移除對應位於該頂面31及閘極溝渠的圍壁331及該終端溝渠的圍繞面41的表面露出的該第二絕緣層203。即可得到如圖4所示之結構。
接著，進行步驟94，蝕刻移除部分多晶矽204，並形成一第三絕緣層205。
該步驟94是利用光阻保護該終端溝渠42的多晶矽204，並蝕刻移除位於該等閘極溝渠內部分的多晶矽204。令該等閘極溝渠內的多晶矽204的高度不大於該閘極溝渠深度的1/2。然後，將該光阻移除，再以熱氧化方式或低壓化學氣相沉積形成一層填置並覆蓋該終端溝渠、該等閘極溝渠及該頂面31裸露的區域的第三絕緣層205，得到如圖5所示結構。於該步驟94，該第三絕緣層205材料是以氧化矽為例，且約移除0.7~1.5um的多晶矽204。
然後，進行步驟95，蝕刻移除部分的該第三絕緣層205至與該多晶矽204之間具有一預定的厚度T。
詳細的說，該步驟95是蝕刻移除對應位於該頂面31、該終端溝渠的該第三絕緣層205，讓該氮化物層202及該終端溝渠42的多晶矽204露出，並移除部分填置於該等閘極溝渠的第三絕緣層205至與該多晶矽204之間具有預定的厚度T，而得到如圖6所示之結構。要說明的是，該厚度T可視元件需求而有所調整，於本實施例中該厚度T約為2000~4000 Å。
接著，進行步驟96，蝕刻移除部分的氮化物層202。
該步驟96是蝕刻移除裸露出之氮化物層202，令被該氮化物層202遮覆的第一絕緣層201露出，得到如圖7所示之結構。其中，配合參閱圖2，殘留在該等閘極溝渠底部的第一絕緣層201、氮化物層202、第二絕緣層203及第三絕緣層205即為共同構成如圖2所示的該第一隔離層36、第二隔離層371及第三隔離層372。而被該第二絕緣層203及第三絕緣層205包覆的多晶矽204則成為如圖2所示的屏蔽電極38。
然後，配合參閱圖8，進行步驟97，利用低壓化學氣相沉積形成一第四絕緣層206。
詳細地說，該步驟97是在溫度介於650℃~750℃的條件下，以四乙基正矽酸鹽(TEOS)為反應氣體，利用低壓化學氣相沉積方式形成覆蓋於該第一絕緣層201、氮化物層202、第二絕緣層203、第三絕緣層205及多晶矽204露出的表面的第四絕緣層206。於本實施例中該第四絕緣層206的厚度約為100~500 Å。
續參閱圖8，接著，進行步驟98，於該等閘極溝渠332沉積多晶矽207。
詳細地說，該步驟98是先於該等閘極溝渠332沉積多晶矽207，再將對應位於該頂面31的第四絕緣層206蝕刻移除，得到如圖8所示之結構。其中，再配合參閱圖2，經該步驟98蝕刻後殘留於該閘極溝渠上半部的第四絕緣層206即會構成如圖2所示的該第四隔離層373，而被該第四絕緣層206環圍的多晶矽207則成為該閘極電極39。另外，留存於該終端溝渠的第一絕緣層201、氮化物層202、第二絕緣層203，及第四絕緣層206會共同構成該絕緣單元43，而留存於該終端溝渠的多晶矽204則為成為該導電部44。而完成該等閘極溝渠結構33及邊緣終端結構4的製作。
要說明的，再參閱圖1，習知具有屏蔽電極(如圖1所示的溝渠式源極電極128a)的溝渠式功率電晶體，為了可具有較佳的元件特性，因此，在該絕緣區125a，或是在該絕緣區125a與該溝渠源極電極128a之間還需要有較低的介面陷阱電荷(interface trap charge)及介電層陷阱電荷(dielectric trap charge)，且在該閘極電極127與溝渠源極電極128a之間的絕緣區125a需要具有較高的品質且厚度要夠厚，才有辦法耐受操作時該閘極電極127與溝渠式源極電極128a之間的電位差。
而一般為了製得較厚的隔離層，以有效隔離屏蔽電極38與閘極電極39，因此，通常會利用多次熱氧化方式以得到較厚的氧化矽隔離層。然而，因為熱氧化製程溫度較高(通常介於950℃~1150℃)，因此，當熱氧化次數較多時，該等閘極溝渠的頂部區域容易因為氧化變大，導致相鄰的閘極溝渠之間的距離(mesa)變小，而使得後續製作導電插塞時與相鄰的閘極溝渠的距離過近，而影響元件的臨界電壓(threshold voltage，V th)，也容易造成製程的變異性，而不利於高密度元件的製作。因此，本案藉由溫度不大於750℃的低壓化學氣相沉積形成介於屏蔽電極38與閘極電極39之間的絕緣氧化物，不僅可解決該閘極電極39與氮化物(氮化物層202)接觸的問題，也可以避免因利用多次熱氧化製程造成相鄰的閘極溝渠距離減小的缺點。
然後，進行步驟99，進行離子佈植，完成該等主動區3A的製作。
該步驟99是於該等閘極溝渠結構33周圍形成第二型摻雜的井區34及第一型摻雜且具高摻雜濃度的源極35，完成該等主動區3A的製作。
之後，再於該半導體基體3的頂面31形成絕緣層5。
接著，於該絕緣層5對應該等源極35、閘極電極39，及該導電部44的位置形成穿孔，並經由該等穿孔對該半導體基體3進行離子佈植後再沉積金屬，以形成與該半導體積體3成歐姆接觸的源極導電插塞61、閘極導電插塞(圖未示)，及終端導電插塞62後，再形成該汲極電極21及分別與該等源極導電插塞61、閘極導電插塞，及終端導電插塞62電連接的導電層63。即可得到如圖2所示之功率電晶體。
要說明的是，該終端溝渠的多晶矽204的高度可以是跟該終端溝渠的深度相當，或是小於該終端溝渠42的深度，當該多晶矽的高度是小於該終端溝渠的深度時，則是於進行該步驟94，無須利用光阻保護該終端溝渠的多晶矽204，同時蝕刻移除該終端溝渠的多晶矽204，以減小該多晶矽204的高度即可。
此外，參閱圖9，要說明的是，於一些實施例中，該半導體基體還包含至少一介於相鄰的兩個主動部3A之間的整流結構7，該整流結構7可整合於功率金氧半場效電晶體，或單獨為溝槽式整流蕭特基二極體(Trench MOS Barrier Schottky Rectifiers - TMBS)，圖9是以該整流結構7整合於功率金氧半場效電晶體為例，具有一與該漂移區32成蕭特基接觸(Schottky contact)的蕭特基導電插塞71。藉由該整流結構7可減少該溝渠式功率電晶體於順向導通及關閉時回覆時間(recovery)的功耗。
當該半導體基體還包含如圖9所示的該整流結構7時，該步驟99則進一步形成穿過該絕緣層5並與該半導體基體3成蕭特基接觸的蕭特基導電插塞71，再利用該導電層63將該蕭特基導電插塞71對外電連接即可。
綜上所述，本發明的溝渠式功率電晶體藉由該隔離單元37的製程設計，利用低壓化學氣相沉積方式形成該第四隔離層373，避免因利用多次熱氧化製程形成後氧化層造成相鄰的閘極溝渠距離減小的缺點。此外，再配合該隔離單元37的結構設計，利用讓該第四隔離層373包覆該閘極電極39界於該閘極電極39與該屏蔽電極38之間，讓該閘極電極39與氮化物材料有效隔離。因此，可避免因該閘極電極39與該第二隔離層371接觸或是過於接近，造成氮化物與閘極電極39間交互作用產生誘發電荷，而降低該溝渠式功率電晶的操作效能及可靠度的問題。本發明該功率電晶體因可具有較高的耐壓性，因此，可提升漂移區的摻雜濃度，進而可降低導通電阻，而進一步降低元件操作的功耗，故確實能達成本發明的目的。
惟以上所述者，僅為本發明的實施例而已，當不能以此限定本發明實施的範圍，凡是依本發明申請專利範圍及專利說明書內容所作的簡單的等效變化與修飾，皆仍屬本發明專利涵蓋的範圍內。
2‧‧‧基板
41‧‧‧圍繞面
21‧‧‧汲極電極
42‧‧‧絕緣單元
22‧‧‧汲極區
421‧‧‧第一阻絕層
3‧‧‧半導體基體
422‧‧‧第二阻絕層
31‧‧‧頂面
423‧‧‧第三阻絕層
32‧‧‧漂移區
43‧‧‧導電部
3A‧‧‧主動部
5‧‧‧絕緣層
33‧‧‧溝渠閘極結構
6‧‧‧導電單元
331‧‧‧圍壁
61‧‧‧源極導電插塞
34‧‧‧井區
62‧‧‧終端導電插塞
35‧‧‧源極
63‧‧‧導電層
36‧‧‧第一隔離層
7‧‧‧整流結構
37‧‧‧隔離單元
71‧‧‧蕭特基導電插塞
37A‧‧‧下隔離區
91~99‧‧‧步驟
371‧‧‧第二隔離層
201‧‧‧第一絕緣層
372‧‧‧第三隔離層
202‧‧‧氮化物層
37B‧‧‧上隔離區
203‧‧‧第二絕緣層
373‧‧‧第四隔離層
204、207‧‧‧多晶矽
38‧‧‧屏蔽電極
205‧‧‧第三絕緣層
39‧‧‧閘極電極
206‧‧‧第四絕緣層
4‧‧‧邊緣終端結構
T‧‧‧厚度
本發明的其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中： 圖1是一側剖示意圖，說明習知溝渠式功率電晶體； 圖2是一側剖示意圖，說明本發明溝渠式功率電晶體的實施例； 圖3是一文字流程圖，說明該實施例的製作流程； 圖4是一結構示意圖，輔助說明經過步驟53形成的結構； 圖5是一結構示意圖，輔助說明經過步驟54形成的結構； 圖6是一結構示意圖，輔助說明經過步驟55形成的結構； 圖7是一結構示意圖，輔助說明經過步驟56形成的結構； 圖8是一結構示意圖，輔助說明經過步驟58形成的結構；及 圖9是一結構示意圖，說明該溝渠式功率電晶體還具有整流結構的態樣。
2‧‧‧基板
21‧‧‧汲極電極
22‧‧‧汲極區
3‧‧‧半導體基體
31‧‧‧頂面
32‧‧‧漂移區
3A‧‧‧主動部
373‧‧‧第四隔離層
38‧‧‧屏蔽電極
39‧‧‧閘極電極
4‧‧‧邊緣終端結構
41‧‧‧圍繞面
42‧‧‧絕緣單元
421‧‧‧第一絕緣層
33‧‧‧溝渠閘極結構
331‧‧‧圍壁
34‧‧‧井區
35‧‧‧源極
36‧‧‧第一隔離層
37‧‧‧隔離單元
37A‧‧‧下隔離區
371‧‧‧第二隔離層
372‧‧‧第三隔離層
37B‧‧‧上隔離區
422‧‧‧第二絕緣層
423‧‧‧第三絕緣層
43‧‧‧導電部
5‧‧‧絕緣層
6‧‧‧導電單元
61‧‧‧源極導電插塞
62‧‧‧終端導電插塞
63‧‧‧導電層
T‧‧‧厚度

Claims (10)

  1. 一種溝渠式功率電晶體，包含：一半導體基體，包括一頂面，及至少一主動部，該至少一主動部具有：一溝渠閘極結構，具有一自該頂面向下延伸並界定出一閘極溝渠的圍壁、一由絕緣材料構成並延伸覆蓋該圍壁表面的第一隔離層、一由絕緣材料構成，填置於該閘極溝渠並覆蓋該第一隔離層的隔離單元、一位於該閘極溝渠的底部的屏蔽電極，及一位於該屏蔽電極上方的閘極電極，其中，該隔離單元具有一介於該頂面與該閘極溝渠的底部之間的上隔離區，及一介於該上隔離區與該閘極溝渠的底部之間的下隔離區，該下隔離區具有自該第一隔離層表面依序形成的一第二隔離層及一第三隔離層，該第二隔離層是氮化物，且該第二隔離層與該第三隔離層是由不同的絕緣材料構成，該屏蔽電極位於該下隔離區並被該第三隔離層包覆，該上隔離區具有一由絕緣材料構成，覆蓋該第一隔離層表面及該下隔離區表面，且構成材料與該第二隔離層不同的第四隔離層，該閘極電極位於該上隔離區，該閘極電極的周面被該第四隔離層包覆且頂面會自該閘極溝渠對外露出；一井區，自該頂面向下並延伸至該溝渠閘極結構；一源極，形成在該井區內，並延伸至該溝渠閘極結構；及一環圍該至少一主動部的邊緣終端結構，具有一自該頂面向下延伸並界定出一終端溝渠的圍繞面，一個由絕緣 材料構成並填置於該終端溝渠的絕緣單元，及一被該絕緣單元包覆的導電部，該導電部自鄰近該終端溝渠的底面向上延伸，且高度不小於該終端溝渠的深度的1/2。
  2. 如請求項1所述的溝渠式功率電晶體，其中，該第三隔離層及該第四隔離層是氧化物。
  3. 如請求項1所述的溝渠式功率電晶體，其中，該第一隔離層是氧化物。
  4. 如請求項3所述的溝渠式功率電晶體，其中，該絕緣單元由絕緣材料構成，具有自該圍繞面的表面依序形成的一第一阻絕層、一第二阻絕層，及一第三阻絕層，該第二阻絕層與該第三阻絕層是由不同的絕緣材料構成，且該導電部被該第三阻絕層包覆。
  5. 如請求項4所述的溝渠式功率電晶體，其中，該第一阻絕層與該第三阻絕層是氧化物，該第二阻絕層是氮化物。
  6. 如請求項1所述的溝渠式功率電晶體，還包含一覆蓋該半導體基體的頂面的絕緣層，及一可穿過該絕緣層用於對外電連接的導電單元，該導電單元具有一與該源極成歐姆接觸的源極導電插塞、一與該閘極電極成歐姆接觸的閘極導電插塞，及一與該導電部成歐姆接觸的終端導電插塞。
  7. 如請求項1所述的溝渠式功率電晶體，其中，該半導體基體具有多個主動部，且該半導體基體還包含至少一介於相鄰的兩個主動部之間的整流結構，該整流結構具有一與該半導體基體成蕭特基接觸的蕭特基導電插塞。
  8. 一種溝渠式功率電晶體的製作方法，包含： 步驟A，提供一半導體半成品，該半導體半成品具有一半導體基體、及多個自該半導體基體的頂面向下形成並定義出一閘極溝渠的圍壁；步驟B，自該半導體基體的頂面及該等閘極溝渠的圍壁表面依序沉積一第一絕緣層、一氮化物層，以及一第二絕緣層，且該第一絕緣層與該第二絕緣層選自與該氮化物層不同的絕緣材料；步驟C，於該等閘極溝渠填置多晶矽，接著蝕刻移除對應位於該頂面及該等閘極溝渠的圍壁表面露出的該第二絕緣層；步驟D，蝕刻移除位於該等閘極溝渠內部分的多晶矽，再以熱氧化方式形成一層覆蓋該頂面並填置於該等閘極溝渠且覆蓋該多晶矽的第三絕緣層；步驟E，蝕刻移除對應位於該頂面31的該第三絕緣層讓該氮化物層露出，並移除部分填置於該等閘極溝渠的第三絕緣層至與該多晶矽之間具有一預定的厚度；步驟F，蝕刻移除裸露出之氮化物層，令被該氮化物層遮覆的第一絕緣層露出；步驟G，利用低壓化學氣相沉積，於溫度介於650℃~750℃的條件下，於該第一絕緣層、氮化物層、第二絕緣層、第三絕緣層及多晶矽露出的表面沉積形成一第四絕緣層；步驟H，於該等閘極溝渠的第四絕緣層上沉積多晶矽，並將對應位於該頂面的第四絕緣層蝕刻移除。 步驟I，於該等閘極溝渠周圍利用離子佈植形成井區及源極，形成多個主動部，再形成一覆蓋該半導體基體的頂面及該等主動部的絕緣層，及一與該等主動部成歐姆接觸，用於將該等主動部對外電連接的導電單元。
  9. 如請求項8所述溝渠式功率電晶體的製作方法，其中，該步驟A還包含一環圍該等閘極溝渠的終端溝渠，該步驟B是同時自該半導體基體的頂面、該等閘極溝渠的圍壁及該終端溝渠的圍繞面上依序沉積該第一絕緣層、該氮化物層及該第二絕緣層，該步驟C是同時於該等閘極溝渠及該終端溝渠填置多晶矽，並蝕刻移除對應位於該頂面31、該圍壁，及該圍繞面上的該第二絕緣層，該步驟D的第三絕緣層會填置並覆蓋該終端溝渠、該等閘極溝渠及該頂面31裸露的區域，該步驟E是移除對應位於該頂面31及該終端溝渠的該第三絕緣層，讓該氮化物層及該終端溝渠的多晶矽露出，該步驟I還會得到一環圍該等主動部的邊緣終端結構，且該導電單元還可用與令該邊緣終端結構對外電連接。
  10. 如請求項9所述溝渠式功率電晶體的製作方法，其中，該步驟I還進一步形成至少一位於該等閘極溝渠之間，與該半導體基體成蕭特基接觸的整流結構。
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