TWI682990B - Etching composition, etching method thereof and producing method of semiconductor substrate product - Google Patents

Etching composition, etching method thereof and producing method of semiconductor substrate product Download PDF

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TWI682990B
TWI682990B TW104106129A TW104106129A TWI682990B TW I682990 B TWI682990 B TW I682990B TW 104106129 A TW104106129 A TW 104106129A TW 104106129 A TW104106129 A TW 104106129A TW I682990 B TWI682990 B TW I682990B
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etching
etching composition
mass
substrate
layer
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TW201538688A (en
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水谷篤史
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日商富士軟片股份有限公司
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/44Compositions for etching metallic material from a metallic material substrate of different composition
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09KMATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00Etching, surface-brightening or pickling compositions
    • C09K13/04Etching, surface-brightening or pickling compositions containing an inorganic acid
    • C09K13/06Etching, surface-brightening or pickling compositions containing an inorganic acid with organic material
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/28Acidic compositions for etching iron group metals
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/30Acidic compositions for etching other metallic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

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Abstract

An etching method for a substrate is described, wherein the substrate includes NiPt and a first material including at least one of In, Al, Ga, Sb and As. The etching method applies, to the substrate, an acidic etching composition containing halide ions, and nitric acid or nitrate ions.

Description

蝕刻組成物、使用其的蝕刻方法以及半導體基板產 品的製造方法 Etching composition, etching method using the same, and semiconductor substrate production Manufacturing method

本發明是有關於一種蝕刻組成物、使用其的蝕刻方法以及半導體基板產品的製造方法。 The present invention relates to an etching composition, an etching method using the same, and a method of manufacturing a semiconductor substrate product.

積體電路的製造包括多階段的多種加工步驟。於其製造過程中,將多種材料的堆積、微影、蝕刻等重複多次。其中,金屬或金屬化合物的層的蝕刻成為重要的製程。必須對特定金屬進行選擇性蝕刻,且不腐蝕其他材料地使之殘存。要求以使包含類似金屬種類的多種層中的特定層、或腐蝕性更高的層殘留的形態來僅去除既定材料的層。半導體基板內的配線或積體電路的尺寸逐漸變小,在不會將應殘留的層(材料)腐蝕的情況下準確地進行蝕刻的重要性提高。 The manufacturing of integrated circuits includes multiple processing steps in multiple stages. In its manufacturing process, the accumulation, lithography, etching, etc. of multiple materials are repeated multiple times. Among them, the etching of the metal or metal compound layer becomes an important process. Certain metals must be selectively etched and remain without corroding other materials. It is required to remove only a layer of a predetermined material in a form in which a specific layer of a plurality of layers containing similar metal species, or a layer with a higher corrosivity remains. The size of the wiring or integrated circuit in the semiconductor substrate gradually becomes smaller, and the importance of accurately etching without corroding the layer (material) that should remain is increased.

若以場效電晶體(field effect transistor)為例來看,則伴隨其急速的微細化,強烈要求形成於源極.汲極區域的上表面的矽化物層的薄膜化或新穎材料的開發。 Taking the field effect transistor as an example, with its rapid miniaturization, it is strongly required to be formed at the source. The thinning of the silicide layer on the upper surface of the drain region or the development of novel materials.

於形成矽化物層的自對準矽化(Salicide:Self-Aligned Silicide)製程中,對形成於半導體基板上的包含矽等的源極區域及汲極區域的一部分以及附著於其上表面的金屬層進行退火。關於金屬層,應用鎢(W)、鈦(Ti)、鈷(Co)等,最近採用鎳(Ni)。藉此,可於源極.汲極電極等的上側形成低電阻的矽化物層。為了進一步的微細化,亦提出有形成添加有作為貴金屬的鉑(Pt)的NiPt矽化物層。 In the salicide (Self-Aligned Silicide) process for forming the silicide layer, a part of the source and drain regions including silicon and the like formed on the semiconductor substrate and the metal layer attached to the upper surface Perform annealing. For the metal layer, tungsten (W), titanium (Ti), cobalt (Co), etc. are used, and nickel (Ni) has recently been used. By this, can be at the source. A low-resistance silicide layer is formed on the upper side of the drain electrode and the like. For further miniaturization, it has also been proposed to form a NiPt silicide layer added with platinum (Pt) as a precious metal.

於自對準矽化步驟後,藉由蝕刻將其中殘留的金屬層去除。該蝕刻通常藉由濕式蝕刻來進行,應用鹽酸與硝酸的混合液(王水)作為其化學液。專利文獻1揭示有使用除了硝酸及鹽酸以外還添加有甲苯磺酸的化學液的例子。 After the self-aligned silicidation step, the remaining metal layer is removed by etching. This etching is usually carried out by wet etching, and a mixed solution of hydrochloric acid and nitric acid (aqua regia) is used as its chemical solution. Patent Document 1 discloses an example of using a chemical liquid to which toluenesulfonic acid is added in addition to nitric acid and hydrochloric acid.

作為電晶體的通道層的材料變化,為了提高電晶體的電子輸送特性即移動度而進行材料研究。p型金屬氧化物半導體(p-metal oxide semiconductor,pMOS)中,被認為有前途的是Ge的應用,n型金屬氧化物半導體(n-metal oxide semiconductor,pMOS)中,提出有被稱為III-V族的InGa、InGaAs、InAlAs、InP、GaP、InSb等的應用(例如參照非專利文獻1)。 As the material of the channel layer of the transistor changes, materials are studied in order to improve the electron transport characteristics of the transistor, that is, the mobility. Among the p-metal oxide semiconductors (pMOS), the application of Ge is considered to be promising. Among the n-metal oxide semiconductors (pMOS), there is a proposal called III -Application of Group V InGa, InGaAs, InAlAs, InP, GaP, InSb, etc. (for example, refer to Non-Patent Document 1).

[現有技術文獻] [Prior Art Literature] [專利文獻] [Patent Literature]

[專利文獻1]國際公開第2012/125401號 [Patent Literature 1] International Publication No. 2012/125401

[非專利文獻] [Non-patent literature]

[非專利文獻1]應用物理學會,2010年春季應用物理學 會學術講演會;東京大學,橫山正史,「確立面向最終實現互補金屬氧化物半導體(complementary metal oxide semiconductor,CMOS)電晶體的通道形成技術」 [Non-Patent Literature 1] Applied Physics Society, Spring 2010 Applied Physics Academic Lectures; Masaishi Yokoyama, University of Tokyo, "Establishment of Channel Formation Technology for Complementary Metal Oxide Semiconductor (CMOS) Transistors"

本發明的課題在於提供一種蝕刻組成物、蝕刻方法以及半導體基板產品的製造方法,所述蝕刻組成物可於含有InGaAs或InAlAs等所謂III-V族材料的層所存在的基板中,選擇性地去除包含特定金屬的層,且顯示出優異的蝕刻特性。 An object of the present invention is to provide an etching composition, an etching method, and a method for manufacturing a semiconductor substrate product, which can be selectively contained in a substrate containing a layer containing a so-called III-V group material such as InGaAs or InAlAs, selectively The layer containing the specific metal is removed, and exhibits excellent etching characteristics.

依據本發明,提供以下的手段。 According to the present invention, the following means are provided.

即,本發明為一種蝕刻方法,其是NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料(以下有時稱為III-V族材料)所存在的基板的蝕刻方法,且所述蝕刻方法將包含鹵素離子(鹵化物離子)、與硝酸或硝酸根離子的酸性蝕刻組成物應用於基板。 That is, the present invention is an etching method which is an etching method of a substrate in which NiPt and a first material containing at least one of In, Al, Ga, Sb, and As (hereinafter sometimes referred to as a group III-V material) exist. , And the etching method applies an acid etching composition containing halogen ions (halide ions), nitric acid or nitrate ions to the substrate.

於所述蝕刻方法中,較佳為酸性蝕刻組成物的鹵素離子的含量為10質量%以下,酸性蝕刻組成物更包含磺酸,或者所述酸性蝕刻組成物的含水量為50質量%以下(更佳為35質量%以下)。 In the etching method, it is preferable that the content of halogen ions of the acid etching composition is 10% by mass or less, the acid etching composition further includes sulfonic acid, or the water content of the acid etching composition is 50% by mass or less ( It is more preferably 35% by mass or less).

另外,於所述蝕刻方法中,可於所述基板上進而存在Ge,所述第一材料較佳為InGaAs、InP、InAs、AlGaSb、InSb、InAs、GaAs、InAsSb、GaSb、AlSb、AlAs、InAlAs及GaP中的至少一種,更佳為InGaAs或InAlAs。 In addition, in the etching method, Ge may be further present on the substrate, and the first material is preferably InGaAs, InP, InAs, AlGaSb, InSb, InAs, GaAs, InAsSb, GaSb, AlSb, AlAs, InAlAs At least one of GaP and InGaAs is more preferably InGaAs or InAlAs.

另外,本發明為一種酸性蝕刻組成物,其是NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻組成物,且所述酸性蝕刻組成物包含鹵素離子、與硝酸或硝酸根離子。 In addition, the present invention is an acid etching composition which is an etching composition of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present, and the acid etching composition includes Halogen ions, and nitric acid or nitrate ions.

另外,本發明為一種半導體基板產品的製造方法,其包括如下的蝕刻步驟:對含有NiPt的層以及含有第一材料的層所存在的基板,應用包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物,所述第一材料包含In、Al、Ga、Sb及As中的至少一種。 In addition, the present invention is a method for manufacturing a semiconductor substrate product, which includes the following etching step: applying an acidity including halogen ions, nitric acid or nitrate ions to a substrate where a layer containing NiPt and a layer containing a first material are present Etching the composition, the first material includes at least one of In, Al, Ga, Sb, and As.

依據本發明的蝕刻組成物、使用其的蝕刻方法以及半導體基板產品的製造方法,可於不去除III-V族材料的情況下選擇性地去除NiPt,表現出優異的蝕刻特性。 According to the etching composition of the present invention, an etching method using the same, and a method of manufacturing a semiconductor substrate product, NiPt can be selectively removed without removing a III-V group material, and exhibits excellent etching characteristics.

本發明的所述及其他特徵及優點是參照適當隨附的圖式,根據下述記載而進一步明確。 The above-mentioned and other features and advantages of the present invention will be further clarified from the following description with reference to the accompanying drawings as appropriate.

1‧‧‧金屬層(第二層) 1‧‧‧Metal layer (second layer)

2‧‧‧半導體層(第一層) 2‧‧‧semiconductor layer (first layer)

3‧‧‧矽化物層(第三層) 3‧‧‧ Silicide layer (third layer)

21‧‧‧矽基板 21‧‧‧Si substrate

22‧‧‧閘極絕緣膜 22‧‧‧Gate insulating film

23‧‧‧閘極電極 23‧‧‧Gate electrode

25‧‧‧側壁 25‧‧‧Side wall

26‧‧‧源極電極 26‧‧‧Source electrode

26A‧‧‧NiPt-Ge-Si源極電極部 26A‧‧‧NiPt-Ge-Si source electrode part

26B‧‧‧經退火的矽化物源極電極 26B‧‧‧Annealed silicide source electrode

27‧‧‧汲極電極 27‧‧‧ Drain electrode

27A‧‧‧NiPt-Ge-Si汲極電極部 27A‧‧‧NiPt-Ge-Si drain electrode part

27B‧‧‧經退火的矽化物汲極電極 27B‧‧‧Annealed silicide drain electrode

28‧‧‧NiPt膜 28‧‧‧NiPt film

圖1(a)、(b)及(c)是表示本發明的一實施形態的半導體基板的製作步驟例的示意剖面圖。 1(a), (b) and (c) are schematic cross-sectional views showing an example of a manufacturing process of a semiconductor substrate according to an embodiment of the present invention.

圖2(A)、(B)、(C)、(D)及(E)是表示本發明的一實施形態的金屬氧化物半導體(metal oxide semiconductor,MOS)電晶體的製造例的步驟圖。 2(A), (B), (C), (D), and (E) are step diagrams showing a manufacturing example of a metal oxide semiconductor (MOS) transistor according to an embodiment of the present invention.

本說明書中記載的範圍或比率的數值極限(即,其上限或下限)全部包含在內。本說明書中記載的範圍包含該範圍以內的所有中間的數值。換言之,本說明書中記載的該範圍以內的所有中間的數值被視為藉由該範圍的揭示而全部得到揭示者。多種所揭示的要素的所有可能的組合只要未特別排除,則均被視為本發明的範圍內所包含者。 The numerical limits of the ranges or ratios described in this specification (that is, the upper or lower limits thereof) are all included. The range described in this specification includes all intermediate values within the range. In other words, all intermediate values within the range described in this specification are deemed to have been disclosed by the disclosure of the range. All possible combinations of the various disclosed elements are considered to be included within the scope of the present invention unless specifically excluded.

只要無特別說明,則%為質量%。只要無特別說明,則所有溫度均於攝氏溫度(℃)下測定。 Unless otherwise specified,% means mass%. Unless otherwise specified, all temperatures are measured at degrees Celsius (°C).

首先,基於圖1(a)、(b)及(c)以及圖2(A)、(B)、(C)、(D)及(E),對本發明的蝕刻方法的較佳實施形態進行說明。 First, based on FIGS. 1(a), (b) and (c) and FIGS. 2(A), (B), (C), (D) and (E), a preferred embodiment of the etching method of the present invention is carried out Instructions.

本發明為一種蝕刻方法,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料(所謂III-V族材料,以下有時簡稱為III-V族材料)所存在的基板的蝕刻方法,所述蝕刻方法將包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物應用於基板。 The present invention is an etching method in which NiPt and a first material containing at least one of In, Al, Ga, Sb, and As (so-called III-V group material, hereinafter sometimes simply referred to as III-V group material) exist. The etching method of the substrate is applied to the substrate with an acid etching composition containing halogen ions, nitric acid or nitrate ions.

另外,所述蝕刻方法中,亦可於基板上進而存在Ge(鍺)。 In addition, in the above etching method, Ge (germanium) may be further present on the substrate.

本發明中,可於不去除III-V族材料的情況下(視情況,亦不去除Ge)選擇性地去除NiPt,可實現後述基板或半導體基板產品的性能提高或良率提高。 In the present invention, NiPt can be selectively removed without removing the III-V group material (or Ge as the case may be), and the performance or yield of the substrate or semiconductor substrate product described later can be improved.

[蝕刻步驟] [Etching step]

圖1(a)、(b)及(c)是表示蝕刻前後的半導體基板的圖。本實施形態的製造例中,於含有包含In、Al、Ga、Sb及As中的 至少一種的第一材料的半導體層(第一層)2的上表面配置有金屬層(第二層)1。 1(a), (b) and (c) are diagrams showing semiconductor substrates before and after etching. In the manufacturing example of this embodiment, the product containing In, Al, Ga, Sb, and As A metal layer (second layer) 1 is arranged on the upper surface of the semiconductor layer (first layer) 2 of at least one first material.

半導體層(第一層)2可列舉源極電極、汲極電極、通道摻雜層,該些較佳為包含III-V族材料或Ge(鍺)。III-V族材料(第一材料)較佳為InGaAs、InP、InAs、AlGaSb、InSb、InAs、GaAs、InAsSb、GaSb、AlSb、AlAs、InAlAs及GaP中的至少一種,更佳為InGaAs或InAlAs。本發明中,可不去除所述第一材料或者其矽化物,而是選擇性地去除其他金屬,因此可實現後述基板或半導體基板產品的性能提高或良率提高。 The semiconductor layer (first layer) 2 may include a source electrode, a drain electrode, and a channel doped layer, and these preferably include group III-V materials or Ge (germanium). The group III-V material (first material) is preferably at least one of InGaAs, InP, InAs, AlGaSb, InSb, InAs, GaAs, InAsSb, GaSb, AlSb, AlAs, InAlAs, and GaP, more preferably InGaAs or InAlAs. In the present invention, the first material or its silicide may not be removed, but other metals may be selectively removed, so that the performance or yield of the substrate or semiconductor substrate product described later can be improved.

金屬層(第二層)1的構成材料可列舉:鈦(Ti)、鈷(Co)、鎳(Ni)、鎳鉑(NiPt)、鎢(W)、鉭(Ta)、鈮(Nb)等金屬種類(單一金屬或者複合金屬),近年來,就低接觸電阻的觀點而言,採用NiPt。金屬層1的形成可使用通常應用於此種金屬膜的形成的方法,具體而言,可列舉藉由化學氣相沈積(Chemical Vapor Deposition,CVD)進行的成膜。此時的金屬層1的厚度並無特別限定,可列舉5nm以上、50nm以下的膜的例子。本發明中,為了發揮本發明的蝕刻組成物的選擇去除的效果,較佳為金屬層1為NiPt層(Pt含有率較佳為超過0質量%且為20質量%以下)、Ni層(Pt含有率為0質量%)。 The constituent materials of the metal layer (second layer) 1 include titanium (Ti), cobalt (Co), nickel (Ni), nickel platinum (NiPt), tungsten (W), tantalum (Ta), niobium (Nb), etc. As the metal type (single metal or composite metal), in recent years, NiPt has been adopted from the viewpoint of low contact resistance. For the formation of the metal layer 1, a method generally applied to the formation of such a metal film can be used, and specifically, a film formation by chemical vapor deposition (Chemical Vapor Deposition, CVD) can be cited. The thickness of the metal layer 1 at this time is not particularly limited, and examples of films of 5 nm or more and 50 nm or less can be cited. In the present invention, in order to exert the selective removal effect of the etching composition of the present invention, it is preferable that the metal layer 1 is a NiPt layer (Pt content rate is preferably more than 0% by mass and 20% by mass or less), and a Ni layer (Pt The content rate is 0% by mass).

金屬層1除了包含所述列舉的金屬原子以外,亦可包含其他元素。例如,不可避免地混入的氧或氮亦可存在。不可避免的雜質的量較佳為抑制在例如1ppt~10ppm(質量基準)左右。 The metal layer 1 may contain other elements in addition to the metal atoms listed above. For example, inevitably mixed oxygen or nitrogen may also be present. The amount of inevitable impurities is preferably suppressed to about 1 ppt to 10 ppm (mass basis), for example.

所述步驟(a)中,於半導體層2(含III-V族材料的層)的上側形成金屬層1後,進行退火(燒結),於其界面上形成金屬-Si反應膜(第三層:矽化物層)3(步驟(b))。退火只要根據通常應用於製造此種元件的條件即可,例如可列舉於200℃~1000℃下進行處理。此時的矽化物層3的厚度並無特別限定,可列舉設為50nm以下的層的例子,進而可列舉設為10nm以下的層的例子。下限值並不特別存在,實際上為1nm以上。該矽化物層3被用作低電阻膜,作為將位於其下部的源極電極、汲極電極與配置於其上部的配線進行電性連接的導電部而發揮功能。因此,若矽化物層3中產生缺損或腐蝕,則阻礙其導通,有時會導致元件誤動作等的品質下降。尤其是如今,基板內部的積體電路結構微細化,即便是微小的損傷,亦可能對元件的性能造成大的影響。因此,理想的是儘可能防止此種缺損或腐蝕。 In the step (a), after the metal layer 1 is formed on the upper side of the semiconductor layer 2 (layer containing III-V materials), annealing (sintering) is performed to form a metal-Si reaction film (third layer) on the interface : Silicide layer) 3 (step (b)). Annealing may be performed according to conditions generally used for manufacturing such devices, and examples include treatment at 200°C to 1000°C. At this time, the thickness of the silicide layer 3 is not particularly limited, and examples of the layer being 50 nm or less can be cited, and further examples of the layer being 10 nm or less can be cited. The lower limit value does not particularly exist, and is actually 1 nm or more. The silicide layer 3 is used as a low-resistance film, and functions as a conductive portion that electrically connects the source electrode and the drain electrode located below the source electrode and the wiring disposed above. Therefore, if a defect or corrosion occurs in the silicide layer 3, its conduction is hindered, and the quality of the device such as malfunction of the device may be degraded. Especially nowadays, the integrated circuit structure inside the substrate is miniaturized, and even slight damage may have a great influence on the performance of the device. Therefore, it is desirable to prevent such defects or corrosion as much as possible.

此外,本說明書中,在廣義上,矽化物層3為包含於第一層的半導體層2(含III-V族材料的層)中的概念。因此,當相對於第一層,將第二層選擇性地去除時,是指不僅包含相對於未經矽化物化的半導體層2(含III-V族材料的層)而將第二層(金屬層)1優先去除的態樣,而且包含相對於矽化物層3而將第二層(金屬層)1優先去除的態樣的含義。 In addition, in this specification, in a broad sense, the silicide layer 3 is a concept included in the semiconductor layer 2 (layer containing III-V material) of the first layer. Therefore, when the second layer is selectively removed relative to the first layer, it means that the second layer (metal) is not only contained relative to the unsilicided semiconductor layer 2 (layer containing III-V materials). Layer 1) is preferentially removed, and includes the meaning of preferentially removing the second layer (metal layer) 1 relative to the silicide layer 3.

繼而,對殘存的金屬層1進行蝕刻(步驟(b)->步驟(c))。本實施形態中,此時應用蝕刻組成物,自金屬層1的上側賦予蝕刻組成物而使其接觸,藉此去除金屬層1。 Then, the remaining metal layer 1 is etched (step (b)->step (c)). In the present embodiment, an etching composition is applied at this time, and the etching composition is applied from the upper side of the metal layer 1 and brought into contact, thereby removing the metal layer 1.

半導體層2(含III-V族材料的層)包含磊晶層,可藉由化學氣相成長(CVD)法,於具有特定結晶性的矽基板上進行結晶成長而形成。或者亦可藉由電子束磊晶(分子束磊晶(Molecular Beam Epitaxy,MBE))法等,製成以所需的結晶性形成的磊晶層。 The semiconductor layer 2 (layer containing III-V materials) includes an epitaxial layer, which can be formed by crystal growth on a silicon substrate having a specific crystallinity by a chemical vapor growth (CVD) method. Alternatively, an electron beam epitaxy (Molecular Beam Epitaxy (Molecular Beam Epitaxy, MBE)) method or the like can be used to form an epitaxial layer formed with desired crystallinity.

將半導體層2(含III-V族材料的層)設為P型層時,摻雜濃度為1×1014cm-3~1×1021cm-3左右的硼(B)。設為N型層時,以1×1014cm-3~1×1021cm-3的濃度摻雜磷(P)。 When the semiconductor layer 2 (layer containing a III-V material) is a P-type layer, boron (B) has a doping concentration of about 1×10 14 cm −3 to 1×10 21 cm −3 . When the N-type layer is used, phosphorus (P) is doped at a concentration of 1×10 14 cm −3 to 1×10 21 cm −3 .

經過自對準矽化步驟,在所述半導體層(第一層)2與金屬層(第二層)1之間形成含有兩者的元素的層作為矽化物層3。該矽化物層3在廣義上包含於所述第一層中,但在狹義上與其區別稱呼時稱為「第三層」。其組成並無特別限定,是由InxGayAszMp(M:金屬元素)的式子所表示。此時,作為x+y+z+p=1,x較佳為0.05以上、0.80以下,y較佳為0.05以上、0.40以下,z較佳為0.01以上、0.60以下,p較佳為0.05以上、0.70以下。其中,第三層中亦可包含其他元素。這與所述金屬層(第二層)1中所描述的相同。 After the self-aligned silicidation step, a layer containing both elements is formed as the silicide layer 3 between the semiconductor layer (first layer) 2 and the metal layer (second layer) 1. The silicide layer 3 is included in the first layer in a broad sense, but it is called a "third layer" when it is distinguished from it in a narrow sense. The composition is not particularly limited, and it is represented by the formula of In x Ga y As z M p (M: metal element). At this time, as x+y+z+p=1, x is preferably 0.05 or more and 0.80 or less, y is preferably 0.05 or more and 0.40 or less, z is preferably 0.01 or more and 0.60 or less, and p is preferably 0.05 or more , Below 0.70. Among them, the third layer may also contain other elements. This is the same as described in the metal layer (second layer) 1.

此外,各元素的濃度設為利用以下的測定方法來測定的值。具體而言,對於基板,利用蝕刻化學分析電子能譜儀(Electron Spectroscopy for Chemical Analysis,ESCA)(日本真空(Ulvac-phi)製造,克安太拉(Quantera)),於0nm~30nm為止的深度方向上進行分析,將3nm~15nm分析結果中的Ge濃度的平均值作為元素濃度(質量%)。 In addition, the concentration of each element is a value measured by the following measurement method. Specifically, for the substrate, using an Electron Spectroscopy for Chemical Analysis (ESCA) (manufactured by Ulvac-phi, Quantera), at a depth of 0 nm to 30 nm The analysis was performed in the direction, and the average value of the Ge concentration in the analysis results of 3 nm to 15 nm was taken as the element concentration (mass %).

(MOS電晶體的加工) (Processing of MOS transistor)

III-V族化合物半導體具有極高的電子遷移率,因此被期待作為下一代MOS電晶體材料。使用III-V族化合物半導體的邏輯MOS電晶體或可進行超低電壓動作的量子穿隧電晶體的開發正在進行。 Group III-V compound semiconductors have extremely high electron mobility and are therefore expected to be the next-generation MOS transistor material. The development of logic MOS transistors using III-V compound semiconductors or quantum tunneling transistors capable of ultra-low voltage operation is in progress.

圖2(A)、(B)、(C)、(D)及(E)是表示MOS電晶體的製造例的步驟圖。圖2(A)為MOS電晶體結構的形成步驟,圖2(B)為金屬膜的濺鍍步驟,圖2為(C)第一次的退火步驟,圖2(D)為金屬膜的選擇去除步驟,圖2(E)為第二次的退火步驟。 2(A), (B), (C), (D), and (E) are step diagrams showing a manufacturing example of a MOS transistor. Figure 2(A) is the step of forming the MOS transistor structure, Figure 2(B) is the sputtering step of the metal film, Figure 2 is (C) the first annealing step, and Figure 2(D) is the selection of the metal film Removal step, Figure 2(E) is the second annealing step.

如圖所示,介隔形成於矽基板21的表面的閘極絕緣膜22而形成閘極電極23。亦可於閘極電極23的兩側另外形成外延(extension)區域。亦可於閘極電極23的上側形成有防止與NiPt層的接觸的保護層(未圖示)。進而,形成有包含矽氧化膜或者矽氮化膜的側壁25,藉由離子注入而形成有源極區域26以及汲極區域27。 As shown in the figure, the gate electrode 23 is formed via the gate insulating film 22 formed on the surface of the silicon substrate 21. Extension regions may be additionally formed on both sides of the gate electrode 23. A protective layer (not shown) for preventing contact with the NiPt layer may be formed on the upper side of the gate electrode 23. Furthermore, a side wall 25 including a silicon oxide film or a silicon nitride film is formed, and the source region 26 and the drain region 27 are formed by ion implantation.

繼而,如圖所示,形成NiPt膜28,實施急速退火處理。於矽基板上,存在包含氧化矽或氧化鋁的絕緣膜以及III-V族材料層或Ge。藉由退火,使NiPt膜28中的元素於矽基板中擴散而進行矽化物化。其結果為,源極電極26以及汲極電極27的上部經矽化物化,形成NiPt-III-V族材料-Si源極電極部26A以及NiPt-III-V族材料-Si汲極電極部27A。此外,根據矽基板的部位,形成NiPt-Ge-Si源極電極部26A以及NiPt-Ge-Si汲極電極部27A。此 時,視需要如圖2(E)所示般進行第二次的退火,藉此可使電極構件變化為所需的狀態(經退火的矽化物源極電極26B、經退火的矽化物汲極電極27B)。所述第一次與第二次的退火溫度並無特別限定,例如可於400℃~1100℃下進行。 Then, as shown in the figure, a NiPt film 28 is formed, and a rapid annealing process is performed. On the silicon substrate, there is an insulating film containing silicon oxide or aluminum oxide and a group III-V material layer or Ge. By annealing, the elements in the NiPt film 28 are diffused in the silicon substrate to be silicided. As a result, the upper portions of the source electrode 26 and the drain electrode 27 are silicided to form a NiPt-III-V material-Si source electrode portion 26A and a NiPt-III-V material-Si drain electrode portion 27A. In addition, the NiPt-Ge-Si source electrode portion 26A and the NiPt-Ge-Si drain electrode portion 27A are formed according to the position of the silicon substrate. this When necessary, the second annealing is performed as shown in FIG. 2(E), thereby changing the electrode member to a desired state (annealed silicide source electrode 26B, annealed silicide drain Electrode 27B). The annealing temperature of the first time and the second time is not particularly limited, for example, it can be performed at 400°C to 1100°C.

無助於矽化物化而殘留的NiPt膜28可藉由使用本發明的蝕刻組成物而去除(圖2(C)、(D))。此時,圖示者是大幅地示意化來表示,堆積於經矽化物化的層(26A、27A)的上部而殘留的NiPt膜可存在,亦可不存在。半導體基板或其產品的結構亦簡略化地圖示,視需要只要以具有必要構件者的形式來解釋即可。 The NiPt film 28 remaining without contributing to silicidation can be removed by using the etching composition of the present invention (FIG. 2(C), (D)). At this time, the figure shows a schematic representation, and the NiPt film deposited on the silicided layers (26A, 27A) and remaining may or may not exist. The structure of the semiconductor substrate or its product is also shown in a simplified manner, as long as it is explained in the form of those having the necessary members as necessary.

若列舉構成材料的較佳例,則可例示如下所述的形態。 If the preferred examples of the constituent materials are listed, the following forms can be exemplified.

Figure 104106129-A0305-02-0012-1
Figure 104106129-A0305-02-0012-1

此外,作為PMOS側的通道,應用Ge,於NMOS側被認為有前途的是InGaAs的應用。 In addition, as a channel on the PMOS side, Ge is applied, and the application of InGaAs is considered promising on the NMOS side.

被蝕刻的金屬膜可列舉:貴金屬(例如Pt、Au、Pd、Ir、 Ni、Mo、Rh及Re)、鑭系金屬(例如鉺、釓、鐿、釔、鈥及鏑)、以及該些金屬的合金(例如NiPt(3%~20%))。特別是可選擇性地去除NiPt。 The metal film to be etched may include noble metals (eg Pt, Au, Pd, Ir, Ni, Mo, Rh and Re), lanthanide metals (such as erbium, ytterbium, ytterbium, yttrium, ytterbium and dysprosium), and alloys of these metals (such as NiPt (3%-20%)). In particular, NiPt can be selectively removed.

積體為高度的積體電路且暴露於所述蝕刻組成物中的可能性高的材料,並且不期望被蝕刻的材料可列舉:高介電常數(high-k)材料(例如HfO2、HfON及HfSiON)、金屬閘極材料(例如TiN、TaN、TiAlN及W)、間隙(interstitial)層(例如Al2O3及La2O5)、填充金屬(fill metal)(例如鋁)、電介質(例如Si3N4及SiO2)、半導體(例如經p型摻雜及n型摻雜的Si、Ge及SiGe)、被蝕刻的金屬的矽化物(例如鎳鉑矽化物)、接點材料(例如NiGe、NiPtGe及NiInSb)、以及III-V材料(例如InGaAs、InSb、GaP、GaAs、InAs、AlGaSb、InAs、InAsSb、GaSb、AlSb、AlAs、InAlAs及InP)。本揭示的所述蝕刻組成物及製程使對該些膜造成的損傷最小化或不造成損傷,但是最適合於去除不需要的金屬。 The integrated body is a material with a high integrated circuit and a high possibility of being exposed to the etching composition, and materials that are not expected to be etched include high-k materials (eg, HfO 2 , HfON And HfSiON), metal gate materials (such as TiN, TaN, TiAlN, and W), interstitial layers (such as Al 2 O 3 and La 2 O 5 ), fill metals (such as aluminum), dielectrics ( For example, Si 3 N 4 and SiO 2 ), semiconductors (such as p-doped and n-doped Si, Ge, and SiGe), etched metal silicides (such as nickel platinum silicide), and contact materials ( For example, NiGe, NiPtGe, and NiInSb), and III-V materials (such as InGaAs, InSb, GaP, GaAs, InAs, AlGaSb, InAs, InAsSb, GaSb, AlSb, AlAs, InAlAs, and InP). The etching composition and process of the present disclosure minimize or do not cause damage to these films, but are most suitable for removing unnecessary metals.

於某一實施形態下,本說明書中記載的金屬蝕刻製程包括:(a)部分或者整體暴露於本揭示的蝕刻組成物中,藉此提供具有可蝕刻的金屬膜的半導體基板;(b)使被蝕刻的金屬膜與本揭示的蝕刻組成物接觸,進而(c)利用溶劑(例如包含水的溶劑)對經蝕刻的半導體基板進行清洗。 In one embodiment, the metal etching process described in this specification includes: (a) partial or entire exposure to the etching composition of the present disclosure, thereby providing a semiconductor substrate having an etchable metal film; (b) The etched metal film is in contact with the etching composition of the present disclosure, and (c) the etched semiconductor substrate is cleaned with a solvent (for example, a solvent containing water).

蝕刻組成物可利用本領域技術人員所公知的任意適當的方法而與半導體基板接觸。此種方法並不限定於該些,可列舉:將半導體基板浸漬於蝕刻組成物的浴中,或者於半導體基板上吹附或 流動蝕刻組成物。吹附或流動蝕刻組成物的方法可於基板由蝕刻組成物所覆蓋的時刻結束,或者可持續蝕刻組成物與半導體基板接觸的時間的一部分或者全部時間。典型而言,半導體基板與蝕刻組成物可於數秒以內完全接觸。於蝕刻週期(etching period)的中間階段、或者貫穿該週期期間,根據個別的製程而使用加成性蝕刻組成物。 The etching composition can be brought into contact with the semiconductor substrate by any suitable method known to those skilled in the art. This method is not limited to these, and examples include immersing a semiconductor substrate in a bath of an etching composition, or blowing or attaching on a semiconductor substrate Flow etching composition. The method of blowing or flowing the etching composition may end at the time when the substrate is covered by the etching composition, or may continue a part or all of the time when the etching composition contacts the semiconductor substrate. Typically, the semiconductor substrate and the etching composition can be completely in contact within a few seconds. In the middle of the etching period, or throughout the period, the additive etching composition is used according to individual processes.

蝕刻週期期間的製程可包括攪拌方法,或者可排除攪拌方法。例如,於浸漬的實施形態的製程中,可對蝕刻組成物進行循環或者攪拌。或者,可於蝕刻中使基板旋轉,或者上下移動。於吹附或流動的實施形態的製程中,半導體基板被水平放置,但基板可在水平方向上旋轉。於實施形態的任一者中,均可為了引發攪拌而使半導體基板振動。若為本領域技術人員,則可根據個別的應用來決定接觸及攪拌方法的最佳組合。 The process during the etching cycle may include a stirring method, or the stirring method may be excluded. For example, in the process of the immersion embodiment, the etching composition may be circulated or stirred. Alternatively, the substrate may be rotated during etching or moved up and down. In the process of blowing or flowing, the semiconductor substrate is placed horizontally, but the substrate can be rotated in the horizontal direction. In any of the embodiments, the semiconductor substrate can be vibrated to cause stirring. If it is a person skilled in the art, the best combination of contact and stirring methods can be determined according to individual applications.

蝕刻週期通常可實行約30秒至約30分鐘。該時間依存於:被蝕刻的膜的厚度、避免對其他露出膜的不良影響的必要度、所使用的個別的蝕刻組成物、所使用的個別的接觸方法、以及所採用的溫度。 The etching cycle can usually be performed for about 30 seconds to about 30 minutes. This time depends on the thickness of the film to be etched, the necessity to avoid adverse effects on other exposed films, the individual etching composition used, the individual contact method used, and the temperature used.

金屬膜被蝕刻的情況下的溫度通常在20℃至60℃之間。較佳的溫度範圍為約20℃至約50℃。最佳的溫度範圍為約30℃至約50℃。 The temperature when the metal film is etched is usually between 20°C and 60°C. The preferred temperature range is about 20°C to about 50°C. The optimal temperature range is about 30°C to about 50°C.

繼蝕刻步驟之後,利用包含水、較佳為去離子水的溶劑來清洗半導體基板。若為適當的清洗方法,則可採用任一種方法。可 例示:將半導體基板浸漬於停滯水或者流水中,或者於半導體基板上吹附或流動水。於蝕刻週期期間亦可採用所述攪拌。 Following the etching step, the semiconductor substrate is cleaned with a solvent containing water, preferably deionized water. If it is an appropriate cleaning method, either method can be used. can Examples: immersing the semiconductor substrate in stagnant water or running water, or blowing or flowing water on the semiconductor substrate. The agitation can also be used during the etching cycle.

所述水性溶劑可包含追加的水溶性有機溶媒。若使用水溶性有機溶媒,則有助於有機殘留物的去除或速乾。 The aqueous solvent may include an additional water-soluble organic solvent. If a water-soluble organic solvent is used, it will help to remove organic residues or dry quickly.

繼清洗步驟之後,作為任意的步驟,藉由使用乾燥方法來進行半導體基板的乾燥。乾燥方法的例子可列舉:噴霧如氮氣之類的非氧化性氣體、使基板旋轉、或者於加熱板上或者烘箱中進行煅燒。 Following the cleaning step, as an arbitrary step, the semiconductor substrate is dried by using a drying method. Examples of the drying method include spraying a non-oxidizing gas such as nitrogen, rotating the substrate, or performing calcination on a hot plate or in an oven.

上文已對應用本發明的蝕刻方法的具體例進行了說明,但並不限定於該具體例,亦可應用於其他半導體的製造方法。例如可列舉:WO2011/087610(日本專利特表2013-511164)的圖1~圖8中揭示的電晶體、WO2011/090583(日本專利特表2013-513975)的圖1~圖22中揭示的裝置。 The specific example of applying the etching method of the present invention has been described above, but it is not limited to this specific example, and can also be applied to other semiconductor manufacturing methods. For example, the transistors disclosed in FIGS. 1 to 8 of WO2011/087610 (Japanese Patent Special Table 2013-511164) and the devices disclosed in FIGS. 1 to 22 of WO2011/090583 (Japanese Patent Special Table 2013-513975) can be cited. .

[蝕刻組成物] [Etching composition]

繼而,對本發明的蝕刻組成物的較佳實施形態進行說明。 Next, a preferred embodiment of the etching composition of the present invention will be described.

本發明為一種酸性蝕刻組成物,其是NiPt以及包含In、Al、Ga、Sb及As中的至少1種的第一材料(III-V族材料)所存在的基板的蝕刻組成物,且包含鹵素離子、與硝酸或硝酸根離子。若酸性蝕刻組成物的鹵素離子的含量為10質量%以下,則較佳為:酸性蝕刻組成物更包含磺酸;酸性蝕刻組成物(水性組成物)的含水量為50質量%以下(更佳為35質量%以下)。酸性蝕刻組成物較佳為水性組成物,較佳為液狀。以下,包括任意者,對各成 分進行說明。 The present invention is an acidic etching composition, which is an etching composition of a substrate where NiPt and a first material (III-V material) containing at least one of In, Al, Ga, Sb, and As are present and includes Halogen ions, and nitric acid or nitrate ions. If the content of halogen ions in the acidic etching composition is 10% by mass or less, it is preferable that the acidic etching composition further contains sulfonic acid; the water content of the acidic etching composition (aqueous composition) is 50% by mass or less (more preferably 35% by mass or less). The acidic etching composition is preferably an aqueous composition, and is preferably liquid. The following, including any Explain separately.

(鹵素離子) (Halogen ion)

本發明的蝕刻組成物中包含鹵素離子。其中,鹵素離子較佳為氯離子、溴離子、碘離子、以及氟離子,更佳為氯離子、溴離子。鹵素離子的供給源並無特別限定,可作為與後述有機陽離子的鹽而供給,亦可藉由添加氫化物(鹽酸、氫溴酸等)而供給。 The etching composition of the present invention contains halogen ions. Among them, the halogen ions are preferably chloride ions, bromide ions, iodine ions, and fluoride ions, more preferably chloride ions, bromide ions. The supply source of the halogen ion is not particularly limited, and it can be supplied as a salt with an organic cation described later, or by adding a hydride (hydrochloric acid, hydrobromic acid, etc.).

蝕刻組成物中,鹵素離子的濃度較佳為0.01質量%以上,更佳為0.05質量%以上,特佳為含有0.1質量%以上。上限較佳為30質量%以下,更佳為27質量%以下,尤佳為25質量%以下,特佳為10質量%以下。藉由將鹵素離子設為所述範圍,不僅可維持金屬層(第二層)的良好蝕刻性,而且可有效地抑制含III-V族材料的層(第一層)或其矽化物層(第三層)的損傷,因此較佳。關於蝕刻組成物的成分的鑑定,未必需要作為化合物而被確認,例如於鹽酸的情況下,藉由在水溶液中鑑定出氯離子(Cl-),來掌握其存在及量。 In the etching composition, the concentration of halogen ions is preferably 0.01% by mass or more, more preferably 0.05% by mass or more, and particularly preferably 0.1% by mass or more. The upper limit is preferably 30% by mass or less, more preferably 27% by mass or less, particularly preferably 25% by mass or less, and particularly preferably 10% by mass or less. By setting the halogen ion to the above range, not only can the good etching property of the metal layer (second layer) be maintained, but also the layer containing the III-V material (first layer) or its silicide layer can be effectively suppressed ( The third layer) is therefore better. The identity of the components of the etching composition, does not necessarily need to be confirmed as a compound, for example, in the case of hydrochloric acid, identified by chloride ions (Cl -) in an aqueous solution, and to control an amount which is present.

此外,本發明中,所述鹵素離子可僅使用一種,亦可併用兩種以上。於併用兩種以上的情況下,其併用比例並無特別限定,合計使用量較佳為作為兩種以上離子的總和而設為所述濃度範圍。 In the present invention, only one kind of the halogen ion may be used, or two or more kinds may be used in combination. When two or more types are used in combination, the combination ratio is not particularly limited, and the total amount used is preferably the sum of two or more ions and is set to the concentration range.

(硝酸或硝酸根離子) (Nitric acid or nitrate ion)

本實施形態的蝕刻組成物中包含硝酸或硝酸根離子。 The etching composition of this embodiment contains nitric acid or nitrate ions.

蝕刻組成物中,所述硝酸或硝酸根離子的濃度較佳為0.1質量 %以上,更佳為0.5質量%以上,特佳為含有1質量%以上。上限較佳為23質量%以下,更佳為20質量%以下,尤佳為16質量%以下,特佳為3質量%以下。相對於鹵素離子100質量份,所述硝酸或硝酸根離子較佳為10質量份以上,更佳為30質量份以上,特佳為50質量份以上。上限較佳為3000質量份以下,更佳為1000質量份以下,特佳為600質量份以下。 In the etching composition, the concentration of the nitric acid or nitrate ion is preferably 0.1 mass % Or more, more preferably 0.5% by mass or more, particularly preferably 1% by mass or more. The upper limit is preferably 23% by mass or less, more preferably 20% by mass or less, particularly preferably 16% by mass or less, and particularly preferably 3% by mass or less. The nitric acid or nitrate ion is preferably 10 parts by mass or more, more preferably 30 parts by mass or more, and particularly preferably 50 parts by mass or more with respect to 100 parts by mass of halogen ions. The upper limit is preferably 3000 parts by mass or less, more preferably 1000 parts by mass or less, and particularly preferably 600 parts by mass or less.

藉由將硝酸或硝酸根離子的濃度設為所述範圍,不僅可維持金屬層(第二層)的良好蝕刻性,而且可有效地抑制含III-V族材料的層(第一層)或其矽化物層(第三層)的損傷,因此較佳為。此外,關於蝕刻組成物的成分的鑑定,例如未必需要作為硝酸而被確認,藉由在水溶液中鑑定出硝酸根離子(NO3 -),來掌握其存在及量。此外,硝酸或硝酸根離子可僅使用一種,亦可併用兩種以上。 By setting the concentration of nitric acid or nitrate ion to the above range, not only can the good etching property of the metal layer (second layer) be maintained, but also the layer containing the III-V material (first layer) or The damage of the silicide layer (third layer) is therefore preferred. Further, regarding the identified components of the etching composition, for example, need not necessarily be confirmed as nitric acid, identified by nitrate ions (NO 3 -) in aqueous solution, the presence and amount thereof to master. In addition, nitric acid or nitrate ions may be used alone or in combination of two or more.

(磺酸化合物) (Sulfonic acid compound)

本發明的蝕刻組成物中可含有磺酸化合物。磺酸化合物可為烷基磺酸化合物(較佳為碳數1~12,更佳為1~6,特佳為1~3),亦可為芳基磺酸化合物(較佳為碳數6~14,更佳為6~10)。烷基磺酸化合物可為具有芳烷基的磺酸化合物(較佳為碳數7~15,更佳為7~11)。 The etching composition of the present invention may contain a sulfonic acid compound. The sulfonic acid compound may be an alkyl sulfonic acid compound (preferably 1 to 12 carbon atoms, more preferably 1 to 6 and particularly preferably 1 to 3) or an aryl sulfonic acid compound (preferably carbon number 6 ~14, more preferably 6~10). The alkylsulfonic acid compound may be a sulfonic acid compound having an aralkyl group (preferably having 7 to 15 carbon atoms, more preferably 7 to 11).

烷基磺酸化合物較佳為:甲磺酸、乙磺酸、辛基磺酸、甲烷二磺酸、乙烷二磺酸、苄基磺酸等。 The alkylsulfonic acid compound is preferably: methanesulfonic acid, ethanesulfonic acid, octylsulfonic acid, methanedisulfonic acid, ethanedisulfonic acid, benzylsulfonic acid, or the like.

芳基磺酸化合物較佳為下述式(S-1)~式(S-3)的任一者。 式中,Z1、Z2為有時經由連結基L的磺酸基。R56為取代基,其中較佳為烷基(較佳為碳數1~12,更佳為1~6,特佳為1~3)。n51及n56為0~5的整數。n53為0~4的整數。n51、n53及n56的最大值與位於相同環上的Z1或Z2的數量相對應而減少。n52為1~6的整數,較佳為1或2。n54及n55分別獨立地為0~4的整數,n54+n55為1以上。n54+n55較佳為1或2。n57及n58分別獨立地為0~5的整數,n57+n58為1以上。n57+n58較佳為1或2。存在多個的R56可相互相同,亦可不同。連結基L較佳為O、S、NRN、伸烷基(較佳為碳數1~12,更佳為1~6,特佳為1~3)、或者其組合。RN較佳為烷基(較佳為碳數1~12,更佳為1~6,特佳為1~3)、芳基(較佳為碳數6~22,更佳為6~14)、或者氫原子。 The arylsulfonic acid compound is preferably any one of the following formula (S-1) to formula (S-3). In the formula, Z 1 and Z 2 are sulfonic acid groups via a linking group L. R 56 is a substituent, and among them, an alkyl group is preferred (preferably having 1 to 12 carbon atoms, more preferably 1 to 6, and particularly preferably 1 to 3). n 51 and n 56 are integers from 0 to 5. n 53 is an integer from 0 to 4. The maximum values of n 51 , n 53 and n 56 decrease corresponding to the number of Z 1 or Z 2 located on the same ring. n 52 is an integer of 1 to 6, preferably 1 or 2. n 54 and n 55 are independently integers of 0 to 4, and n 54 +n 55 are 1 or more. n 54 +n 55 is preferably 1 or 2. n 57 and n 58 are independently integers from 0 to 5, and n 57 +n 58 are 1 or more. n 57 +n 58 is preferably 1 or 2. A plurality of R 56 may be the same as each other or different. L is preferably a linking group O, S, NR N, an alkylene group (preferably having 1 to 12 carbon atoms, more preferably 1 to 6, particularly preferably 1 to 3), or combinations thereof. R N is preferably an alkyl group (preferably a carbon number of 1 to 12, more preferably 1 to 6, particularly preferably 1 to 3), an aryl group (preferably a carbon number of 6 to 22, more preferably 6 to 14 ), or hydrogen atoms.

Figure 104106129-A0305-02-0018-2
Figure 104106129-A0305-02-0018-2

芳基磺酸化合物的具體例可列舉:對甲苯磺酸、苯磺酸、2-萘磺酸、萘-1-磺酸、1,5-萘二磺酸、2,6-萘二磺酸等。 Specific examples of the arylsulfonic acid compound include p-toluenesulfonic acid, benzenesulfonic acid, 2-naphthalenesulfonic acid, naphthalene-1-sulfonic acid, 1,5-naphthalene disulfonic acid, and 2,6-naphthalene disulfonic acid. Wait.

蝕刻組成物中,磺酸化合物的濃度較佳為1質量%以上,更佳為5質量%以上,特佳為含有30質量%以上。上限較佳為80質量%以下,更佳為75質量%以下,特佳為70質量%以下。藉由以所 述濃度應用磺酸化合物,就可實現良好的金屬層的蝕刻,而且可實現III-V族材料或鍺層的有效保護的方面而言較佳。 In the etching composition, the concentration of the sulfonic acid compound is preferably 1% by mass or more, more preferably 5% by mass or more, and particularly preferably 30% by mass or more. The upper limit is preferably 80% by mass or less, more preferably 75% by mass or less, and particularly preferably 70% by mass or less. By all The application of the sulfonic acid compound at the above-mentioned concentration is preferable in terms of achieving good etching of the metal layer and achieving effective protection of the III-V group material or the germanium layer.

(有機陽離子) (Organic cation)

本發明的蝕刻組成物中可包含有機陽離子,較佳為具有碳原子且呈現出鹼性的陽離子。其中,較佳為有機鎓,更佳為有機銨。具體而言,較佳為碳數5以上的有機銨,更佳為碳數8以上的有機銨。上限實際上為碳數35以下。 The etching composition of the present invention may contain organic cations, preferably cations having carbon atoms and exhibiting basicity. Among them, organic onium is preferred, and organic ammonium is more preferred. Specifically, it is preferably an organic ammonium having 5 or more carbon atoms, and more preferably an organic ammonium having 8 or more carbon atoms. The upper limit is actually 35 or less carbon number.

關於有機陽離子在系統內發揮的作用,雖包含推定,但考慮如下。本發明的蝕刻組成物中,理解為鹵素離子與硝酸根離子主要發揮金屬層(第二層)的蝕刻作用。關於磺酸化合物,理解為具有使III-V族材料或鍺的溶解度下降而抑制其溶出的作用。因此,較佳為應用相應的量。藉此,含III-V族材料的層(第一層)與金屬層(第二層)的選擇去除性提高,但並不充分。本發明中,藉由使有機陽離子共存於其中,而使所述有機陽離子吸附於含III-V族材料的層或鍺表面,構成有效的防蝕表面。藉此,與利用磺酸化合物而得的抑制III-V族材料或鍺的溶出的效果互相結合,表現出顯著的蝕刻的選擇性。進而,若有機陽離子的碳數變多(5以上),則可更顯著地抑制III-V族材料或鍺的溶解。利用所述作用,有機陽離子只要微量地存在於系統內即可,特佳為選定與所述磺酸化合物的協同作用提高的量以及種類者。 The role played by the organic cation in the system includes estimation, but it is considered as follows. In the etching composition of the present invention, it is understood that the halogen ion and the nitrate ion mainly play an etching role of the metal layer (second layer). The sulfonic acid compound is understood to have the effect of reducing the solubility of the group III-V material or germanium and inhibiting its elution. Therefore, it is preferable to apply the corresponding amount. As a result, the selective removal of the layer containing the III-V material (first layer) and the metal layer (second layer) is improved, but it is not sufficient. In the present invention, by coexisting organic cations therein, the organic cations are adsorbed on the layer containing the III-V material or the surface of germanium to constitute an effective anticorrosive surface. This is combined with the effect of inhibiting the dissolution of III-V materials or germanium by using a sulfonic acid compound, and exhibits remarkable etching selectivity. Furthermore, if the carbon number of the organic cation becomes larger (5 or more), the dissolution of the group III-V material or germanium can be more significantly suppressed. By using the action, the organic cation may be present in the system in a trace amount, and it is particularly preferable to select the amount and type of the synergistic effect with the sulfonic acid compound to increase.

有機鎓可列舉:含氮鎓(四級銨等)、含磷鎓(四級鏻等)、含硫鎓(例如SRy3 +:Ry為碳數1~6的烷基)。其中較佳為 含氮鎓(四級銨、吡啶鎓、吡唑鎓、咪唑鎓等)。有機陽離子較佳為其中的四級銨。 Examples of the organic onium include nitrogen-containing onium (quaternary ammonium, etc.), phosphonium-containing (quaternary phosphonium, etc.), and sulfur-containing onium (for example, SRy 3 + : Ry is an alkyl group having 1 to 6 carbon atoms). Among them, nitrogen-containing onium (quaternary ammonium, pyridinium, pyrazolium, imidazolium, etc.) is preferred. The organic cation is preferably a quaternary ammonium.

有機鎓可列舉下述式(Q-1)所表示的離子。 Examples of the organic onium include ions represented by the following formula (Q-1).

Figure 104106129-A0305-02-0020-3
Figure 104106129-A0305-02-0020-3

式中,RQ1~RQ4分別獨立地為碳數1~35的烷基、碳數2~35的烯基、碳數2~35的炔基、碳數6~14的芳基、碳數7~15的芳烷基、下述式(y)所表示的基團。其中,RQ1~RQ4的碳數的合計較佳為5以上,更佳為8以上。 In the formula, R Q1 to R Q4 are independently C 1 to 35 alkyl, C 2 to 35 alkenyl, C 2 to 35 alkynyl, C 6 to 14 aryl, C Aralkyl groups of 7 to 15 and groups represented by the following formula (y). Among them, the total number of carbon atoms of R Q1 to R Q4 is preferably 5 or more, and more preferably 8 or more.

Y1-(Ry1-Y2)my-Ry2-* (y) Y 1 -(Ry 1 -Y 2 )my-Ry 2 -* (y)

Y1為碳數1~12的烷基、碳數2~12的烯基、碳數2~12的炔基、碳數7~14的芳烷基、碳數6~14的芳基、羥基、硫基、碳數1~4的烷氧基、或者碳數1~4的硫代烷氧基。Y2表示O、S、CO、NRN(RN為氫原子或者碳數1~6的烷基)。Ry1及Ry2分別獨立地為碳數1~6的伸烷基、碳數2~6的伸烯基、碳數2~6的伸炔基、碳數6~10的伸芳基、或者它們的組合。my表示0~6的整數。當my為2以上時,多個Ry1及Y2可分別不同。Ry1及 Ry2亦可進而具有取代基T。*為結合鍵。 Y 1 is an alkyl group having 1 to 12 carbons, an alkenyl group having 2 to 12 carbons, an alkynyl group having 2 to 12 carbons, an aralkyl group having 7 to 14 carbons, an aryl group having 6 to 14 carbons, and a hydroxyl group , Thio, alkoxy having 1 to 4 carbons, or thioalkoxy having 1 to 4 carbons. Y 2 represents O, S, CO, NR N (R N is hydrogen or alkyl having 1 to 6). Ry 1 and Ry 2 are independently C 1-6 alkylene, C 2-6 alkenyl, C 2-6 alkynyl, C 6-10 aryl, or Their combination. my represents an integer from 0 to 6. When my is 2 or more, multiple Ry 1 and Y 2 may be different. Ry 1 and Ry 2 may further have a substituent T. *It is a combination key.

所述有機陽離子較佳為選自由烷基銨陽離子、芳基銨陽離子、以及烷基.芳基銨陽離子所組成的組群中的至少一種。 The organic cation is preferably selected from alkyl ammonium cation, aryl ammonium cation, and alkyl. At least one of the group consisting of aryl ammonium cations.

具體而言,較佳為四烷基銨(較佳為碳數5~35,更佳為8~25,特佳為10~25)。此時,烷基中,亦可於不損及本發明效果的範圍內取代任意的取代基(例如羥基、烯丙基、芳基)。另外,烷基可為直鏈,亦可為支鏈,亦可為環狀。具體而言,可列舉:四甲基銨(tetramethyl ammonium,TMA)、四乙基銨(tetraethyl ammonium,TEA)、苄基三甲基銨、乙基三甲基銨、2-羥基乙基三甲基銨、苄基三乙基銨、十六烷基三甲基銨、四丁基銨(tetrabutyl ammonium,TBA)、四己基銨(tetrahexyl ammonium,THA)、四丙基銨(tetrapropyl ammonium,TPA)、月桂基吡啶鎓、鯨蠟基吡啶鎓、月桂基三甲基銨、十六烷基三甲基銨、十八烷基三甲基銨、二癸基二甲基銨、二月桂基二甲基銨、二硬脂基二甲基銨、二油烯基二甲基銨、月桂基二甲基苄基銨、鯨蠟基三甲基銨等。 Specifically, it is preferably a tetraalkylammonium (preferably having a carbon number of 5 to 35, more preferably 8 to 25, and particularly preferably 10 to 25). At this time, in the alkyl group, any substituent (for example, a hydroxyl group, an allyl group, and an aryl group) may be substituted within a range that does not impair the effects of the present invention. In addition, the alkyl group may be linear, branched, or cyclic. Specifically, tetramethylammonium (TMA), tetraethylammonium (TEA), benzyltrimethylammonium, ethyltrimethylammonium, 2-hydroxyethyltrimethylammonium Ammonium, benzyltriethylammonium, cetyltrimethylammonium, tetrabutylammonium (TBA), tetrahexylammonium (THA), tetrapropylammonium (TPA) , Laurylpyridinium, cetylpyridinium, lauryltrimethylammonium, cetyltrimethylammonium, octadecyltrimethylammonium, didecyldimethylammonium, dilauryldimethyl Ammonium, distearyl dimethyl ammonium, dioleyl dimethyl ammonium, lauryl dimethyl benzyl ammonium, cetyl trimethyl ammonium, etc.

有機陽離子的供給源並無特別限定,可列舉於所述鹵素離子的鹽、或與氫氧化物離子的鹽。 The supply source of the organic cation is not particularly limited, and examples thereof include salts of the halogen ions or salts with hydroxide ions.

蝕刻組成物中,有機陽離子的濃度較佳為1×10-6mol/L以上,更佳為1×10-5mol/L以上,特佳為含有5×10-5mol/L以上。上限較佳為1mol/L以下,更佳為0.5mol/L以下,特佳為0.1mol/L以下。藉由將有機陽離子設為所述範圍,不僅可維持金屬層(第二層)的良好蝕刻性,而且可有效地抑制含III-V族材料的層(第一層) 或其矽化物層(第三層)的損傷,因此較佳。 In the etching composition, the concentration of the organic cation is preferably 1×10 −6 mol/L or more, more preferably 1×10 −5 mol/L or more, and particularly preferably 5×10 −5 mol/L or more. The upper limit is preferably 1 mol/L or less, more preferably 0.5 mol/L or less, and particularly preferably 0.1 mol/L or less. By setting the organic cation to the above range, not only can the good etching properties of the metal layer (second layer) be maintained, but also the layer containing the III-V material (first layer) or its silicide layer can be effectively suppressed ( The third layer) is therefore better.

有機陽離子較佳為其ClogP為-4以上,尤佳為0以上。藉由將有機陽離子的ClogP設為該範圍,就可實現有效地保護含III-V族材料的層的高蝕刻選擇性的方面而言較佳。 The organic cation preferably has a ClogP of -4 or more, particularly preferably 0 or more. By setting the ClogP of the organic cation to this range, it is preferable in terms of achieving a high etching selectivity that can effectively protect the layer containing the III-V material.

辛醇-水分配係數(logP值)的測定通常可利用JIS日本工業標準Z7260-107(2000)中記載的燒瓶滲透法來實施。另外,辛醇-水分配係數(logP值)亦可藉由計算化學方法或者經驗方法代替實測來估算。作為計算方法,已知使用克里朋的碎片(Crippen's fragmentation)法(「化學資訊與電腦科技期刊(J.Chem.Inf.Comput.Sci.)」,27,21(1987))、維斯瓦納坦的碎片(Viswanadhan's fragmentation)法(「化學資訊與電腦科技期刊(J.Chem.Inf.Comput.Sci.)」,29,163(1989))、布羅陀的碎片(Broto's fragmentation)法(「歐洲醫藥化學雜誌-化學理論(Eur.J.Med.Chem.-Chim.Theor.)」,19,71(1984))。於本發明中,使用克里朋的碎片(Crippen's fragmentation)法(「化學資訊與電腦科技期刊(J.Chem.Inf.Comput.Sci.)」,27,21(1987))。所謂ClogP值,是指藉由計算而求出在1-辛醇與水中的分配係數P的常用對數logP而得的值。關於計算ClogP值時使用的方法或軟體,可使用任意者,只要無特別說明,則本發明中使用ChemDraw Ultra 12.0(商品名)。 The measurement of the octanol-water partition coefficient (logP value) can usually be carried out by the flask permeation method described in JIS Japanese Industrial Standard Z7260-107 (2000). In addition, the octanol-water partition coefficient (logP value) can also be estimated by computational chemistry methods or empirical methods instead of actual measurements. As a calculation method, it is known to use Crippen's fragmentation method ("J. Chem. Inf. Comput. Sci.", 27, 21 (1987)), Wisla Viswanadhan's fragmentation method ("J. Chem. Inf. Comput. Sci.", 29, 163 (1989)), Broto's fragmentation method (Broto's fragmentation) method ( "Eur. J. Med. Chem.-Chim. Theor.", 19, 71 (1984)). In the present invention, the Crippen's fragmentation method ("J. Chem. Inf. Comput. Sci.", 27, 21 (1987)) is used. The ClogP value refers to a value obtained by calculating the common logP of the partition coefficient P in 1-octanol and water by calculation. As for the method or software used to calculate the ClogP value, any one can be used, and unless otherwise specified, ChemDraw Ultra 12.0 (trade name) is used in the present invention.

於化合物或取代基.連結基等包含烷基.伸烷基、烯基.伸烯基、炔基.伸炔基等時,該些可為環狀,亦可為鏈狀,另外,可 為直鏈,亦可為支鏈,可經任意的基團所取代,亦可為未經取代。此時,烷基.伸烷基、烯基.伸烯基、炔基.伸炔基可介隔包含雜原子的基團(例如O、S、CO、NRN等),亦可與其一起形成環結構。另外,於包含芳基、雜環基等時,它們可為單環,亦可為縮環,同樣地,可經取代,亦可為未經取代。 For compounds or substituents. Linking groups, etc. include alkyl. Extend alkyl, alkenyl. Alkenyl, alkynyl. In the case of alkynyl groups, etc., these may be cyclic or chain-like, and may be linear or branched, may be substituted with any group, or may be unsubstituted. At this time, alkyl. Extend alkyl, alkenyl. Alkenyl, alkynyl. Extending alkynyl group may be interposed (e.g. O, S, CO, NR N and the like) containing a hetero atom, may form a ring structure together therewith. In addition, when an aryl group, a heterocyclic group, or the like is included, they may be a single ring or a condensed ring. Similarly, they may be substituted or unsubstituted.

本說明書中,以化合物的取代基或連結基的選擇項為代表,所謂溫度、厚度的各技術事項的清單可分別獨立地記載,亦可相互組合。 In the present specification, the choice of the substituent or the linking group of the compound is represented as a representative, and the list of each technical item of so-called temperature and thickness may be separately described or may be combined with each other.

(水介質) (Aqueous medium)

本發明的蝕刻組成物,於其一實施形態中,較佳為應用水(水介質)作為其介質。水(水介質)可為於不損及本發明效果的範圍內包含溶解成分的水性介質,或者亦可包含不可避免的微量混合成分。其中,較佳為蒸餾水或離子交換水、或超純水等實施了淨化處理的水,特佳為使用半導體製造時所使用的超純水。水的濃度並無特別限定,較佳為10質量%以上,更佳為15質量%以上。上限較佳為95質量%以下,更佳為90質量%以下,尤佳為85質量%以下,進而更佳為50質量%以下,特佳為35質量%以下。 In one embodiment, the etching composition of the present invention preferably uses water (aqueous medium) as its medium. The water (aqueous medium) may be an aqueous medium containing dissolved components within a range that does not impair the effects of the present invention, or may contain unavoidable trace mixing components. Among them, the purified water such as distilled water, ion-exchanged water, or ultrapure water is preferable, and the ultrapure water used in semiconductor manufacturing is particularly preferable. The concentration of water is not particularly limited, but it is preferably 10% by mass or more, and more preferably 15% by mass or more. The upper limit is preferably 95% by mass or less, more preferably 90% by mass or less, particularly preferably 85% by mass or less, even more preferably 50% by mass or less, and particularly preferably 35% by mass or less.

(pH值) (pH value)

本發明中,較佳為將蝕刻組成物的pH值(25℃)設為3以下,更佳為設為1以下。就確保第二層的充分蝕刻速度,並且有效地防止第一層或其第三層的損傷的觀點而言,較佳為設為所述範圍。 In the present invention, the pH value (25° C.) of the etching composition is preferably 3 or less, and more preferably 1 or less. From the viewpoint of ensuring a sufficient etching rate of the second layer and effectively preventing damage to the first layer or the third layer, it is preferably within the above range.

此外,本發明中,於室溫(25℃)下利用堀場(HORIBA)公 司製造的F-51(商品名)來測定pH值。 In addition, in the present invention, the HORIBA company is used at room temperature (25°C) Division F-51 (trade name) to measure the pH.

任意的添加劑可列舉溶劑、羧酸或其他的錯合劑、抗腐蝕劑、黏度降低劑、以及界面活性劑,為了使性能最佳化或者降低成本,可用於所有的實施形態中。所述羧酸可為了藉由對氯化物錯合物的形成進行補充來改善所述金屬離子的溶解度而使用。所述界面活性劑不僅出於作為表面張力調整劑的現有目的,亦可為了抑制鋁、二氧化矽、氮化矽、矽化物、鎢及TiN之類的多種露出面上的腐蝕而用作濕潤劑。作為將成為目標物的某種有機殘留物去除的解決對策,所述溶劑可變更漢森(Hansen)溶解度參數,使溶液的氧化電位變化。所使用的添加劑可為不同類型的混合物、相同等級的添加物的混合物、或者相同等級及不同類型的兩者的添加劑的混合物。所述添加劑必須注意在低pH值以及氧化條件下穩定。 Examples of the optional additives include solvents, carboxylic acids or other complexing agents, corrosion inhibitors, viscosity reducing agents, and surfactants. In order to optimize performance or reduce costs, they can be used in all embodiments. The carboxylic acid can be used to improve the solubility of the metal ion by supplementing the formation of chloride complexes. The surfactant is not only used for the current purpose of being a surface tension adjuster, but also used as a wetting agent to suppress corrosion on various exposed surfaces such as aluminum, silicon dioxide, silicon nitride, silicide, tungsten, and TiN. Agent. As a solution to the removal of certain organic residues that are the target, the solvent can change the Hansen solubility parameter to change the oxidation potential of the solution. The additives used may be mixtures of different types, mixtures of additives of the same grade, or mixtures of additives of the same grade and different types. The additives must be stable under low pH and oxidizing conditions.

於某一實施形態中,本說明書中記載的所述蝕刻組成物包含一種以上的有機溶媒。於某一實施形態中,適合用於本說明書中記載的所述蝕刻組成物中的所述有機溶媒除了二醇、醚、以及多元醇等穩定化劑以外。可自所述蝕刻組成物中去除的特定有機溶媒(或者穩定化劑)的例子可列舉:甘醇二甲醚、二甘醇二甲醚、三甘醇二甲醚、冠醚類、乙二醇、三丙二醇、以及丙二醇甲醚。於某一實施形態中,所述蝕刻組成物包含所述經去除的溶媒的一種以上。 In one embodiment, the etching composition described in this specification includes one or more organic solvents. In one embodiment, the organic solvent suitable for use in the etching composition described in this specification is in addition to stabilizers such as glycols, ethers, and polyols. Examples of specific organic solvents (or stabilizing agents) that can be removed from the etching composition include: glyme, diglyme, triethylene glycol dimethyl ether, crown ethers, ethylene glycol Alcohol, tripropylene glycol, and propylene glycol methyl ether. In one embodiment, the etching composition contains one or more of the removed solvents.

所述添加劑的濃度亦可依存於所述添加劑個別的有效性或者 目的。所使用的所述加成性溶劑的濃度為約3%~約35%。所述羧酸、其他錯合劑、黏度降低劑、以及界面活性劑的濃度為約0.001%~約10%。 The concentration of the additive may also depend on the individual effectiveness of the additive or purpose. The concentration of the additive solvent used is about 3% to about 35%. The concentration of the carboxylic acid, other complexing agent, viscosity reducing agent, and surfactant is about 0.001% to about 10%.

(套組) (Set)

本發明中的蝕刻組成物亦可製成將其原料分成多份而成的套組。例如可列舉如下態樣:準備於水中含有所述鹵素離子及有機陽離子的液組成物作為第一液,且準備含有硝酸或硝酸根離子的液組成物作為第二液。此時,其他的磺酸化合物等成分可預先分別獨立地或者一併含有於第一液、第二液、或者其他的第三液中。 The etching composition in the present invention can also be made into a set in which the raw material is divided into multiple parts. For example, the following may be mentioned: a liquid composition containing the halogen ions and organic cations in water is prepared as the first liquid, and a liquid composition containing nitric acid or nitrate ions is prepared as the second liquid. At this time, components such as other sulfonic acid compounds may be separately contained in the first liquid, the second liquid, or other third liquids in advance or separately.

其使用例較佳為將兩液混合而製備蝕刻組成物,然後適時地應用於所述蝕刻處理的態樣。藉由如此操作,不會導致由各成分的分解所引起的液性能的劣化,可有效地發揮所需的蝕刻作用。此處,所謂混合後「適時」,是指混合後失去所需作用之前的時期,具體而言,較佳為60分鐘以內,更佳為30分鐘以內,尤佳為10分鐘以內,特佳為1分鐘以內。下限並不特別存在,實際上為1秒以上。 The use example is preferably to mix the two liquids to prepare an etching composition, and then apply the etching composition in a timely manner. By doing this, the liquid performance caused by the decomposition of each component is not deteriorated, and the required etching effect can be effectively exerted. Here, the "time" after mixing refers to the period before the desired effect is lost after mixing. Specifically, it is preferably within 60 minutes, more preferably within 30 minutes, particularly preferably within 10 minutes, and particularly preferably Within 1 minute. The lower limit does not particularly exist, and is actually more than 1 second.

此外,本發明的蝕刻組成物鑒於其使用用途,較佳為液中的雜質、例如金屬成分等少。特佳為液中的Na、K、Ca離子濃度在1ppt~1ppm(質量基準)的範圍內。另外,蝕刻組成物中,較佳為平均粒徑為0.5μm以上的粗大粒子數在100個/cm3以下的範圍內,更佳為在50個/cm3以下的範圍內。 In addition, in view of its use, the etching composition of the present invention preferably has less impurities in the liquid, such as metal components. Especially good is that the concentration of Na, K and Ca ions in the liquid is in the range of 1ppt~1ppm (mass basis). In the etching composition, the number of coarse particles having an average particle diameter of 0.5 μm or more is preferably in the range of 100 particles/cm 3 or less, and more preferably in the range of 50 particles/cm 3 or less.

(容器) (container)

本發明的蝕刻組成物(不論是否為套組)只要腐蝕性等不成問題,則可填充與任意的容器中來保管、搬運以及使用。另外,較佳為面向半導體用途,容器的清潔度高,雜質的溶出少者。可使用的容器可列舉愛賽璐化學(Aicello Chemical)(股)製造的「清潔瓶(Clean Bottle)」系列、兒玉(Kodama)樹脂工業(股)製造的「潔淨瓶(Pure Bottle)」等,但並不限定於該些容器。 The etching composition of the present invention (whether or not it is a set) can be stored, transported, and used in any container as long as the corrosion or the like is not a problem. In addition, it is preferably used for semiconductor applications, the cleanliness of the container is high, and the elution of impurities is small. Usable containers include "Clean Bottle" series manufactured by Aicello Chemical Co., Ltd., and "Pure Bottle" manufactured by Kodama Resin Industry Co., Ltd., But it is not limited to these containers.

[蝕刻條件] [Etching condition]

本發明的蝕刻方法中,較佳為使用單片式裝置。具體而言,單片式裝置較佳為具有處理槽,於所述處理槽中搬送所述半導體基板或使其旋轉,於該處理槽內賦予(噴出、噴射、流下、滴加等)所述蝕刻組成物,使所述蝕刻組成物與半導體基板接觸。 In the etching method of the present invention, it is preferable to use a monolithic device. Specifically, the monolithic device preferably has a processing tank, and the semiconductor substrate is transported or rotated in the processing tank, and the processing tank is provided with (discharging, spraying, flowing down, dropping, etc.). The etching composition is brought into contact with the semiconductor substrate.

單片式裝置的優點可列舉:(i)一直供給新鮮的蝕刻組成物,故而再現性良好;(ii)面內均勻性高。進而,容易利用將蝕刻組成物分成多份的套組,例如適合採用將所述第一液與第二液在線上混合並噴出的方法。此時,較佳為對所述第一液與第二液同時進行溫度調節,或僅對其中一者進行溫度調節,在線上混合並噴出的方法。其中,更佳為同時進行溫度調節的實施態樣。進行管線的溫度調節時的管理溫度較佳為設為與後述處理溫度相同的範圍。 The advantages of the monolithic device include: (i) the fresh etching composition is always supplied, so the reproducibility is good; (ii) the in-plane uniformity is high. Furthermore, it is easy to use a kit in which the etching composition is divided into multiple parts, and for example, a method of mixing and ejecting the first liquid and the second liquid on the line is suitable. At this time, it is preferable to adjust the temperature of the first liquid and the second liquid at the same time, or adjust the temperature of only one of them, and mix and eject on the line. Among them, it is more preferable to implement the temperature adjustment simultaneously. The management temperature when adjusting the temperature of the pipeline is preferably in the same range as the processing temperature described later.

單片式裝置較佳為於其處理槽中具備噴嘴,較佳為使該噴嘴於半導體基板的面方向上擺動而將蝕刻組成物噴出至半導體基板上的方法。藉由如此操作,可防止液的劣化,因此較佳。另外, 藉由製成套組而分成2液以上,則可難以產生氣體等,因此較佳。 The monolithic device preferably includes a nozzle in its processing tank, and preferably a method of swinging the nozzle in the plane direction of the semiconductor substrate to eject the etching composition onto the semiconductor substrate. By doing so, the deterioration of the liquid can be prevented, so it is preferable. In addition, By making it into a set and dividing it into two or more liquids, it is difficult to generate gas, etc., so it is preferable.

進行蝕刻的處理溫度較佳為10℃以上,更佳為20℃以上。上限較佳為80℃以下,更佳為70℃以下,尤佳為60℃以下,尤佳為50℃以下,特佳為40℃以下。藉由設為所述下限值以上,可確保對第二層的充分蝕刻速度,因此較佳。藉由設為所述上限值以下,可維持蝕刻處理速度的經時穩定性,因此較佳。另外,藉由可於室溫附近進行處理,亦可削減能量消耗。 The processing temperature for etching is preferably 10°C or higher, and more preferably 20°C or higher. The upper limit is preferably 80°C or lower, more preferably 70°C or lower, particularly preferably 60°C or lower, particularly preferably 50°C or lower, and particularly preferably 40°C or lower. By setting it to the above lower limit or more, a sufficient etching rate for the second layer can be ensured, which is preferable. By setting it to the said upper limit or less, the stability of the etching process speed with time can be maintained, and therefore it is preferable. In addition, by processing near room temperature, energy consumption can also be reduced.

此外,所謂蝕刻的處理溫度,於後述實施例中所示的溫度測定方法中雖然是以應用於基板上的溫度作為基礎,但可於保存溫度下設定,或者於藉由批次處理來管理的情況下可於其槽內的溫度下設定,於藉由循環系統來管理的情況下可於循環流路內的溫度下設定。 In addition, the processing temperature for etching is based on the temperature applied to the substrate in the temperature measurement method shown in the embodiments described below, but can be set at the storage temperature or managed by batch processing In this case, it can be set at the temperature in the tank, and when it is managed by the circulation system, it can be set at the temperature in the circulation flow path.

蝕刻組成物的供給速度並無特別限定,較佳為設為0.05L/min~5L/min,更佳為設為0.1L/min~3L/min。藉由設為所述下限值以上,可進一步良好地確保蝕刻的面內均勻性,因此較佳。藉由設為所述上限值以下,可於連續處理時確保穩定的性能,因此較佳。當使半導體基板旋轉時,雖亦取決於其大小等,但就與所述相同的觀點而言,較佳為以50rpm~1000rpm使其旋轉。 The supply rate of the etching composition is not particularly limited, but it is preferably 0.05 L/min to 5 L/min, and more preferably 0.1 L/min to 3 L/min. By setting it as the said lower limit value or more, since the in-plane uniformity of etching can be ensured more favorably, it is preferable. By setting it to the upper limit or less, it is possible to ensure stable performance during continuous processing, which is preferable. When the semiconductor substrate is rotated, although it also depends on its size, etc., from the same viewpoint as above, it is preferably rotated at 50 rpm to 1000 rpm.

於本發明的較佳實施形態的單片式的蝕刻中,較佳為使半導體基板在既定的方向上搬送或旋轉,於其空間中噴射蝕刻組成物而使所述蝕刻組成物與所述半導體基板接觸。關於蝕刻組成物的供給速度或基板的旋轉速度,與已述的內容相同。 In the monolithic etching according to the preferred embodiment of the present invention, it is preferable that the semiconductor substrate is transported or rotated in a predetermined direction, and the etching composition is sprayed in its space to make the etching composition and the semiconductor Substrate contact. The supply speed of the etching composition or the rotation speed of the substrate is the same as described above.

所述金屬層較佳為以高蝕刻速率進行蝕刻。第二層(金屬層)的蝕刻速率[R2]並無特別限定,但考慮到生產效率,較佳為20Å/min以上,更佳為100Å/min以上,特佳為200Å/min以上。上限並不特別存在,實際上為1200Å/min以下。 The metal layer is preferably etched at a high etching rate. The etching rate [R2] of the second layer (metal layer) is not particularly limited, but considering production efficiency, it is preferably 20Å/min or more, more preferably 100Å/min or more, and particularly preferably 200Å/min or more. The upper limit does not particularly exist, and is actually below 1200Å/min.

金屬層的露出寬度並無特別限定,就本發明的優點變得更顯著的觀點而言,較佳為2nm以上,更佳為4nm以上。溶氧就效果的顯著性的觀點而言,上限值實際上為1000nm以下,較佳為100nm以下,更佳為20nm以下。 The exposed width of the metal layer is not particularly limited, and from the viewpoint that the advantages of the present invention become more prominent, it is preferably 2 nm or more, and more preferably 4 nm or more. In terms of the significance of the effect of dissolved oxygen, the upper limit is actually 1000 nm or less, preferably 100 nm or less, and more preferably 20 nm or less.

第一層或其矽化物層(第三層)的蝕刻速率[R1]並無特別限定,較佳為未被過度去除,較佳為200Å/min以下,更佳為100Å/min以下,尤佳為50Å/min以下,尤佳為20Å/min以下,特佳為10Å/min以下。下限並不特別存在,若考慮到測定極限,則實際上為0.1Å/min以上。 The etching rate [R1] of the first layer or its silicide layer (third layer) is not particularly limited, and it is preferably not excessively removed, preferably 200 Å/min or less, more preferably 100 Å/min or less, particularly preferably It is below 50Å/min, particularly preferably below 20Å/min, and particularly preferably below 10Å/min. The lower limit does not particularly exist, and if the measurement limit is considered, it is actually 0.1 Å/min or more.

於第一層的選擇性蝕刻中,其蝕刻速率比([R2]/[R1])並無特別限定,若以需要高選擇性的元件為前提而言,則較佳為2以上,更佳為10以上,尤佳為20以上,特佳為50以上。上限並無特別規定,越高越好,實際上為5000以下。此外,矽化物層(第三層)的蝕刻條件在廣義上與含III-V族材料的層(第一層)含義相同,且與其退火前的層(例如含III-V族材料的層)通用,可由其蝕刻速度來代用。 In the selective etching of the first layer, the etching rate ratio ([R2]/[R1]) is not particularly limited. If a device with high selectivity is required, it is preferably at least 2 or more. It is more than 10, especially good is more than 20, especially good is more than 50. The upper limit is not specified, the higher the better, in fact it is 5000 or less. In addition, the etching condition of the silicide layer (third layer) has the same meaning in a broad sense as the layer containing the III-V material (first layer), and is the same as the layer before the annealing (for example, the layer containing the III-V material) Universal, can be substituted by its etching speed.

進而,本發明的較佳實施形態的蝕刻組成物中,由於亦可抑制Al、Cu、Ti、W等的金屬電極層,HfO、HfSiO、AlOx、SiO、 SiOC、SiON、TiN、SiN、TiAlC等的絕緣膜層(有時將該些層統稱為第四層)的損傷,因此亦較佳為應用於包含該些層的半導體基板。此外,本說明書中,於將金屬化合物的組成藉由其元素的組合來表述的情況下,是指廣泛包含任意組成的化合物的含義。例如,所謂SiOC(SiON),是指Si、O及C(N)共存,並非是指其量的比率為1:1:1。這在本說明書中通用,對於其他的金屬化合物亦相同。 Furthermore, in the etching composition according to the preferred embodiment of the present invention, since metal electrode layers such as Al, Cu, Ti, and W can also be suppressed, HfO, HfSiO, AlO x , SiO, SiOC, SiON, TiN, SiN, TiAlC The damage of the insulating film layer (sometimes referred to collectively as the fourth layer) of the insulating film layer is preferably applied to a semiconductor substrate including these layers. In addition, in this specification, when the composition of a metal compound is expressed by a combination of its elements, it means that the compound of an arbitrary composition is widely included. For example, SiOC (SiON) refers to the coexistence of Si, O, and C(N), and does not mean that the ratio of the amounts is 1:1:1. This is common in this specification, and is the same for other metal compounds.

蝕刻一片基板所需要的時間較佳為10秒以上,更佳為50秒以上。上限較佳為300秒以下,更佳為200秒以下。 The time required to etch a substrate is preferably 10 seconds or more, and more preferably 50 seconds or more. The upper limit is preferably 300 seconds or less, and more preferably 200 seconds or less.

[半導體基板產品的製造] [Manufacture of semiconductor substrate products]

本實施形態中,較佳為經由以下步驟來製造具有所需結構的半導體基板產品:製成於矽晶圓上形成有含有所述III-V族材料或Ge的層以及金屬層的半導體基板的步驟;對所述半導體基板進行退火的步驟;以及對半導體基板賦予蝕刻組成物,使蝕刻組成物與金屬層接觸而將所述金屬層選擇性地去除的步驟。此時,蝕刻時使用所述特定的蝕刻組成物。所述步驟的順序不作限定性解釋,亦可於各步驟間更包括其他步驟。 In this embodiment, it is preferable to manufacture a semiconductor substrate product having a desired structure through the following steps: a semiconductor substrate on which a layer containing the III-V group material or Ge and a metal layer are formed on a silicon wafer A step of annealing the semiconductor substrate; and a step of imparting an etching composition to the semiconductor substrate, contacting the etching composition with the metal layer, and selectively removing the metal layer. At this time, the specific etching composition is used for etching. The order of the steps is not limited, and other steps may be included between the steps.

晶圓尺寸並無特別限定,可適當使用直徑8吋、直徑12吋、或者直徑14吋的晶圓(1吋=25.4mm)。 The wafer size is not particularly limited, and a wafer with a diameter of 8 inches, a diameter of 12 inches, or a diameter of 14 inches (1 inch = 25.4 mm) can be used as appropriate.

此外,本說明書中提及「準備」時,是指除了將特定材料合成或調合等來準備以外,還包括藉由購入等來置辦既定的材料。另外,本說明書中,雖將為了對半導體基板的各材料進行蝕刻而 使用蝕刻組成物的情況稱為「應用」,其實施態樣並無特別限定。例如,廣泛包含使蝕刻組成物與基板接觸的情況,具體而言,可於批次式裝置中浸漬而進行蝕刻,亦可於單片式裝置中藉由噴出而進行蝕刻。 In addition, when "preparation" is mentioned in this specification, it means that in addition to preparation by combining or blending specific materials, it also includes the purchase of predetermined materials by purchase. In addition, in this specification, although in order to etch each material of the semiconductor substrate The case of using an etching composition is called "application", and its implementation is not particularly limited. For example, the case where the etching composition is brought into contact with the substrate is widely included. Specifically, it may be immersed in a batch-type device to perform etching, or may be etched by spraying in a monolithic device.

本說明書中,所謂半導體基板,是以不僅包含晶圓,而且包含於其中施予電路結構的基板結構體整體的含義來使用。所謂半導體基板構件,是指構成所述定義的半導體基板的構件,可包含一種材料,亦可包含多種材料。此外,有時將加工完畢的半導體基板作為半導體基板產品而區別稱呼,視需要進一步進行區別,將對其施加加工而切割取出的晶片及其加工產品稱為半導體元件。即,在廣義上,半導體元件或組裝有該半導體元件的半導體產品屬於半導體基板產品。 In this specification, the semiconductor substrate is used to mean not only the wafer but also the entire substrate structure in which the circuit structure is applied. The semiconductor substrate member refers to a member that constitutes the semiconductor substrate as defined above, and may include one material or multiple materials. In addition, the processed semiconductor substrate is sometimes referred to as a semiconductor substrate product, and it is further distinguished as necessary, and the wafer and its processed product that are cut and taken out by processing are called semiconductor elements. That is, in a broad sense, a semiconductor element or a semiconductor product incorporating the semiconductor element belongs to a semiconductor substrate product.

[實施例] [Example]

以下,列舉實施例,對本發明進行更詳細的說明,但本發明並不限定於以下的實施例。此外,只要無特別說明,則實施例中作為配方或調配量來表示的%以及份為質量基準。 Hereinafter, the present invention will be described in more detail with examples, but the present invention is not limited to the following examples. In addition, unless otherwise specified, the% and part expressed as a formula or a blended amount in the examples are based on mass.

[實施例1] [Example 1]

(試驗基板的製作) (Fabrication of test substrate)

於市售的矽基板(直徑:12吋)上,以500Å的膜厚分別形成NiPt層、InGaAs層、InAlAs層、Ge層,準備四種空白晶圓。 On a commercially available silicon substrate (diameter: 12 inches), NiPt layer, InGaAs layer, InAlAs layer, and Ge layer were formed with a thickness of 500Å to prepare four blank wafers.

(蝕刻試驗) (Etching test)

對於所述空白晶圓,利用單片式裝置(SPS-Europe B.V.公司 製造,POLOS(商品名)),於下述條件下進行蝕刻,實施評價試驗。 For the blank wafer, a monolithic device (SPS-Europe B.V. Manufacturing, POLOS (trade name)), etching was performed under the following conditions, and an evaluation test was carried out.

.處理溫度:記載於表中 . Processing temperature: recorded in the table

.噴出量:1L/min. . Spray volume: 1L/min.

.晶圓轉數:500rpm . Wafer speed: 500rpm

.噴嘴移動速度:7cm/S . Nozzle moving speed: 7cm/S

.蝕刻組成物:記載於表中 . Etching composition: described in the table

(處理溫度的測定方法) (Measurement method of processing temperature)

將堀場製作所股份有限公司製造的放射溫度計IT-550F(商品名)固定於所述單片式裝置內的晶圓上方30cm的高度處。使溫度計面向距離晶圓中心2cm的外側的晶圓表面上,一邊流通化學液一邊測量溫度。溫度是自放射溫度計數位輸出,且由個人電腦來連續記錄。將其中溫度穩定的10秒的溫度加以平均而得的值作為晶圓上的溫度。 A radiation thermometer IT-550F (trade name) manufactured by Horiba Manufacturing Co., Ltd. was fixed at a height of 30 cm above the wafer in the monolithic device. With the thermometer facing the wafer surface 2 cm away from the center of the wafer, the temperature was measured while circulating the chemical solution. The temperature is output from the self-emission temperature counter, and is continuously recorded by the personal computer. The temperature on which the temperature is stable for 10 seconds is averaged as the temperature on the wafer.

(蝕刻速度) (Etching speed)

關於蝕刻速度(etching rate,ER),藉由使用橢圓偏光法(分光橢圓偏光儀,使用日本J.A.沃蘭(J.A.Woollam Japan)股份有限公司的Vase),測定蝕刻處理前後的膜厚而算出。採用5點的平均值(測定條件:測定範圍:1.2eV-2.5eV,測定角:70度、75度)。 The etching rate (ER) was calculated by measuring the film thickness before and after the etching process using an ellipsometry (spectral ellipsometer, using Vase of J.A. Woollam Japan Co., Ltd.). The average value of 5 points was used (measurement conditions: measurement range: 1.2 eV-2.5 eV, measurement angle: 70 degrees, 75 degrees).

Figure 104106129-A0305-02-0032-4
Figure 104106129-A0305-02-0032-4

本揭示雖已於本說明書中參照具體的實施形態來進行了說明,但當然,可在不脫離本說明書所記載的本發明思想的精神及範圍的範圍內進行變更、修正及變形。因此,意圖包含不脫離隨附的申請範圍的精神及範圍的範圍內的所述所有的變更、修正及變形。 Although this disclosure has been described with reference to specific embodiments in this specification, of course, changes, corrections, and modifications can be made without departing from the spirit and scope of the inventive idea described in this specification. Therefore, it is intended to include all the changes, modifications, and variations within the scope of the spirit and scope of the accompanying application scope.

雖已對本發明連同其實施態樣一併進行了說明,但只要我們未特別指定,則不會在說明的任一細節部分限定我們的發明,認為可於不違反隨附的申請範圍所示的發明的精神及範圍的情況下廣泛地解釋。 Although the present invention has been described together with its implementation forms, as long as we do not specifically specify it, our invention will not be limited in any detail of the description, and it is believed that it can be used without violating the scope of the accompanying application. The spirit and scope of the invention are widely explained.

本申請案主張基於2014年2月26日向日本提出專利申請的日本專利特願2014-038710的優先權,於本說明書中參照該申請案,將其內容作為本說明書的記載的一部分而併入。 This application claims priority based on Japanese Patent Application No. 2014-038710 for which a patent application was filed in Japan on February 26, 2014. This application is referred to in this specification, and its content is incorporated as part of the description of this specification.

Claims (19)

一種蝕刻方法,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻方法;並且所述蝕刻方法將包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物應用於基板,所述酸性蝕刻組成物中,鹽酸的含量為3~7質量%,且硝酸的含量為5~10質量%,所述第一材料為InGaAs、InAlAs及Ge中的至少一種。 An etching method which is an etching method of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present; and the etching method will include halogen ions, nitric acid or nitrate ions The acidic etching composition is applied to the substrate. In the acidic etching composition, the content of hydrochloric acid is 3 to 7 mass%, and the content of nitric acid is 5 to 10 mass%. The first material is InGaAs, InAlAs and Ge At least one. 如申請專利範圍第1項所述的蝕刻方法,其中所述酸性蝕刻組成物的鹵素離子的含量為10質量%以下。 The etching method as described in item 1 of the patent application range, wherein the content of halogen ions of the acidic etching composition is 10% by mass or less. 如申請專利範圍第1項所述的蝕刻方法,其中所述酸性蝕刻組成物更包含磺酸。 The etching method as described in item 1 of the patent application scope, wherein the acidic etching composition further contains sulfonic acid. 如申請專利範圍第1項所述的蝕刻方法,其中所述酸性蝕刻組成物的含水量為50質量%以下。 The etching method as described in item 1 of the patent application range, wherein the water content of the acidic etching composition is 50% by mass or less. 如申請專利範圍第1項所述的蝕刻方法,其中所述酸性蝕刻組成物的含水量為35質量%以下。 The etching method as described in item 1 of the patent application range, wherein the water content of the acidic etching composition is 35% by mass or less. 如申請專利範圍第1項所述的蝕刻方法,其中於所述基板中進而亦存在Ge。 The etching method as described in item 1 of the patent application scope, wherein Ge is further present in the substrate. 如申請專利範圍第1項所述的蝕刻方法,其中所述第一材料為InGaAs、InP、InAs、AlGaSb、InSb、InAs、GaAs、InAsSb、 GaSb、AlSb、AlAs、InAlAs及GaP中的至少一種。 The etching method as described in item 1 of the patent application scope, wherein the first material is InGaAs, InP, InAs, AlGaSb, InSb, InAs, GaAs, InAsSb, At least one of GaSb, AlSb, AlAs, InAlAs, and GaP. 如申請專利範圍第1項所述的蝕刻方法,其中所述第一材料為InGaAs或InAlAs。 The etching method as described in item 1 of the patent application range, wherein the first material is InGaAs or InAlAs. 一種蝕刻方法,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻方法;並且所述蝕刻方法將包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物應用於基板,所述酸性蝕刻組成物中,硝酸的含量為0.1~10質量%,且鹵素離子的含量為3~10質量%。 An etching method which is an etching method of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present; and the etching method will include halogen ions, nitric acid or nitrate ions The acidic etching composition is applied to the substrate. In the acidic etching composition, the content of nitric acid is 0.1 to 10% by mass, and the content of halogen ions is 3 to 10% by mass. 一種蝕刻方法,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻方法;並且所述蝕刻方法將包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物應用於基板,所述酸性蝕刻組成物中,鹵素離子的含量為3質量%以上。 An etching method which is an etching method of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present; and the etching method will include halogen ions, nitric acid or nitrate ions Of the acidic etching composition is applied to the substrate, and the content of halogen ions in the acidic etching composition is 3% by mass or more. 一種蝕刻方法,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻方法;並且所述蝕刻方法將包含鹵素離子、與硝酸或硝酸根離子的酸性 蝕刻組成物應用於基板,所述酸性蝕刻組成物中,鹵素離子的含量為3~10質量%。 An etching method which is an etching method of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present; and the etching method will include halogen ions, nitric acid or nitrate ions Acidity The etching composition is applied to the substrate. In the acidic etching composition, the content of halogen ions is 3 to 10% by mass. 一種酸性蝕刻組成物,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻組成物;並且包含鹵素離子、與硝酸或硝酸根離子,所述酸性蝕刻組成物中,鹽酸的含量為3~7質量%,且硝酸的含量為5~10質量%,所述第一材料為InGaAs、InAlAs及Ge中的至少一種。 An acidic etching composition, which is an etching composition of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present; and contains halogen ions, nitric acid, or nitrate ions. In the acid etching composition, the content of hydrochloric acid is 3 to 7 mass%, and the content of nitric acid is 5 to 10 mass%, and the first material is at least one of InGaAs, InAlAs, and Ge. 一種酸性蝕刻組成物,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻組成物;並且包含鹵素離子、與硝酸或硝酸根離子,所述酸性蝕刻組成物中,硝酸的含量為0.1~10質量%,且鹵素離子的含量為3~10質量%。 An acidic etching composition, which is an etching composition of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present; and contains halogen ions, nitric acid, or nitrate ions. In the acid etching composition, the content of nitric acid is 0.1 to 10% by mass, and the content of halogen ions is 3 to 10% by mass. 一種酸性蝕刻組成物,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻組成物;並且包含鹵素離子、與硝酸或硝酸根離子, 所述酸性蝕刻組成物中,鹵素離子的含量為3質量%以上。 An acidic etching composition, which is an etching composition of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present; and contains halogen ions, nitric acid, or nitrate ions, In the acid etching composition, the content of halogen ions is 3% by mass or more. 一種酸性蝕刻組成物,其為NiPt以及包含In、Al、Ga、Sb及As中的至少一種的第一材料所存在的基板的蝕刻組成物;並且包含鹵素離子、與硝酸或硝酸根離子,所述酸性蝕刻組成物中,鹵素離子的含量為3~10質量%。 An acidic etching composition, which is an etching composition of a substrate where NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present; and contains halogen ions, nitric acid, or nitrate ions. In the acid etching composition, the content of halogen ions is 3 to 10% by mass. 一種半導體基板產品的製造方法,其包括如下的蝕刻步驟:對含有NiPt的層以及含有第一材料的層所存在的基板,應用包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物,所述第一材料包含In、Al、Ga、Sb及As中的至少一種,所述酸性蝕刻組成物中,鹽酸的含量為3~7質量%,且硝酸的含量為5~10質量%,所述第一材料為InGaAs、InAlAs及Ge中的至少一種。 A method for manufacturing a semiconductor substrate product includes the following etching step: applying an acid etching composition containing halogen ions, nitric acid or nitrate ions to a substrate containing a layer containing NiPt and a layer containing a first material The first material includes at least one of In, Al, Ga, Sb, and As. In the acid etching composition, the content of hydrochloric acid is 3 to 7 mass%, and the content of nitric acid is 5 to 10 mass%. The first material is at least one of InGaAs, InAlAs, and Ge. 一種半導體基板產品的製造方法,其包括如下的蝕刻步驟:對含有NiPt的層以及含有第一材料的層所存在的基板,應用包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物,所述第一材料包含In、Al、Ga、Sb及As中的至少一種,所述酸性蝕刻組成物中,硝酸的含量為0.1~10質量%,且 鹵素離子的含量為3~10質量%。 A method for manufacturing a semiconductor substrate product includes the following etching step: applying an acid etching composition containing halogen ions, nitric acid or nitrate ions to a substrate containing a layer containing NiPt and a layer containing a first material The first material includes at least one of In, Al, Ga, Sb, and As, and the content of nitric acid in the acidic etching composition is 0.1 to 10% by mass, and The content of halogen ion is 3 to 10% by mass. 一種半導體基板產品的製造方法,其包括如下的蝕刻步驟:對含有NiPt的層以及含有第一材料的層所存在的基板,應用包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物,所述第一材料包含In、Al、Ga、Sb及As中的至少一種,所述酸性蝕刻組成物中,鹵素離子的含量為3質量%以上。 A method for manufacturing a semiconductor substrate product includes the following etching step: applying an acid etching composition containing halogen ions, nitric acid or nitrate ions to a substrate containing a layer containing NiPt and a layer containing a first material The first material includes at least one of In, Al, Ga, Sb, and As. In the acidic etching composition, the content of halogen ions is 3% by mass or more. 一種半導體基板產品的製造方法,其包括如下的蝕刻步驟:對含有NiPt的層以及含有第一材料的層所存在的基板,應用包含鹵素離子、與硝酸或硝酸根離子的酸性蝕刻組成物,所述第一材料包含In、Al、Ga、Sb及As中的至少一種,所述酸性蝕刻組成物中,鹵素離子的含量為3~10質量%。 A method for manufacturing a semiconductor substrate product includes the following etching step: applying an acid etching composition containing halogen ions, nitric acid or nitrate ions to a substrate containing a layer containing NiPt and a layer containing a first material The first material includes at least one of In, Al, Ga, Sb, and As. In the acidic etching composition, the content of halogen ions is 3 to 10% by mass.
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