TWI676290B

TWI676290B - High electron mobility transistor and method for forming the same

Info

Publication number: TWI676290B
Application number: TW107130131A
Authority: TW
Inventors: 周鈺傑; Yu Chieh Chou; 林信志; Hsin Chih Lin; 洪章响; Chang Xiang Hung
Original assignee: 世界先進積體電路股份有限公司; Vanguard International Semiconductor Corporation
Priority date: 2018-08-29
Filing date: 2018-08-29
Publication date: 2019-11-01
Also published as: TW202010130A

Abstract

本發明實施例提供一種高電子移動率電晶體，包括：緩衝層位於基板上；阻障層位於緩衝層上，通道區位於緩衝層中，鄰近緩衝層與阻障層之介面；能帶調整層位於阻障層上，由上而下包括第一能帶調整層、第二能帶調整層、及第三能帶調整層；鈍化層位於阻障層上，鄰接能帶調整層；閘極電極位於能帶調整層上，並與能帶調整層電性連接；及源極/汲極電極，分別位於閘極電極之兩相對側，穿過鈍化層，設於阻障層上；第一能帶調整層、第二能帶調整層、及第三能帶調整層分別包括N型摻雜、未摻雜、及P型摻雜三五族半導體或二六族半導體。 An embodiment of the present invention provides a high electron mobility transistor, including: a buffer layer is located on the substrate; a barrier layer is located on the buffer layer; a channel region is located in the buffer layer; the interface between the buffer layer and the barrier layer is adjacent; Located on the barrier layer, including the first band adjustment layer, the second band adjustment layer, and the third band adjustment layer from top to bottom; the passivation layer is located on the barrier layer and adjacent to the band adjustment layer; the gate electrode It is located on the energy band adjustment layer and is electrically connected to the energy band adjustment layer; and the source / drain electrodes are respectively located on two opposite sides of the gate electrode, pass through the passivation layer, and are disposed on the barrier layer; The band adjustment layer, the second energy band adjustment layer, and the third energy band adjustment layer include an N-type doped, undoped, and P-type doped Group III semiconductor or Group II semiconductor.

Description

高電子移動率電晶體及其形成方法 High electron mobility transistor and its forming method

本發明實施例係有關於一種半導體技術，特別是有關於一種高電子移動率電晶體。 Embodiments of the present invention relate to a semiconductor technology, and more particularly to a high electron mobility transistor.

高電子移動率電晶體(High Electron Mobility Transistor，HEMT)因具有高崩潰電壓、高輸出電壓等優點，廣泛應用於高功率半導體裝置當中，以滿足消費電子產品、通訊硬體、電動車、或家電市場需求。 High Electron Mobility Transistor (HEMT) is widely used in high-power semiconductor devices due to its advantages such as high breakdown voltage and high output voltage to meet consumer electronics, communications hardware, electric vehicles, or home appliances. Market demand.

增強型(enhancement mode，E-mode)高電子移動率電晶體在未外加閘極電壓時，即為截止狀態。傳統上，使用P型三五族半導體與閘極電性連接以做為能帶調整層。隨著超高壓應用的需求，需要更高的高電子移動率電晶體的臨界電壓(threshold voltage，Vt)。然而，產生的閘極漏電亦更大，而易造成元件損傷。 Enhancement mode (E-mode) high electron mobility transistor is in the off state when no gate voltage is applied. Traditionally, P-type semiconductors are used to be electrically connected to the gate as a band adjustment layer. With the requirements of ultra-high voltage applications, higher threshold voltages (Vt) of high electron mobility transistors are required. However, the resulting gate leakage is also greater, which can easily cause component damage.

雖然現有的高電子移動率電晶體大致符合需求，但並非各方面皆令人滿意，特別是提升高電子移動率電晶體的臨界電壓與降低其閘極漏電仍需進一步改善。 Although the existing high electron mobility transistors are generally in line with the requirements, they are not satisfactory in all aspects. In particular, improving the threshold voltage and reducing the gate leakage of high electron mobility transistors still needs to be further improved.

根據一實施例，本發明提供一種高電子移動率電晶體包括：緩衝層，位於基板上；阻障層，位於緩衝層上，通道區位於緩衝層中，鄰近緩衝層與阻障層之介面；能帶調整層，位於阻障層上，由上而下包括第一能帶調整層、第二能帶調整層、及第三能帶調整層；鈍化層，位於阻障層上，鄰接能帶調整層；閘極電極，位於能帶調整層上，並與能帶調整層電性連接；及源極/汲極電極，分別位於閘極電極之兩相對側，穿過鈍化層，設於阻障層上；第一能帶調整層包括N型摻雜三五族半導體或N型摻雜二六族半導體，第二能帶調整層包括未摻雜三五族半導體或未摻雜二六族半導體，第三能帶調整層包括P型摻雜三五族半導體或P型摻雜二六族半導體。 According to an embodiment, the present invention provides a high electron mobility transistor including: a buffer layer on a substrate; a barrier layer on the buffer layer; The track area is located in the buffer layer, adjacent to the interface between the buffer layer and the barrier layer; the band adjustment layer is located on the barrier layer, and includes a first band adjustment layer, a second band adjustment layer, and a third layer from top to bottom. Band adjustment layer; passivation layer, located on the barrier layer, adjacent to the band adjustment layer; gate electrode, located on the band adjustment layer, and electrically connected to the band adjustment layer; and source / drain electrodes, respectively It is located on two opposite sides of the gate electrode, passes through the passivation layer, and is disposed on the barrier layer; the first energy band adjustment layer includes an N-type doped group III semiconductor or an N-type doped group II semiconductor, and a second energy band The adjustment layer includes an undoped III-V semiconductor or an undoped II-VI semiconductor, and the third band adjustment layer includes a P-type doped III-V semiconductor or a P-type doped II-VI semiconductor.

根據其他的實施例，本發明提供一種高電子移動率電晶體的形成方法，包括：形成緩衝層於基板上；形成阻障層於緩衝層上，通道區位於緩衝層中，鄰近緩衝層與阻障層之介面；形成一能帶調整層於阻障層上，由上而下包括第一能帶調整層、第二能帶調整層、及第三能帶調整層；形成鈍化層於阻障層上，鄰接能帶調整層；形成閘極電極於能帶調整層上，並與能帶調整層電性連接；及形成源極/汲極電極分別位於閘極電極之兩相對側，穿過鈍化層，設於阻障層上；第一能帶調整層包括N型摻雜三五族半導體或N型摻雜二六族半導體，第二能帶調整層包括未摻雜三五族半導體或未摻雜二六族半導體，第三能帶調整層包括P型摻雜三五族半導體或P型摻雜二六族半導體。 According to other embodiments, the present invention provides a method for forming a high electron mobility transistor, including: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; a channel region is located in the buffer layer; Interface of barrier layer; forming a band adjustment layer on the barrier layer, including a first band adjustment layer, a second band adjustment layer, and a third band adjustment layer from top to bottom; forming a passivation layer on the barrier On the layer, adjacent to the band adjustment layer; forming a gate electrode on the band adjustment layer and electrically connecting with the band adjustment layer; and forming a source / drain electrode on two opposite sides of the gate electrode, passing through A passivation layer is provided on the barrier layer; the first energy band adjustment layer includes an N-type doped Group III semiconductor or an N-type doped Group II or Six semiconductor, and the second energy band adjustment layer includes an undoped Group III or Five semiconductor or The undoped group two and six semiconductors, and the third band adjustment layer include a p-type doped group three or five semiconductor or a p-type doped group six or six semiconductor.

為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉數個實施例，並配合所附圖式，作詳細說明如下。 In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, several embodiments are described below in detail, in conjunction with the accompanying drawings, as follows.

100‧‧‧高電子移動率電晶體 100‧‧‧High Electron Mobility Transistor

102‧‧‧基板 102‧‧‧ substrate

104‧‧‧緩衝層 104‧‧‧Buffer layer

106‧‧‧阻障層 106‧‧‧ barrier layer

108‧‧‧通道區 108‧‧‧ passage area

110‧‧‧能帶調整層 110‧‧‧ band adjustment layer

110a‧‧‧第一能帶調整層 110a‧‧‧First band adjustment layer

110b‧‧‧第二能帶調整層 110b‧‧‧Second band adjustment layer

110c‧‧‧第三能帶調整層 110c‧‧‧Third band adjustment layer

110P‧‧‧能帶調整層 110P‧‧‧band adjustment layer

110NP‧‧‧能帶調整層 110NP‧‧‧ Band Adjustment Layer

112‧‧‧第一鈍化層 112‧‧‧first passivation layer

112a‧‧‧第二鈍化層 112a‧‧‧Second passivation layer

114‧‧‧源極/汲極電極 114‧‧‧source / drain electrode

116‧‧‧閘極電極 116‧‧‧Gate electrode

以下將配合所附圖式詳述本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本發明實施例的特徵。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention.

第1~3、4A、4B、4C、5~8圖係根據一些實施例繪示出形成高電子移動率電晶體不同階段的剖面示意圖。 Figures 1 to 3, 4A, 4B, 4C, and 5 to 8 are schematic cross-sectional views illustrating different stages of forming a high electron mobility transistor according to some embodiments.

第9圖係根據一些實施例所繪示之高電子移動率電晶體的汲極電流-閘極電壓圖。 FIG. 9 is a diagram of a drain current-gate voltage of a high electron mobility transistor according to some embodiments.

第10圖係根據一些實施例所繪示之高電子移動率電晶體的閘極電流-閘極電壓圖。 FIG. 10 is a gate current-gate voltage diagram of a high electron mobility transistor according to some embodiments.

以下公開許多不同的實施方法或是例子來實行本發明實施例之不同特徵，以下描述具體的元件及其排列的實施例以闡述本發明實施例。當然這些實施例僅用以例示，且不該以此限定本發明實施例的範圍。例如，在說明書中提到第一特徵形成於第二特徵之上，其包括第一特徵與第二特徵是直接接觸的實施例，另外也包括於第一特徵與第二特徵之間另外有其他特徵的實施例，亦即，第一特徵與第二特徵並非直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本發明實施例，不代表所討論的不同實施例及/或結構之間有特定的關係。 Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes specific embodiments of the elements and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present invention should not be limited by this. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and also includes the other between the first feature and the second feature. An embodiment of a feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.

此外，其中可能用到與空間相對用詞，例如「在...下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，這些空間相對用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間相對用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相對形容詞也將依轉向後的方位來解釋。 In addition, space-relative terms may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spaces are relatively relative Words are used to facilitate the description of one or more elements or features in the illustration. In relation to another element (s) or feature, these spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used in it will also be interpreted according to the orientation after turning.

在此，「約」、「大約」、「大抵」之用語通常表示在一給定值或範圍的20%之內，較佳是10%之內，且更佳是5%之內，或3%之內，或2%之內，或1%之內，或0.5%之內。應注意的是，說明書中所提供的數量為大約的數量，亦即在沒有特定說明「約」、「大約」、「大抵」的情況下，仍可隱含「約」、「大約」、「大抵」之含義。 Here, the terms "about", "approximately", and "mostly" generally indicate within a given value or range within 20%, preferably within 10%, and more preferably within 5%, or 3 Within%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the description is an approximate quantity, that is, the "about", "approximately", "approximately", "approximately", " "Maybe."

雖然所述的一些實施例中的步驟以特定順序進行，這些步驟亦可以其他合邏輯的順序進行。在不同實施例中，可替換或省略一些所述的步驟，亦可於本發明實施例所述的步驟之前、之中、及/或之後進行一些其他操作。本發明實施例中的高電子移動率電晶體可加入其他的特徵。在不同實施例中，可替換或省略一些特徵。 Although the steps in some of the embodiments described are performed in a particular order, these steps may also be performed in other logical orders. In different embodiments, some of the steps described may be replaced or omitted, and some other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. The high electron mobility transistor in the embodiment of the present invention may add other features. In different embodiments, some features may be replaced or omitted.

本發明實施例提供一種高電子移動率電晶體(high electron mobility transistor，HEMT)，在閘極下方形成能帶調整層，其由上而下依序為N型摻雜、未摻雜、及P型摻雜三五族半導體或二六族半導體的能帶調整層結構，可有效提高臨界電壓，並降低閘極漏電。 An embodiment of the present invention provides a high electron mobility transistor (HEMT). An energy band adjustment layer is formed under a gate electrode, and the band adjustment layer is N-type doped, undoped, and P in order from top to bottom. The band adjustment layer structure of the type-doped III-V semiconductor or II-V semiconductor can effectively increase the threshold voltage and reduce gate leakage.

第1至8圖係根據一些實施例繪示出形成高電子移動率電晶體100不同階段的剖面示意圖。如第1圖所繪示，提供一基板102。在一些實施例中，此基板102可為Al₂O₃(藍寶石 (sapphire))基板。此外，上述半導體基板亦可為元素半導體，包括矽(silicon)或鍺(germanium)；化合物半導體，包括氮化鎵(gallium nitride，GaN)、碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)；合金半導體，包括矽鍺合金(SiGe)、磷砷鎵合金(GaAsP)、砷鋁銦合金(AlInAs)、砷鋁鎵合金(AlGaAs)、砷銦鎵合金(GaInAs)、磷銦鎵合金(GaInP)及/或磷砷銦鎵合金(GaInAsP)或上述材料之組合。在一些實施例中，基板102可為單晶基板、多層基板(multi-layer substrate)、梯度基板(gradient substrate)、其他適當之基板或上述之組合。此外，基板102也可以是絕緣層上覆半導體(semiconductor on insulator)基板，上述絕緣層覆半導體基板可包括底板、設置於底板上之埋藏氧化層、或設置於埋藏氧化層上之半導體層。 1 to 8 are schematic cross-sectional views illustrating different stages of forming the high electron mobility transistor 100 according to some embodiments. As shown in FIG. 1, a substrate 102 is provided. In some embodiments, the substrate 102 may be an Al ₂ O ₃ (sapphire) substrate. In addition, the above semiconductor substrate may also be an element semiconductor, including silicon or germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide, and gallium arsenide Gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium alloy (SiGe), phosphorous arsenic alloy (GaAsP), AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or any of the above materials combination. In some embodiments, the substrate 102 may be a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In addition, the substrate 102 may also be a semiconductor on insulator substrate. The insulating semiconductor substrate may include a base plate, a buried oxide layer provided on the base plate, or a semiconductor layer provided on the buried oxide layer.

接著，如第2圖所繪示，在基板102上形成緩衝層104。在一些實施例中，緩衝層104包括III-V族半導體，例如GaN。緩衝層104亦可包括AlGaN、AlN、GaAs、GaInP、AlGaAs、InP、InAlAs、InGaAs、其他適當的III-V族半導體材料、或上述之組合。在一些實施例中，緩衝層104厚度小於20μm。在一些實施例中，可使用分子束磊晶法(molecular-beam epitaxy，MBE)、有機金屬氣相沉積法(metalorganic chemical vapor deposition，MOCVD)、氫化物氣相磊晶法(hydride vapor phase epitaxy，HVPE)、其他適當之方法、或上述之組合在基板102上形成緩衝層104。 Next, as shown in FIG. 2, a buffer layer 104 is formed on the substrate 102. In some embodiments, the buffer layer 104 includes a III-V semiconductor, such as GaN. The buffer layer 104 may also include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other appropriate III-V semiconductor materials, or a combination thereof. In some embodiments, the thickness of the buffer layer 104 is less than 20 μm. In some embodiments, molecular-beam epitaxy (MBE), organic metal vapor deposition (MOCVD), hydride vapor phase epitaxy, (HVPE), other appropriate methods, or a combination thereof to form a buffer layer 104 on the substrate 102.

接著，如第3圖所繪示，在緩衝層104上形成阻障層106，在一些實施例中，阻障層106包括與緩衝層104相異之材料。阻障層106可包括III-V族半導體，例如Al_xGa_1-xN，其中0<x<1。阻障層106亦可包括GaN、AlN、GaAs、GaInP、AlGaAs、InP、InAlAs、InGaAs、其他適當的III-V族材料或上述之組合。在一些實施例中，阻障層106厚度小於100nm。在一些實施例中，可使用分子束磊晶法、有機金屬氣相沉積法、氫化物氣相磊晶法、其他適當之方法、或上述之組合在緩衝層104上形成阻障層106。 Next, as shown in FIG. 3, a barrier layer 106 is formed on the buffer layer 104. In some embodiments, the barrier layer 106 includes a material different from the buffer layer 104. The barrier layer 106 may include a III-V semiconductor, such as Al _x Ga _1-x N, where 0 <x <1. The barrier layer 106 may also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or a combination thereof. In some embodiments, the thickness of the barrier layer 106 is less than 100 nm. In some embodiments, the barrier layer 106 may be formed on the buffer layer 104 using a molecular beam epitaxy method, an organic metal vapor deposition method, a hydride vapor epitaxy method, other suitable methods, or a combination thereof.

由於緩衝層104與阻障層106之材料相異，其能帶間隙(band gap)不同，緩衝層104與阻障層106的介面處形成異質接面(heterojunction)。異質接面處的能帶彎曲，導帶(conduction band)彎曲深處形成量子井(quantum well)，將壓電效應(Piezoelectricity)所產生的電子約束於量子井中，因此在緩衝層104與阻障層106的介面處形成二維電子氣(two-dimensional electron gas，2DEG)，進而形成導通電流。如第3圖所示，在緩衝層104與阻障層106的介面處形成通道區108，通道區108即為二維電子氣形成導通電流之處。 Because the materials of the buffer layer 104 and the barrier layer 106 are different, and their band gaps are different, a heterojunction is formed at the interface between the buffer layer 104 and the barrier layer 106. The energy band at the heterojunction is bent, and the quantum well is formed deep in the conduction band. The electrons generated by the piezoelectric effect are confined in the quantum well. Therefore, the buffer layer 104 and the barrier A two-dimensional electron gas (2DEG) is formed at the interface of the layer 106 to form an on-current. As shown in FIG. 3, a channel region 108 is formed at the interface between the buffer layer 104 and the barrier layer 106, and the channel region 108 is where the two-dimensional electron gas forms a conduction current.

接著，如第4A圖所繪示，在阻障層106上形成能帶調整層(band adjustment layer)110。在一些實施例中，能帶調整層110由上而下包括第一能帶調整層110a、第二能帶調整層110b、第三能帶調整層110c。在一些實施例中，第一能帶調整層110a與第二能帶調整層110b直接接觸，且第二能帶調整層110b與第三能帶調整層110c直接接觸。 Next, as shown in FIG. 4A, a band adjustment layer 110 is formed on the barrier layer 106. In some embodiments, the energy band adjustment layer 110 includes a first energy band adjustment layer 110a, a second energy band adjustment layer 110b, and a third energy band adjustment layer 110c from top to bottom. In some embodiments, the first band adjustment layer 110a is in direct contact with the second band adjustment layer 110b, and the second band adjustment layer 110b is in direct contact with the third band adjustment layer 110c.

在一些實施例中，第三能帶調整層110c包括P型摻雜三五族半導體或P型摻雜二六族半導體。舉例而言，第三能帶調整層110c包括P型摻雜之GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、InGaAs、CdS、CdTe、SiGe、SiC、或ZnS。在一些實施例中，第三能帶調整層110c係以Mg、Zn、Ca、Be、Sr、Ba、Ra、C、Ag、Au、Li、或Na進行P型摻雜，其P型摻雜濃度介於1E15/cm³至1E25/cm³之間。在一些實施例中，第三能帶調整層110c之厚度為能帶調整層110之厚度的1%至99%，較佳為能帶調整層110之厚度的50%至90%，第三能帶調整層110c之厚度介於1nm至1000nm。在一些實施例中，可藉由調整第三能帶調整層110c的P型摻雜濃度以及厚度調整能帶的高低。舉例而言，第三能帶調整層110c的P型摻雜濃度較高以及厚度較厚時，能帶可能較高，因而在通道區108中所產生的二維電子氣可能較少。反之，第三能帶調整層110c的P型摻雜濃度較低以及厚度較薄時，能帶可能較低，因而在通道區108中所產生的二維電子氣可能較多。在一些實施例中，可使用分子束磊晶法、有機金屬氣相沉積法、化學氣相沉積法、氫化物氣相磊晶法，在阻障層106上沉積P型摻雜三五族半導體材料或P型摻雜二六族半導體材料以形成第三能帶調整層110c。 In some embodiments, the third band adjustment layer 110c includes a P-type doped III-V semiconductor or a P-type doped II-VI semiconductor. For example, the third band adjustment layer 110c includes P-doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe, SiGe, SiC, or ZnS. In some embodiments, the third band adjustment layer 110c is P-type doped with Mg, Zn, Ca, Be, Sr, Ba, Ra, C, Ag, Au, Li, or Na, and the P-type doped The concentration is between 1E15 / cm ³ and 1E25 / cm ³ . In some embodiments, the thickness of the third band adjustment layer 110c is 1% to 99% of the thickness of the band adjustment layer 110, and preferably 50% to 90% of the thickness of the band adjustment layer 110. The thickness of the band adjustment layer 110c is between 1 nm and 1000 nm. In some embodiments, the P-type doping concentration of the third band adjustment layer 110 c and the height of the band can be adjusted by adjusting the P-type doping concentration of the third band adjustment layer 110 c. For example, when the P-type doping concentration of the third band adjustment layer 110c is higher and the thickness is thicker, the band may be higher, so that two-dimensional electron gas generated in the channel region 108 may be less. Conversely, when the P-type doping concentration of the third energy band adjustment layer 110c is low and the thickness is thin, the energy band may be lower, so more two-dimensional electron gas may be generated in the channel region 108. In some embodiments, molecular beam epitaxy, organic metal vapor deposition, chemical vapor deposition, and hydride vapor epitaxy can be used to deposit P-type doped Group III semiconductors on the barrier layer 106. Material or P-type doped two or six semiconductor materials to form the third band adjustment layer 110c.

在一些實施例中，第二能帶調整層110b包括未摻雜三五族半導體或未摻雜二六族半導體。舉例而言，第二能帶調整層110b包括未摻雜之GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、InGaAs、CdS、CdTe、SiGe、SiC、或ZnS。在一些實施例中，第二能帶調整層110b之厚度為能帶調整層110 之厚度的1%至99%，較佳為能帶調整層110之厚度的10%至50%。在一些實施例中，第二能帶調整層110b厚度介於10nm至1000nm。第二能帶調整層110b之厚度若太厚，則閘極電阻太高，第二能帶調整層110b之厚度若太薄，則在對能帶調整層110施加逆向偏壓時空乏區太小，無法有效降低閘極漏電。在一些實施例中，可使用分子束磊晶法、有機金屬氣相沉積法、化學氣相沉積法、氫化物氣相磊晶法，在第三能帶調整層110c上沉積未摻雜三五族半導體材料或未摻雜二六族半導體材料以形成第二能帶調整層110b。 In some embodiments, the second band adjustment layer 110b includes an undoped III-V semiconductor or an undoped II-VI semiconductor. For example, the second band adjustment layer 110b includes undoped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe, SiGe, SiC, or ZnS. In some embodiments, the thickness of the second band adjustment layer 110 b is the band adjustment layer 110. 1% to 99% of the thickness, preferably 10% to 50% of the thickness of the band adjustment layer 110. In some embodiments, the thickness of the second band adjustment layer 110b is between 10 nm and 1000 nm. If the thickness of the second energy band adjustment layer 110b is too thick, the gate resistance is too high. If the thickness of the second energy band adjustment layer 110b is too thin, the empty space is too small when a reverse bias is applied to the energy band adjustment layer 110. , Can not effectively reduce the gate leakage. In some embodiments, molecular beam epitaxy, organic metal vapor deposition, chemical vapor deposition, and hydride vapor epitaxy can be used to deposit undoped quintile on the third band adjustment layer 110c. Group semiconductor material or undoped group two or six semiconductor material to form the second band adjustment layer 110b.

在一些實施例中，第一能帶調整層110a包括N型摻雜三五族半導體或N型摻雜二六族半導體。舉例而言，第一能帶調整層110a包括N型摻雜之GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、InGaAs、CdS、CdTe、SiC、SiGe、或ZnS。在一些實施例中，第一能帶調整層110a係以Si、C、Ge、Sn、Pb、Cl、Br、或I進行N型摻雜，其N型摻雜濃度介於1E15/cm³至1E25/cm³之間。在一些實施例中，第一能帶調整層110a之厚度為能帶調整層110之厚度的1%至99%，較佳為能帶調整層110之厚度的10%至50%，第一能帶調整層110a的厚度介於1nm至1000nm。在一些實施例中，可藉由調整第一能帶調整層110a的N型摻雜濃度以及厚度調整能帶的高低。舉例而言，當第一能帶調整層110a的N型摻雜濃度較高以及厚度較厚時，在高電子移動率電晶體100開啟(閘極電壓大於零)時，能帶調整層110整體能帶較不易降低。反之，當第一能帶調整層110a的N型摻雜濃度較低以及厚度較薄時，在高電子移動率電晶體100開啟 (閘極電壓大於零)時，能帶調整層110整體能帶較容易降低。在一些實施例中，可使用分子束磊晶法、有機金屬氣相沉積法、化學氣相沉積法、氫化物氣相磊晶法，在第二能帶調整層110b上沉積N型摻雜三五族半導體材料或N型摻雜二六族半導體材料以形成第一能帶調整層110a。 In some embodiments, the first band adjustment layer 110a includes an N-type doped III-V semiconductor or an N-type doped II-VI semiconductor. For example, the first band adjustment layer 110a includes N-doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe, SiC, SiGe, or ZnS. In some embodiments, the first band adjustment layer 110a is N-type doped with Si, C, Ge, Sn, Pb, Cl, Br, or I, and the N-type doping concentration is between 1E15 / cm ³ to 1E25 / cm ^3. In some embodiments, the thickness of the first band adjustment layer 110a is 1% to 99% of the thickness of the band adjustment layer 110, and preferably 10% to 50% of the thickness of the band adjustment layer 110. The thickness of the band adjustment layer 110a is between 1 nm and 1000 nm. In some embodiments, the N-type doping concentration of the first energy band adjustment layer 110a and the height of the energy band can be adjusted by adjusting the N-type doping concentration of the first energy band adjustment layer 110a. For example, when the N-type doping concentration of the first band adjustment layer 110a is high and the thickness is thick, when the high electron mobility transistor 100 is turned on (gate voltage is greater than zero), the entire band adjustment layer 110 is formed. The energy band is less easily reduced. Conversely, when the N-type doping concentration of the first band adjustment layer 110a is low and the thickness is thin, when the high electron mobility transistor 100 is turned on (gate voltage is greater than zero), the overall band of the band adjustment layer 110 is Easier to lower. In some embodiments, molecular beam epitaxy, organometallic vapor deposition, chemical vapor deposition, and hydride vapor epitaxy can be used to deposit N-type doped three on the second band adjustment layer 110b. The Group 5 semiconductor material or the N-type doped Group 2 or 6 semiconductor material forms the first band adjustment layer 110a.

在一些實施例中，第一能帶調整層110a、第二能帶調整層110b、及第三能帶調整層110c可包括同一種三五族半導體材料或二六族半導體材料，藉由N型摻雜、未摻雜、P型摻雜之摻質及濃度調整能帶調整層110的能帶結構。在另一些實施例中，第一能帶調整層110a、第二能帶調整層110b、及第三能帶調整層110c可包括不同三五族半導體材料或二六族半導體材料，可藉由不同材料不同的能帶結構，以及N型摻雜、未摻雜、P型摻雜之摻質及濃度調整能帶調整層110的能帶結構。 In some embodiments, the first energy band adjustment layer 110a, the second energy band adjustment layer 110b, and the third energy band adjustment layer 110c may include the same Group III semiconductor material or the Group II semiconductor material. The doped, undoped, and P-doped dopants and the energy band structure of the energy band adjustment layer 110. In other embodiments, the first band adjustment layer 110a, the second band adjustment layer 110b, and the third band adjustment layer 110c may include different Group III semiconductor materials or Group II semiconductor materials. Different band structures of materials, and dopants of N-type doped, undoped and P-type doped and concentration-adjusted band adjustment layer 110.

接著，可藉由微影及蝕刻製程將第一能帶調整層110a、第二能帶調整層110b、及第三能帶調整層110c圖案化而形成能帶調整層110。微影製程可包括光阻塗佈(例如旋轉塗佈)、軟烤(soft baking)、罩幕對準、曝光圖案、曝光後烘烤、光阻顯影、清洗及乾燥(例如硬烤(hard baking))、其他合適的技術、或上述之組合。蝕刻製程可包括乾蝕刻製程(例如反應離子蝕刻、非等向性電漿蝕刻)、濕蝕刻製程、或上述之組合。在一些實施例中，能帶調整層110位於後續將形成的閘極電極的下方。 Then, the first band adjustment layer 110a, the second band adjustment layer 110b, and the third band adjustment layer 110c may be patterned by a lithography and etching process to form the band adjustment layer 110. Lithography processes can include photoresist coating (e.g. spin coating), soft baking, mask alignment, exposure pattern, post-exposure baking, photoresist development, cleaning and drying (e.g. hard baking )), Other suitable technologies, or a combination thereof. The etching process may include a dry etching process (for example, reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination thereof. In some embodiments, the band adjustment layer 110 is located below a gate electrode to be formed later.

值得注意的是，在前述說明中，係分別沉積第三能帶調整層110c、第二能帶調整層110b、及第一能帶調整層 110a後再一起圖案化而形成能帶調整層110。然而，本發明實施例並不以此為限。在一些實施例中，可在分別沉積第三能帶調整層110c、第二能帶調整層110b、及第一能帶調整層110a後分別圖案化以形成能帶調整層能帶調整層110。 It is worth noting that in the foregoing description, the third band adjustment layer 110c, the second band adjustment layer 110b, and the first band adjustment layer were separately deposited. After 110a, they are patterned together to form the band adjustment layer 110. However, the embodiments of the present invention are not limited thereto. In some embodiments, the third band adjustment layer 110c, the second band adjustment layer 110b, and the first band adjustment layer 110a may be separately patterned to form the band adjustment layer band adjustment layer 110 after being deposited.

相較於如第4B圖所示的僅包括第三能帶調整層110c的P能帶調整層結構110P或如第4C圖所示的由上而下僅包括第一能帶調整層110a及第三能帶調整層110c的NP能帶調整層結構110NP，藉由形成由上而下包括第一能帶調整層110a、第二能帶調整層110b、第三能帶調整層110c的NIP能帶調整層110可提高高電子移動率電晶體100開啟(閘極電壓大於零)時的能帶。如此一來，緩衝層104與阻障層106之介面處的導帶能量較高，導致通道區108中二維電子氣較少。若欲於通道區108形成導通電流，需再增加閘極電壓，才能使能帶下降，形成導通電流。因此，NIP能帶調整層結構110可提升高電子移動率電晶體100的臨界電壓，消除超高壓雜訊干擾。在一些實施例中，具有NIP能帶調整層結構110的電子移動率電晶體100可適用於大於1000V的應用。 Compared to the P band adjustment layer structure 110P including only the third band adjustment layer 110c as shown in FIG. 4B or the first band adjustment layer 110a and the first band adjustment layer as shown in FIG. 4C from top to bottom The NP band adjustment layer structure 110NP of the three band adjustment layer 110c forms a NIP band including the first band adjustment layer 110a, the second band adjustment layer 110b, and the third band adjustment layer 110c from top to bottom. The adjustment layer 110 can increase the energy band when the high electron mobility transistor 100 is turned on (gate voltage is greater than zero). As a result, the conduction band energy at the interface between the buffer layer 104 and the barrier layer 106 is higher, resulting in less two-dimensional electron gas in the channel region 108. If the on-state current is to be formed in the channel region 108, the gate voltage needs to be increased before the energy band can be lowered to form the on-state current. Therefore, the NIP band adjustment layer structure 110 can increase the threshold voltage of the high electron mobility transistor 100 and eliminate the ultra-high voltage noise interference. In some embodiments, the electron mobility transistor 100 having the NIP band adjustment layer structure 110 may be suitable for applications greater than 1000V.

此外，相較於P能帶調整層結構110P或NP能帶調整層結構110NP，NIP能帶調整層結構110在高電子移動率電晶體100開啟(閘極電壓大於零)時是逆向偏壓，此時第二能帶調整層110b可使空乏區變大。如此一來，閘極漏電可大幅降低，因而可增加閘極電壓操作範圍。 In addition, compared with the P band adjustment layer structure 110P or the NP band adjustment layer structure 110NP, the NIP band adjustment layer structure 110 is reverse biased when the high electron mobility transistor 100 is turned on (gate voltage is greater than zero), At this time, the second band adjustment layer 110b can increase the empty area. In this way, the gate leakage can be greatly reduced, thereby increasing the operating range of the gate voltage.

值得注意的是，在第4A圖中能帶調整層110包括三層能帶調整層110a、110b、110c，然而，本發明實施例並不以此為限，能帶調整層110可包括三層以上的能帶調整層，其整體而言由上而下包括N型摻雜三五族半導體或N型摻雜二六族半導體、未摻雜三五族半導體或未摻雜二六族半導體、及P型摻雜三五族半導體或P型摻雜二六族半導體，視製程需求而定。 It should be noted that the band adjustment layer 110 in FIG. 4A includes three band adjustment layers 110a, 110b, and 110c. However, the embodiment of the present invention does not use This is a limitation. The energy band adjustment layer 110 may include three or more energy band adjustment layers. Generally speaking, the energy band adjustment layer 110 includes an N-type doped group III semiconductor or an N-type doped group II semiconductor, and an undoped layer. The three or five group semiconductors or undoped two or six group semiconductors, and the P type doped three or five group semiconductors or the p type doped two or six group semiconductors depend on the process requirements.

接著，如第5圖所示，形成第一鈍化層112於阻障層106上並鄰接能帶調整層110。在一些實施例中，第一鈍化層112可包括SiO₂、SiN₃、SiON、Al₂O₃、AlN、聚亞醯胺(polyimide，PI)、苯環丁烯(benzocyclobutene，BCB)、聚苯并噁唑(polybenzoxazole，PBO)、其他絕緣材料、或上述之組合。第一鈍化層112厚度介於1nm至1000nm之間。在一些實施例中，可使用有機金屬氣相沉積法、化學氣相沉積法、旋轉塗佈法、其他適當之方法、或上述之組合形成第一鈍化層112。在一些實施例中，第一鈍化層112可毯覆性地(blanketly)形成於阻障層106及能帶調整層110上。接著，第一鈍化層112可經化學機械研磨(chemical mechanical polishing，CMP)而具有平坦的上表面。在一些實施例中，第一鈍化層112的頂表面與能帶調整層110的頂表面等高。第一鈍化層112可保護下方的膜層，並提供物理隔離及結構支撐。 Next, as shown in FIG. 5, a first passivation layer 112 is formed on the barrier layer 106 and is adjacent to the band adjustment layer 110. In some embodiments, the first passivation layer 112 may include SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzene Polybenzoxazole (PBO), other insulating materials, or a combination thereof. The thickness of the first passivation layer 112 is between 1 nm and 1000 nm. In some embodiments, the first passivation layer 112 may be formed using an organic metal vapor deposition method, a chemical vapor deposition method, a spin coating method, other suitable methods, or a combination thereof. In some embodiments, the first passivation layer 112 may be blanket formed on the barrier layer 106 and the band adjustment layer 110. Then, the first passivation layer 112 may have a flat upper surface by chemical mechanical polishing (CMP). In some embodiments, the top surface of the first passivation layer 112 is the same height as the top surface of the band adjustment layer 110. The first passivation layer 112 can protect the underlying film layer and provide physical isolation and structural support.

接著，如第6圖所示，形成源極/汲極電極114，其穿過第一鈍化層112，設置於阻障層106上。在一些實施例中，源極/汲極電極114各自可包括Ti、Al、W、Au、Pd、其他適當之金屬材料、其合金、或上述之組合。在一些實施例中，可進行微影製程及蝕刻製程，於第一鈍化層112中形成源極/汲極電極開口，接著以化學氣相沉積法、物理氣相沉積法(例如蒸鍍或濺鍍)、電鍍、原子層沉積法、其他適當之方法、或上述之組合於第一鈍化層112上沉積導電材料並填入上述源極/汲極電極開口中，之後以蝕刻製程去除開口以外的導電材料，以形成源極/汲極電極114。 Next, as shown in FIG. 6, a source / drain electrode 114 is formed, which passes through the first passivation layer 112 and is disposed on the barrier layer 106. In some embodiments, each of the source / drain electrodes 114 may include Ti, Al, W, Au, Pd, other suitable metal materials, an alloy thereof, or a combination thereof. In some embodiments, a lithography process and an etching process may be performed to form a source / drain electrode in the first passivation layer 112. The electrode is opened, and then conductive is deposited on the first passivation layer 112 by chemical vapor deposition, physical vapor deposition (such as evaporation or sputtering), electroplating, atomic layer deposition, other appropriate methods, or a combination thereof. The material is filled into the above source / drain electrode opening, and then conductive materials other than the opening are removed by an etching process to form the source / drain electrode 114.

接著，如第7圖所示，形成第二鈍化層112a於第一鈍化層112、能帶調整層110、及源極/汲極電極114上。在一些實施例中，第二鈍化層112a可包括SiO₂、SiN₃、SiON、Al₂O₃、AlN、聚亞醯胺(polyimide，PI)、苯環丁烯(benzocyclobutene，BCB)、聚苯并噁唑(polybenzoxazole，PBO)、其他絕緣材料、或上述之組合。在一些實施例中，第一鈍化層112與第二鈍化層112a材料相同。在另一些實施例中，第一鈍化層112與第二鈍化層112a材料不同。第二鈍化層112a厚度介於1nm至1000nm之間。在一些實施例中，可使用有機金屬氣相沉積法、化學氣相沉積法、旋轉塗佈法、其他適當之方法、或上述之組合形成第二鈍化層112a。在一些實施例中，可順應性地(conformally)形成第二鈍化層112a於第一鈍化層112、能帶調整層110、及源極/汲極電極114上。 Next, as shown in FIG. 7, a second passivation layer 112 a is formed on the first passivation layer 112, the band adjustment layer 110, and the source / drain electrode 114. In some embodiments, the second passivation layer 112a may include SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzene Polybenzoxazole (PBO), other insulating materials, or a combination thereof. In some embodiments, the first passivation layer 112 is the same material as the second passivation layer 112a. In other embodiments, the materials of the first passivation layer 112 and the second passivation layer 112a are different. The thickness of the second passivation layer 112a is between 1 nm and 1000 nm. In some embodiments, the second passivation layer 112a may be formed using an organic metal vapor deposition method, a chemical vapor deposition method, a spin coating method, other suitable methods, or a combination thereof. In some embodiments, a second passivation layer 112 a may be conformally formed on the first passivation layer 112, the band adjustment layer 110, and the source / drain electrode 114.

接著，如第8圖所繪示，形成閘極電極116於能帶調整層110上。在一些實施例中，閘極電極116可包括多晶矽、金屬(例如鎢、鈦、鋁、銅、鉬、鎳、鉑、其相似物、或以上之組合)、金屬合金、金屬氮化物(例如氮化鎢、氮化鉬、氮化鈦、氮化鉭、其相似物、或以上之組合)、金屬矽化物(例如矽化鎢、矽化鈦、矽化鈷、矽化鎳、矽化鉑、矽化鉺、其相似物、或以上之組合)、金屬氧化物(氧化釕、氧化銦錫、其相似物、或以上之組合)、其他適用的導電材料、或上述之組合。在一些實施例中，可進行微影製程及蝕刻製程，以於第二鈍化層112a中形成閘極開口，接著使用化學氣相沉積製程(例如低壓氣相沉積製程或電漿輔助化學氣相沉積製程)、物理氣相沉積製程(例如電阻加熱蒸鍍法、電子束蒸鍍法、或濺鍍法)、電鍍法、原子層沉積製程、其他合適的製程、或上述之組合於第二鈍化層112a上沉積導電材料，並填入上述閘極開口中，之後以蝕刻製程去除開口以外的導電材料以形成閘極電極116。在一些實施例中，閘極電極116與能帶調整層110上電性連接。 Next, as shown in FIG. 8, a gate electrode 116 is formed on the band adjustment layer 110. In some embodiments, the gate electrode 116 may include polycrystalline silicon, a metal (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or a combination thereof), a metal alloy, a metal nitride (e.g., nitrogen Tungsten silicide, molybdenum nitride, titanium nitride, tantalum nitride, or the like, or metal silicides (such as tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, hafnium silicide, etc.) Things, Or a combination thereof), a metal oxide (ruthenium oxide, indium tin oxide, the like, or a combination thereof), other applicable conductive materials, or a combination thereof. In some embodiments, a lithography process and an etching process may be performed to form a gate opening in the second passivation layer 112a, and then a chemical vapor deposition process (such as a low pressure vapor deposition process or a plasma-assisted chemical vapor deposition) is used. Process), physical vapor deposition process (such as resistance heating evaporation, electron beam evaporation, or sputtering), electroplating, atomic layer deposition, other suitable processes, or a combination of the above on the second passivation layer A conductive material is deposited on 112a and filled into the gate opening, and then conductive materials other than the opening are removed by an etching process to form the gate electrode 116. In some embodiments, the gate electrode 116 is electrically connected to the band adjustment layer 110.

如上所述，藉由於閘極下方由上而下形成包括N型摻雜三五族半導體或N型摻雜二六族半導體、未摻雜三五族半導體或未摻雜二六族半導體、及P型摻雜三五族半導體或P型摻雜二六族半導體的NIP能帶調整層，可提高高電子移動率電晶體的臨界電壓，消除超高壓雜訊干擾，並可降低閘極漏電電流，以增加閘極操作範圍。 As described above, the formation of N-type doped Group III semiconductors or N-type doped Group II semiconductors, undoped Group III or V semiconductors or undoped Group II or VI semiconductors, and N-type band adjustment layer for P-type doped III or V semiconductors or P-type doped II or 6 semiconductors can increase the critical voltage of high electron mobility transistors, eliminate extra-high voltage noise interference, and reduce gate leakage current To increase the gate operating range.

第9圖係根據一些實施例所繪示之高電子移動率電晶體的汲極電流-閘極電壓圖。虛線數據代表高電子移動率電晶體包括P能帶調整層結構110P，鍊線數據代表高電子移動率電晶體包括NP能帶調整層結構110NP，實線數據代表高電子移動率電晶體包括NIP能帶調整層110。 FIG. 9 is a diagram of a drain current-gate voltage of a high electron mobility transistor according to some embodiments. The dotted line data represents the high electron mobility transistor including the P band adjustment layer structure 110P, the chain line data represents the high electron mobility transistor including the NP band adjustment layer structure 110NP, and the solid line data represents the high electron mobility transistor including the NIP energy Belt adjustment layer 110.

如第9圖所示，在相同汲極電流之下，具有NIP結構能帶調整層110的高電子移動率電晶體的閘極電壓較大。亦即，具有NIP結構能帶調整層110的高電子移動率電晶體的臨界電壓較大。因此，NIP結構能帶調整層110在高電子移動率電晶體開啟(閘極電壓大於零)時，可有效增加臨界電壓。 As shown in FIG. 9, under the same drain current, the gate voltage of the high electron mobility transistor having the NIP structure band adjustment layer 110 is large. That is, the criticality of the high electron mobility transistor having the NIP structure band adjustment layer 110 The voltage is high. Therefore, the NIP structure band adjustment layer 110 can effectively increase the threshold voltage when the high electron mobility transistor is turned on (gate voltage is greater than zero).

第10圖係根據一些實施例所繪示之高電子移動率電晶體的閘極電流-閘極電壓圖。虛線數據代表高電子移動率電晶體包括P能帶調整層結構110P，鍊線數據代表高電子移動率電晶體包括NP能帶調整層結構110NP，實線數據代表高電子移動率電晶體包括NIP能帶調整層110。 FIG. 10 is a gate current-gate voltage diagram of a high electron mobility transistor according to some embodiments. The dotted line data represents the high electron mobility transistor including the P band adjustment layer structure 110P, the chain line data represents the high electron mobility transistor including the NP band adjustment layer structure 110NP, and the solid line data represents the high electron mobility transistor including the NIP energy Belt adjustment layer 110.

如第10圖所示，在相同的閘極電壓下，具有NIP結構能帶調整層110的高電子移動率電晶體的閘極電流較小。亦即，具有NIP結構能帶調整層110的高電子移動率電晶體的閘極漏電較小。因此，NIP結構能帶調整層110可有效增加閘極操作之範圍。 As shown in FIG. 10, under the same gate voltage, the gate current of the high electron mobility transistor having the NIP structure band adjustment layer 110 is small. That is, the gate leakage of the high electron mobility transistor having the NIP structure band adjustment layer 110 is small. Therefore, the NIP structure band adjustment layer 110 can effectively increase the range of gate operation.

綜上所述，本發明實施例提供一種形成高電子移動率電晶體的方法，於閘極下方由上而下形成包括N型摻雜三五族半導體或N型摻雜二六族半導體、未摻雜三五族半導體或未摻雜二六族半導體、及P型摻雜三五族半導體或P型摻雜二六族半導體的能帶調整層(NIP結構能帶調整層)，可提高高電子移動率電晶體的臨界電壓，消除超高壓雜訊干擾，並可降低閘極漏電電流，以增加閘極操作範圍。 In summary, the embodiment of the present invention provides a method for forming a high electron mobility transistor, and an N-type doped Group III semiconductor or an N-type doped Group II semiconductor, Band adjustment layers (NIP structure band adjustment layers) for doped Group III semiconductors or undoped Group II semiconductors and P-type doped Group III semiconductors or P-type doped Group II semiconductors The critical voltage of the electron mobility transistor can eliminate the extra-high voltage noise interference and reduce the gate leakage current to increase the gate operating range.

應注意的是，雖然以上描述了本發明一些實施例的優點與功效，但並非各個實施例都需要達到所有的優點與功效。 It should be noted that, although the advantages and effects of some embodiments of the present invention have been described above, not all embodiments need to achieve all the advantages and effects.

上述內容概述許多實施例的特徵，因此任何所屬技術領域中具有通常知識者，可更加理解本發明實施例之各面向。任何所屬技術領域中具有通常知識者，可能無困難地以本發明實施例為基礎，設計或修改其他製程及結構，以達到與本發明實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解，在不脫離本發明實施例之精神和範圍內做不同改變、代替及修改，如此等效的創造並沒有超出本發明實施例的精神及範圍。 The above outlines the features of many embodiments, so anyone with ordinary knowledge in the technical field can better understand the various embodiments of the present invention. Facing. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the embodiments of the present invention without difficulty to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such equivalent creations do not exceed the spirit and scope of the embodiments of the present invention.

Claims

一種高電子移動率電晶體(high electron mobility transistor,HEMT)，包括：一緩衝層，位於一基板上；一阻障層，位於該緩衝層上，其中一通道區位於該緩衝層中，鄰近該緩衝層與該阻障層之一介面；一能帶調整層(band adjustment layer)，位於該阻障層上，由上而下包括一第一能帶調整層、一第二能帶調整層、及一第三能帶調整層；一第一鈍化層，位於該阻障層上，鄰接該能帶調整層，且該能帶調整層完全嵌入該第一鈍化層中；一閘極電極，位於該能帶調整層上，並與該能帶調整層電性連接；一源極/汲極電極，分別位於該閘極電極之兩相對側，穿過該第一鈍化層，設於該阻障層上；及一第二鈍化層，位於該能帶調整層之頂表面上；其中該第一能帶調整層包括N型摻雜三五族半導體或N型摻雜二六族半導體，該第二能帶調整層包括未摻雜三五族半導體或未摻雜二六族半導體，該第三能帶調整層包括P型摻雜三五族半導體或P型摻雜二六族半導體。A high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a barrier layer on the buffer layer; and a channel region in the buffer layer adjacent to the buffer layer. An interface between the buffer layer and the barrier layer; a band adjustment layer is located on the barrier layer and includes a first band adjustment layer, a second band adjustment layer, And a third band adjustment layer; a first passivation layer located on the barrier layer, adjacent to the band adjustment layer, and the band adjustment layer is completely embedded in the first passivation layer; a gate electrode is located at The energy band adjustment layer is electrically connected to the energy band adjustment layer; a source / drain electrode is located on two opposite sides of the gate electrode, passes through the first passivation layer, and is disposed on the barrier Layer; and a second passivation layer on the top surface of the band adjustment layer; wherein the first band adjustment layer includes an N-type doped Group III semiconductor or an N-type doped Group II semiconductor. The two-band adjustment layer includes an undoped III-V semiconductor or an undoped II-VI semiconductor Conductor, the third band adjustment layer includes a P-type doped III-V semiconductor or a P-type doped semiconductor twenty-six.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第一能帶調整層與該第二能帶調整層直接接觸，且該第二能帶調整層與該第三能帶調整層直接接觸。The high electron mobility transistor according to item 1 of the scope of the patent application, wherein the first energy band adjustment layer is in direct contact with the second energy band adjustment layer, and the second energy band adjustment layer is in contact with the third energy band. The adjustment layer is in direct contact.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第二能帶調整層包括未摻雜之GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、InGaAs、CdS、CdTe、SiGe、SiC、或ZnS。The high electron mobility transistor according to item 1 of the patent application scope, wherein the second band adjustment layer includes undoped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe, SiGe, SiC, or ZnS.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第二能帶調整層厚度介於1nm至1000nm。The high electron mobility transistor according to item 1 of the patent application range, wherein the thickness of the second band adjustment layer is between 1 nm and 1000 nm.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第二能帶調整層之厚度為該能帶調整層之厚度的1%至99%。The high electron mobility transistor described in item 1 of the scope of patent application, wherein the thickness of the second band adjustment layer is 1% to 99% of the thickness of the band adjustment layer.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第一能帶調整層包括N型摻雜之GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、InGaAs、CdS、CdTe、SiC、SiGe、或ZnS。The high electron mobility transistor according to item 1 of the patent application scope, wherein the first band adjustment layer includes N-doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe , SiC, SiGe, or ZnS.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第一能帶調整層以Si、C、Ge、Sn、Pb、Cl、Br、或I進行摻雜。The high electron mobility transistor according to item 1 of the patent application scope, wherein the first band adjustment layer is doped with Si, C, Ge, Sn, Pb, Cl, Br, or I.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第一能帶調整層之N型摻雜濃度介於1E15/cm³至1E25/cm³之間。The high electron mobility transistor according to item 1 of the patent application scope, wherein the N-type doping concentration of the first band adjustment layer is between 1E15 / cm ³ and 1E25 / cm ³ .

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第一能帶調整層之厚度為該能帶調整層之厚度的1%至99%。The high electron mobility transistor described in item 1 of the scope of the patent application, wherein the thickness of the first band adjustment layer is 1% to 99% of the thickness of the band adjustment layer.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第三能帶調整層包括P型摻雜之GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、InGaAs、CdS、CdTe、SiC、SiGe、或ZnS。The high electron mobility transistor according to item 1 of the patent application scope, wherein the third band adjustment layer includes P-type doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS, CdTe , SiC, SiGe, or ZnS.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第三能帶調整層以Mg、Zn、Ca、Be、Sr、Ba、Ra、C、Ag、Au、Li、或Na進行摻雜。The high electron mobility transistor according to item 1 of the patent application scope, wherein the third band adjustment layer is made of Mg, Zn, Ca, Be, Sr, Ba, Ra, C, Ag, Au, Li, or Na Doping.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第三能帶調整層之P型摻雜濃度介於1E15/cm³至1E25/cm³之間。The high electron mobility transistor according to item 1 of the scope of the patent application, wherein the P-type doping concentration of the third band adjustment layer is between 1E15 / cm ³ and 1E25 / cm ³ .

如申請專利範圍第1項所述之高電子移動率電晶體，其中該第三能帶調整層之厚度為該能帶調整層之厚度的1%至99%。The high electron mobility transistor described in item 1 of the scope of patent application, wherein the thickness of the third band adjustment layer is 1% to 99% of the thickness of the band adjustment layer.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該阻障層包括Al_xGa_1-xN，其中0<x<1。The high electron mobility transistor described in item 1 of the patent application scope, wherein the barrier layer includes Al _x Ga _1-x N, where 0 <x <1.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該緩衝層包括GaN。The high electron mobility transistor according to item 1 of the patent application scope, wherein the buffer layer includes GaN.

如申請專利範圍第1項所述之高電子移動率電晶體，其中該鈍化層包括SiO₂、SiN₃、SiON、Al₂O₃、AlN、聚亞醯胺(polyimide，PI)、苯環丁烯(benzocyclobutene，BCB)、或聚苯并噁唑(polybenzoxazole，PBO)。The high electron mobility transistor as described in item 1 of the scope of the patent application, wherein the passivation layer includes SiO ₂ , SiN ₃ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), phencyclidine Benzocyclobutene (BCB) or polybenzoxazole (PBO).

一種高電子移動率電晶體(high electron mobility transistor,HEMT)的形成方法，包括：形成一緩衝層於一基板上；形成一阻障層於該緩衝層上，其中一通道區位於該緩衝層中，鄰近該緩衝層與該阻障層之一介面；形成一能帶調整層(band adjustment layer)於該阻障層上，由上而下包括一第一能帶調整層、一第二能帶調整層、及一第三能帶調整層；形成一第一鈍化層於該阻障層上，鄰接該能帶調整層，且該能帶調整層完全嵌入該第一鈍化層中；形成一閘極電極於該能帶調整層上，並與該能帶調整層電性連接；形成一源極/汲極電極分別位於該閘極電極之兩相對側，穿過該第一鈍化層，設於該阻障層上；及形成一第二鈍化層於該能帶調整層之頂表面上；其中該第一能帶調整層包括N型摻雜三五族半導體或N型摻雜二六族半導體，該第二能帶調整層包括未摻雜三五族半導體或未摻雜二六族半導體，該第三能帶調整層包括P型摻雜三五族半導體或P型摻雜二六族半導體。A method for forming a high electron mobility transistor (HEMT) includes: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer, wherein a channel region is located in the buffer layer; Adjacent to the interface between the buffer layer and the barrier layer; forming a band adjustment layer on the barrier layer, including a first band adjustment layer and a second band from top to bottom An adjustment layer and a third energy band adjustment layer; forming a first passivation layer on the barrier layer, adjacent to the energy band adjustment layer, and the energy band adjustment layer is completely embedded in the first passivation layer; forming a gate An electrode is on the band adjustment layer and is electrically connected to the band adjustment layer. A source / drain electrode is formed on two opposite sides of the gate electrode, passes through the first passivation layer, and is disposed on On the barrier layer; and forming a second passivation layer on the top surface of the band adjustment layer; wherein the first band adjustment layer includes an N-type doped Group III semiconductor or an N-type doped Group II semiconductor The second band adjustment layer includes an undoped III-V semiconductor or Twenty-six doped semiconductors, the energy band adjustment layer comprises a third P-type doped III-V semiconductor or a P-type doped semiconductor twenty-six.

如申請專利範圍第17項所述之高電子移動率電晶體的形成方法，其中該第二能帶調整層包括未摻雜之GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、InGaAs、CdS、CdTe、SiGe、SiC、或ZnS。The method for forming a high electron mobility transistor as described in item 17 of the patent application scope, wherein the second band adjustment layer includes undoped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, CdS , CdTe, SiGe, SiC, or ZnS.

如申請專利範圍第17項所述之高電子移動率電晶體的形成方法，其中該第二能帶調整層厚度介於1nm至1000nm。The method for forming a high electron mobility transistor as described in item 17 of the patent application, wherein the thickness of the second band adjustment layer is between 1 nm and 1000 nm.

如申請專利範圍第17項所述之高電子移動率電晶體的形成方法，其中該第二能帶調整層之厚度為該能帶調整層之厚度的1%至99%。The method for forming a high electron mobility transistor as described in item 17 of the scope of the patent application, wherein the thickness of the second band adjustment layer is 1% to 99% of the thickness of the band adjustment layer.