TWI658588B - High hole mobility transistor - Google Patents
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Abstract
本發明實施例提供一種高電洞移動率電晶體，包括：背阻障層，位於基板上；導通層，位於背阻障層上；通道區，位於導通層中，鄰近導通層與背阻障層之介面；摻雜層，位於導通層上；閘極電極，位於摻雜層上；源極/汲極電極，分別位於閘極電極之兩相對側；及能帶調整層，位於摻雜層上，並與閘極電極電性連接；其中能帶調整層為N型摻雜三五族半導體。 An embodiment of the present invention provides a high hole mobility transistor including a back barrier layer on a substrate, a conduction layer on the back barrier layer, and a channel region in the conduction layer, which is adjacent to the conduction layer and the back barrier. Interface of the layer; doped layer on the conduction layer; gate electrode on the doped layer; source / drain electrode on two opposite sides of the gate electrode; and band adjustment layer on the doped layer And is electrically connected to the gate electrode; wherein the band adjustment layer is an N-type doped III-V semiconductor.
Description
本發明實施例係有關於一種半導體技術，特別是有關於一種高電洞移動率電晶體。 Embodiments of the present invention relate to a semiconductor technology, and more particularly to a high hole mobility transistor.
GaN材料因具有寬能帶間隙及高速移動電子，廣泛應用於高功率半導體裝置當中，特別是射頻與功率上的應用。 GaN materials are widely used in high-power semiconductor devices due to their wide band gaps and high-speed mobile electronics, especially in RF and power applications.
傳統上，高電子移動率電晶體(High Electron Mobility Transistor，HEMT)利用三五族半導體堆疊，在其介面處形成異質接面(heterojunction)。由於異質接面處的能帶彎曲，導帶(conduction band)彎曲深處形成位能井(potential well)，並在位能井中形成二維電子氣(two-dimensional electron gas，2DEG)。由於在通道中移動的是電子，因此高電子移動率電晶體為N型元件。 Traditionally, High Electron Mobility Transistors (HEMT) use three or five semiconductor stacks to form heterojunctions at their interfaces. Due to the band bending at the heterojunction, a potential well is formed deep in the conduction band and a two-dimensional electron gas (2DEG) is formed in the potential band. Since electrons move in the channel, the high electron mobility transistor is an N-type element.
傳統上，亦可利用三五族半導體堆疊，在其介面處形成二維電洞氣(two-dimensional hold gas，2DHG)，並且利用凹蝕閘極(gate recess)的方式，改變能帶結構，減少二維電洞氣，形成增強型(enhancement mode，E-mode)高電洞移動率電晶體(High Hole Mobility Transistor，HHMT)。然而，由於凹蝕閘極深度與均勻性不易控制，容易導致電性參數的異常值。此外，閘極下凹的區域亦會造成通道高阻值。 Traditionally, a three-five semiconductor stack can also be used to form a two-dimensional hold gas (2DHG) at its interface, and the band structure can be changed by using a gate recess. Reducing the two-dimensional hole gas to form an enhancement mode (E-mode) high hole mobility transistor (HHMT). However, because the depth and uniformity of the etched gate are not easy to control, it is easy to cause abnormal values of electrical parameters. In addition, the recessed area of the gate will also cause high resistance of the channel.
雖然現有的高電洞移動率電晶體大致符合需求， 但並非各方面皆令人滿意，特別是增強型高電洞移動率電晶體之均勻性及通道阻值仍需進一步改善。 Although existing high hole mobility transistors are generally in demand, But not all aspects are satisfactory, especially the uniformity and channel resistance of enhanced high hole mobility transistors need to be further improved.
本發明實施例提供一種高電洞移動率電晶體，包括：背阻障層，位於基板上；導通層，位於背阻障層上；通道區，位於導通層中，鄰近導通層與背阻障層之介面；摻雜層，位於導通層上；閘極電極，位於摻雜層上；源極/汲極電極，分別位於閘極電極之兩相對側；及能帶調整層，位於摻雜層上，並與閘極電極電性連接；其中該能帶調整層為N型摻雜三五族半導體。 An embodiment of the present invention provides a high hole mobility transistor including a back barrier layer on a substrate, a conduction layer on the back barrier layer, and a channel region in the conduction layer, which is adjacent to the conduction layer and the back barrier. Interface of the layer; doped layer on the conduction layer; gate electrode on the doped layer; source / drain electrode on two opposite sides of the gate electrode; and band adjustment layer on the doped layer And is electrically connected to the gate electrode; wherein the band adjustment layer is an N-type doped III-V semiconductor.
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉數個實施例，並配合所附圖式，作詳細說明如下。 In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, several embodiments are described below in detail, in conjunction with the accompanying drawings, as follows.
100、200、300、400‧‧‧高電洞移動率電晶體 100, 200, 300, 400‧‧‧ high hole mobility transistor
102‧‧‧基板 102‧‧‧ substrate
104‧‧‧背阻障層 104‧‧‧back barrier
106‧‧‧導通層 106‧‧‧Conducting layer
108‧‧‧摻雜層 108‧‧‧ doped layer
110‧‧‧通道區 110‧‧‧passage zone
112‧‧‧能帶調整層 112‧‧‧ Band adjustment layer
114‧‧‧鈍化層 114‧‧‧ passivation layer
116‧‧‧閘極電極 116‧‧‧Gate electrode
118‧‧‧源極/汲極電極 118‧‧‧source / drain electrode
120C、122C‧‧‧導帶 120C, 122C‧‧‧Guide band
120V、122V‧‧‧價帶 120V, 122V‧‧‧valence band
120F‧‧‧費米能階 120F‧‧‧ Fermi Level
224、324、424‧‧‧介電層 224, 324, 424‧‧‧ dielectric layers
AA’‧‧‧線段 AA’‧‧‧ Segment
以下將配合所附圖式詳述本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本發明實施例的特徵。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention.
第1圖係根據一些實施例繪示出高電洞移動率電晶體之剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a high hole mobility transistor according to some embodiments.
第2圖係根據一些實施例繪示出高電洞移動率電晶體之能帶圖。 FIG. 2 is a band diagram of a high hole mobility transistor according to some embodiments.
第3圖係根據另一些實施例繪示出高電洞移動率電晶體之剖面示意圖。 FIG. 3 is a schematic cross-sectional view of a high hole mobility transistor according to other embodiments.
第4圖係根據又一些實施例繪示出高電洞移動率電晶體之 剖面示意圖。 FIG. 4 is a diagram illustrating a high hole mobility transistor according to still other embodiments. Schematic cross-section.
第5圖係根據再一些實施例繪示出高電洞移動率電晶體之剖面示意圖。 FIG. 5 is a schematic cross-sectional view of a high hole mobility transistor according to still other embodiments.
以下公開許多不同的實施方法或是例子來實行本發明實施例之不同特徵，以下描述具體的元件及其排列的實施例以闡述本發明實施例。當然這些實施例僅用以例示，且不該以此限定本發明實施例的範圍。例如，在說明書中提到第一特徵形成於第二特徵之上，其包括第一特徵與第二特徵是直接接觸的實施例，另外也包括於第一特徵與第二特徵之間另外有其他特徵的實施例，亦即，第一特徵與第二特徵並非直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本發明實施例，不代表所討論的不同實施例及/或結構之間有特定的關係。 Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes specific embodiments of the elements and their arrangements to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present invention should not be limited by this. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment in which the first feature and the second feature are in direct contact, and also includes the other between the first feature and the second feature. An embodiment of a feature, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.
此外，其中可能用到與空間相關用詞，例如「在...下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間相關用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。 In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. These space-related terms Words are used to facilitate the description of the relationship between one or more elements or features and other elements or features in the illustration. These spatially related terms include different positions of the device in use or operation, as well as in the drawings. The described orientation. When the device is turned to a different orientation (rotated 90 degrees or other orientation), the spatially related adjectives used in it will also be interpreted in terms of the orientation after turning.
在此，「約」、「大約」、「大抵」之用語通常表示在一給定值或範圍的20%之內，較佳是10%之內，且更佳是5%之內，或3%之內，或2%之內，或1%之內，或0.5%之內。應注意 的是，說明書中所提供的數量為大約的數量，亦即在沒有特定說明「約」、「大約」、「大抵」的情況下，仍可隱含「約」、「大約」、「大抵」之含義。 Here, the terms "about", "approximately", and "mostly" generally indicate within a given value or range within 20%, preferably within 10%, and more preferably within 5%, or 3 Within%, or within 2%, or within 1%, or within 0.5%. Should pay attention It is said that the quantity provided in the description is an approximate quantity, that is, without approximation "about", "approximately", and "probably", "approximately", "approximately", and "probably" may still be implied Meaning.
本發明實施例提供一種高電洞移動率電晶體(high hole mobility transistor，HHMT)，在通道區上形成能帶調整層(band adjustment layer)，以降低能帶，使二維電洞氣(two-dimensional hold gas，2DHG)消失，形成增強型(enhancement mode，E-mode)高電洞移動率電晶體，此元件相較於傳統製程具較佳的均勻度，且可保持通道為低阻值。 An embodiment of the present invention provides a high hole mobility transistor (HHMT). A band adjustment layer is formed on a channel region to reduce the energy band and enable two-dimensional hole gas (two- Dimensional hold gas (2DHG) disappears, forming an enhancement mode (E-mode) high hole mobility transistor. This element has better uniformity than traditional processes, and can maintain the channel with a low resistance value.
第1圖繪示出本發明一些實施例之高電洞移動率電晶體100之剖面圖。如第1圖所繪示，提供一基板102。在一些實施例中，基板102可包括Si、SiC、或Al2O3(藍寶石(sapphire))，可為單層基板、多層基板、梯度基板、其他適當之基板或上述之組合。在一些實施例中，基板102可為單晶基板。在一些實施例中，基板102亦可包括絕緣層覆半導體(semiconductor on insulator，SOI)基板，上述絕緣層覆半導體基板可包括底板、設置於底板上之埋藏氧化層、或設置於埋藏氧化層上之半導體層。在一些實施例中，基板102可包括單層或多層緩衝層(buffer layer)，避免矽基板與形成於其上的元件晶格失配(lattice mismatch)。在一些實施例中，基板102亦可包括III-V族半導體，例如GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、InGaAs、或上述之組合。在一些實施例中，基板為可耐受高壓的基板材料。 FIG. 1 is a cross-sectional view of a high hole mobility transistor 100 according to some embodiments of the present invention. As shown in FIG. 1, a substrate 102 is provided. In some embodiments, the substrate 102 may include Si, SiC, or Al 2 O 3 (sapphire), and may be a single-layer substrate, a multilayer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In some embodiments, the substrate 102 may be a single crystal substrate. In some embodiments, the substrate 102 may also include a semiconductor on insulator (SOI) substrate. The insulating semiconductor substrate may include a base plate, a buried oxide layer provided on the base plate, or a buried oxide layer. Of the semiconductor layer. In some embodiments, the substrate 102 may include a single layer or multiple buffer layers to avoid a lattice mismatch between the silicon substrate and a device formed thereon. In some embodiments, the substrate 102 may also include a III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the substrate is a substrate material that can withstand high voltages.
接著，在基板102上形成背阻障層(back barrier layer)104。在一些實施例中，背阻障層104包括III-V族半導體，例如AlxGa1-xN或AlxInyGa1-x-yN，其中0<x<1，且0<y<1。在一些實施例中，背阻障層104厚度介於0.1um至5um之間。在一些實施例中，可使用分子束磊晶法(molecular-beam epitaxy，MBE)、有機金屬氣相沉積法(metalorganic chemical vapor deposition，MOCVD)、化學氣相沉積法(chemical vapor deposition，CVD)、氫化物氣相磊晶法(hydride vapor phase epitaxy，HVPE)、其他適當之方法、或上述之組合在基板102上形成背阻障層104。 Next, a back barrier layer 104 is formed on the substrate 102. In some embodiments, the back barrier layer 104 includes a III-V semiconductor, such as Al x Ga 1-x N or Al x In y Ga 1-xy N, where 0 <x <1, and 0 <y <1 . In some embodiments, the thickness of the back barrier layer 104 is between 0.1um and 5um. In some embodiments, molecular-beam epitaxy (MBE), metal organic vapor deposition (MOCVD), chemical vapor deposition (CVD), A hydride vapor phase epitaxy (HVPE) method, other suitable methods, or a combination of the above is used to form the back barrier layer 104 on the substrate 102.
接著，在背阻障層104上形成導通層106。在一些實施例中，導通層106包括未摻雜的III-V族半導體，例如未摻雜的GaN。在一些實施例中，導通層106厚度介於0.1um至5um之間。在一些實施例中，可使用分子束磊晶法(molecular-beam epitaxy，MBE)、有機金屬氣相沉積法(metalorganic chemical vapor deposition，MOCVD)、化學氣相沉積法(chemical vapor deposition，CVD)、氫化物氣相磊晶法(hydride vapor phase epitaxy，HVPE)、其他適當之方法、或上述之組合在背阻障層104上形成導通層106。 Next, a conductive layer 106 is formed on the back barrier layer 104. In some embodiments, the conductive layer 106 includes an undoped III-V semiconductor, such as undoped GaN. In some embodiments, the thickness of the conductive layer 106 is between 0.1um and 5um. In some embodiments, molecular-beam epitaxy (MBE), metal organic vapor deposition (MOCVD), chemical vapor deposition (CVD), The hydride vapor phase epitaxy (HVPE), other appropriate methods, or a combination thereof may form a conductive layer 106 on the back barrier layer 104.
接著，在導通層106上形成摻雜層108。在一些實施例中，摻雜層108包括P型摻雜III-V族半導體，例如P型摻雜的GaN。在一些實施例中，摻雜層108可以Mg、Zn、Ca、Be、Sr、Ba、Ra、或C進行摻雜，其P型摻雜濃度介於1E15/cm3至1E20/cm3之間。摻雜層108厚度介於0.1um至5um之間。在一些實施例中，可使用分子束磊晶法(molecular-beam epitaxy，MBE)、有機金屬氣相沉積法(metalorganic chemical vapor deposition， MOCVD)、化學氣相沉積法(chemical vapor deposition，CVD)、氫化物氣相磊晶法(hydride vapor phase epitaxy，HVPE)、其他適當之方法、或上述之組合在導通層106上形成摻雜層108。在一些實施例中，可使用原位(in-situ)摻雜，或以離子佈植(ion implantation)的方式形成摻雜層108。 Next, a doped layer 108 is formed on the conductive layer 106. In some embodiments, the doped layer 108 includes a P-type doped III-V semiconductor, such as P-type doped GaN. In some embodiments, the doping layer 108 may be doped with Mg, Zn, Ca, Be, Sr, Ba, Ra, or C, and its P-type doping concentration is between 1E15 / cm 3 and 1E20 / cm 3 . . The thickness of the doped layer 108 is between 0.1um and 5um. In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), A doped layer 108 is formed on the conductive layer 106 by a hydride vapor phase epitaxy (HVPE), other suitable methods, or a combination thereof. In some embodiments, the doping layer 108 may be formed using in-situ doping, or by ion implantation.
由於摻雜層108/導通層106與背阻障層104材料能帶間隙(band gap)不同之故，在摻雜層108/導通層106與背阻障層104的介面處形成異質接面(heterojunction)，又因摻雜層108摻雜P型摻質，拉高了能帶，使異質接面處能帶彎曲，在價帶(valence band)彎曲處形成量子井(quantum well)，將電洞約束於量子井中，因此在導通層106與背阻障層104的介面處形成二維電洞氣(two-dimensional hole gas，2DHG)，進而形成導通電流。如第1圖所示，在導通層106與背阻障層104的介面處形成通道區110，通道區110即為二維電洞氣形成導通電流之處。通道區110厚度介於1nm至100nm之間。 Because the band gaps of the materials of the doped layer 108 / the conductive layer 106 and the back barrier layer 104 are different, a heterojunction is formed at the interface between the doped layer 108 / the conductive layer 106 and the back barrier layer 104 ( heterojunction), and the doped layer 108 is doped with a P-type dopant, which raises the energy band, bends the band at the heterojunction, and forms a quantum well at the bend of the valence band. The hole is confined in the quantum well, so a two-dimensional hole gas (2DHG) is formed at the interface between the conducting layer 106 and the back barrier layer 104, and then a conducting current is formed. As shown in FIG. 1, a channel region 110 is formed at an interface between the conductive layer 106 and the back barrier layer 104. The channel region 110 is a place where a two-dimensional hole gas forms a conduction current. The thickness of the channel region 110 is between 1 nm and 100 nm.
接著，在摻雜層108上形成能帶調整層(band adjustment layer)112。在一些實施例中，能帶調整層112為N型摻雜三五族半導體，包括N型摻雜之GaN、AlGaN、AlN、GaAs、AlGaAs、InP、InAlAs、或InGaAs，其N型摻雜濃度介於1E15/cm3至1E20/cm3之間。能帶調整層112厚度介於10nm至5000nm之間。在一些實施例中，可使用分子束磊晶法(molecular-beam epitaxy，MBE)、有機金屬氣相沉積法(metalorganic chemical vapor deposition，MOCVD)、化學氣相沉積法(chemical vapor deposition，CVD)、氫化物氣相磊晶法(hydride vapor phase epitaxy，HVPE)、其他適當之方法、或上述之組合以沉積N型摻雜三五族半導體，再經由例如微影製程與蝕刻製程，將其圖案化形成能帶調整層112。在一些實施例中，能帶調整層112位於後續所形成的閘極電極之下方。 Next, a band adjustment layer 112 is formed on the doped layer 108. In some embodiments, the band adjustment layer 112 is an N-type doped III-V semiconductor, including N-type doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs, and its N-type doping concentration. Between 1E15 / cm 3 and 1E20 / cm 3 . The band adjustment layer 112 has a thickness between 10 nm and 5000 nm. In some embodiments, molecular-beam epitaxy (MBE), metal organic vapor deposition (MOCVD), chemical vapor deposition (CVD), Hydrogen vapor phase epitaxy (HVPE), other appropriate methods, or a combination of the above to deposit N-type doped III-V semiconductors, and then pattern them by, for example, a lithography process and an etching process A band adjustment layer 112 is formed. In some embodiments, the band adjustment layer 112 is located below the gate electrode formed later.
能帶調整層112由於摻雜N型摻質，可降低能帶，使高電洞移動率電晶體100成為增強型(enhancement mode，E-mode)高電洞移動率電晶體(將於下詳述)。與空乏型(depletion mode，D-mode)高電洞移動率電晶體相較之下，增強型(E-mode)高電洞移動率電晶體較為安全，待機功耗(standby power dissipation)較低，亦可降低電路複雜性以及製作成本。 The band adjustment layer 112 is doped with an N-type dopant, which can reduce the energy band and make the high hole mobility transistor 100 an enhancement mode (E-mode) high hole mobility transistor (to be described in detail below). As described). Compared with the depletion mode (D-mode) high hole mobility transistor, the enhanced (E-mode) high hole mobility transistor is safer and has lower standby power dissipation , Can also reduce circuit complexity and production costs.
接著，在摻雜層108及能帶調整層112上形成鈍化層(passivation layer)114。鈍化層114可包括SiO2、SiN3、SiON、Al2O3、AlN、聚亞醯胺(polyimide，PI)、苯環丁烯(benzocyclobutene，BCB)、聚苯并噁唑(polybenzoxazole，PBO)、其他絕緣材料、或上述之組合。鈍化層114厚度介於0.1um至1um之間。在一些實施例中，可使用有機金屬氣相沉積法(metalorganic chemical vapor deposition，MOCVD)、化學氣相沉積法(chemical vapor deposition，CVD)、旋轉塗佈法(spin-coating)、其他適當之方法、或上述之組合形成鈍化層114。在一些實施例中，鈍化層114可順應性地(conformally)形成於摻雜層108及能帶調整層112之上。在一些實施例中，鈍化層114經化學機械研磨(chemical mechanical polishing，CMP)而具有平坦的上表面。鈍化層114可保護下方的膜層，並提供物理隔 離及結構支撐。 Next, a passivation layer 114 is formed on the doped layer 108 and the band adjustment layer 112. The passivation layer 114 may include SiO 2 , SiN 3 , SiON, Al 2 O 3 , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) , Other insulating materials, or a combination of the above. The thickness of the passivation layer 114 is between 0.1um and 1um. In some embodiments, organic metal vapor deposition (MOCVD), chemical vapor deposition (CVD), spin-coating, and other suitable methods may be used. Or a combination thereof to form the passivation layer 114. In some embodiments, the passivation layer 114 may be conformally formed on the doped layer 108 and the energy band adjustment layer 112. In some embodiments, the passivation layer 114 has a flat upper surface by chemical mechanical polishing (CMP). The passivation layer 114 can protect the underlying film layer and provide physical isolation and structural support.
接著，在能帶調整層112上形成閘極電極116，並在閘極電極116兩側的形成源極/汲極電極118。在一些實施例中，閘極電極116可包括金屬材料、多晶矽、金屬矽化物、其他適當之導電材料、或上述之組合。在一些實施例中，源極/汲極電極118可包括Ti、Al、Au、Pd、其他適當之金屬材料、其合金、或上述之組合。在一些實施例中，可先以微影與蝕刻製程在鈍化層114中形成開口，使一部分能帶調整層112及摻雜層108露出。再以電鍍法、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、物理氣相沉積製程(physical vapor deposition，PVD)、化學氣相沉積法(chemical vapor deposition，CVD)、原子層沉積製程(atomic layer deposition，ALD)、其他適當之方法、或上述之組合在鈍化層114開口處填入電極材料，以形成閘極電極116與源極/汲極電極118。 Next, a gate electrode 116 is formed on the band adjustment layer 112, and a source / drain electrode 118 is formed on both sides of the gate electrode 116. In some embodiments, the gate electrode 116 may include a metal material, polycrystalline silicon, metal silicide, other suitable conductive materials, or a combination thereof. In some embodiments, the source / drain electrode 118 may include Ti, Al, Au, Pd, other suitable metal materials, alloys thereof, or a combination thereof. In some embodiments, an opening may be formed in the passivation layer 114 by a lithography and etching process, so that a part of the band adjustment layer 112 and the doped layer 108 are exposed. Electroplating, sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition An atomic layer deposition (ALD), other suitable method, or a combination thereof is used to fill the electrode material at the opening of the passivation layer 114 to form the gate electrode 116 and the source / drain electrode 118.
第1圖中的實施例僅為一範例，本發明實施例並不以此為限。例如，可在摻雜層108上另外形成其他摻雜層(圖未示)，其摻質與摻雜濃度可能與摻雜層108相同或不同。如此一來，藉由調整不同摻雜層的組成與濃度，可具有更高的自由度，以調整高電洞移動率電晶體的能帶結構。 The embodiment in FIG. 1 is only an example, and the embodiment of the present invention is not limited thereto. For example, another doping layer (not shown) may be formed on the doping layer 108, and the dopant and doping concentration may be the same as or different from the doping layer 108. In this way, by adjusting the composition and concentration of different doped layers, it can have a higher degree of freedom to adjust the band structure of the high hole mobility transistor.
第2圖為第1圖中沿線段AA’之剖面方向的能帶圖，比較例為未設置能帶調整層112的高電洞移動率電晶體之能帶結構，包括導帶120C及價帶120V。實施例為設置能帶調整層112的高電洞移動率電晶體之能帶結構，包括導帶122C及價帶122V。在第2圖的比較例中，P型摻雜層108使導通層106與背阻 障層104的介面處量子井能量高於費米能階(fermi level)120F，因此在導通層106中的費米能階以上形成二維電洞氣，進而形成導通電流。 Fig. 2 is an energy band diagram along the section direction of line AA 'in Fig. 1. A comparative example is an energy band structure of a high hole mobility transistor without an energy band adjustment layer 112, including a conduction band 120C and a valence band. 120V. The embodiment is an energy band structure of a high hole mobility transistor provided with an energy band adjustment layer 112, including a conduction band 122C and a valence band 122V. In the comparative example of FIG. 2, the P-type doped layer 108 connects the conductive layer 106 and the back resistor. The quantum well energy at the interface of the barrier layer 104 is higher than the Fermi level 120F. Therefore, a two-dimensional hole gas is formed above the Fermi level in the conduction layer 106, thereby forming a conduction current.
在第2圖的實施例中，能帶調整層112為N型摻雜三五族半導體，N型摻雜造成能帶降低，使導通層106與背阻障層104的介面處價帶122V之能量低於費米能階(fermi level)120F，導致導通層106中無二維電洞氣產生，因而無導通電流。 In the embodiment shown in FIG. 2, the energy band adjustment layer 112 is an N-type doped Group III semiconductor. The N-type doping causes the energy band to decrease, and the valence band at the interface between the conduction layer 106 and the back barrier layer 104 is 122V The energy is lower than the Fermi level 120F, which results in that no two-dimensional hole gas is generated in the conducting layer 106, and therefore there is no conducting current.
上述實施例中，由於能帶調整層112降低能帶，未外加閘極電壓時，高電洞移動率電晶體100為截止狀態，因此高電洞移動率電晶體100為增強型(enhancement mode，E-mode)高電洞移動率電晶體。 In the above embodiment, since the energy band adjustment layer 112 lowers the energy band, the high hole mobility transistor 100 is in an off state when the gate voltage is not applied. Therefore, the high hole mobility transistor 100 is in an enhancement mode. E-mode) high hole mobility transistor.
如上所述，本發明在高電洞移動率電晶體的通道區上設置能帶調整層，利用N型摻雜改變能帶，形成增強型高電洞移動率電晶體。由於並非使用傳統的凹蝕閘極的方式形成，可避免因凹蝕閘極而導致均勻性不佳的問題，同時維持低通道阻值。 As described above, the present invention provides an energy band adjustment layer on a channel region of a high hole mobility transistor, and uses N-type doping to change the energy band to form an enhanced high hole mobility transistor. Since it is not formed by using the traditional etched gate, the problem of poor uniformity caused by the etched gate can be avoided, while maintaining a low channel resistance value.
第3圖繪示出本發明另一些實施例之高電洞移動率電晶體200之剖面圖。其中與前述實施例相同或相似的製程或元件將沿用相同的元件符號，其詳細內容將不再贅述。與前述實施例的差別在於，在能帶調整層112與閘極電極116之間進一步設置了介電層224，形成金屬-絕緣體-半導體(metal-insulator-semiconductor，MIS)結構。介電層224包括SiO2、SiN3、SiON、Al2O3、MgO、Sc2O3、HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、LaO、ZrO、TiO2、ZnO2、ZrO2、AlSiN3、 SiC、或Ta2O5、類似的材料、或上述之組合。在一些實施例中，可使用化學氣相沉積法(chemical vapor deposition，CVD)、電漿強化化學氣相沉積(plasma enhanced CVD，PECVD)、高密度電漿化學氣相沉積(high density plasma CVD，HDPCVD)、原子層沉積製程(atomic layer deposition，ALD)、旋轉塗佈法(spin-coating)、及/或其他合適技術沉積介電材料，再經由例如微影製程與蝕刻製程，將其圖案化形成介電層224。介電層224可降低閘極漏電電流，提升閘極可承受的電壓範圍，進一步使通道阻值降低。介電層224厚度介於1nm至100nm之間。若介電層224厚度太厚，則可能影響元件速度，若介電層224厚度太薄，則可能增加閘極漏電電流。 FIG. 3 is a cross-sectional view of a high hole mobility transistor 200 according to another embodiment of the present invention. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the foregoing embodiment is that a dielectric layer 224 is further provided between the band adjustment layer 112 and the gate electrode 116 to form a metal-insulator-semiconductor (MIS) structure. The dielectric layer 224 includes SiO 2 , SiN 3 , SiON, Al 2 O 3 , MgO, Sc 2 O 3 , HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO 2 , ZnO 2 , ZrO 2 , AlSiN 3 , SiC, or Ta 2 O 5 , similar materials, or a combination thereof. In some embodiments, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), high density plasma chemical vapor deposition (CVD), (HDPCVD), atomic layer deposition (ALD), spin-coating, and / or other suitable techniques to deposit the dielectric material, and then pattern it by, for example, a lithography process and an etching process. A dielectric layer 224 is formed. The dielectric layer 224 can reduce the gate leakage current, increase the voltage range that the gate can withstand, and further reduce the channel resistance. The thickness of the dielectric layer 224 is between 1 nm and 100 nm. If the thickness of the dielectric layer 224 is too thick, it may affect the device speed. If the thickness of the dielectric layer 224 is too thin, the gate leakage current may be increased.
如第3圖所示之實施例中，在增強型高電洞移動率電晶體的能帶調整層與閘極電極間設置介電層，可降低閘極漏電電流，並提升閘極可承受的電壓範圍。 In the embodiment shown in FIG. 3, a dielectric layer is provided between the band adjustment layer of the enhanced high hole mobility transistor and the gate electrode, which can reduce the gate leakage current, and improve the gate withstand voltage. voltage range.
第4圖繪示出本發明另一些實施例之高電洞移動率電晶體300之剖面圖。其中與前述實施例相同或相似的製程或元件將沿用相同的元件符號，其詳細內容將不再贅述。與前述實施例的差別在於，介電層324延伸至摻雜層108的上表面。 FIG. 4 is a cross-sectional view of a high hole mobility transistor 300 according to another embodiment of the present invention. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that the dielectric layer 324 extends to the upper surface of the doped layer 108.
相較於增強型高電洞移動率電晶體200的製程，增強型高電洞移動率電晶體300的製程在形成能帶調整層112後，順應性地(conformally)形成介電層324於摻雜層108及能帶調整層112上，接著再形成鈍化層114。 Compared with the process of the enhanced high hole mobility transistor 200, the process of the enhanced high hole mobility transistor 300 is formed conformally with the dielectric layer 324 after doping the band adjustment layer 112. A passivation layer 114 is formed on the impurity layer 108 and the band adjustment layer 112.
介電層324可降低閘極漏電電流，提升閘極可承受的電壓範圍，進一步使通道阻值降低。同時，由於未對介電層 324進行蝕刻製程，增強型高電洞移動率電晶體300製程可節省生產時間及成本。 The dielectric layer 324 can reduce the gate leakage current, increase the voltage range that the gate can withstand, and further reduce the channel resistance. At the same time, since the dielectric layer is not 324 performs an etching process, and the enhanced high hole mobility transistor 300 process can save production time and costs.
第5圖繪示出本發明另一些實施例之高電洞移動率電晶體400之剖面圖。其中與前述實施例相同或相似的製程或元件將沿用相同的元件符號，其詳細內容將不再贅述。與前述實施例的差別在於，介電層424延伸至鈍化層114的上表面。 FIG. 5 is a cross-sectional view of a high hole mobility transistor 400 according to another embodiment of the present invention. The processes or components that are the same as or similar to those of the foregoing embodiments will use the same component symbols, and the detailed content will not be described again. The difference from the previous embodiment is that the dielectric layer 424 extends to the upper surface of the passivation layer 114.
相較於增強型高電洞移動率電晶體200的製程，增強型高電洞移動率電晶體400製程在形成鈍化層114後，經由例如微影製程與蝕刻製程，在鈍化層114中形成開口，使一部分的能帶調整層112露出。接著，順應性地(conformally)形成介電層424於能帶調整層112及鈍化層114上，再形成閘極電極116。 Compared with the process of the enhanced high hole mobility transistor 200, the enhanced high hole mobility transistor 400 process, after forming the passivation layer 114, forms an opening in the passivation layer 114 through, for example, a lithography process and an etching process. A part of the band adjustment layer 112 is exposed. Next, a dielectric layer 424 is conformally formed on the band adjustment layer 112 and the passivation layer 114, and then a gate electrode 116 is formed.
介電層424可降低閘極漏電電流，提升閘極可承受的電壓範圍，進一步使通道阻值降低。增強型高電洞移動率電晶體400的製程提供另一種形成介電層424的方式，可視製程需求選擇。 The dielectric layer 424 can reduce the gate leakage current, increase the voltage range that the gate can withstand, and further reduce the channel resistance. The process of the enhanced high hole mobility transistor 400 provides another way to form the dielectric layer 424, which can be selected according to process requirements.
綜上所述，本發明實施例提供一種高電洞移動率電晶體(High Hole Mobility Transistor，HHMT)結構，於通道區上方形成能帶調整層，藉由能帶結構改變，使局部二維電洞氣(two-dimensional hole gas，2DHG)消失，形成增強型高電洞移動率電晶體，同時保持良好均勻性及通道低阻值。此外，可在能帶調整層與閘極電極間設置介電層，降低閘極漏電電流，提升閘極可承受的電壓範圍，進一步使通道阻值降低。 In summary, an embodiment of the present invention provides a high hole mobility transistor (HHMT) structure. An energy band adjustment layer is formed above the channel region, and the local two-dimensional electricity is changed by the energy band structure change. Two-dimensional hole gas (2DHG) disappears, forming an enhanced high hole mobility transistor while maintaining good uniformity and low resistance of the channel. In addition, a dielectric layer can be provided between the band adjustment layer and the gate electrode to reduce the gate leakage current, increase the voltage range that the gate can withstand, and further reduce the channel resistance.
上述內容概述許多實施例的特徵，因此任何所屬技術領域中具有通常知識者，可更加理解本發明實施例之各面 向。任何所屬技術領域中具有通常知識者，可能無困難地以本發明實施例為基礎，設計或修改其他製程及結構，以達到與本發明實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解，在不脫離本發明實施例之精神和範圍內做不同改變、代替及修改，如此等效的創造並沒有超出本發明實施例的精神及範圍。 The foregoing outlines the features of many embodiments, so anyone with ordinary knowledge in the technical field can better understand the aspects of the embodiments of the present invention to. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the embodiments of the present invention without difficulty to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions and modifications can be made without departing from the spirit and scope of the embodiments of the present invention. Such equivalent creations do not exceed the spirit and scope of the embodiments of the present invention.
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| CN101790790A (en) * | 2007-08-30 | 2010-07-28 | 英特尔公司 | High hole mobility p-channel ge transistor structure on the Si substrate |
| US20150155376A1 (en) * | 2013-11-29 | 2015-06-04 | Gachon University Of Industry-Academic Cooperation Foundation | Silicon-compatible germanium-based transistor with high-hole-mobility |
| US20150221727A1 (en) * | 2013-03-15 | 2015-08-06 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Inverted P-Channel III-Nitride Field Effect Transistor with Hole Carriers in the Channel |
| US20150325680A1 (en) * | 2012-10-31 | 2015-11-12 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101790790A (en) * | 2007-08-30 | 2010-07-28 | 英特尔公司 | High hole mobility p-channel ge transistor structure on the Si substrate |
| US20150325680A1 (en) * | 2012-10-31 | 2015-11-12 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US20150221727A1 (en) * | 2013-03-15 | 2015-08-06 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Inverted P-Channel III-Nitride Field Effect Transistor with Hole Carriers in the Channel |
| US20150155376A1 (en) * | 2013-11-29 | 2015-06-04 | Gachon University Of Industry-Academic Cooperation Foundation | Silicon-compatible germanium-based transistor with high-hole-mobility |
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