TWI673711B

TWI673711B - Memory device

Info

Publication number: TWI673711B
Application number: TW107135120A
Authority: TW
Inventors: 中岡裕司
Original assignee: 華邦電子股份有限公司
Priority date: 2018-10-04
Filing date: 2018-10-04
Publication date: 2019-10-01
Also published as: TW202015051A

Abstract

一種記憶體裝置，包括資料接收器、閂鎖驅動器以及電壓偏移器。資料接收器操作在第一電壓，用以接收致能信號、參考信號以及輸入資料信號，並依據第一電壓輸出內部資料信號。閂鎖驅動器接收寫入選擇信號以及內部資料信號，並依據第一電壓閂鎖內部資料信號，以及依據第二電壓輸出至少一閂鎖資料信號。電壓偏移器依據第二電壓接收至少一閂鎖資料信號，並依據至少一閂鎖資料信號以產生至少一輸出資料信號，其中電壓偏移器依據第一電壓設定至少一輸出資料信號的電壓值，其中第一電壓的電壓值大於第二電壓的電壓值。A memory device includes a data receiver, a latch driver, and a voltage shifter. The data receiver is operated at a first voltage for receiving an enable signal, a reference signal, and an input data signal, and outputs an internal data signal according to the first voltage. The latch driver receives the write selection signal and the internal data signal, latches the internal data signal according to the first voltage, and outputs at least one latch data signal according to the second voltage. The voltage shifter receives at least one latched data signal according to the second voltage, and generates at least one output data signal according to the at least one latched data signal. The voltage shifter sets the voltage value of the at least one output data signal according to the first voltage. , Wherein the voltage value of the first voltage is greater than the voltage value of the second voltage.

Description

記憶體裝置Memory device

本發明是有關於一種記憶體裝置，且特別是有關於一種可提昇操作速度並且降低功率消耗的記憶體裝置。The present invention relates to a memory device, and more particularly, to a memory device capable of improving operation speed and reducing power consumption.

在習知的低功率雙倍資料速率4X（low power double data rate 4X，LPDDR4X）的標準的半導體記憶體裝置中，出於降低功率消耗的目的，會設計使記憶體裝置中資料接收器具有較低的操作電壓（例如是0.6伏特），而記憶體裝置的周遭電路則會設計具有較高的操作電壓（例如是1.1伏特）。In the conventional low power double data rate 4X (LPDDR4X) standard semiconductor memory device, for the purpose of reducing power consumption, a data receiver in the memory device is designed to have a relatively low Low operating voltage (for example, 0.6 volts), and the peripheral circuit of the memory device is designed to have higher operating voltage (for example, 1.1 volts).

然而，當以較低的操作電壓來驅動記憶體裝置的資料接收器時，會因電壓太低而導致記憶體裝置速度下降的問題，此外，由於記憶體裝置的其他周遭電路均是以較高的操作電壓來進行驅動，會使得記憶體裝置的降低功率消耗效果不顯著。因此，如何對記憶體裝置的資料接收器及周遭電路進行設計則成為一個重要的課題。However, when the data receiver of the memory device is driven with a lower operating voltage, the speed of the memory device decreases due to the low voltage. In addition, other peripheral circuits of the memory device are higher The driving voltage of the memory device for driving will make the power consumption reduction effect of the memory device insignificant. Therefore, how to design the data receiver and surrounding circuits of a memory device has become an important issue.

本發明提供一種記憶體裝置，可藉由不同電壓值的操作電壓來分別驅動資料接收器及其他周遭電路，藉此提升記憶體裝置的操作速度，並達到降低記憶體裝置功率消耗之目的。The invention provides a memory device, which can drive a data receiver and other peripheral circuits by operating voltages with different voltage values, thereby improving the operating speed of the memory device and reducing the power consumption of the memory device.

本發明的記憶體裝置，包括資料接收器、閂鎖驅動器以及電壓偏移器。資料接收器操作在第一電壓，用以接收致能信號、參考信號以及輸入資料信號，並依據第一電壓輸出內部資料信號。閂鎖驅動器耦接至資料接收器，用以接收寫入選擇信號以及內部資料信號，並依據第一電壓閂鎖內部資料信號，以及依據第二電壓輸出至少一閂鎖資料信號。電壓偏移器耦接至閂鎖驅動器，依據第二電壓接收至少一閂鎖資料信號，並依據至少一閂鎖資料信號以產生至少一輸出資料信號，其中電壓偏移器依據第一電壓設定至少一輸出資料信號的電壓值，其中，第一電壓的電壓值大於第二電壓的電壓值。The memory device of the present invention includes a data receiver, a latch driver, and a voltage shifter. The data receiver is operated at a first voltage for receiving an enable signal, a reference signal, and an input data signal, and outputs an internal data signal according to the first voltage. The latch driver is coupled to the data receiver for receiving a write selection signal and an internal data signal, latching the internal data signal according to a first voltage, and outputting at least one latch data signal according to a second voltage. The voltage shifter is coupled to the latch driver, receives at least one latch data signal according to the second voltage, and generates at least one output data signal according to the at least one latch data signal. The voltage shifter sets at least one according to the first voltage. A voltage value of the output data signal, wherein the voltage value of the first voltage is greater than the voltage value of the second voltage.

基於上述，本發明藉由電壓值較大的第一電壓來驅動資料接收器，並透過將閂鎖驅動器及電壓偏移器分級驅動的方式，分別以第一電壓驅動閂鎖驅動器來閂鎖內部資料信號，再以電壓值較小的第二電壓驅動閂鎖驅動器以輸出至少一閂鎖資料信號，接著分別以第二電壓來驅動電壓偏移器來接收至少一閂鎖資料信號，再透過第一電壓來驅動電壓偏移器以設定至少一輸出資料信號的電壓值，藉此提升記憶體裝置的操作速度，並達到降低記憶體裝置功率消耗之目的。Based on the above, the present invention drives the data receiver with a first voltage having a larger voltage value, and drives the latch driver with the first voltage to latch the interior by stepwise driving the latch driver and the voltage shifter. Data signal, and then drive the latch driver with a second voltage having a lower voltage value to output at least one latch data signal, and then drive the voltage shifter with a second voltage to receive at least one latch data signal, and then pass the first A voltage is used to drive the voltage shifter to set the voltage value of at least one output data signal, thereby increasing the operating speed of the memory device and achieving the purpose of reducing the power consumption of the memory device.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

請參照圖1，圖1繪示本發明一實施例的記憶體裝置的電路方塊示意圖。記憶體裝置100包括資料接收器110、閂鎖驅動器120以及電壓偏移（level shift）器130。資料接收器110操作於第一電壓V1，會接收致能信號En、參考信號Ref以及輸入資料信號Din，並且資料接收器110會依據第一電壓V1來輸出內部資料信號IDS至閂鎖驅動器120。閂鎖驅動器120耦接至資料接收器110，操作於第一電壓V1及第二電壓V2，並且會接收重置信號Reset、寫入選擇信號WDQS以及來自資料接收器110的內部資料信號IDS，其中，閂鎖驅動器120可依據重置信號Reset進行重置操作，並且可依據寫入選擇信號WDQS來進行寫入操作。Please refer to FIG. 1. FIG. 1 is a schematic circuit block diagram of a memory device according to an embodiment of the present invention. The memory device 100 includes a data receiver 110, a latch driver 120, and a level shifter 130. The data receiver 110 operates at the first voltage V1, and receives the enable signal En, the reference signal Ref, and the input data signal Din, and the data receiver 110 outputs the internal data signal IDS to the latch driver 120 according to the first voltage V1. The latch driver 120 is coupled to the data receiver 110, operates at the first voltage V1 and the second voltage V2, and receives a reset signal Reset, a write selection signal WDQS, and an internal data signal IDS from the data receiver 110, where The latch driver 120 may perform a reset operation according to a reset signal Reset, and may perform a write operation according to a write selection signal WDQS.

接著，閂鎖驅動器120會依據第一電壓V1來對內部資料信號IDS進行閂鎖，並且在閂鎖內部資料信號IDS後，依據第二電壓V2來輸出至少一閂鎖資料信號（例如是閂鎖資料信號LDS）至電壓偏移器130，需要注意的是，為簡化說明，本實施例僅繪示一個閂鎖資料信號LDS以作為示範性實施例，然本領域具通常知識者可依據實際應用時的需求，調整閂鎖資料信號的數量，本發明對此並不加以限制。Then, the latch driver 120 latches the internal data signal IDS according to the first voltage V1, and after latching the internal data signal IDS, outputs at least one latched data signal (for example, a latch) according to the second voltage V2. (Data signal LDS) to the voltage offset device 130, it should be noted that, to simplify the description, this embodiment only shows a latched data signal LDS as an exemplary embodiment, but those with ordinary knowledge in the art may use the actual application In the present invention, the number of latch data signals is adjusted, which is not limited in the present invention.

電壓偏移器130耦接至閂鎖驅動器120，操作於第一電壓V1及第二電壓V2，會依據第二電壓V2來接收閂鎖資料信號LDS，並且依據閂鎖資料信號LDS來產生至少一輸出資料信號（例如是輸出資料信號ODS），其中電壓偏移器130會依據第一電壓來設定輸出資料信號ODS的電壓值，在此請注意，為簡化說明，本實施例同樣僅繪示一個輸出資料信號ODS作為示範性實施例，然本發明對輸出資料信號的數量並不加以限制。The voltage shifter 130 is coupled to the latch driver 120 and operates at the first voltage V1 and the second voltage V2. It receives the latch data signal LDS according to the second voltage V2, and generates at least one according to the latch data signal LDS. Output data signal (for example, output data signal ODS), in which the voltage shifter 130 will set the voltage value of the output data signal ODS according to the first voltage. Please note that for simplicity, this embodiment only shows one The output data signal ODS is taken as an exemplary embodiment, but the present invention does not limit the number of output data signals.

值得一提的是，在本實施例中，第一電壓V1的電壓值會大於第二電壓V2的電壓值，亦即本實施例是以不同電壓值的第一電壓V1及第二電壓V2來分別驅動資料接收器110、閂鎖驅動器120以及電壓偏移器130以進行多個動作。如此一來，便可透過提供電壓值較大的第一電壓V1來操作資料接收器110，達到提升記憶體裝置100操作速度的目的。此外，亦透過對閂鎖驅動器120以及電壓偏移器130分級驅動的方式，以電壓值較大的第一電壓V1來驅動閂鎖驅動器120，藉此來接收並閂鎖內部資料信號IDS，並以電壓值較小的第二電壓V2來驅動閂鎖驅動器120以輸出閂鎖資料信號LDS，再以電壓值較小的第二電壓V2來驅動電壓偏移器130，以接收閂鎖資料信號LDS，並以電壓值較大的第一電壓V1來驅動電壓偏移器130以設定輸出資料信號ODS，藉此達到降低記憶體裝置100的功率消耗之目的。It is worth mentioning that in this embodiment, the voltage value of the first voltage V1 will be greater than the voltage value of the second voltage V2, that is, this embodiment uses the first voltage V1 and the second voltage V2 with different voltage values. The data receiver 110, the latch driver 120, and the voltage shifter 130 are respectively driven to perform a plurality of operations. In this way, the data receiver 110 can be operated by providing the first voltage V1 with a larger voltage value, so as to improve the operation speed of the memory device 100. In addition, the latch driver 120 and the voltage shifter 130 are also driven in stages to drive the latch driver 120 with the first voltage V1 having a larger voltage value, thereby receiving and latching the internal data signal IDS, and The latch driver 120 is driven by the second voltage V2 with a smaller voltage value to output the latch data signal LDS, and the voltage offset device 130 is driven by the second voltage V2 with a smaller voltage value to receive the latch data signal LDS The first voltage V1 with a larger voltage value is used to drive the voltage shifter 130 to set the output data signal ODS, thereby reducing the power consumption of the memory device 100.

請參照圖2，圖2繪示本發明另一實施例的記憶體裝置的電路方塊示意圖。記憶體裝置200包括資料接收器210、閂鎖驅動器220以及電壓偏移器230。資料接收器210操作在第一電壓V1，會接收致能信號En、參考信號Ref以及輸入資料信號Din，並依據第一電壓V1來輸出內部資料信號IDS。詳細來說明，資料接收器210包括電晶體T1~T6以及反向電路210a。電晶體T1的第一端接收第一電壓V1，電晶體T1的控制端接收致能信號En，電晶體T1的第二端耦接至電晶體T2的第一端。電晶體T2的第一端耦接至電晶體T1的第二端，電晶體T2的控制端接收參考信號Ref，電晶體T2的第二端耦接至電晶體T3的第一端。電晶體T3的第一端耦接至電晶體T2的第二端，電晶體T3的控制端與第一端相互耦接，電晶體T3的第二端接收接地電壓GND。Please refer to FIG. 2. FIG. 2 is a schematic circuit block diagram of a memory device according to another embodiment of the present invention. The memory device 200 includes a data receiver 210, a latch driver 220, and a voltage shifter 230. The data receiver 210 operates at the first voltage V1, receives the enable signal En, the reference signal Ref, and the input data signal Din, and outputs the internal data signal IDS according to the first voltage V1. To explain in detail, the data receiver 210 includes transistors T1 to T6 and an inversion circuit 210a. The first terminal of the transistor T1 receives a first voltage V1, the control terminal of the transistor T1 receives an enable signal En, and the second terminal of the transistor T1 is coupled to the first terminal of the transistor T2. The first terminal of the transistor T2 is coupled to the second terminal of the transistor T1, the control terminal of the transistor T2 receives the reference signal Ref, and the second terminal of the transistor T2 is coupled to the first terminal of the transistor T3. The first terminal of the transistor T3 is coupled to the second terminal of the transistor T2. The control terminal and the first terminal of the transistor T3 are coupled to each other. The second terminal of the transistor T3 receives a ground voltage GND.

電晶體T4的第一端耦接至電晶體T1的第二端，電晶體T4的控制端接收輸入資料信號Din，電晶體T4的第二端耦接至電晶體T5的第一端。電晶體T5的第一端耦接至電晶體T4的第二端，電晶體T5的控制端耦接至電晶體T3的控制端，電晶體T5的第二端接收接地電壓GND，其中，電晶體T1可形成一電流源，電晶體T2、T4可形成一差動對，電晶體T3、T5則可形成一主動負載，亦即在本實施例中，電晶體T1~T5可形成一差動放大器。電晶體T6的第一端耦接至電晶體T5的第一端，電晶體T6的控制端接收致能信號En，電晶體T6的第二端接收接地電壓GND。反向電路210a耦接至電晶體T6的第一端，並用以輸出內部資料信號IDS。The first terminal of transistor T4 is coupled to the second terminal of transistor T1. The control terminal of transistor T4 receives the input data signal Din, and the second terminal of transistor T4 is coupled to the first terminal of transistor T5. The first terminal of the transistor T5 is coupled to the second terminal of the transistor T4, the control terminal of the transistor T5 is coupled to the control terminal of the transistor T3, and the second terminal of the transistor T5 receives a ground voltage GND, wherein the transistor T1 can form a current source, transistors T2 and T4 can form a differential pair, and transistors T3 and T5 can form an active load, that is, in this embodiment, transistors T1 to T5 can form a differential amplifier. . The first terminal of the transistor T6 is coupled to the first terminal of the transistor T5. The control terminal of the transistor T6 receives the enable signal En, and the second terminal of the transistor T6 receives the ground voltage GND. The inverting circuit 210a is coupled to the first terminal of the transistor T6 and is used to output an internal data signal IDS.

進一步來說明，反向電路210a中包括電晶體T7~T8。電晶體T7的第一端接收第一電壓V1，電晶體T7的控制端耦接至電晶體T6的第一端，並且電晶體T7的第二端會輸出內部資料信號IDS。電晶體T8的第一端耦接至電晶體T7的第二端，電晶體T8的控制端耦接至電晶體T7的控制端，電晶體T8的第二端會接收接地電壓GND。To further explain, the inverter circuit 210a includes transistors T7 to T8. The first terminal of the transistor T7 receives the first voltage V1, the control terminal of the transistor T7 is coupled to the first terminal of the transistor T6, and the second terminal of the transistor T7 outputs an internal data signal IDS. The first terminal of the transistor T8 is coupled to the second terminal of the transistor T7. The control terminal of the transistor T8 is coupled to the control terminal of the transistor T7. The second terminal of the transistor T8 receives the ground voltage GND.

值得一提的是，本實施例的反向電路210a可以本領域具通常知識者所熟知的其他記憶體裝置電路的反向電路的架構來據以實施，本發明對此並不加以限制。It is worth mentioning that the inversion circuit 210a of this embodiment can be implemented according to the structure of the inversion circuit of other memory device circuits known to those skilled in the art, which is not limited in the present invention.

此外，閂鎖驅動器220包括第一閂鎖驅動電路221以及第二閂鎖驅動電路222。第一閂鎖驅動電路221耦接至資料接收器210，操作於第一電壓V1及第二電壓V2，會接收重置信號Reset、寫入選擇信號WDQS以及內部資料信號IDS，並且依據第一電壓V1閂鎖來自資料接收器210的內部資料信號IDS，以及依據第二電壓V2輸出至少一閂鎖資料信號中的一個閂鎖資料信號（例如是第一閂鎖資料信號LDS1）。而第二閂鎖驅動電路222則同樣耦接至資料接收器210，並且同樣操作於第一電壓V1及第二電壓V2，會接收重置信號Reset、寫入選擇信號WDQS以及內部資料信號IDS，以依據第一電壓V1閂鎖來自資料接收器210的內部資料信號IDS，並依據第二電壓V2輸出至少一閂鎖資料信號中的一個閂鎖資料信號（例如是第二閂鎖資料信號LDS2），其中第一閂鎖驅動電路221及第二閂鎖驅動電路222會依據重置信號Reset進行重置操作。此外，第一閂鎖驅動電路221及第二閂鎖驅動電路222會分別依據寫入選擇信號WDQS進行寫入操作，其中，第一閂鎖驅動電路221所接收的寫入選擇信號WDQS與第二閂鎖驅動電路222所接收的寫入選擇信號WDQS呈現反向。In addition, the latch driver 220 includes a first latch driving circuit 221 and a second latch driving circuit 222. The first latch driving circuit 221 is coupled to the data receiver 210 and operates at the first voltage V1 and the second voltage V2. The first latch driving circuit 221 receives the reset signal Reset, the write selection signal WDQS, and the internal data signal IDS. V1 latches from the internal data signal IDS of the data receiver 210, and outputs one latch data signal (for example, the first latch data signal LDS1) of at least one latch data signal according to the second voltage V2. The second latch driving circuit 222 is also coupled to the data receiver 210 and is also operated at the first voltage V1 and the second voltage V2. The internal data signal IDS from the data receiver 210 is latched according to the first voltage V1, and one latch data signal (for example, the second latch data signal LDS2) is output according to the second voltage V2. The first latch driving circuit 221 and the second latch driving circuit 222 perform a reset operation according to a reset signal Reset. In addition, the first latch driving circuit 221 and the second latch driving circuit 222 respectively perform a write operation according to the write selection signal WDQS, wherein the write selection signal WDQS received by the first latch driving circuit 221 and the second The write selection signal WDQS received by the latch driving circuit 222 is inverted.

此外，本發明另有提到，本實施例的第一閂鎖資料信號LDS1例如是奇通道信號，而第二閂鎖資料信號LDS2則例如是偶通道信號，如此一來，可藉由在記憶體裝置中準備奇通道及偶通道兩個路徑，使記憶體裝置在時脈信號上升及下降時皆能傳輸資料，亦即在一個時脈週期內可傳輸兩次資料，以提升記憶體裝置的操作速度。In addition, the present invention further mentions that the first latched data signal LDS1 in this embodiment is, for example, an odd channel signal, and the second latched data signal LDS2 is, for example, an even channel signal. In this way, the In the body device, two paths, odd and even, are prepared so that the memory device can transmit data when the clock signal rises and falls, that is, data can be transmitted twice in a clock cycle to improve the memory device's performance. Operating speed.

另一方面，電壓偏移器230包括第一電壓偏移電路231以及第二電壓偏移電路232。第一電壓偏移電路231耦接至第一閂鎖驅動電路221，操作於第一電壓V1及第二電壓V2，會依據第二電壓V2來接收第一閂鎖資料信號LDS1，並依據第一閂鎖資料信號LDS1來產生至少一輸出資料信號中的一個輸出資料信號（例如是第一輸出資料信號ODS1），其中第一電壓偏移電路231會依據第一電壓V1來設定第一輸出資料信號ODS1的電壓值。相對地，第二電壓偏移電路232則耦接至第二閂鎖驅動電路222，依據第二電壓V2來接收第二閂鎖資料信號LDS2，並且會依據第二閂鎖資料信號LDS2來產生至少一輸出資料信號中的一個輸出資料信號（例如是第二閂鎖資料信號ODS2），其中第二輸出資料信號ODS2的電壓值由第二電壓偏移電路232依據第一電壓V1來設定。On the other hand, the voltage shifter 230 includes a first voltage shift circuit 231 and a second voltage shift circuit 232. The first voltage offset circuit 231 is coupled to the first latch driving circuit 221, operates at the first voltage V1 and the second voltage V2, and receives the first latch data signal LDS1 according to the second voltage V2, and according to the first The data signal LDS1 is latched to generate one of the at least one output data signal (for example, the first output data signal ODS1). The first voltage offset circuit 231 sets the first output data signal according to the first voltage V1. The voltage value of ODS1. In contrast, the second voltage offset circuit 232 is coupled to the second latch driving circuit 222, receives the second latch data signal LDS2 according to the second voltage V2, and generates at least according to the second latch data signal LDS2. One of the output data signals (for example, the second latched data signal ODS2), wherein the voltage value of the second output data signal ODS2 is set by the second voltage offset circuit 232 according to the first voltage V1.

接著，詳細來說明關於第一閂鎖驅動電路221以及第二閂鎖驅動電路222的內部電路結構，為方便說明，在此僅繪示第一閂鎖驅動電路221的內部電路結構，並以第一閂鎖驅動電路221作為示範性實施例來進行說明，請同步參照圖2及圖3，圖3繪示本發明圖2實施例的閂鎖驅動電路的內部電路結構示意圖。第一閂鎖驅動電路221包括閂鎖電路221a以及驅動電路221b。閂鎖電路221a耦接至資料接收器210，用以接收重置信號Reset、寫入選擇信號WDQS以及內部資料信號IDS，會依據第一電壓V1來對內部資料信號IDS進行閂鎖。驅動電路221b耦接至閂鎖電路221a，會依據第二電壓V2來輸出第一閂鎖資料信號LDS1。Next, the internal circuit structures of the first latch drive circuit 221 and the second latch drive circuit 222 will be described in detail. For convenience of explanation, only the internal circuit structure of the first latch drive circuit 221 is shown here, and the first A latch driving circuit 221 is described as an exemplary embodiment. Please refer to FIG. 2 and FIG. 3 synchronously. FIG. 3 illustrates a schematic diagram of an internal circuit structure of the latch driving circuit according to the embodiment of FIG. 2 of the present invention. The first latch driving circuit 221 includes a latch circuit 221a and a driving circuit 221b. The latch circuit 221a is coupled to the data receiver 210 for receiving a reset signal Reset, a write selection signal WDQS, and an internal data signal IDS, and latches the internal data signal IDS according to the first voltage V1. The driving circuit 221b is coupled to the latch circuit 221a, and outputs the first latch data signal LDS1 according to the second voltage V2.

進一步來說，閂鎖電路221a包括反向器INV1~INV4、傳輸閘TC1~TC2以及閂鎖器IVC1~ IVC2。反向器INV1的輸入端接收寫入選擇信號WDQS，反向器INV1的輸出端耦接至反向器INV2的輸入端，並輸出反向寫入選擇信號。反向器INV2的輸入端耦接至反向器INV1的輸出端，反向器INV2的輸出端耦接至傳輸閘TC1的P通道控制端。反向器INV3的輸入端接收內部資料信號IDS，反向器INV3的輸出端耦接至傳輸閘TC1的輸入端，並輸出反向內部資料信號。傳輸閘TC1的N通道控制端耦接至反向器INV1的輸出端，傳輸閘TC1的P通道控制端耦接至反向器INV2的輸出端，傳輸閘TC1的輸入端耦接至反向器INV3的輸出端，以及傳輸閘TC1的輸出端耦接至閂鎖器IVC1的輸入端，其中，傳輸閘TC1接收反向內部資料信號，並且會受控於反向寫入選擇信號以被導通或被斷開。Further, the latch circuit 221a includes inverters INV1 to INV4, transmission gates TC1 to TC2, and latches IVC1 to IVC2. The input terminal of the inverter INV1 receives the write selection signal WDQS, and the output terminal of the inverter INV1 is coupled to the input terminal of the inverter INV2 and outputs a reverse write selection signal. The input terminal of the inverter INV2 is coupled to the output terminal of the inverter INV1, and the output terminal of the inverter INV2 is coupled to the P channel control terminal of the transmission gate TC1. The input terminal of the inverter INV3 receives the internal data signal IDS, and the output terminal of the inverter INV3 is coupled to the input terminal of the transmission gate TC1 and outputs a reverse internal data signal. The N-channel control terminal of transmission gate TC1 is coupled to the output of inverter INV1, the P-channel control terminal of transmission gate TC1 is coupled to the output of inverter INV2, and the input terminal of transmission gate TC1 is coupled to the inverter The output of INV3 and the output of transmission gate TC1 are coupled to the input of latch IVC1. The transmission gate TC1 receives the reverse internal data signal and is controlled by the reverse write selection signal to be turned on or Was disconnected.

閂鎖器IVC1的輸入端耦接至傳輸閘TC1的輸出端，閂鎖器IVC1的輸出端耦接至傳輸閘TC2的輸入端，用以對反向內部資料信號進行閂鎖。傳輸閘TC2的P通道控制端耦接至反向器INV1的輸出端，傳輸閘TC2的N通道控制端耦接至反向器INV2的輸出端，傳輸閘TC2的輸入端耦接至閂鎖器IVC1的輸出端，以及傳輸閘TC2的輸出端耦接至閂鎖器IVC2的輸入端，其中，傳輸閘TC2接收閂鎖器IVC1中的信號，並且會受控於反向寫入選擇信號以被導通或被斷開。反向器INV4的輸入端接收重置信號Reset，反向器INV4的輸出端耦接至閂鎖器IVC2的輸入端，以輸出反向重置信號。閂鎖器IVC2的輸入端耦接至傳輸閘TC2的輸出端，閂鎖器IVC2的輸出端耦接至驅動電路221b，會閂鎖來自閂鎖器IVC1中的信號以及反向重置信號。The input terminal of the latch IVC1 is coupled to the output terminal of the transmission gate TC1, and the output terminal of the latch IVC1 is coupled to the input terminal of the transmission gate TC2 to latch the reverse internal data signal. The P channel control terminal of the transmission gate TC2 is coupled to the output of the inverter INV1, the N channel control terminal of the transmission gate TC2 is coupled to the output of the inverter INV2, and the input terminal of the transmission gate TC2 is coupled to the latch. The output of IVC1 and the output of transmission gate TC2 are coupled to the input of latch IVC2, where transmission gate TC2 receives the signal in latch IVC1 and is controlled by the reverse write selection signal to be On or off. The input terminal of the inverter INV4 receives the reset signal Reset, and the output terminal of the inverter INV4 is coupled to the input terminal of the latch IVC2 to output a reverse reset signal. The input terminal of the latch IVC2 is coupled to the output terminal of the transmission gate TC2, and the output terminal of the latch IVC2 is coupled to the driving circuit 221b, which will latch the signal from the latch IVC1 and the reverse reset signal.

詳細來說明閂鎖電路221a中各元件間的作動方式。於閂鎖電路221a中，反向器INV3會接收內部資料信號IDS，以產生反向內部資料信號，而反向器INV4則會接收重置信號Reset，以產生反向重置信號。當寫入選擇信號WDQS為邏輯低準位（例如是0）時，反向器INV1會接收寫入選擇信號WDQS，以產生為邏輯高準位（例如是1）的反向寫入選擇信號，此時傳輸閘TC1會受控於為邏輯高準位的反向寫入選擇信號而被導通，接收反向內部資料信號並傳輸至閂鎖器IVC1以進行閂鎖，此時傳輸閘TC2受控於反向寫入選擇信號而被斷開。The operation of each element in the latch circuit 221a will be described in detail. In the latch circuit 221a, the inverter INV3 receives the internal data signal IDS to generate a reverse internal data signal, and the inverter INV4 receives a reset signal Reset to generate a reverse reset signal. When the write selection signal WDQS is at a logic low level (for example, 0), the inverter INV1 receives the write selection signal WDQS to generate a reverse write selection signal for a logic high level (for example, 1). At this time, the transmission gate TC1 is controlled by the reverse write selection signal for the logic high level to be turned on. The reverse internal data signal is received and transmitted to the latch IVC1 for latching. At this time, the transmission gate TC2 is controlled. It is turned off in the reverse write selection signal.

接著，當寫入選擇信號WDQS轉態為邏輯高準位（即1）時，則反向寫入選擇信號會轉態為邏輯低準位（即0），此時傳輸閘TC1會受控於為邏輯低準位的反向寫入選擇信號而被斷開，而傳輸閘TC2則受控於為邏輯低準位的反向寫入選擇信號而被導通，以接收閂鎖器IVC1中的資料並傳輸至閂鎖器IVC2，使閂鎖器IVC2對閂鎖器IVC1中的資料以及反向重置信號進行閂鎖，以輸出一反向第一閂鎖資料信號至驅動電路221b。Then, when the write selection signal WDQS transitions to a logic high level (ie, 1), the reverse write selection signal transitions to a logic low level (ie, 0). At this time, the transmission gate TC1 will be controlled by It is turned off for the reverse write select signal of the logic low level, and the transmission gate TC2 is controlled to be turned on for the reverse write select signal of the logic low level to receive the data in the latch IVC1 And transmitted to the latch IVC2, so that the latch IVC2 latches the data in the latch IVC1 and the reverse reset signal to output a reverse first latch data signal to the driving circuit 221b.

此外，本發明另有提到，閂鎖器IVC1中包括反向器INV5~ INV6，反向器INV5的輸入端耦接至傳輸閘TC1的輸出端，反向器INV5的輸出端耦接至傳輸閘TC2的輸入端。反向器INV6的輸入端耦接至反向器INV5的輸出端，反向器INV6的輸出端耦接至反向器INV5的輸入端。閂鎖器IVC2則包括反向器INV7以及反及閘NAND1。反及閘NAND1的第一端耦接至傳輸閘TC2的輸出端，反及閘NAND1的第二端耦接至反向器INV4的輸出端，反及閘NAND1的輸出端則與反向器INV7的輸入端相互耦接，並且反向器INV7的輸出端耦接至反及閘NAND1的第一端。In addition, the present invention further mentions that the latch IVC1 includes inverters INV5 to INV6. The input of the inverter INV5 is coupled to the output of the transmission gate TC1, and the output of the inverter INV5 is coupled to the transmission. Gate TC2 input. The input terminal of the inverter INV6 is coupled to the output terminal of the inverter INV5, and the output terminal of the inverter INV6 is coupled to the input terminal of the inverter INV5. The latch IVC2 includes an inverter INV7 and a reverse-gate NAND1. The first terminal of the inverter NAND1 is coupled to the output of the transmission gate TC2, the second terminal of the inverter NAND1 is coupled to the output of the inverter INV4, and the output of the inverter NAND1 is connected to the inverter INV7. The input terminals are coupled to each other, and the output terminal of the inverter INV7 is coupled to the first terminal of the inverting gate NAND1.

另一方面，驅動電路221b包括電晶體T9a~T10a。電晶體T9a的第一端接收第二電壓V2，電晶體T9a的控制端耦接至閂鎖電路221a中閂鎖器IVC2的輸出端，電晶體T9a的第二端則輸出第一閂鎖資料信號LDS1。電晶體T10a的第一端耦接至電晶體T9a的第二端，電晶體T10a的控制端同樣耦接至閂鎖電路221a中閂鎖器IVC2的輸出端，並且電晶體T10a的第二端接收接地電壓GND，如此一來，驅動電路221b在接收到反向第一閂鎖資料信號後，便會依據第二電壓V2來輸出第一閂鎖資料信號LDS1，其中，本實施例的驅動電路221b的電晶體T9a為P型電晶體，電晶體T10a為N型電晶體。此外，本實施例的第二閂鎖驅動電路222的內部電路結構及元件作動方式與第一閂鎖驅動電路221相類似，故本領域具通常知識者可依據前述關於第一閂鎖驅動電路221實施方式的說明，來實現本實施例第二閂鎖驅動電路222的內部電路結構，在此不重複贅述。On the other hand, the driving circuit 221b includes transistors T9a to T10a. The first terminal of the transistor T9a receives the second voltage V2, the control terminal of the transistor T9a is coupled to the output terminal of the latch IVC2 in the latch circuit 221a, and the second terminal of the transistor T9a outputs the first latch data signal LDS1. The first terminal of the transistor T10a is coupled to the second terminal of the transistor T9a. The control terminal of the transistor T10a is also coupled to the output terminal of the latch IVC2 in the latch circuit 221a, and the second terminal of the transistor T10a receives The ground voltage GND. In this way, after receiving the reverse first latch data signal, the driving circuit 221b outputs the first latch data signal LDS1 according to the second voltage V2. Among them, the driving circuit 221b of this embodiment The transistor T9a is a P-type transistor, and the transistor T10a is an N-type transistor. In addition, the internal circuit structure and component operation method of the second latch driving circuit 222 in this embodiment are similar to those of the first latch driving circuit 221, so those having ordinary knowledge in the art may refer to the aforementioned first latch driving circuit 221 The description of the implementation manner is used to implement the internal circuit structure of the second latch driving circuit 222 of this embodiment, and details are not repeated here.

值得一提的是，請同步參照圖2及圖4，圖4繪示本發明圖2實施例的閂鎖驅動電路的另一實施方式的內部電路結構示意圖。與前述圖3實施例不同的地方在於，本實施例的閂鎖電路221a更包括反向器INVa，並且本實施例的驅動電路221b中電晶體T9b及電晶體T10b均為N型電晶體。詳細來說明，反向器INVa的輸入端耦接至閂鎖器IVC2的輸出端，並且反向器INVa的輸出端耦接至驅動電路221b中電晶體T9b的控制端，其中，反向器INVa接收來自閂鎖器IVC2的反向第一閂鎖資料信號以傳輸第一閂鎖資料信號LDS1至電晶體T9b的控制端。如此一來，本實施例的驅動電路221b可藉由使用為N型電晶體的電晶體T9b、T10b，來增加驅動電路221b的驅動能力並提升操作速度。除此之外，驅動電路221b中的電晶體T9b會因基體效應（Body effect），而使得驅動電路221b的第一閂鎖資料信號LDS1的電壓值最高可實質上等於第二電壓V2的電壓值減去電晶體T9b的閾值電壓的電壓值，藉此達到省電及降低功率消耗的效果。相對的，本實施例的第二閂鎖驅動電路222中的閂鎖電路同樣可包括反向器INVa，並且驅動電路中的電晶體同樣可以均替換為N型電晶體，本領域具通常知識者可依據前述關於閂鎖電路221a及驅動電路221b實施方式的說明，實現本實施例第二閂鎖驅動電路222的內部電路結構，在此不重複贅述。It is worth mentioning that please refer to FIG. 2 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of an internal circuit structure of another embodiment of the latch driving circuit according to the embodiment of FIG. 2 of the present invention. The difference from the foregoing embodiment of FIG. 3 is that the latch circuit 221a of this embodiment further includes an inverter INVa, and the transistors T9b and T10b in the driving circuit 221b of this embodiment are N-type transistors. To explain in detail, the input terminal of the inverter INVa is coupled to the output terminal of the latch IVC2, and the output terminal of the inverter INVa is coupled to the control terminal of the transistor T9b in the driving circuit 221b, where the inverter INVa Receive the reverse first latch data signal from the latch IVC2 to transmit the first latch data signal LDS1 to the control terminal of the transistor T9b. In this way, the driving circuit 221b of this embodiment can increase the driving capability of the driving circuit 221b and increase the operation speed by using the transistors T9b and T10b which are N-type transistors. In addition, the transistor T9b in the driving circuit 221b may have a body effect, so that the voltage value of the first latch data signal LDS1 of the driving circuit 221b may be at most substantially equal to the voltage value of the second voltage V2. The voltage value of the threshold voltage of the transistor T9b is subtracted, thereby achieving the effects of saving power and reducing power consumption. In contrast, the latch circuit in the second latch driving circuit 222 of this embodiment may also include an inverter INVa, and the transistors in the driving circuit may also be replaced with N-type transistors. Those having ordinary knowledge in the art The internal circuit structure of the second latch driving circuit 222 of this embodiment may be implemented according to the foregoing description of the implementation of the latch circuit 221a and the driving circuit 221b, and details are not repeated here.

此外，本實施例的閂鎖電路221a及驅動電路221b的其餘電路結構及作動方式與圖3實施例相類似，在此不重複贅述。In addition, the remaining circuit structures and operating modes of the latch circuit 221a and the driving circuit 221b in this embodiment are similar to those in the embodiment in FIG. 3, and are not repeated here.

接著，詳細來說明關於第一電壓偏移電路231以及第二電壓偏移電路232的內部電路結構，為方便說明，在此同樣僅繪示第一電壓偏移電路231的內部電路結構，並以第一電壓偏移電路231作為示範性實施例來進行說明，請同步參照圖2及圖5，圖5繪示本發明圖2實施例的電壓偏移電路的內部電路結構示意圖。第一電壓偏移電路231包括第一輸入電路231a以及第一輸出設定電路231b，第一輸入電路231a耦接至第一閂鎖驅動電路221，會依據第二電壓V2來接收第一閂鎖資料信號LDS1。第一輸出設定電路231b則耦接至第一輸入電路231a，並依據第一閂鎖資料信號LDS1來產生第一輸出資料信號ODS1，其中第一輸出設定電路231b會依據第一電壓V1來設定第一輸出資料信號ODS1的電壓值。Next, the internal circuit structures of the first voltage offset circuit 231 and the second voltage offset circuit 232 will be described in detail. For convenience of explanation, only the internal circuit structure of the first voltage offset circuit 231 is also shown here, and The first voltage offset circuit 231 is described as an exemplary embodiment. Please refer to FIG. 2 and FIG. 5 synchronously. FIG. 5 is a schematic diagram illustrating an internal circuit structure of the voltage offset circuit according to the embodiment of FIG. 2 of the present invention. The first voltage offset circuit 231 includes a first input circuit 231a and a first output setting circuit 231b. The first input circuit 231a is coupled to the first latch driving circuit 221 and receives the first latch data according to the second voltage V2. Signal LDS1. The first output setting circuit 231b is coupled to the first input circuit 231a and generates a first output data signal ODS1 according to the first latch data signal LDS1. The first output setting circuit 231b sets the first output data signal ODS1 according to the first voltage V1. A voltage value of the output data signal ODS1.

進一步來說，本實施例的第一輸入電路231a包括反向器INV9、INV10。反向器INV9的輸入端耦接至第一閂鎖驅動電路221，並且會接收第一閂鎖資料信號LDS1，反向器INV9的輸出端耦接至第一輸出設定電路231b。反向器INV10的輸入端耦接至反向器INV9的輸出端，並且反向器INV10的輸出端耦接至第一輸出設定電路231b。Further, the first input circuit 231a of this embodiment includes inverters INV9 and INV10. The input terminal of the inverter INV9 is coupled to the first latch driving circuit 221 and receives the first latch data signal LDS1. The output terminal of the inverter INV9 is coupled to the first output setting circuit 231b. An input terminal of the inverter INV10 is coupled to an output terminal of the inverter INV9, and an output terminal of the inverter INV10 is coupled to the first output setting circuit 231b.

另一方面，第一輸出設定電路231b包括電晶體T11~T16。電晶體T11的第一端接收第一電壓V1，電晶體T11的控制端耦接至電晶體T14的第一端，電晶體T11的第二端耦接至電晶體T13的控制端。電晶體T12的第一端耦接至電晶體T11的第二端，電晶體T12的控制端耦接至第一輸入電路231a中反向器INV9的輸出端，電晶體T12的第二端接收接地電壓GND。電晶體T13的第一端接收第一電壓V1，電晶體T13的控制端耦接至電晶體T11的第二端，電晶體T13的第二端耦接至電晶體T11的控制端。電晶體T14的第一端耦接至電晶體T13的第二端，電晶體T14的控制端耦接至第一輸入電路231a中反向器INV10的輸出端，電晶體T14的第二端接收接地電壓GND。電晶體T15的第一端接收第一電壓V1，電晶體T15的控制端耦接至電晶體T13的第二端，電晶體T15的第二端耦接至電晶體T16的第一端，並輸出第一輸出資料信號ODS1。電晶體T16的第一端耦接至電晶體T15的第二端，電晶體T16的控制端耦接至電晶體T15的控制端，電晶體T16的第二端接收接地電壓GND。On the other hand, the first output setting circuit 231b includes transistors T11 to T16. The first terminal of the transistor T11 receives the first voltage V1, the control terminal of the transistor T11 is coupled to the first terminal of the transistor T14, and the second terminal of the transistor T11 is coupled to the control terminal of the transistor T13. The first terminal of transistor T12 is coupled to the second terminal of transistor T11, the control terminal of transistor T12 is coupled to the output terminal of inverter INV9 in first input circuit 231a, and the second terminal of transistor T12 receives ground Voltage GND. The first terminal of the transistor T13 receives the first voltage V1, the control terminal of the transistor T13 is coupled to the second terminal of the transistor T11, and the second terminal of the transistor T13 is coupled to the control terminal of the transistor T11. The first terminal of transistor T14 is coupled to the second terminal of transistor T13, the control terminal of transistor T14 is coupled to the output terminal of inverter INV10 in first input circuit 231a, and the second terminal of transistor T14 receives ground Voltage GND. The first terminal of the transistor T15 receives the first voltage V1, the control terminal of the transistor T15 is coupled to the second terminal of the transistor T13, the second terminal of the transistor T15 is coupled to the first terminal of the transistor T16, and outputs The first output data signal is ODS1. The first terminal of the transistor T16 is coupled to the second terminal of the transistor T15, the control terminal of the transistor T16 is coupled to the control terminal of the transistor T15, and the second terminal of the transistor T16 receives a ground voltage GND.

此外，需要注意的是，本實施例的第二電壓偏移電路232的內部電路結構與第一電壓偏移電路231的內部電路結構相類似，故本領域具通常知識者可依據前述關於第一電壓偏移電路231實施方式的說明，來實現本實施例第二電壓偏移電路232的內部電路結構，在此不重複贅述。In addition, it should be noted that the internal circuit structure of the second voltage offset circuit 232 in this embodiment is similar to the internal circuit structure of the first voltage offset circuit 231, so those having ordinary knowledge in the art may refer to The description of the implementation of the voltage offset circuit 231 implements the internal circuit structure of the second voltage offset circuit 232 of this embodiment, and details are not repeated here.

基於上述說明，本實施例可藉由提供較大電壓值的第一電壓V1來操作資料接收器210的方式，來提升記憶體裝置200的操作速度，並且在閂鎖驅動器220中，分別提供不同電壓值的第一電壓V1及第二電壓V2至第一閂鎖驅動電路221及第二閂鎖驅動電路222中的閂鎖電路及驅動電路，以分級驅動其電路動作，並且在電壓偏移器230中，分別提供不同電壓值的第一電壓V1及第二電壓V2至第一電壓偏移電路231及第二電壓偏移電路232中的輸入電路及輸出設定電路，分級驅動其電路動作，據此達到降低記憶體裝置200的功率消耗之目的。Based on the above description, this embodiment can increase the operating speed of the memory device 200 by operating the data receiver 210 by providing the first voltage V1 with a larger voltage value, and differently provided in the latch driver 220. The voltages of the first voltage V1 and the second voltage V2 to the latch circuits and the driving circuits in the first latch driving circuit 221 and the second latch driving circuit 222 are to drive the circuit operation in stages, and the voltage shifter In 230, the first voltage V1 and the second voltage V2 with different voltage values are respectively provided to the input circuit and the output setting circuit in the first voltage offset circuit 231 and the second voltage offset circuit 232, and the circuit operations are driven in stages. This achieves the purpose of reducing power consumption of the memory device 200.

綜上所述，本發明透過具有較大電壓值的第一電壓來驅動資料接收器，以提升記憶體裝置的操作速度，並且會以第一電壓驅動閂鎖驅動器來閂鎖內部資料信號，並且以具有較小電壓值的第二電壓驅動閂鎖驅動器來輸出至少一閂鎖資料信號，接著以第二電壓來驅動電壓偏移器以接收至少一閂鎖資料信號，再透過第一電壓驅動電壓偏移器來輸出至少一輸出資料信號，藉此透過分級驅動的方式，來達到降低記憶體裝置的功率消耗之目的。In summary, the present invention drives the data receiver through a first voltage with a larger voltage value to increase the operating speed of the memory device, and drives the latch driver to latch the internal data signal with the first voltage, and The latch driver is driven with a second voltage having a smaller voltage value to output at least one latch data signal, and then the voltage shifter is driven with a second voltage to receive at least one latch data signal, and the voltage is driven through the first voltage The offset device outputs at least one output data signal, thereby achieving the purpose of reducing the power consumption of the memory device through a hierarchical driving method.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。［產業利用性］Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. [Industrial availability]

本發明透過兩個不同電壓值的第一電壓及第二電壓來分別驅動記憶體裝置中的資料接收器、閂鎖驅動器以及電壓偏移器，以依據第一電壓及第二電壓來進行不同的操作，進而提升記憶體裝置的操作速度，並可實現記憶體裝置的低功率消耗性能。The invention drives the data receiver, the latch driver, and the voltage shifter in the memory device through two first voltages and second voltages with different voltage values, so as to perform different operations according to the first voltage and the second voltage. Operation, thereby increasing the operating speed of the memory device and achieving low power consumption performance of the memory device.

100、200‧‧‧記憶體裝置100, 200‧‧‧ memory devices

110、210‧‧‧資料接收器110, 210‧‧‧ Data Receiver

120、220‧‧‧閂鎖驅動器120, 220‧‧‧ Latch Drive

130、230‧‧‧電壓偏移器130, 230‧‧‧Voltage Shifter

210a‧‧‧反向電路210a‧‧‧Reverse circuit

221、222‧‧‧閂鎖驅動電路221, 222‧‧‧latch drive circuit

221a‧‧‧閂鎖電路221a‧‧‧Latch circuit

221b‧‧‧驅動電路221b‧‧‧Drive circuit

231、232‧‧‧電壓偏移電路231, 232‧‧‧ voltage offset circuit

231a‧‧‧第一輸入電路231a‧‧‧first input circuit

231b‧‧‧第一輸出設定電路231b‧‧‧First output setting circuit

Din‧‧‧輸入資料信號Din‧‧‧Input data signal

En‧‧‧致能信號En‧‧‧ enable signal

GND‧‧‧接地電壓GND‧‧‧ ground voltage

IDS‧‧‧內部資料信號IDS‧‧‧ Internal Data Signal

INV1~INV7、INV9~INV10、INVa‧‧‧反向器INV1 ~ INV7, INV9 ~ INV10, INVa‧‧‧Inverter

IVC1、IVC2‧‧‧閂鎖器IVC1, IVC2‧‧‧ latch

LDS、LDS1、LDS2‧‧‧閂鎖資料信號LDS, LDS1, LDS2‧‧‧ Latch data signal

NAND1‧‧‧反及閘NAND1‧‧‧Reverse gate

ODS、ODS1、ODS2‧‧‧輸出資料信號ODS, ODS1, ODS2‧‧‧ output data signal

Ref‧‧‧參考信號Ref‧‧‧ Reference Signal

Reset‧‧‧重置信號Reset‧‧‧ Reset signal

T1~T8、T9a、T9b、T10a、T10b、T11~T16‧‧‧電晶體T1 ~ T8, T9a, T9b, T10a, T10b, T11 ~ T16‧‧‧Transistors

TC1、TC2‧‧‧傳輸閘TC1, TC2‧‧‧Transmission gate

V1‧‧‧第一電壓V1‧‧‧ the first voltage

V2‧‧‧第二電壓V2‧‧‧Second voltage

WDQS‧‧‧寫入選擇信號WDQS‧‧‧write selection signal

圖1繪示本發明一實施例的記憶體裝置的電路方塊示意圖。圖2繪示本發明另一實施例的記憶體裝置的電路方塊示意圖。圖3繪示本發明圖2實施例的閂鎖驅動電路的內部電路結構示意圖。圖4繪示本發明圖2實施例的閂鎖驅動電路的另一實施方式的內部電路結構示意圖。圖5繪示本發明圖2實施例的電壓偏移電路的內部電路結構示意圖。FIG. 1 is a schematic circuit block diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a schematic circuit block diagram of a memory device according to another embodiment of the present invention. FIG. 3 is a schematic diagram showing an internal circuit structure of the latch driving circuit according to the embodiment of FIG. 2 of the present invention. FIG. 4 is a schematic diagram of the internal circuit structure of the latch driving circuit according to the embodiment of FIG. 2 according to another embodiment of the present invention. FIG. 5 is a schematic diagram showing an internal circuit structure of the voltage offset circuit according to the embodiment of FIG. 2 of the present invention.

Claims

一種記憶體裝置，包括：一資料接收器，操作在一第一電壓，用以接收一致能信號、一參考信號以及一輸入資料信號，並依據該第一電壓輸出一內部資料信號；一閂鎖驅動器，耦接至該資料接收器，用以接收一寫入選擇信號以及該內部資料信號，並依據該第一電壓閂鎖該內部資料信號，以及依據一第二電壓輸出至少一閂鎖資料信號；以及一電壓偏移器，耦接至該閂鎖驅動器，依據該第二電壓接收該至少一閂鎖資料信號，並依據該至少一閂鎖資料信號以產生至少一輸出資料信號，其中該電壓偏移器依據該第一電壓設定該至少一輸出資料信號的電壓值，其中，該第一電壓的電壓值大於該第二電壓的電壓值。 A memory device includes: a data receiver operating at a first voltage for receiving a uniform energy signal, a reference signal and an input data signal, and outputting an internal data signal according to the first voltage; a latch A driver coupled to the data receiver for receiving a write selection signal and the internal data signal, latching the internal data signal according to the first voltage, and outputting at least one latched data signal according to a second voltage And a voltage shifter coupled to the latch driver, receiving the at least one latch data signal according to the second voltage, and generating at least one output data signal according to the at least one latch data signal, wherein the voltage The offset device sets a voltage value of the at least one output data signal according to the first voltage, wherein the voltage value of the first voltage is greater than the voltage value of the second voltage.

如申請專利範圍第1項所述的記憶體裝置，其中該閂鎖驅動器更接收一重置信號，以進行重置操作。 The memory device according to item 1 of the patent application scope, wherein the latch driver further receives a reset signal to perform a reset operation.

如申請專利範圍第2項所述的記憶體裝置，其中該資料接收器包括：一第一電晶體，其第一端接收該第一電壓，該第一電晶體的控制端接收該致能信號；一第二電晶體，其第一端耦接至該第一電晶體的第二端，該第二電晶體的控制端接收該參考信號；一第三電晶體，其第一端耦接至該第二電晶體的第二端，該第三電晶體的控制端耦接至該第三電晶體的第一端，該第三電晶體的第二端接收一接地電壓；一第四電晶體，其第一端耦接至該第一電晶體的第二端，該第四電晶體的控制端接收該輸入資料信號；一第五電晶體，其第一端耦接至該第四電晶體的第二端，該第五電晶體的控制端耦接至該第三電晶體的控制端，該第五電晶體的第二端接收該接地電壓；一第六電晶體，其第一端耦接至該第五電晶體的第一端，該第六電晶體的控制端接收該致能信號，該第六電晶體的第二端接收該接地電壓；以及一反向電路，耦接至該第六電晶體的第一端，用以輸出該內部資料信號。 The memory device according to item 2 of the patent application scope, wherein the data receiver includes: a first transistor, a first terminal of which receives the first voltage, and a control terminal of the first transistor receives the enable signal A second transistor having a first terminal coupled to the second terminal of the first transistor and a control terminal of the second transistor receiving the reference signal; a third transistor having a first terminal coupled to The second end of the second transistor, the The control terminal of the third transistor is coupled to the first terminal of the third transistor, and the second terminal of the third transistor receives a ground voltage; a fourth transistor is coupled to the first terminal of the first transistor. The second terminal of the transistor, the control terminal of the fourth transistor receives the input data signal; a fifth transistor, the first terminal of which is coupled to the second terminal of the fourth transistor, The control terminal is coupled to the control terminal of the third transistor, and the second terminal of the fifth transistor receives the ground voltage; a sixth transistor, the first terminal of which is coupled to the first terminal of the fifth transistor A control terminal of the sixth transistor receives the enabling signal, a second terminal of the sixth transistor receives the ground voltage; and a reverse circuit is coupled to the first terminal of the sixth transistor for Output the internal data signal.

如申請專利範圍第3項所述的記憶體裝置，其中該反向電路包括：一第七電晶體，其第一端接收該第一電壓，該第七電晶體的控制端耦接至該第六電晶體的第一端，該第七電晶體的第二端輸出該內部資料信號；以及一第八電晶體，其第一端耦接至該第七電晶體的第二端，該第八電晶體的控制端耦接至該第七電晶體的控制端，該第八電晶體的第二端接收該接地電壓。 The memory device according to item 3 of the scope of patent application, wherein the inverting circuit includes a seventh transistor, a first terminal of which receives the first voltage, and a control terminal of the seventh transistor is coupled to the first transistor. A first terminal of a six transistor, a second terminal of the seventh transistor outputting the internal data signal; and an eighth transistor, a first terminal of which is coupled to a second terminal of the seventh transistor, the eighth transistor The control terminal of the transistor is coupled to the control terminal of the seventh transistor, and the second terminal of the eighth transistor receives the ground voltage.

如申請專利範圍第2項所述的記憶體裝置，其中該閂鎖驅動器包括：一第一閂鎖驅動電路，耦接至該資料接收器，接收該重置信號、該寫入選擇信號以及該內部資料信號，並依據該第一電壓閂鎖該內部資料信號，以及依據該第二電壓輸出該至少一閂鎖資料信號中的一第一閂鎖資料信號；以及一第二閂鎖驅動電路，耦接至該資料接收器，接收該重置信號、該寫入選擇信號以及該內部資料信號，並依據該第一電壓閂鎖該內部資料信號，以及依據該第二電壓輸出該至少一閂鎖資料信號中的一第二閂鎖資料信號。 The memory device according to item 2 of the patent application scope, wherein the latch driver comprises: A first latch driving circuit is coupled to the data receiver, receives the reset signal, the write selection signal, and the internal data signal, and latches the internal data signal according to the first voltage, and according to the first voltage. Two voltages output a first latch data signal of the at least one latch data signal; and a second latch driving circuit coupled to the data receiver to receive the reset signal, the write selection signal, and the An internal data signal, latching the internal data signal according to the first voltage, and outputting a second latch data signal of the at least one latch data signal according to the second voltage.

如申請專利範圍第5項所述的記憶體裝置，其中該第一閂鎖資料信號為一奇通道信號，該第二閂鎖資料信號為一偶通道信號。 According to the memory device in claim 5, the first latch data signal is an odd channel signal, and the second latch data signal is an even channel signal.

如申請專利範圍第5項所述的記憶體裝置，其中該第一閂鎖驅動電路及該第二閂鎖驅動電路中的每一包括：一閂鎖電路，耦接至該資料接收器，接收該重置信號、該寫入選擇信號以及該內部資料信號，並依據該第一電壓閂鎖該內部資料信號；以及一驅動電路，耦接至該閂鎖電路，其中，該第一閂鎖驅動電路中的驅動電路依據該第二電壓輸出該第一閂鎖資料信號，其中，該第二閂鎖驅動電路中的驅動電路依據該第二電壓輸出該第二閂鎖資料信號。 The memory device according to item 5 of the scope of patent application, wherein each of the first latch driving circuit and the second latch driving circuit includes: a latch circuit coupled to the data receiver and receiving The reset signal, the write selection signal, and the internal data signal, and latching the internal data signal according to the first voltage; and a driving circuit coupled to the latch circuit, wherein the first latch drives The driving circuit in the circuit outputs the first latch data signal according to the second voltage, wherein the driving circuit in the second latch driving circuit outputs the second latch data signal according to the second voltage.

如申請專利範圍第7項所述的記憶體裝置，其中該閂鎖電路包括：一第一傳輸閘，接收一反向內部資料信號，並且受控於一反向寫入選擇信號以被導通或斷開，；一第一閂鎖器，耦接至該第一傳輸閘，用以閂鎖該反向內部資料信號；一第二傳輸閘，耦接至該第一閂鎖器，用以接收該第一閂鎖器中的信號，並且受控於該反向寫入選擇信號以被導通或斷開；以及一第二閂鎖器，耦接至該第二傳輸閘，用以閂鎖該第一閂鎖器中的信號以及一反向重置信號。 The memory device according to item 7 of the patent application scope, wherein the latch circuit includes: a first transmission gate, receiving a reverse internal data signal, and controlled by a reverse write selection signal to be turned on or Disconnected; a first latch is coupled to the first transmission gate to latch the reverse internal data signal; a second transmission gate is coupled to the first latch to receive A signal in the first latch and controlled by the reverse write select signal to be turned on or off; and a second latch coupled to the second transmission gate to latch the A signal in the first latch and a reverse reset signal.

如申請專利範圍第8項所述的記憶體裝置，其中該第一閂鎖器包括：一第一反向器，其輸入端耦接至該第一傳輸閘的輸出端，該第一反向器的輸出端耦接至該第二傳輸閘的輸入端；以及一第二反向器，其輸入端耦接至該第一反向器的輸出端，該第二反向器的輸出端耦接至該第一反向器的輸入端，其中該第二閂鎖器包括：一第一反及閘，該第一反及閘的第一端耦接至該第二傳輸閘的輸出端，該第一反及閘的第二端接收該反向重置信號；以及一第三反向器，其輸入端耦接至該第一反及閘的輸出端，該第三反向器的輸出端耦接至該第一反及閘的第一端。 The memory device according to item 8 of the scope of patent application, wherein the first latch includes: a first inverter whose input terminal is coupled to the output terminal of the first transmission gate, and the first inverter The output terminal of the inverter is coupled to the input terminal of the second transmission gate; and a second inverter whose input terminal is coupled to the output terminal of the first inverter, and the output terminal of the second inverter is coupled Connected to the input end of the first inverter, wherein the second latch comprises: a first inverse gate; the first end of the first inverse gate is coupled to the output end of the second transmission gate; The second terminal of the first inverting gate receives the inverse reset signal; and a third inverter whose input terminal is coupled to the output of the first inverting gate. Terminal, the output terminal of the third inverter is coupled to the first terminal of the first inverter gate.

如申請專利範圍第9項所述的記憶體裝置，其中該閂鎖電路更包括：一第四反向器，其輸入端耦接至該第二閂鎖器的輸出端，該第四反向器的輸出端耦接至該驅動電路。 The memory device according to item 9 of the patent application scope, wherein the latch circuit further includes: a fourth inverter whose input terminal is coupled to the output terminal of the second latch, and the fourth inverter The output terminal of the device is coupled to the driving circuit.

如申請專利範圍第7項所述的記憶體裝置，其中該驅動電路包括：一第一電晶體，其第一端接收該第二電壓，該第一電晶體的控制端耦接至該閂鎖電路；以及一第二電晶體，其第一端耦接至該第一電晶體的第二端，該第二電晶體的控制端耦接至該閂鎖電路，該第二電晶體的第二端接收該接地電壓，其中，該第一閂鎖驅動電路的驅動電路中的第一電晶體的第二端輸出該第一閂鎖資料信號，其中，該第二閂鎖驅動電路的驅動電路中的第一電晶體的第二端輸出該第二閂鎖資料信號。 The memory device according to item 7 of the patent application scope, wherein the driving circuit includes a first transistor, a first terminal of which receives the second voltage, and a control terminal of the first transistor is coupled to the latch. A circuit; and a second transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal of the second transistor coupled to the latch circuit, and a second transistor Receiving the ground voltage, wherein the second terminal of the first transistor in the driving circuit of the first latch driving circuit outputs the first latch data signal, wherein the driving circuit of the second latch driving circuit The second terminal of the first transistor outputs the second latch data signal.

如申請專利範圍第11項所述的記憶體裝置，其中該第一電晶體為P型或N型電晶體，該第二電晶體為N型電晶體。 According to the eleventh aspect of the patent application scope, the first transistor is a P-type or N-type transistor, and the second transistor is an N-type transistor.

如申請專利範圍第5項所述的記憶體裝置，其中該電壓偏移器包括：一第一電壓偏移電路，耦接至該第一閂鎖驅動電路，依據該第二電壓接收該第一閂鎖資料信號，並依據該第一閂鎖資料信號以產生該至少一輸出資料信號中的一第一輸出資料信號，其中該第一電壓偏移電路依據該第一電壓設定該第一輸出資料信號的電壓值；以及一第二電壓偏移電路，耦接至該第二閂鎖驅動電路，依據該第二電壓接收該第二閂鎖資料信號，並依據該第二閂鎖資料信號以產生該至少一輸出資料信號中的一第二輸出資料信號，其中該第二電壓偏移電路依據該第一電壓設定該第二輸出資料信號的電壓值。 The memory device according to item 5 of the scope of patent application, wherein the voltage shifter comprises: a first voltage shift circuit coupled to the first latch driving circuit, and receiving the first voltage according to the second voltage. Latch the data signal and based on the first latch data signal To generate a first output data signal of the at least one output data signal, wherein the first voltage offset circuit sets a voltage value of the first output data signal according to the first voltage; and a second voltage offset circuit, Coupled to the second latch driving circuit, receiving the second latch data signal according to the second voltage, and generating a second output data signal among the at least one output data signal according to the second latch data signal Wherein the second voltage offset circuit sets a voltage value of the second output data signal according to the first voltage.

如申請專利範圍第13項所述的記憶體裝置，其中該第一電壓偏移電路包括：一第一輸入電路，耦接至該第一閂鎖驅動電路，依據該第二電壓接收該第一閂鎖資料信號；以及一第一輸出設定電路，耦接至該第一輸入電路，依據該第一閂鎖資料信號以產生該第一輸出資料信號，其中該第一輸出設定電路依據該第一電壓設定該第一輸出資料信號的電壓值，其中該第二電壓偏移電路包括：一第二輸入電路，耦接至該第二閂鎖驅動電路，依據該第二電壓接收該第二閂鎖資料信號；以及一第二輸出設定電路，耦接至該第二輸入電路，依據該第二閂鎖資料信號以產生該第二輸出資料信號，其中該第二輸出設定電路依據該第一電壓設定該第二輸出資料信號的電壓值。 The memory device according to item 13 of the scope of patent application, wherein the first voltage offset circuit includes: a first input circuit coupled to the first latch driving circuit, and receiving the first voltage according to the second voltage A latched data signal; and a first output setting circuit coupled to the first input circuit to generate the first output data signal according to the first latched data signal, wherein the first output setting circuit is based on the first The voltage sets the voltage value of the first output data signal, wherein the second voltage offset circuit includes: a second input circuit coupled to the second latch driving circuit, and receiving the second latch according to the second voltage A data signal; and a second output setting circuit coupled to the second input circuit to generate the second output data signal according to the second latched data signal, wherein the second output setting circuit is set according to the first voltage A voltage value of the second output data signal.

如申請專利範圍第14項所述的記憶體裝置，其中該第一輸入電路以及該第二輸入電路中的每一包括：一第一反向器以及一第二反向器，該第二反向器的輸入端與該第一反向器的輸出端相互耦接，其中，該第一輸入電路的第一反向器的輸入端接收該第一閂鎖資料信號，該第一輸入電路的第一反向器的輸出端以及第二反向器的輸出端耦接至該第一輸出設定電路，其中，該第二輸入電路的第一反向器的輸入端接收該第二閂鎖資料信號，該第二輸入電路的第一反向器的輸出端以及第二反向器的輸出端耦接至該第二輸出設定電路。 The memory device according to item 14 of the scope of patent application, wherein each of the first input circuit and the second input circuit includes: a first inverter and a second inverter, the second inverter The input end of the commutator is coupled to the output end of the first inverter. The input end of the first inverter of the first input circuit receives the first latch data signal. An output terminal of the first inverter and an output terminal of the second inverter are coupled to the first output setting circuit, wherein the input terminal of the first inverter of the second input circuit receives the second latch data. The signal, the output terminal of the first inverter of the second input circuit and the output terminal of the second inverter are coupled to the second output setting circuit.

如申請專利範圍第15項所述的記憶體裝置，其中該第一輸出設定電路以及該第二輸出設定電路中的每一包括：一第一電晶體，其第一端接收該第一電壓；一第二電晶體，其第一端耦接至該第一電晶體的第二端，該第二電晶體的第二端接收該接地電壓；一第三電晶體，其第一端接收該第一電壓，該第三電晶體的控制端耦接至該第一電晶體的第二端，該第三電晶體的第二端耦接至該第一電晶體的控制端；一第四電晶體，其第一端耦接至該第三電晶體的第二端，該第四電晶體的第二端接收該接地電壓；一第五電晶體，其第一端接收該第一電壓，該第五電晶體的控制端耦接至該第三電晶體的第二端；以及一第六電晶體，其第一端耦接至該第五電晶體的第二端，該第六電晶體的控制端耦接至該第五電晶體的控制端，該第六電晶體的第二端接收該接地電壓，其中，該第一輸出設定電路中的第二電晶體的控制端以及第四電晶體的控制端耦接至該第一輸入電路，並且該第一輸出設定電路中的第五電晶體的第二端產生該第一輸出資料信號，其中，該第二輸出設定電路中的第二電晶體的控制端以及第四電晶體的控制端耦接至該第二輸入電路，並且該第二輸出設定電路中的第五電晶體的第二端產生該第二輸出資料信號。The memory device according to item 15 of the scope of patent application, wherein each of the first output setting circuit and the second output setting circuit includes: a first transistor having a first terminal receiving the first voltage; A second transistor having a first terminal coupled to a second terminal of the first transistor, a second terminal of the second transistor receiving the ground voltage, and a third transistor having a first terminal receiving the first transistor. A voltage, the control terminal of the third transistor is coupled to the second terminal of the first transistor, and the second terminal of the third transistor is coupled to the control terminal of the first transistor; a fourth transistor A first terminal thereof is coupled to a second terminal of the third transistor, a second terminal of the fourth transistor receives the ground voltage; a fifth transistor, a first terminal of which receives the first voltage, and the first terminal A control terminal of the five transistor is coupled to the second terminal of the third transistor; and A sixth transistor has a first terminal coupled to a second terminal of the fifth transistor, a control terminal of the sixth transistor coupled to a control terminal of the fifth transistor, and a first terminal of the sixth transistor. Two terminals receive the ground voltage, wherein the control terminal of the second transistor and the control terminal of the fourth transistor in the first output setting circuit are coupled to the first input circuit, and the The second terminal of the fifth transistor generates the first output data signal, wherein the control terminal of the second transistor and the control terminal of the fourth transistor in the second output setting circuit are coupled to the second input circuit, And the second terminal of the fifth transistor in the second output setting circuit generates the second output data signal.