TWI664713B - 半導體裝置以及功率放大器模組 - Google Patents

半導體裝置以及功率放大器模組 Download PDF

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TWI664713B
TWI664713B TW107105250A TW107105250A TWI664713B TW I664713 B TWI664713 B TW I664713B TW 107105250 A TW107105250 A TW 107105250A TW 107105250 A TW107105250 A TW 107105250A TW I664713 B TWI664713 B TW I664713B
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metal film
semiconductor device
film
metal
substrate
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TW107105250A
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TW201839957A (zh
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大部功
梅本康成
柴田雅博
那倉健一
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日商村田製作所股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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Abstract

本發明提供一種在使用了包含化合物半導體的基板的半導體裝置中，能夠抑制晶片面積的增大的半導體裝置。在包含化合物半導體的基板上形成電路元件。在電路元件上，接合焊墊被配置為與電路元件至少局部重疊。接合焊墊包含第1金屬膜以及形成於第1金屬膜上的第2金屬膜。第2金屬膜的金屬材料比第1金屬膜的金屬材料硬。

Description

半導體裝置以及功率放大器模組
本發明涉及半導體裝置以及功率放大器模組。
在下述的專利文獻1以及專利文獻2中，公開了使用異質結雙極電晶體(HBT)的高頻放大模組用的半導體裝置。在該半導體裝置設置有HBT保護用的保護電路。保護電路在靜電等的過電壓被施加於HBT的情況下，防止HBT的破壞。保護電路具有將複數個二極體串聯連接的電路結構，被連接於HBT的集電極與發射極之間。
在下述的專利文獻3中，公開了在佈線或者有源元件上形成有電極焊墊的半導體裝置。用於在接合時保護佈線或者有源元件的突起電極形成於電極焊墊(接合焊墊)的表面上。突起電極在將電極焊墊的表面上的Al置換為可與Ni產生置換反應的Zn之後，藉由在電極焊墊的表面對NiP進行非電解鍍而形成。記載了除了NiP，也可以使用能進行非電解鍍的Cu系金屬。
在先技術文獻
專利文獻
專利文獻1：JP特開2005-236259號公報
專利文獻2：國際公開第2001/018865號
專利文獻3：特開2000-164623號公報
在專利文獻1以及專利文獻2中公開的半導體裝置中，必須將用於配置構成保護電路的複數個二極體的區域確保在半導體基板上。因此，芯片面积变大。晶片面積的增大使得化合物半導體裝置的低成本化的實現變得困難。
如專利文獻3中公開的半導體裝置那樣，藉由在佈線或者有源元件上配置接合焊墊(bonding pad)，能夠抑制晶片面積的增大。雖在矽系半導體工藝中，對佈線、接合焊墊使用了Al，但在化合物半導體工藝中，通常對佈線、接合焊墊不使用Al。因此，難以將專利文獻3中公開的技術直接應用於化合物半導體製程。
本發明的目的在於，提供一種在使用了包含化合物半導體的基板的半導體裝置中，能夠抑制晶片面積的增大的半導體裝置。本發明的另一目的在於，提供一種使用了該半導體裝置的功率放大器模組。
基於本發明的第1觀點的半導體裝置具有：電路元件，形成在包含化合物半導體的基板上；和接合焊墊，在前述電路元件上，被配置為與前述電路元件至少局部重疊，前述接合焊墊包含第1金屬膜以及形成於前述第1金屬膜上的第2金屬膜，前述第2金屬膜的金屬材料的楊氏模量比前述第1金屬膜的金屬材料的楊氏模量大。
由於電路元件與接合焊墊被配置為局部重疊，因此不需要確保用於配置接合焊墊的專用區域。由此，能夠抑制晶片面積的增大。藉由第2金屬膜作為應力分散板而發揮作用，能夠使接合時在電路元件產生的應力分散， 抑制電路元件的破損。
基於本發明的第2觀點的半導體裝置除了基於第1觀點的半導體裝置的結構，還具有以下特徵：前述接合焊墊進一步包含形成於前述第2金屬膜上的第3金屬膜，前述第3金屬膜由與前述第1金屬膜相同的金屬材料形成。
作為第3金屬膜，能夠使用與接合線的接觸電阻低的金屬材料。與接合線直接接合於第2金屬膜的情況相比，能夠降低接合焊墊與接合線的接觸電阻。
基於本發明的第3觀點的半導體裝置除了基於第2觀點的半導體裝置的結構，還具有以下特徵：前述第1金屬膜以及前述第3金屬膜由Au形成，前述第2金屬膜具有包含至少1種金屬材料的層，前述至少1種金屬材料是選自於由Cu、Ni以及Mo所組成的群。
作為形成於化合物半導體基板上的複數個電路元件的連接用的佈線，能夠使用一般被利用的Au。由於Cu、Ni以及Mo比Au硬，因此第2金屬膜作為應力分散板而發揮作用。
基於本發明的第4觀點的半導體裝置除了基於第3觀點的半導體裝置的結構，還具有以下特徵：前述第2金屬膜具有包含至少2種金屬材料的2層，前述至少2種金屬材料是選自於由Cu、Ni以及Mo所組成的群。
藉由將複數個金屬材料組合，作為第2金屬膜的整體，也能夠提高硬度、電阻率等選擇的自由度。
基於本發明的第5至第7觀點的半導體裝置除了基於第2至第4觀點的半導體裝置的結構，還具有以下特徵：在前述第1金屬膜上進一步具有保護膜，前述保護膜具有在俯視情況下被配置於前述第1金屬膜的內側的開口，前述第2金屬膜以及前述第3金屬膜在俯視情況下被配置於前述開口的內 側。
接合時施加於第2金屬膜以及第3金屬膜的載荷不被傳遞到保護膜。因此，接合時保護膜難以損傷。
基於本發明的第8至第10觀點的半導體裝置除了基於第5至第7觀點的半導體裝置的結構，進一步具有第4金屬膜，前述第4金屬膜覆蓋前述開口的內側的前述第1金屬膜的上表面之中未被前述第2金屬膜覆蓋的區域、前述第2金屬膜的側面以及前述第3金屬膜的側面和上表面，並且由與前述第1金屬膜相同的金屬材料形成。
由於包含不同種類金屬的第2金屬膜與第3金屬膜的接合介面被第4金屬膜覆蓋，因此能夠抑制不同種類金屬接觸腐蝕的產生。
基於本發明的第11至第13觀點的半導體裝置除了基於第1至第3觀點的半導體裝置的結構，還具有以下特徵：前述基板的化合物半導體具有閃鋅礦型結晶構造，前述基板的上表面是從(100)面起的偏離角為4°以下的面，前述電路元件是選自於由異質結雙極電晶體、場效應電晶體、二極體、電容器以及電阻元件所組成的群的1個元件。
在將形成於具有閃鋅礦型結晶構造的化合物半導體基板上的異質結雙極電晶體、場效應電晶體、二極體、電容器以及電阻元件等的電路元件與接合焊墊重疊配置的結構中，能夠抑制這些電路元件的損傷。
基於本發明的第14以及第15觀點的半導體裝置除了基於第11以及第12觀點的半導體裝置的結構，還具有以下特徵：前述電路元件具有包含從前述基板外延生長的半導體層的檯面構造，前述檯面構造的上表面的平面形狀是包含與〔01-1〕方向平行的邊和與〔011〕方向平行的邊的長方形或者正方形，與〔011〕方向平行的邊比與〔01- 1〕方向平行的邊短。
若使用包含與〔01-1〕方向平行的邊和與〔011〕方向平行的邊的長方形或者正方形的蝕刻光罩，藉由濕式蝕刻來對半導體層進行各向異性蝕刻，則從與〔011〕方向平行的邊起進行側面蝕刻，形成簷狀的部分。這裡，所謂“各向異性蝕刻”，是指利用了基於結晶面的蝕刻速度的不同的蝕刻。該簷狀的部分由於接合時產生的應力而容易破損。由於與〔011〕方向平行的邊比與〔01-1〕方向平行的邊短，因此形成簷狀的部分的區域變窄。因此，能夠抑制接合時的破損。
基於本發明的第16以及第17觀點的半導體裝置除了基於第11以及第12觀點的半導體裝置的結構，還具有以下特徵：前述電路元件具有包含從前述基板外延生長的半導體層的檯面構造，前述檯面構造的上表面的平面形狀是包含與〔001〕方向平行的邊以及與〔010〕方向平行的邊的多邊形。
若使用包含與〔001〕方向平行的邊和與〔010〕方向平行的邊的多邊形的蝕刻光罩，藉由濕式蝕刻來對半導體層進行各向異性蝕刻，則與這些邊對應地形成幾乎垂直豎立的側面。由於未形成簷狀的部分，因此能夠抑制接合時的破損。
基於本發明的第18以及第19觀點的半導體裝置除了基於第16以及第17觀點的半導體裝置的結構，還具有以下特徵：前述檯面構造的上表面的平面形狀是還包含與〔01-1〕方向平行的邊的平行六邊形。
與平行於〔01-1〕方向的邊對應的側面緩慢傾斜。由於未形成簷狀的部分，因此能夠抑制接合時的破損。
基於本發明的第20觀點的功率放大器模組具有：半導體裝置，前述半導體裝置包含：具有形成於包含化合物半導體的基板上的異質結雙極電晶體的功率放大電路、連接在前述異質結雙極電晶體的發射 極-集電極間的保護電路、以及作為前述功率放大電路的輸出端子的接合焊墊，構成前述功率放大電路以及前述保護電路的至少1個電路元件與前述接合焊墊被配置為局部重疊，前述接合焊墊包含第1金屬膜和第2金屬膜的至少2層，前述第2金屬膜的金屬材料的楊氏模量比前述第1金屬膜的金屬材料的楊氏模量大；印刷佈線基板，安裝前述半導體裝置；以及接合線，與前述接合焊墊接合，將前述接合焊墊與前述印刷佈線基板的佈線連接。
由於至少一個電路元件與接合焊墊被局部重疊地配置，因此不需要確保用於配置接合焊墊的專用區域。由此，能夠抑制半導體裝置的晶片面積的增大。藉由第2金屬膜作為應力分散板而發揮作用，能夠使接合時在電路元件產生的應力分散，抑制電路元件的破損。
由於電路元件與接合焊墊被局部重疊地配置，因此不需要確保用於配置接合焊墊的專用區域。由此，能夠抑制晶片面積的增大。藉由第2金屬膜作為應力分散板而發揮作用，能夠使接合時在電路元件產生的應力分散，抑制電路元件的破損。
40‧‧‧基板
41‧‧‧異質結雙極電晶體(HBT)
42‧‧‧保護電路
43、44‧‧‧通孔
45‧‧‧背面電極
47‧‧‧二極體
70‧‧‧集電極電極
71‧‧‧基極電極
72‧‧‧發射極電極
73、74‧‧‧通孔用連接焊墊
80‧‧‧陰極電極
81‧‧‧陽極電極
83‧‧‧簷狀的部分
101‧‧‧緩衝層
102‧‧‧子集電極層
103‧‧‧集電極層
104‧‧‧基極層
105‧‧‧發射極層
106、107‧‧‧接觸層
108‧‧‧元件分離區域
109‧‧‧層間絕緣膜
110‧‧‧開口
111‧‧‧佈線
112、113‧‧‧層間絕緣膜
120‧‧‧接合焊墊用的第1金屬膜
121‧‧‧保護膜
122‧‧‧接合焊墊用的開口
127‧‧‧鍍覆用的種子電極層
130‧‧‧接合焊墊用的第2金屬膜
130A‧‧‧下側金屬膜
130B‧‧‧上側金屬膜
131‧‧‧接合焊墊用的第3金屬膜
132‧‧‧接合焊墊用的第4金屬膜
140‧‧‧接合焊墊
143‧‧‧基於比較例的半導體裝置的接合焊墊
150‧‧‧發射極區域
160‧‧‧抗蝕劑膜
161‧‧‧開口
163‧‧‧抗蝕劑膜
164‧‧‧開口
166‧‧‧蠟
167‧‧‧藍寶石基板
170‧‧‧抗蝕劑膜
171、172‧‧‧開口
200‧‧‧印刷佈線基板
201、202‧‧‧下墊板
203、204‧‧‧接合焊墊
221‧‧‧導電性粘接劑
225‧‧‧接合線
230‧‧‧矽半導體晶片
231‧‧‧導電性粘接劑
232‧‧‧接合焊墊
235‧‧‧接合線
240‧‧‧密封用固化樹脂
500‧‧‧半導體裝置
501‧‧‧信號輸入用的接合焊墊
502‧‧‧初級的HBT
503、504‧‧‧偏置電路
505‧‧‧接合線
506‧‧‧金屬球
510‧‧‧毛細管
511‧‧‧表示向第3金屬膜施加的應力的分佈的曲線
512‧‧‧表示向保護電路施加的應力的分佈的曲線
520‧‧‧輸入匹配電路
521‧‧‧輸入端子
522‧‧‧信號輸出用的接合焊墊
523‧‧‧接合線
540‧‧‧輸出匹配電路
541‧‧‧信號輸入用的接合焊墊
542‧‧‧輸出端子
圖1A是基於第1實施例的半導體裝置的一部分的俯視圖，圖1B以及圖1C分別是圖1A的一點鏈線1B-1B以及一點鏈線1C-1C處的剖視圖。
圖2是包含基於第1實施例的半導體裝置的功率放大器模組的等效電路圖。
圖3A以及圖3B是基於第1實施例的半導體裝置的接合焊墊的引線接合前以及引線接合中的示意性的剖視圖，圖3C以及圖3D是基於比較例的半導體裝置的 接合焊墊的引線接合前以及引線接合中的示意性的剖視圖。
圖4是表示各種金屬的維氏硬度、楊氏模量以及電阻率的圖表。
圖5是基於第2實施例的半導體裝置的剖視圖。
圖6是基於第3實施例的半導體裝置的剖視圖。
圖7A以及圖7B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖8A以及圖8B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖9A以及圖9B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖10A以及圖10B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖11A以及圖11B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖12A以及圖12B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖13A以及圖13B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖14A以及圖14B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖15A以及圖15B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖16A以及圖16B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖17A以及圖17B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖18A以及圖18B是基於第3實施例的半導體裝置的製造中途階段的剖視 圖。
圖19A以及圖19B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖20A以及圖20B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖21A以及圖21B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖22A以及圖22B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖23A以及圖23B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖24A以及圖24B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖25A以及圖25B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖26A以及圖26B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖27A以及圖27B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖28A以及圖28B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖29A以及圖29B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖30A以及圖30B是基於第3實施例的半導體裝置的製造中途階段的剖視 圖。
圖31A以及圖31B是基於第3實施例的半導體裝置的製造中途階段的剖視圖。
圖32A是基於第4實施例的半導體裝置的剖視圖，圖32B以及圖32C分別是基於第4實施例的變形例的半導體裝置的剖視圖。
圖33A是在上表面為(100)面的GaAs基板藉由各向異性蝕刻而形成的正八邊形的檯面的俯視圖，圖33B、圖33C、圖33D以及圖33E分別是圖33A的一點鏈線33B-33B、33C-33C、33D-33D以及33E-33E處的剖視圖。
圖34A是基於第5實施例的半導體裝置的1個二極體的俯視圖，圖34B以及圖34C分別是圖34A的一點鏈線34B-34B以及一點鏈線34C-34C處的剖視圖。
圖35A是基於第6實施例的半導體裝置的1個二極體的俯視圖，圖35B以及圖35C分別是圖35A的一點鏈線35B-35B以及一點鏈線35C-35C處的剖視圖。
圖36A是基於第7實施例的半導體裝置的1個二極體的俯視圖，圖36B是圖36A的一點鏈線36B-36B處的剖視圖。
圖37是基於第8實施例的功率放大器模組的剖視圖。
〔第1實施例〕
參照圖1A至圖4的附圖，對基於第1實施例的半導體裝置進行說明。圖1A是基於第1實施例的半導體裝置的一部分的俯視圖。在包含半絕緣性的GaAs的基板40上，形成異質結雙極電晶體(HBT)41、保護電路42等的電路元件。複數個接合焊墊140被配置為與構成保護電路42的電路元件局部重疊。
圖1B是圖1A的一點鏈線1B-1B處的剖視圖。在基板40上依次層 疊緩衝層101、子集電極層102、集電極層103、基極層104、發射極層105、接觸層106、107。緩衝層101由非摻雜的GaAs形成，子集電極層102以及集電極層103由n型的GaAs形成。基极层104由p型的GaAs形成。发射极层105由n型的InGaP形成。接觸層106、107分別由n型的GaAs以及n型的InGaAs形成。
藉由向緩衝層101以及子集電極層102的一部分的區域注入硼(B)，來形成元件分離區域108。包含子集電極層102、集電極層103、基極層104以及發射極層105的HBT41形成在基板40上。在子集電極層102上形成集電極電極70，集電極電極70與子集電極層102歐姆連接。形成在發射極層105上的基極電極71貫通發射極層105並與基極層104歐姆連接。形成在接觸層107上的發射極電極72與接觸層107歐姆連接。
在HBT41的側向的元件分離區域108上，形成通孔用連接焊墊73。在基板40的整個區域形成層間絕緣膜109，以覆蓋HBT41、通孔用連接焊墊73。對層間絕緣膜109例如使用氮化矽(SiN)。在層間絕緣膜109的規定的位置、例如配置有集電極電極70、基極電極71、發射極電極72、通孔用連接焊墊73的位置形成複數個接觸孔。
形成在層間絕緣膜109上的佈線111將發射極電極72和通孔用連接焊墊73連接。進一步地，其他複數個佈線111連接於集電極電極70、基極電極71。
在基板40的整個區域形成層間絕緣膜112以覆蓋佈線111，在其上方進一步形成上側的層間絕緣膜113。對層間絕緣膜112例如使用SiN，對上側的層間絕緣膜113使用聚醯亞胺。在層間絕緣膜113上形成保護膜121。對保護膜121例如使用SiN。
從基板40的背面向通孔用連接焊墊73形成通孔43。形成於基板40的背面的背面電極45通過通孔43內而與通孔用連接焊墊73連接。
圖1C是圖1A的一點鏈線1C-1C處的剖視圖。在基板40上，形成利用了集電極層103與基極層104的pn結的複數個二極體47。藉由將複數個二極體47串聯連接來構成保護電路42(圖1A)。
形成於二極體47的各自的子集電極層102上的陰極電極80與子集電極層102歐姆連接。形成於二極體47的各自的發射極層105上的陽極電極81貫通發射極層105而與基極層104歐姆連接。在1個二極體47的側向的元件分離區域108上形成通孔用連接焊墊74。
在基板40的整個區域形成層間絕緣膜109，以覆蓋二極體47以及通孔用連接焊墊74。在層間絕緣膜109的規定的位置、例如配置有陰極電極80、陽極電極81、通孔用連接焊墊74的位置，形成接觸孔。藉由形成於層間絕緣膜109上的複數個佈線111將複數個二極體47的陰極電極80和陽極電極81連接，從而將複數個二極體47串聯連接。其他佈線111將包含複數個二極體47的串聯電路的端部的陰極電極80和通孔用連接焊墊74連接。包含複數個二極體47的串聯電路的端部的陽極電極81藉由其他佈線111而與HBT41(圖1B)的集電極電極70連接。
在基板40的整個區域形成層間絕緣膜112以覆蓋佈線111。在層間絕緣膜112上形成接合焊墊用的第1金屬膜120。第1金屬膜120被配置於與複數個二極體47部分重疊的位置。
在第1金屬膜120以及層間絕緣膜112上形成保護膜121。在保護膜121形成接合用的複數個開口122。該複數個開口122被配置於俯視情況下第1金屬膜120的內側、並且與複數個二極體47部分重疊的位置。
形成鍍覆用的種子電極層127以覆蓋開口122的底面以及側面。種子電極層127擴展到保護膜121的上表面的包圍開口122的邊框狀的區域。在種子電極層127上依次層疊接合焊墊用的第2金屬膜130以及第3金屬膜131。由 第1金屬膜120、第2金屬膜130以及第3金屬膜131構成接合焊墊140。
第2金屬膜130的金屬材料比第1金屬膜120的金屬材料硬。金屬材料的硬度例如能夠由維氏硬度、楊氏模量等定義。第3金屬膜131由與第1金屬膜120相同的金屬材料形成。例如，第1金屬膜120以及第3金屬膜131由金(Au)形成，第2金屬膜130由銅(Cu)形成。
形成從基板40的背面達到至通孔用連接焊墊74的通孔44。形成於基板40的背面的背面電極45通過通孔44內而與通孔用連接焊墊74連接。
圖2是包含基於第1實施例的半導體裝置的功率放大器模組的等效電路圖。該功率放大器模組包含：輸入匹配電路520、半導體裝置500以及輸出匹配電路540。
半導體裝置500包含構成功率放大電路的初級的HBT502以及輸出級的HBT41。輸入信號被輸入到信號輸入用的接合焊墊501。輸入信號被輸入到初級的HBT502的基極電極。初級的HBT502的輸出被輸入到輸出級的HBT41的基極電極71(圖1B)。
偏置電路503、504分別向初級的HBT502以及輸出級的HBT41提供偏置電流。在輸出級的HBT41的集電極-發射極之間連接保護電路42。保護電路42包含串聯連接的複數個、例如10個二極體47。輸出級的HBT41的集電極與作為輸出端子的複數個接合焊墊140連接。
向輸入匹配電路520的輸入端子521輸入高頻信號。輸入匹配電路520的信號輸出用的接合焊墊522藉由接合線523而與半導體裝置500的信號輸入用的接合焊墊501連接。
半導體裝置500的信號輸出用的複數個接合焊墊140分別藉由複數個接合線505而與輸出匹配電路540的信號輸入用的複數個接合焊墊541連接。被輸入到輸入匹配電路520的輸入端子521的高頻信號經由輸入匹配電路 520，被半導體裝置500放大，經由輸出匹配電路540而被輸出到輸出端子542。
〔第1實施例的效果〕
接下來，對第1實施例的優良效果進行說明。
在第1實施例中，保護電路42(圖1A)具有保護HBT41(圖1B)使其免於靜電破壞、過電壓破壞、負載變動破壞的功能。此外，在第1實施例中，由於該保護電路42(圖1A)與接合焊墊140被部分重疊地配置，因此不需要確保用於配置接合焊墊140的專用的區域。由此，能夠抑制晶片面積的增大。
接下來，參照從圖3A至圖3D的附圖，對第1實施例的其他效果進行說明。圖3A以及圖3B是基於第1實施例的半導體裝置的接合焊墊140的引線接合前以及引線接合中的示意性的剖視圖。
在毛細管510支承接合線505。作為接合線505，例如使用金(Au)線。在接合線505的前端形成金屬球506。若將毛細管510向接合焊墊140按壓並施加熱量或者超聲波，則接合焊墊140的第3金屬膜131以及金屬球506變形並且兩者接合。在第3金屬膜131，沿著金屬球506的外周產生相對較大的應力。以曲線511來表示向第3金屬膜131施加的應力的分佈。
在第3金屬膜131產生的應力透過相對較硬的第2金屬膜130而被傳遞到保護電路42。藉由第2金屬膜130作為應力分散板而發揮作用，從而在比第2金屬膜130更靠下方的保護電路42產生的應力的分佈變得比在第3金屬膜131產生的應力的分佈平緩。以曲線512來表示在保護電路42產生的應力的分佈。
圖3C以及圖3D是基於比較例的半導體裝置的接合焊墊143的引線接合前以及引線接合中的示意性的剖視圖。在比較例中，接合焊墊143由包含與第1金屬膜120以及第3金屬膜131(圖3A、圖3B)相同的金屬材料的單一的金屬膜形成。由於接合焊墊143比第2金屬膜130(圖3A、圖3B)柔軟，因此使 應力分散的功能較弱。因此，如曲線512所示，沿著金屬球506的外周，在保護電路42產生較大的應力。在產生較大的應力的位置，在構成保護電路42的電路元件容易產生損傷。
在第1實施例中，由於接合焊墊140的第2金屬膜130作為應力分散板而發揮作用，因此在接合時，在保護電路42難以產生損傷。進一步地，由於作為第3金屬膜131，使用比第2金屬膜130柔軟的金屬材料，因此能夠確保接合線505與接合焊墊140的良好的電連接。
從得到穩定的接觸介面的觀點出發，較佳為對第1金屬膜120使用與其方的佈線111(圖1B、圖1C)相同的金屬材料。在由化合物半導體形成電路元件的情況下，一般對佈線111使用Au。因此，較佳為對第1金屬膜120使用Au。
接下來，參照圖4，說明對於接合焊墊140的第2金屬膜130較佳的金屬材料。第2金屬膜130為了提高作為應力分散板的效果，較佳為使用比第1金屬膜120硬的金屬材料。這裡，所謂“硬”，是指維氏硬度高、或者楊氏模量大。進一步地，從第2金屬膜130構成接合焊墊140的一部分的觀點出發，較佳為使用電阻率較低的金屬材料。
圖4是表示各種金屬的維氏硬度、楊氏模量以及電阻率的圖表。圖4所示出的維氏硬度是在全部金屬中以相同的試驗力測定得出的值。
在對第1金屬膜120使用Au的情況下，較佳為對第2金屬膜130使用維氏硬度或者楊氏模量比金(Au)高的金屬材料。作為一個例子，較佳為對第2金屬膜130使用具有比30HV高的維氏硬度的金屬材料或者具有比90GPa大的楊氏模量的金屬材料。作為維氏硬度或者楊氏模量比Au高並且電阻率並不明顯高的金屬材料，舉例：銅(Cu)、鎳(Ni)、鉬(Mo)。較佳為對第2金屬膜130使用Cu、Ni或者Mo。
在接合焊墊140對於使應力分散而足夠厚的情況下，***較硬的第2金屬膜130(圖1C)的效果較低。在接合焊墊140的厚度為10μm以下的情況下，可得到***第2金屬膜130的顯著的效果。
〔第1實施例的變形例〕
在第1實施例中，接合焊墊140(圖1A)與構成保護電路42的二極體47(圖1C)局部重疊。此外，也可以設為接合焊墊140與HBT41(圖1A、圖1B)重疊的構成。在基板40(圖1B、圖1C)上，如圖2所示那樣形成電容器、電阻元件等的電路元件。也可以設為將接合焊墊140與這些電路元件局部重疊的構成。也可能在包含化合物半導體的基板40上，形成HBT以外的有源元件、例如高電子遷移率電晶體(HEMT)、MES型場效應電晶體(MESFET)等的場效應電晶體。也可以設為將接合焊墊140與使用了化合物半導體的這些有源元件局部重疊的構成。
雖在圖1A中，表示了接合焊墊140的個數是3個的例子，但接合焊墊140的個數並不局限於3個。配置1個以上的接合焊墊140即可。雖在圖2中，表示了輸出級的HBT41是1個的例子，但一般藉由並聯連接的複數個HBT構成輸出級。
也可以在包含Cu的第2金屬膜130(圖1C)與包含Au的第3金屬膜131(圖1C)的介面，配置擴散防止膜。作為擴散防止膜，能夠使用TiW、Ni等。
雖在第1實施例中，作為基板40，使用了GaAs基板，但也可以使用其他的化合物半導體基板。例如，也可以作為基板40，使用InP基板。
雖在第1實施例中，作為一個例子，將第1金屬膜120與第2金屬膜130設為相同的厚度，但較佳為使第2金屬膜130的厚度為第1金屬膜120的厚 度以上。藉由使第2金屬膜130較厚，能夠提高第2金屬膜130的作為應力分散板的功能。
〔第2實施例〕
接下來，參照圖5，對基於第2實施例的半導體裝置進行說明。以下，針對與基於第1實施例的半導體裝置的構成共通的構成，省略說明。
圖5是基於第2實施例的半導體裝置的剖視圖。在第1實施例中，如圖1C所示，接合焊墊140的第2金屬膜130以及第3金屬膜131擴展到開口122的邊緣的外側，其外周部分與保護膜121重疊。與此相對地，在第2實施例中，第2金屬膜130以及第3金屬膜131在俯視情況下被配置於開口122的內側。即，第2金屬膜130以及第3金屬膜131與保護膜121不重疊。另外，種子電極層127也在俯視情況下被配置於開口122的內側。
在第2實施例中，即使在接合時向接合焊墊140的第2金屬膜130以及第3金屬膜131施加載荷，也不向保護膜121施加載荷。因此，能夠減少接合時向保護膜121施加的機械應力。其結果，能夠抑制向保護膜121的裂縫的產生。
〔第3實施例〕
接下來，參照圖6，對基於第3實施例的半導體裝置進行說明。以下，針對與基於第2實施例的半導體裝置的構成共通的構成，省略說明。
圖6是基於第3實施例的半導體裝置的剖視圖。在第2實施例中，是包含接合焊墊140的種子電極層127、第2金屬膜130以及第3金屬膜131(圖5)的多層構造的側面以及上表面露出的狀態。在第3實施例中，包含種子電極層127、第2金屬膜130以及第3金屬膜131的多層構造的側面以及上表面被第4金 屬膜132覆蓋。第4金屬膜132進一步覆蓋開口122內的第1金屬膜120的上表面之中未形成種子電極層127的區域。對第4金屬膜132例如使用與第3金屬膜131相同的金屬材料。
在第3實施例中，第2金屬膜130與第3金屬膜131的不同種類金屬的接觸面不露出。因此，特別是能夠抑制高濕度環境下的不同種類金屬接觸腐蝕。
接下來，參照圖7A、圖7B至圖30A、圖30B的附圖，對基於第3實施例的半導體裝置的製造方法進行說明。基於第3實施例的半導體裝置的製造方法也能夠應用於基於第1實施例以及第2實施例的半導體裝置的製造。
圖7A、圖7B至圖30A、圖30B的附圖是基於第3實施例的半導體裝置的製造中途階段的剖視圖。圖7A、圖7B至圖30A、圖30B的附圖之中，在末尾附上A的附圖對應於圖1A的一點鏈線1B-1B處的剖視圖，在末尾附上B的附圖對應於圖1A的一點鏈線1C-1C處的剖視圖。
如圖7A以及圖7B所示，在包含半絕緣性的GaAs的基板40上，使緩衝層101、子集電極層102、集電極層103、基極層104、發射極層105、接觸層106、107依次外延生長。對這些半導體層的形成，例如能夠使用有機金屬氣相外延(MOVPE)法。基板40的上表面是從(100)面起的偏離角為4°以下的面。
接下來，對從緩衝層101到接觸層107的各半導體層的材料、摻雜濃度以及膜厚的一個例子進行說明。緩衝層101由非摻雜的GaAs形成，其膜厚為0.1μm。子集電極層102由n型GaAs形成，作為n型摻雜劑的Si的摻雜濃度為5×1018cm-3，膜厚為0.6μm。集電極層103由n型GaAs形成，Si的摻雜濃度為1×1016cm-3，膜厚為1.0μm。基極層104由p型GaAs形成，作為p型摻雜劑的C的摻雜濃度為5×1019cm-3，膜厚為96nm。發射極層105由n型InGaP形成，InP的摩 爾比為0.48，Si的摻雜濃度為4×1017cm-3，膜厚為35nm。接觸層106由n型GaAs形成，Si的摻雜濃度為5×1018cm-3，膜厚為50nm。上側的接觸層107由n型InGaAs形成，InAs的摩爾比為0.5，Si的摻雜濃度為1×1019cm-3，膜厚為50nm。
如圖8A所示，在接觸層107的規定的區域上形成發射極電極72。在圖8B所示的剖面，未配置發射極電極72。發射極電極72具有從基板40側起依次層疊厚度10nm的Mo膜、厚度5nm的Ti膜、厚度30nm的Pt膜以及厚度200nm的Au膜的4層構造。發射極電極72能夠藉由蒸鍍以及剝離法來形成。
如圖9A所示，藉由將接觸層107、106加工為規定的形狀，形成發射極區域150。在發射極區域150上配置發射極電極72。在圖9B所示的剖面，接觸層107、106被除去，發射極層105露出。接觸層107、106的加工中，能夠應用光刻以及濕式蝕刻。對該濕式蝕刻，例如能夠使用將磷酸、雙氧水以及水混合而成的蝕刻液。作為一個例子，能夠使用將濃度85重量%的磷酸、濃度35重量%的雙氧水和水以體積比1：2：40的比例進行混合而成的蝕刻液。該蝕刻液具有不實質地蝕刻包含InGaP的發射極層105而選擇性地蝕刻包含GaAs的接觸層107、106的選擇性。
如圖10A所示，在發射極區域150的兩側形成基極電極71。基極電極71在應用光刻、蒸鍍以及剝離法在發射極層105上形成金屬膜之後，藉由進行燒結，貫通發射極層105並與基極層104歐姆連接。用於形成基極電極71的金屬膜包含從基板40側起依次被層疊的厚度30nm的Pt膜、厚度50nm的Ti膜、厚度50nm的Pt膜以及厚度200nm的Au膜。
如圖10B所示，基極電極71(圖10A)的形成的同時，形成複數個陽極電極81。陽極電極81也貫通發射極層105並與基極層104歐姆連接。
如圖11A以及圖11B所示，藉由光刻以及濕式蝕刻來除去發射極層105的不必要的部分。由此，基極層104露出。作為蝕刻液，例如能夠使用鹽 酸。鹽酸具有不實質地蝕刻包含GaAs的基極層104而選擇性地蝕刻包含InGaP的發射極層105的選擇性。
如圖12A以及圖12B所示，使用對發射極層105進行蝕刻時的蝕刻光罩，除去基極層104以及集電極層103的不必要的部分。由此，子集電極層102露出。對基極層104以及集電極層103的蝕刻，能夠使用與對接觸層107、106(圖9A、圖9B)的蝕刻使用的蝕刻液相同的蝕刻液。蝕刻的停止藉由時間控制來進行。
如圖13A以及圖13B所示，形成用於確保元件間的電絕緣的元件分離區域108。元件分離區域108例如能夠藉由向子集電極層102以及緩衝層101離子注入硼而形成。
如圖14A以及圖14B所示，在HBT41(圖1B)的子集電極層102上形成集電極電極70的同時在二極體47(圖1B)的子集電極層102上形成陰極電極80。進一步地，在元件分離區域108上形成通孔用連接焊墊73、74。對集電極電極70、陰極電極80以及通孔用連接焊墊73、74的形成能夠應用光刻、蒸鍍以及剝離法。集電極電極70、陰極電極80以及通孔用連接焊墊73、74包含從基板40側起依次被層疊的厚度60nm的AuGe膜、厚度10nm的Ni膜以及厚度200nm的Au膜。
如圖15A以及圖15B所示，使層間絕緣膜109堆積於基板40的整個區域，以覆蓋HBT41、二極體47、通孔用連接焊墊73、74。層間絕緣膜109例如由SiN形成，厚度為100nm。對於層間絕緣膜109的堆積，例如能夠應用化學氣相生長(CVD)法。
如圖16A以及圖16B所示，在層間絕緣膜109的規定的位置形成複數個開口110。複數個開口110分別在俯視情況下被配置於集電極電極70、基極電極71、發射極電極72、陰極電極80、陽極電極81以及通孔用連接焊墊73、 74的內側，使這些部分的上表面的一部分的區域露出。對於開口110的形成，能夠應用光刻以及乾式蝕刻。
如圖17A以及圖17B所示，在層間絕緣膜109上形成複數個佈線111。佈線111例如由Au形成，其厚度為1μm。對於佈線111的形成，能夠應用光刻、蒸鍍以及剝離法。一個佈線111將發射極電極72與通孔用連接焊墊73連接。另一個佈線將1個二極體47的陰極電極80與通孔用連接焊墊74連接。另一個佈線111將二極體47的陽極電極81與和其相鄰的二極體47的陰極電極80連接。進一步地，在基極電極71以及集電極電極70也分別連接佈線111。
如圖18A所示，在基板40的整個區域形成層間絕緣膜112，以覆蓋佈線111。層間絕緣膜112例如由SiN形成。進一步地，在層間絕緣膜112上形成層間絕緣膜113。層間絕緣膜113例如藉由塗敷聚醯亞胺並形成厚度1.8μm的聚醯亞胺膜後，進行表面的平坦化而形成。然後，除去配置接合焊墊140(圖1A、圖6)的區域的層間絕緣膜113。在圖18B所示的剖面，層間絕緣膜113被除去，包含SiN的層間絕緣膜112露出。
如圖19B所示，在層間絕緣膜112上形成第1金屬膜120。第1金屬膜120配置為與複數個二極體47局部重疊。在圖19A所示的剖面內，不形成第1金屬膜120。第1金属膜120例如由Au形成，其厚度為2μm。對於第1金屬膜120的形成，例如能夠應用光刻、蒸鍍以及剝離法。第1金屬膜120的形成的同時，在基板40的其他區域形成第2層的佈線。
在基板40的整個區域形成包含SiN的保護膜121，以覆蓋圖19B所示的第1金屬膜120。在圖19A所示的剖面，在層間絕緣膜113上形成保護膜121。保護膜121的厚度例如為500nm。對於保護膜121的形成，例如能夠應用CVD法。
在保護膜121上形成抗蝕劑膜160，在應形成接合焊墊140(圖 1A、圖6)的區域形成開口161。
如圖20A以及圖20B所示，藉由將抗蝕劑膜160作為蝕刻光罩來對保護膜121進行蝕刻，從而在保護膜121形成開口122。第1金屬膜120在開口122的內側露出。對於保護膜121的蝕刻，例如能夠應用乾式蝕刻。在保護膜121形成開口122後，除去抗蝕劑膜160。
如圖21A以及圖21B所示，在基板40的整個區域形成鍍覆用的種子電極層127，以覆蓋保護膜121的上表面、開口122的側面以及底面。種子電極層127例如包含厚度0.1μm的TiW膜和厚度0.1μm的Cu膜的2層。對於種子電極層127的形成，例如能夠應用濺射法。
如圖22A以及圖22B所示，在種子電極層127上形成抗蝕劑膜163。藉由光刻，在應形成第2金屬膜130以及第3金屬膜131(圖6)的區域形成開口164。在開口164內，種子電極層127露出。
如圖23A以及圖23B所示，在開口164內的種子電極層127上，藉由電解鍍來使第2金屬膜130以及第3金屬膜131依次堆積。第2金屬膜130例如由Cu形成，其厚度為2μm。第3金属膜131例如由Au形成，其厚度為1μm。第3金属膜131的上表面比抗蚀剂膜163的上表面低。在形成第2金屬膜130以及第3金屬膜131之後，除去抗蝕劑膜163。
如圖24A以及圖24B所示，對未形成第2金屬膜130的區域的露出的種子電極層127進行蝕刻除去。保護膜121在圖24A的剖面露出，在圖24B的剖面，第1金屬膜120在保護膜121以及形成於保護膜121的開口122內露出。
如圖25B所示，在包含種子電極層127、第2金屬膜130以及第3金屬膜131的層疊構造的側面和上表面、以及在開口122內露出的第1金屬膜120的上表面，形成第4金屬膜132。對於第4金屬膜132的形成，例如能夠應用非電解鍍。第4金屬膜132例如由Au形成，其厚度為0.1μm。在圖25A以及圖25B所示 的保護膜121的上表面不堆積Au。
如圖26A以及圖26B所示，使基板40的表側的面(形成有保護膜121的面)與藍寶石基板167對置，隔著蠟166而將基板40與藍寶石基板167粘貼。
如圖27A以及圖27B所示，藉由從背側對基板40進行研削，使其薄層化到厚度75μm。
如圖28A以及圖28B所示，在被薄層化的基板40的背側的表面形成抗蝕劑膜170。藉由光刻，在抗蝕劑膜170形成開口171、172。開口171、172分別形成于與通孔用連接焊墊73、74對應的位置。
如圖29A以及圖29B所示，將抗蝕劑膜170作為蝕刻光罩，對基板40以及元件分離區域108進行蝕刻。由此，形成貫通基板40以及元件分離區域108的通孔43、44，在其底面，分別露出通孔用連接焊墊73、74。對於基板40以及元件分離區域108的蝕刻，能夠應用各向異性乾式蝕刻。在通孔用連接焊墊73、74露出後，除去抗蝕劑膜170。
如圖30A以及圖30B所示，在基板40的被側的表面以及通孔43、44的側面以及底面形成背面電極45。背面電極45能夠藉由利用非電解鍍來使鈀堆積之後，利用電解鍍來使Au堆積而形成。背面电极45的厚度為4μm。在形成背面電極45之後，從基板40取下蠟166以及藍寶石基板167。
如圖31A以及圖31B所示，接合焊墊140的表層的第4金屬膜132以及保護膜121露出。然後，藉由進行切割等來按照每個晶片進行分離，從而半導體裝置完成。
〔第4實施例〕
接下來，參照圖32A，對基於第4實施例的半導體裝置進行說明。以下，針 對與參照圖1A至圖4的附圖而說明的第1實施例共通的構成，省略說明。
圖32A是基於第4實施例的半導體裝置的剖視圖。在第1實施例中，構成接合焊墊140的第2金屬膜130(圖1C)由包含比第1金屬膜120硬的金屬材料的單層構成。在第4實施例中，第2金屬膜130具有包含不同的金屬材料的下側金屬膜130A以及上側金屬膜130B的2層構造。下側金屬膜130A以及上側金屬膜130B均由比第1金屬膜120硬的金屬材料形成。
例如，作為下側金屬膜130A以及上側金屬膜130B，較佳為使用選自於由Cu、Ni、Mo這3種金屬所組成的群的2種金屬。
接下來，參照圖32B以及圖32C，對基於第4實施例的變形例的半導體裝置進行說明。
圖32B以及圖32C分別是基於第4實施例的變形例的半導體裝置的剖視圖。在圖32B所示的變形例中，與基於第2實施例的半導體裝置的接合焊墊140(圖5)同樣地，第2金屬膜130以及第3金屬膜131被配置於在保護膜121設置的開口122的內側。在圖32C所示的變形例中，與基於第3實施例的半導體裝置的接合焊墊140(圖6)同樣地，包含第2金屬膜130以及第3金屬膜131的層疊構造、以及該層疊構造的周圍的第1金屬膜120的上表面被第4金屬膜132覆蓋。在圖32B以及圖32C所示的變形例中，第2金屬膜130也包含下側金屬膜130A和上側金屬膜130B這2層。
在第4實施例以及第4實施例的變形例中，能夠將第2金屬膜130作為整體來設為所希望的硬度，並且將複數個材料組合以抑制電阻率的增加。其結果，可提供一種可靠性更高的半導體裝置。
〔第5實施例〕
接下來，參照圖33A至圖34C的附圖，對基於第5實施例的半導體裝置進行 說明。以下，針對與第1實施例至第4實施例的各實施例共通的構成，省略說明。在第1實施例至第4實施例的各實施例中，未限定基板40(圖1B、圖1C等)的上表面的面指數、二極體47(圖1C等)的各半導體層的圖案的平面形狀以及取向。在第5實施例中，基板40的上表面的面指數被確定，半導體層的圖案的平面形狀以及較佳的取向被限定。
首先，參照圖33A至圖33E的附圖，對基於濕式蝕刻的各向異性蝕刻特性進行說明。
圖33A是在上表面為(100)面的GaAs基板藉由各向異性蝕刻而形成的正八邊形的檯面的俯視圖。正八邊形的1個邊與〔011〕方向平行。圖33B、圖33C、圖33D以及圖33E分別是圖33A的一點鏈線33B-33B、一點鏈線33C-33C、一點鏈線33D-33D以及一點鏈線33E-33E處的剖視圖。作為進行各向異性蝕刻的蝕刻液，能夠使用弱酸性或者弱鹼性的蝕刻液。
在圖33B所示的剖面，在朝向〔01-1〕方向的側面以及朝向其相反方向的側面容易形成出現了(111)A面的反檯面狀的部分。例如，檯面構造的上層部分為反檯面狀，下層部分為正檯面狀。在反檯面狀的部分，形成在橫向突出的簷狀的部分。這裡，對米勒指數的各要素付與的負號表示對該要素付與了上橫線。在圖33C所示的剖面，在朝向〔0-1-1〕方向的側面以及朝向其相反方向的側面容易出現(111)B面，側面為平緩的斜面。在圖33D以及圖33E所示的剖面，朝向〔00-1〕方向的側面以及朝向其相反方向的側面、朝向〔0-10〕方向的側面以及朝向其相反方向的側面為幾乎垂直豎立的形狀。
圖33B至圖33E的各圖中所示的各向異性蝕刻特性與對在上表面為(100)面的GaAs基板上外延生長的化合物半導體進行各向異性蝕刻時的特性相同。此外，除了GaAs基板，對在具有閃鋅礦型結晶構造的化合物半導體基板以及其上外延生長的化合物半導體層進行各向異性蝕刻的情況下，也可得到 相同的特性。
圖34A是基於第5實施例的半導體裝置的1個二極體47的俯視圖。圖34B以及圖34C分別是圖34A的一點鏈線34B-34B以及一點鏈線34C-34C處的剖視圖。基板40的上表面的面指數為(100)。另外，也可以使用上表面是從(100)面起的偏離角為4°以下的結晶面的基板。
在由元件分離區域108包圍的子集電極層102上，層疊集電極層103、基極層104以及發射極層105。俯視情況下，發射極層105被配置於集電極層103的內側。形成於子集電極層102上的陰極電極80將集電極層103從〔011〕方向、〔0-11〕方向以及〔0-1-1〕方向這三個方向包圍。形成於發射極層105上的陽極電極81貫通發射極層105並與基極層104歐姆連接。
複數個二極體47(圖1C)與〔01-1〕方向平行地排列。該排列方向相當於包含GaAs的基板40的容易裂開方向。換言之，複數個二極體47在與容易裂開方向平行的方向上排列。
發射極層105、基極層104以及集電極層103藉由使用相同的蝕刻光罩來進行各向異性蝕刻而被圖案化(參照圖11B以及圖12B)。該蝕刻光罩的平面形狀是長方形，長邊與〔01-1〕方向平行，短邊與〔011〕方向平行。
如圖34B所示，在相對於〔0-1-1〕方向垂直的剖面，包含集電極層103、基極層104以及發射極層105的檯面的上層部分為反檯面狀，形成簷狀的部分83。圖34A所示的發射極層105相當於上表面的外周線。
如圖34C所示，在相對於〔0-11〕方向垂直的剖面，包含集電極層103、基極層104以及發射極層105的檯面為正檯面狀，形成平緩的斜面。圖34A所示的集電極層103表示底面的外周線。
接下來，對第5實施例的優良效果進行說明。若在接合時對二極體47施加載荷，則在簷狀的部分83容易產生破損。在第5實施例中，發射極層 105的外周線(圖34A)之中，與形成簷狀的部分83的〔011〕方向平行的邊比與形成平緩的斜面的〔01-1〕方向平行的邊短。這樣，形成簷狀的部分83的區域被限定於較窄的範圍。因此，難以產生基於接合時的載荷的破損。
雖在圖34A至圖34C的附圖中，表示了陽極電極81貫通發射極層105並與基極層104歐姆連接的例子，但也可以除去發射極層105而將陽極電極81直接形成於基極層104上。在該情況下，由基極層104和集電極層103的上層部分形成簷狀的部分83。
為了提高抑制簷狀的部分83的破損的效果，較佳為使配置有陽極電極81的檯面狀部分的上表面的短邊的長度為長邊的長度的1/2以下。
〔第6實施例〕
接下來，參照圖35A至圖35C的附圖，對基於第6實施例的半導體裝置進行說明。以下，針對與基於第5實施例的半導體裝置共通的構成，省略說明。
圖35A是基於第6實施例的半導體裝置的1個二極體47的俯視圖。圖35B以及圖35C分別是圖35A的一點鏈線35B-35B以及一點鏈線35C-35C處的剖視圖。在第5實施例中，發射極層105以及集電極層103(圖34A)的平面形狀為長方形。在第6實施例中，發射極層105以及集電極層103的平面形狀為包含與〔01-1〕方向平行的邊、與〔001〕方向平行的邊以及與〔010〕方向平行的邊的多邊形，例如平行六邊形。
如圖35B所示，在相對於與〔01-1〕方向平行的邊垂直交叉的剖面，包含集電極層103、基極層104以及發射極層105的檯面的形狀與圖34C所示的第5實施例的剖面同樣地，為正檯面狀。如圖35A所示，集電極層103的底面比發射極層105的底面更向〔011〕方向以及〔0-1-1〕方向擴展。
如圖35C所示，在與平行於〔010〕方向的邊交叉的剖面，包含 集電極層103、基極層104以及發射極層105的檯面的側面為垂直豎立的形狀。在與平行於〔001〕方向的邊交叉的剖面也相同。
在第6實施例中，在包含二極體47的集電極層103、基極層104以及發射極層105的檯面不形成簷狀的部分。因此，可得到難以產生基於接合時的載荷的破損的效果。
〔第7實施例〕
接下來，參照圖36A以及圖36B，對基於第7實施例的半導體裝置進行說明。以下，針對與基於第6實施例的半導體裝置共通的構成，省略說明。
圖36A是基於第7實施例的半導體裝置的1個二極體47的俯視圖。雖在第6實施例中，發射極層105的平面形狀為平行六邊形(圖35A)，但在第7實施例中，是具有與〔010〕方向平行的邊以及與〔001〕方向平行的邊的正方形。
圖36B是圖36A的一點鏈線36B-36B中的剖視圖。在與平行於〔010〕方向的邊交叉的剖面，包含集電極層103、基極層104以及發射極層105的檯面的側面為垂直豎直的形狀。在與平行於〔001〕方向的邊交叉的剖面也相同。
如上述那樣，在第7實施例中，包含集電極層103、基極層104以及發射極層105的檯面的全部側面為垂直豎直的形狀，不形成簷狀的部分。由此，可得到難以產生基於接合時的載荷的破損的效果。
〔第8實施例〕
接下來，參照圖37來對基於第8實施例的功率放大器模組進行說明。該功率放大器模組搭載了基於從上述的第1實施例至第7實施例的任意一個實施例的 半導體裝置。
圖37是基於第8實施例的功率放大器模組的剖視圖。在印刷佈線基板200安裝有半導體裝置500、矽半導體晶片230以及其他複數個表面安裝型元件。對於半導體裝置500，使用基於第1實施例至第7實施例的任意一個實施例的半導體裝置。在矽半導體晶片230例如形成CMOS電路。
半導體裝置500的背面電極45透過導電性粘接劑221而被固定於印刷佈線基板200的下墊板201並且被電連接。矽半導體晶片230透過導電性粘接劑231而被固定於印刷佈線基板200的下墊板202。在下墊板201、202的最表面形成Au膜。作為導電性粘接劑221、231，例如能夠使用以使銀(Ag)微粒子分散的環氧樹脂為主成分的粘接劑。另外，除了環氧樹脂，也可以使用丙烯酸樹脂、雙馬來醯亞胺樹脂、丁二烯樹脂、矽酮樹脂或者將這些樹脂而成的混合樹脂。
半導體裝置500的複數個接合焊墊140與印刷佈線基板200的接合焊墊203藉由複數個接合線225而被連接。作為接合線225，例如能夠使用直徑20μm的Au線。接合線225使用引線接合器來與接合焊墊140、203接合。
矽半導體晶片230的複數個接合焊墊232分別藉由複數個接合線235來與印刷佈線基板200的複數個接合焊墊204連接。
半導體裝置500、矽半導體晶片230、其他表面安裝型元件、接合線225、235被密封用固化樹脂240密封。
在第8實施例中，作為半導體裝置500，使用基於第1實施例至第7實施例的任意一個實施例的半導體裝置，因此能夠實現半導體裝置500的小型化。進一步地，能夠抑制接合時的半導體裝置500的損傷。由此，提供一種可靠性高的功率放大器模組。
上述的各實施例是示例，當然可以進行不同實施例中所示的結 構的局部置換或者組合。針對基於複數個實施例的相同結構的相同的作用效果，不按照每個實施例來依次提及。进一步地，本发明并不局限于上述的实施例。本領域的技術人員應當清楚，例如能夠進行各種變更、改進、組合等。

Claims (15)

  1. 一種半導體裝置，具有：電路元件，形成在包含化合物半導體的基板上；和接合焊墊，在前述電路元件上，被配置為與前述電路元件至少局部重疊，前述接合焊墊包含第1金屬膜以及形成於前述第1金屬膜上的第2金屬膜，前述第2金屬膜的金屬材料的楊氏模量比前述第1金屬膜的金屬材料的楊氏模量大，前述接合焊墊進一步包含形成於前述第2金屬膜上的第3金屬膜，前述第3金屬膜由與前述第1金屬膜相同的金屬材料形成。
  2. 如請求項1所述之半導體裝置，其中，前述第1金屬膜以及前述第3金屬膜由Au形成，前述第2金屬膜具有包含至少1種金屬材料的層，前述至少1種金屬材料是選自於由Cu、Ni以及Mo所組成的群。
  3. 如請求項2所述之半導體裝置，其中，前述第2金屬膜具有包含至少2種金屬材料的2層，前述至少2種金屬材料是選自於由Cu、Ni以及Mo所組成的群。
  4. 如請求項1所述之半導體裝置，其中，在前述第1金屬膜上進一步具有保護膜，前述保護膜具有在俯視情況下被配置於前述第1金屬膜的內側的開口，前述第2金屬膜以及前述第3金屬膜在俯視情況下被配置於前述開口的內側。
  5. 如請求項2所述之半導體裝置，其中，在前述第1金屬膜上進一步具有保護膜，前述保護膜具有在俯視情況下被配置於前述第1金屬膜的內側的開口，前述第2金屬膜以及前述第3金屬膜在俯視情況下被配置於前述開口的內側。
  6. 如請求項3所述之半導體裝置，其中，在前述第1金屬膜上進一步具有保護膜，前述保護膜具有在俯視情況下被配置於前述第1金屬膜的內側的開口，前述第2金屬膜以及前述第3金屬膜在俯視情況下被配置於前述開口的內側。
  7. 如請求項4所述之半導體裝置，其中，前述半導體裝置進一步具有第4金屬膜，前述第4金屬膜覆蓋前述開口的內側的前述第1金屬膜的上表面之中未被前述第2金屬膜覆蓋的區域、前述第2金屬膜的側面以及前述第3金屬膜的側面和上表面，並且由與前述第1金屬膜相同的金屬材料形成。
  8. 如請求項5所述之半導體裝置，其中，前述半導體裝置進一步具有第4金屬膜，前述第4金屬膜覆蓋前述開口的內側的前述第1金屬膜的上表面之中未被前述第2金屬膜覆蓋的區域、前述第2金屬膜的側面以及前述第3金屬膜的側面和上表面，並且由與前述第1金屬膜相同的金屬材料形成。
  9. 如請求項6所述之半導體裝置，其中，前述半導體裝置進一步具有第4金屬膜，前述第4金屬膜覆蓋前述開口的內側的前述第1金屬膜的上表面之中未被前述第2金屬膜覆蓋的區域、前述第2金屬膜的側面以及前述第3金屬膜的側面和上表面，並且由與前述第1金屬膜相同的金屬材料形成。
  10. 如請求項1所述之半導體裝置，其中，前述基板的化合物半導體具有閃鋅礦型結晶構造，前述基板的上表面是從(100)面起的偏離角為4°以下的面，前述電路元件是選自於由異質結雙極電晶體、場效應電晶體、二極體、電容器以及電阻元件所組成的群的1個元件。
  11. 如請求項2所述之半導體裝置，其中，前述基板的化合物半導體具有閃鋅礦型結晶構造，前述基板的上表面是從(100)面起的偏離角為4°以下的面，前述電路元件是選自於由異質結雙極電晶體、場效應電晶體、二極體、電容器以及電阻元件所組成的群的1個元件。
  12. 如請求項10所述之半導體裝置，其中，前述電路元件具有包含從前述基板外延生長的半導體層的檯面構造，前述檯面構造的上表面的平面形狀是包含與〔01-1〕方向平行的邊和與〔011〕方向平行的邊的長方形或者正方形，與〔011〕方向平行的邊比與〔01-1〕方向平行的邊短。
  13. 如請求項10所述之半導體裝置，其中，前述電路元件具有包含從前述基板外延生長的半導體層的檯面構造，前述檯面構造的上表面的平面形狀是包含與〔001〕方向平行的邊以及與〔010〕方向平行的邊的多邊形。
  14. 如請求項13所述之半導體裝置，其中，前述檯面構造的上表面的平面形狀是還包含與〔01-1〕方向平行的邊的平行六邊形。
  15. 一種功率放大器模組，具有：半導體裝置，前述半導體裝置包含：具有形成於包含化合物半導體的基板上的異質結雙極電晶體的功率放大電路、連接在前述異質結雙極電晶體的發射極-集電極間的保護電路、以及作為前述功率放大電路的輸出端子的接合焊墊，構成前述功率放大電路以及前述保護電路的至少1個電路元件與前述接合焊墊被配置為局部重疊，前述接合焊墊包含第1金屬膜和第2金屬膜的至少2層，前述第2金屬膜的金屬材料的楊氏模量比前述第1金屬膜的金屬材料的楊氏模量大，前述接合焊墊進一步包含形成於前述第2金屬膜上的第3金屬膜，前述第3金屬膜由與前述第1金屬膜相同的金屬材料形成；印刷佈線基板，安裝前述半導體裝置；以及接合線，與前述接合焊墊接合，將前述接合焊墊與前述印刷佈線基板的佈線連接。
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