TWI663821B - Bootstrap circuit and associated direct current-to-direct current converter applying the bootstrap circuit - Google Patents
Bootstrap circuit and associated direct current-to-direct current converter applying the bootstrap circuit Download PDFInfo
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Abstract
一種自舉式電路,其應用於直流轉直流轉換器之第一電晶體,自舉式電路包括第二電晶體、自舉電容以及箝位電路。自舉電容具有第一端以及第二端,第一端與第二電晶體的源極端耦接,第二電晶體的源極端與第一電晶體耦接。箝位電路耦接於第二電晶體的閘極端以及自舉電容的第二端之間,箝位電路被配置用以保持自舉電容的第二端與第二電晶體的閘極端之間的電位差。第二電晶體的汲極端耦接第一參考電壓,第一電晶體的閘極端的電壓準位的最大值大於第一參考電壓。 A bootstrap circuit is applied to a first transistor of a DC-to-DC converter. The bootstrap circuit includes a second transistor, a bootstrap capacitor, and a clamping circuit. The bootstrap capacitor has a first terminal and a second terminal. The first terminal is coupled to the source terminal of the second transistor, and the source terminal of the second transistor is coupled to the first transistor. The clamp circuit is coupled between the gate terminal of the second transistor and the second terminal of the bootstrap capacitor. The clamp circuit is configured to maintain a distance between the second terminal of the bootstrap capacitor and the gate terminal of the second transistor. Potential difference. The drain terminal of the second transistor is coupled to the first reference voltage, and the maximum value of the voltage level of the gate terminal of the first transistor is greater than the first reference voltage.
Description
本發明係關於一種自舉式電路以及使用該自舉式電路之關聯的直流轉直流轉換器。 The invention relates to a bootstrap circuit and an associated DC-to-DC converter using the bootstrap circuit.
以降壓轉換器為例,其藉由轉換多個開關元件的開/關狀態來提供電流至電感以及電容,因此可將輸入電壓降低以得到輸出電壓,其中輸入電壓為電路中最高的電壓值。此外,對於具有高輸入電壓的降壓轉換器而言,為了減少耗能並得到所需的上拉電阻,常使用N型電晶體來實現,其中N型電晶體具有閘極端與源極端之間具有較小的電位差以及汲極端與源極端之間具有較大的電位差的特性。而為了致能N型電晶體,在N型電晶體的閘極端、源極端以及汲極端中,閘極端的電壓準位應該為三端中電壓值最高的電壓準位。因此,當源極端被充以輸入電壓的電壓值時,閘極端的電壓準位在沒有補償的情況下會無法高於源極端的電壓準位,電晶體將會難以被致能。 Taking a buck converter as an example, it provides current to the inductor and capacitor by switching the on / off states of multiple switching elements, so the input voltage can be reduced to obtain the output voltage, where the input voltage is the highest voltage value in the circuit. In addition, for a buck converter with a high input voltage, in order to reduce power consumption and obtain the required pull-up resistor, an N-type transistor is often used to implement it, where the N-type transistor has between the gate and source terminals. It has the characteristics of smaller potential difference and larger potential difference between the drain terminal and the source terminal. In order to enable the N-type transistor, the voltage level of the gate terminal of the N-type transistor should be the highest voltage level among the three terminals among the gate terminal, the source terminal, and the drain terminal. Therefore, when the source terminal is charged with the input voltage value, the voltage level of the gate terminal cannot be higher than the voltage level of the source terminal without compensation, and the transistor will be difficult to be enabled.
本發明的其中一個目的是提供一種自舉式電路及關聯的直流轉直流轉換器,以藉此解決前述問題。 One object of the present invention is to provide a bootstrap circuit and an associated DC-to-DC converter, so as to solve the aforementioned problems.
根據本發明的一個實施例,公開了一種應用於直流轉直流轉換器的第一電晶體的自舉式電路。自舉式電路包括第二電晶體、自舉電容以及箝位電路,其中自舉電容具有第一端以及第二端,第一端與第二電晶體的源極端耦接,第二電晶體的的源極端與第一電晶體耦接。箝位電路耦接於第二電晶體的閘極端以及自舉電容的第二端之間,箝位電路被配置用以保持自舉電容的第二端與第二電晶體的閘極端之間的電位差。第二電晶體的汲極端耦接第一參考電壓,第一電晶體的閘極端的電壓準位的最大值大於第一參考電壓。 According to an embodiment of the present invention, a bootstrap circuit for a first transistor of a DC-to-DC converter is disclosed. The bootstrap circuit includes a second transistor, a bootstrap capacitor, and a clamping circuit. The bootstrap capacitor has a first terminal and a second terminal. The first terminal is coupled to the source terminal of the second transistor. The source terminal is coupled to the first transistor. The clamp circuit is coupled between the gate terminal of the second transistor and the second terminal of the bootstrap capacitor. The clamp circuit is configured to maintain a distance between the second terminal of the bootstrap capacitor and the gate terminal of the second transistor. Potential difference. The drain terminal of the second transistor is coupled to the first reference voltage, and the maximum value of the voltage level of the gate terminal of the first transistor is greater than the first reference voltage.
根據本發明的一個實施例,公開了一種直流轉直流轉換器。直流轉直流轉換器包括開關電路、電感-電容電路、反饋電路以及自舉式電路。開關電路包括第一電晶體以及第二電晶體,其中切換端耦接於第一電晶體的源極端以及第二電晶體的汲極端,第一電晶體的汲極端與第一參考電壓耦接。電感-電容電路包括至少一電感器以及電容,電感-電容電路被配置於藉由開關電路接收來自第一參考電壓源的電感電流以提供能量至隨後負載。反饋電路與電感-電容電路耦接,反饋電路被配置於用以產生輸出電壓在輸出端以及產生反饋電壓。自舉式電路包含第三電晶體、自舉電容以及箝位電路,其中第三電晶體的源極端與第一電晶體耦接,自舉電容具有第一端以及第二端,第一端與第三電晶體的源極端耦接。箝位電路耦接於第三電晶體的閘極端以及自舉電容的第二端之間,箝位電路被配置於維持自舉電容的第二端與第三電晶體的閘極端之間的電位差。第 三電晶體的汲極端與第一參考電壓耦接,電晶體的閘極端的電壓準位的最大值大於第一參考電壓。 According to an embodiment of the present invention, a DC-to-DC converter is disclosed. The DC-to-DC converter includes a switching circuit, an inductor-capacitor circuit, a feedback circuit, and a bootstrap circuit. The switching circuit includes a first transistor and a second transistor. The switching terminal is coupled to the source terminal of the first transistor and the drain terminal of the second transistor. The drain terminal of the first transistor is coupled to the first reference voltage. The inductor-capacitor circuit includes at least one inductor and a capacitor. The inductor-capacitor circuit is configured to receive an inductor current from a first reference voltage source through a switch circuit to provide energy to a subsequent load. The feedback circuit is coupled to the inductor-capacitor circuit. The feedback circuit is configured to generate an output voltage at the output terminal and generate a feedback voltage. The bootstrap circuit includes a third transistor, a bootstrap capacitor, and a clamping circuit. The source terminal of the third transistor is coupled to the first transistor. The bootstrap capacitor has a first terminal and a second terminal. The source terminal of the third transistor is coupled. The clamp circuit is coupled between the gate terminal of the third transistor and the second terminal of the bootstrap capacitor. The clamp circuit is configured to maintain a potential difference between the second terminal of the bootstrap capacitor and the gate terminal of the third transistor. . First The drain terminal of the triode is coupled to the first reference voltage, and the maximum value of the voltage level of the gate terminal of the transistor is greater than the first reference voltage.
對於本領域普通技術人員來說,在閱讀以下各個附圖和附圖中所示的優選實施例的詳細描述後,本發明的這些和其它目的將無疑將變得顯而易見。 For those of ordinary skill in the art, these and other objects of the present invention will no doubt become apparent after reading the following detailed drawings and detailed description of the preferred embodiments shown in the accompanying drawings.
10‧‧‧電流模式降壓型轉換器 10‧‧‧Current Mode Buck Converter
101‧‧‧輸入電壓源 101‧‧‧ input voltage source
102‧‧‧開關電路 102‧‧‧Switch circuit
103‧‧‧電感-電容電路 103‧‧‧Inductive-Capacitor Circuit
104‧‧‧反饋電路 104‧‧‧Feedback circuit
105‧‧‧自舉式電路 105‧‧‧Bootstrap circuit
106‧‧‧峰值電流模式控制電路 106‧‧‧Peak current mode control circuit
116‧‧‧誤差放大器 116‧‧‧Error Amplifier
126‧‧‧加法器 126‧‧‧ Adder
136‧‧‧斜率補償電路 136‧‧‧Slope Compensation Circuit
146‧‧‧PWM比較器 146‧‧‧PWM comparator
156‧‧‧控制邏輯電路 156‧‧‧Control logic circuit
156_1‧‧‧緩衝器 156_1‧‧‧Buffer
166‧‧‧高側端電流感測電路 166‧‧‧High-side current sensing circuit
210‧‧‧箝位電路 210‧‧‧Clamp circuit
220‧‧‧自舉電容 220‧‧‧Boot capacitor
230‧‧‧驅動電流源 230‧‧‧Drive current source
240、250‧‧‧電壓調節電路 240, 250‧‧‧ voltage regulation circuit
260‧‧‧電壓源 260‧‧‧Voltage source
C、C'‧‧‧電容 C, C'‧‧‧ capacitor
Id‧‧‧驅動電流 I d ‧‧‧Drive current
IL‧‧‧電感電流 I L ‧‧‧ inductor current
ILOAD‧‧‧隨後負載電流 I LOAD ‧‧‧Subsequent load current
L‧‧‧電感 L‧‧‧Inductance
MD1、MD2、MD3‧‧‧電晶體 MD1, MD2, MD3‧‧‧ transistor
NS‧‧‧源極端 N S ‧‧‧Source Extreme
NG‧‧‧閘極端 N G ‧‧‧ Gate extreme
SD1、SD2‧‧‧蕭特基二極 SD1, SD2‧‧‧‧Schottky Dipole
CT、CT1-CTn‧‧‧箝位電晶體 CT, CT 1 -CT n ‧‧‧Clamping transistor
N1、N2‧‧‧端子 N 1 , N 2 ‧‧‧ terminals
PWM‧‧‧PWM信號 PWM‧‧‧PWM signal
R1、R'、R2‧‧‧電阻 R 1 , R ', R 2 ‧‧‧ resistance
OUT‧‧‧輸出端 OUT‧‧‧output
Vin‧‧‧輸入電壓 Vin‧‧‧ input voltage
NVt‧‧‧電位差 NV t ‧‧‧potential difference
NSW‧‧‧切換端 N SW ‧‧‧Switch
CTRL‧‧‧控制訊號 CTRL‧‧‧Control signal
VSW‧‧‧電壓準位 V SW ‧‧‧Voltage Level
VO‧‧‧輸出電壓 V O ‧‧‧ Output voltage
Vref‧‧‧參考電壓 V ref ‧‧‧ Reference voltage
Vc‧‧‧輸出電壓 Vc‧‧‧Output voltage
VR‧‧‧斜坡電壓 V R ‧‧‧ Ramp voltage
VFB‧‧‧反饋電壓 V FB ‧‧‧Feedback voltage
VSC‧‧‧電流感測電壓 V SC ‧‧‧ Current Sensing Voltage
VDD‧‧‧高電源電壓 V DD ‧‧‧High power voltage
VGS‧‧‧電位差 V GS ‧‧‧ Potential difference
圖1是應用本發明實施例的自舉式電路的降壓轉換器的示意圖;圖2是根據本發明實施例的自舉式電路的示意圖;以及圖3是根據本發明實施例的箝位電路的示意圖。 1 is a schematic diagram of a buck converter using a bootstrap circuit according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a bootstrap circuit according to an embodiment of the present invention; and FIG. 3 is a clamp circuit according to an embodiment of the present invention Schematic.
整個說明書和權利要求中使用了某些術語來指代特定的部件。如本領域技術人員將認識到的,製造商可以通過不同的名稱來引用組件。本說明書未特定地區分名稱不同但功能卻相同的組件。在下面的描述和權利要求書中,術語「包括」和「包含」以開放式的方式使用,因此不應被解釋為諸如「由...組成」的封閉式術語。另外,術語「耦接」旨在表示間接或直接的電連接。因此,如果一個設備耦接到另一個設備,則此連接可以通過直接電連接,或者通過經由其他設備和連接的間接電連接。 Certain terms are used throughout the description and claims to refer to particular components. As those skilled in the art will recognize, manufacturers may refer to a component by different names. This manual does not specifically identify components with different names but the same functions. In the following description and claims, the terms "including" and "comprising" are used in an open-ended fashion and therefore should not be interpreted as closed terms such as "consisting of". In addition, the term "coupled" is intended to mean an indirect or direct electrical connection. Therefore, if one device is coupled to another device, this connection may be through a direct electrical connection, or through an indirect electrical connection via the other device and the connection.
如現有技術中所述,對於諸如降壓轉換器的直流轉直流轉換器,其需要自舉式電路。圖1舉例說明具有自舉式電路105的電流模式降壓型轉換器10。電流模式降壓型轉換器10包括輸入電壓源101、開關電路102、電感-電容電 路103以及反饋電路104。輸入電壓源101用於提供輸入電壓Vin。開關電路102包括做為開關使用的電晶體MD1和MD2。電感-電容電路103包括電感L和電容C,電感-電容電路103藉由開關電路102接收來自輸入電壓源101的電感電流IL,以提供能量給隨後負載所利用。反饋電路104包括電阻R1和R2,反饋電路104是用於根據電感電流IL於端子N1產生反饋電壓VFB,其中端子N1耦接在電阻R1和R2之間。另外,反饋電路104用以根據電感電流IL以及負載電流ILOAD於輸出端OUT產生輸出電壓VO。如圖1所示,開關電路102更包括切換端NSW,切換端NSW耦接於電晶體MD1的源極端以及電晶體MD2的汲極端之間,且如圖1所示,切換端的電壓準位標示為VSW。在此實施例中,電晶體MD1和MD2由具有較低上拉電阻的N型金屬氧化物半導體場效應電晶體(MOSFET)實現,且低於特定預設值的上拉電阻同時表示電晶體佔有較少的耗能。需注意的是,前述僅是用來進一步說明,並非用以限制本發明。在其他實施例中,電晶體MD1和MD2可以由其他類型的電晶體來實現。此外,在其他實施例中,作為開關的電晶體MD2可由蕭特基二極體(Schottky diode)來取代,但不以此為限。 As described in the prior art, for a DC-to-DC converter such as a buck converter, it requires a bootstrap circuit. FIG. 1 illustrates a current mode buck converter 10 with a bootstrap circuit 105. The current-mode step-down converter 10 includes an input voltage source 101, a switching circuit 102, an inductor-capacitor circuit 103, and a feedback circuit 104. The input voltage source 101 is used to provide an input voltage Vin. The switching circuit 102 includes transistors MD1 and MD2 used as switches. The inductor-capacitor circuit 103 includes an inductor L and a capacitor C. The inductor-capacitor circuit 103 receives the inductor current I L from the input voltage source 101 through the switching circuit 102 to provide energy for subsequent loads to use. The feedback circuit 104 includes resistors R 1 and R 2. The feedback circuit 104 is configured to generate a feedback voltage V FB at the terminal N 1 according to the inductor current IL . The terminal N 1 is coupled between the resistors R 1 and R 2 . In addition, the feedback circuit 104 is configured to generate an output voltage V O at the output terminal OUT according to the inductor current IL and the load current I LOAD . As shown in FIG. 1, the switching circuit 102 further includes a switching terminal N SW . The switching terminal N SW is coupled between the source terminal of the transistor MD1 and the drain terminal of the transistor MD2. As shown in FIG. The bits are labeled V SW . In this embodiment, the transistors MD1 and MD2 are implemented by N-type metal-oxide-semiconductor field-effect transistor (MOSFET) with a low pull-up resistance, and a pull-up resistance lower than a specific preset value also indicates that the transistor has Less energy consumption. It should be noted that the foregoing is only for further explanation, and is not intended to limit the present invention. In other embodiments, the transistors MD1 and MD2 may be implemented by other types of transistors. In addition, in other embodiments, the transistor MD2 as a switch may be replaced by a Schottky diode, but not limited thereto.
自舉式電路105與開關電路102耦接,自舉式電路105是用以提升電晶體MD1的閘極端的電壓準位。自舉式電路105並會在以下段落進一步說明。電流模式降壓型轉換器10更可進一步包括峰值電流模式控制電路106。峰值電流模式控制電路106包括:誤差放大器116、加法器126、PWM比較器146、控制邏輯電路156、電阻R'以及電容C'。誤差放大器116包括負輸入端、正輸入端以及輸出端,負輸入端用來接收反饋電壓VFB,正輸入端用來接收參考電壓Vref,誤差放大器116用以根據反饋電壓VFB以及參考電壓Vref於輸出端產生輸出電壓VC。加法 器126用來接收電流感測電壓VSC以及斜率電壓VR,其中電流感測電壓VSC是由高側端電流感測電路166感測端子N2的電流產生,以及斜率電壓VR是由斜率補償電路136所產生。PWM比較器146包括一輸出端,PWM比較器146用來比較誤差放大器116的輸出電壓VC與加法器126的輸出電壓,並據此於其輸出端產生PWM訊號。控制邏輯電路156是用以產生控制訊號CTRL至開關電路102,使電晶體MD1以及MD2可被PWM訊號控制其運作。在此實施例中,控制邏輯電路156可包括緩衝器156_1(參照圖2),緩衝器156_1用以接收PWM訊號並產生且傳送控制訊號CTRL至開關電路102的電晶體MD1。電阻R'以及電容C'彼此串聯且耦接於誤差放大器116的輸出端,其中電阻R'以及電容C'形成為補償電路。然而,所述補償電路並非限定於以電阻R'以及電容C'來實現。本領域技術人員應該理解,補償電路可以通過不同的架構來實現。同時,具有斜率補償機制的電流模式降壓型轉換器10應該是本領域技術人員所熟知的。 The bootstrap circuit 105 is coupled to the switch circuit 102. The bootstrap circuit 105 is used to raise the voltage level of the gate terminal of the transistor MD1. The bootstrap circuit 105 is further described in the following paragraphs. The current mode buck converter 10 may further include a peak current mode control circuit 106. The peak current mode control circuit 106 includes an error amplifier 116, an adder 126, a PWM comparator 146, a control logic circuit 156, a resistor R ', and a capacitor C'. The error amplifier 116 includes a negative input terminal, a positive input terminal, and an output terminal. The negative input terminal is used to receive the feedback voltage V FB and the positive input terminal is used to receive the reference voltage V ref . The error amplifier 116 is used to receive the feedback voltage V FB and the reference voltage. V ref generates an output voltage V C at the output terminal. The adder 126 is used to receive the current sensing voltage V SC and the slope voltage V R , where the current sensing voltage V SC is generated by the current at the sensing terminal N 2 of the high-side current sensing circuit 166 and the slope voltage V R is Generated by the slope compensation circuit 136. The PWM comparator 146 includes an output terminal. The PWM comparator 146 is used to compare the output voltage V C of the error amplifier 116 with the output voltage of the adder 126 and generate a PWM signal at its output terminal accordingly. The control logic circuit 156 is used to generate a control signal CTRL to the switching circuit 102 so that the transistors MD1 and MD2 can be controlled by the PWM signal to operate. In this embodiment, the control logic circuit 156 may include a buffer 156_1 (refer to FIG. 2). The buffer 156_1 is used to receive the PWM signal and generate and transmit the control signal CTRL to the transistor MD1 of the switching circuit 102. The resistor R ′ and the capacitor C ′ are connected in series with each other and are coupled to the output terminal of the error amplifier 116. The resistor R ′ and the capacitor C ′ are formed as a compensation circuit. However, the compensation circuit is not limited to be implemented with a resistor R ′ and a capacitor C ′. Those skilled in the art should understand that the compensation circuit can be implemented by different architectures. Meanwhile, the current mode buck converter 10 with a slope compensation mechanism should be well known to those skilled in the art.
本發明著重於具有提升電晶體MD1的閘極端的電壓準位的自舉式電路105,以解決現有技術中提到的問題,在此請注意,本發明公開的自舉式電路105不限於應用於如圖1所示的降壓型轉換器。 The present invention focuses on a bootstrap circuit 105 having the voltage level of the gate extreme of the transistor MD1 to solve the problems mentioned in the prior art. Please note that the bootstrap circuit 105 disclosed in the present invention is not limited to applications. For the buck converter shown in Figure 1.
圖2是根據本發明實施例的自舉式電路105的示意圖,所述自舉式電路105並與開關電路102的電晶體MD1耦接。如圖2所示,自舉式電路105包括電晶體MD3、箝位電路210、自舉電容220、驅動電流源230、電壓調節電路240與250以及電壓源260。箝位電路210耦接於電晶體MD3的閘極端以及切換端NSW之間,箝位電路210是用以維持所述兩端之間的電位差。自舉電容220耦接於電晶體MD3的源極端NS以及切換端NSW之間,自舉電容220是用以接收來自輸入電壓Vin 的電流並藉以充電,用以提升源極端NS的電壓準位。驅動電流源230耦接於電晶體MD3的閘極端以及輸入電壓Vin之間,驅動電流源230是用來提供驅動電流Id。電壓調節電路240包括蕭特基二極體SD1,蕭特基二極體SD1耦接於電晶體MD3的汲極端以及輸入電壓Vin之間。由於蕭特基二極體SD1耦接於電晶體MD3的汲極端,電晶體MD3可以輕易的維持於飽和狀態並提供足夠的電流至自舉電容220。電壓調節電路250包括蕭特基二極體SD2,蕭特基二極體SD2耦接於閘極端NG以及電壓源260之間。電壓源260耦接於電壓調節電路250以及參考電壓(即接地電壓)之間,電壓源260是用來提供參考電壓VDD。如圖2所示,電晶體MD3的源極端NS與控制邏輯電路156的緩衝器56_1耦接,其中,緩衝器156_1接收PWM訊號,緩衝器156_1並產生且傳送控制訊號CTRL至電晶體MD1的閘極端。藉由電晶體MD3以足夠的電流提供穩定的能量至自舉電容220,控制邏輯電路156可輕易地控制電晶體MD1的閘極端的電壓準位,使電晶體MD1的閘極端的電壓準位提升至輸入電壓Vin,以解決現有技術中提到的問題。 FIG. 2 is a schematic diagram of a bootstrap circuit 105 according to an embodiment of the present invention. The bootstrap circuit 105 is coupled to the transistor MD1 of the switching circuit 102. As shown in FIG. 2, the bootstrap circuit 105 includes a transistor MD3, a clamp circuit 210, a bootstrap capacitor 220, a driving current source 230, voltage adjustment circuits 240 and 250, and a voltage source 260. The clamp circuit 210 is coupled between the gate terminal of the transistor MD3 and the switching terminal N SW . The clamp circuit 210 is used to maintain a potential difference between the two ends. The bootstrap capacitor 220 is coupled between the source terminal N S of the transistor MD3 and the switching terminal N SW . The bootstrap capacitor 220 is used to receive and charge the current from the input voltage V in to increase the source terminal N S Voltage level. The driving current source 230 is coupled between the gate terminal of the transistor MD3 and the input voltage V in . The driving current source 230 is used to provide a driving current I d . The voltage regulating circuit 240 includes a Schottky diode SD1. The Schottky diode SD1 is coupled between the drain terminal of the transistor MD3 and the input voltage V in . Since the Schottky diode SD1 is coupled to the drain terminal of the transistor MD3, the transistor MD3 can be easily maintained in a saturated state and provide sufficient current to the bootstrap capacitor 220. The voltage regulating circuit 250 includes a Schottky diode SD2. The Schottky diode SD2 is coupled between the gate terminal N G and the voltage source 260. The voltage source 260 is coupled between the voltage adjustment circuit 250 and a reference voltage (ie, a ground voltage). The voltage source 260 is used to provide a reference voltage V DD . As shown in FIG. 2, the source terminal N S of the transistor MD3 is coupled to the buffer 56_1 of the control logic circuit 156. The buffer 156_1 receives the PWM signal, the buffer 156_1 generates and transmits the control signal CTRL to the transistor MD1. Brake extreme. By providing the transistor MD3 with sufficient current to provide stable energy to the bootstrap capacitor 220, the control logic circuit 156 can easily control the voltage level of the gate extreme of the transistor MD1, so that the voltage level of the gate extreme of the transistor MD1 is increased. To the input voltage V in to solve the problems mentioned in the prior art.
圖3為根據本發明實施例的箝位電路210的示意圖。如圖3所示,箝位電路210包括多個箝位電晶體CT1-CTn,其中多個箝位電晶體CT1-CTn的每一者是由二極體形式電晶體來實現。舉例來說,多個箝位電晶體CT1-CTn的每一者的閘極端與汲極端彼此耦接,且多個箝位電晶體CT1-CTn彼此串聯。在此實施例中,多個箝位電晶體CT1-CTn的每一者具有相同的門檻電壓(threshold voltage)Vt,且電晶體MD3的閘極端NG與切換端NSW之間的電位差為NVt。在其他實施例中,多個箝位電晶體CT1-CTn中的每一者的門檻電壓Vt並沒有限制為相同。需注意的是,參考電壓VDD被設計為大於電晶體MD3的閘極端NG與切換端NSW之間的電位 差NVt,即VDD>NVt。根據公開於本案實施例的自舉式電路105,自舉電容220可以在以下的狀態充電: FIG. 3 is a schematic diagram of a clamping circuit 210 according to an embodiment of the present invention. As shown in FIG. 3, the clamp circuit 210 includes a plurality of clamp transistors CT 1 -CT n , wherein each of the plurality of clamp transistors CT 1 -CT n is implemented by a diode-type transistor. For example, the gate terminal and the drain plurality of clamping transistor CT 1 -CT terminal of each of the n coupled to each other, and a plurality of clamping transistor CT 1 -CT n connected in series. In this embodiment, each of the plurality of clamp transistors CT 1 -CT n has the same threshold voltage V t , and the voltage between the gate terminal N G of the transistor MD 3 and the switching terminal N SW is the same. The potential difference is NV t . In other embodiments, the threshold voltage V t of each of the plurality of clamp transistors CT1-CTn is not limited to be the same. It should be noted that the reference voltage V DD is designed to be larger than the potential difference NV t between the gate terminal N G of the transistor MD3 and the switching terminal N SW , that is, V DD > NV t . According to the bootstrap circuit 105 disclosed in the embodiment of the present invention, the bootstrap capacitor 220 can be charged in the following states:
(1)當切換端NSW的電壓準位VSW大於零且電壓準位VSW加上電位差NVt的電壓值小於參考電壓VDD,即VSW>0,VSW+NVt<VDD,自舉電容220上的跨壓為VDD-VSW-VGS,其中VGS為閘極端NG與源極端NS的電位差。 (1) When the voltage level V SW of the switching terminal N SW is greater than zero and the voltage value of the voltage level V SW plus the potential difference NV t is smaller than the reference voltage V DD , that is, V SW > 0, V SW + NV t <V DD The voltage across the bootstrap capacitor 220 is V DD -V SW -V GS , where V GS is the potential difference between the gate terminal N G and the source terminal N S.
(2)當切換端NSW上的電壓準位VSW大於零,且電壓準位VSW加上電位差NVt的電壓值大於參考電壓VDD,即VSW>0,VSW+NVt>VDD,自舉電容220上的跨壓為NVt-VGS。 (2) When the voltage level V SW on the switch end N SW is greater than zero, and the voltage level V SW a voltage value of the potential difference NV t is greater than the reference voltage V DD, i.e. V SW> 0, V SW + NV t> V DD , the voltage across the bootstrap capacitor 220 is NV t -V GS .
(3)當切換端NSW上的電壓準位VSW趨近於零,自舉電容220上的跨壓為VDD-VGS。 (3) When the voltage level V SW at the switching terminal N SW approaches zero, the voltage across the bootstrap capacitor 220 is V DD -V GS .
(4)當切換端NSW上的電壓準位VSW小於零,自舉電容220上的跨壓為VDD-VSW-VGS。 (4) when the voltage level of the switching terminal V SW N SW is less than zero, since the pressure across the V DD -V SW -V GS 220 on the bootstrap capacitance.
除了電壓準位VSW接近輸入電壓Vin的情況外,自舉電容220可在以上所述的情況下被充電,因此,自舉式電路105的效能可以被顯著地提升。現有技術中所提到的問題可有效解決。 Except for the case where the voltage level V SW is close to the input voltage V in , the bootstrap capacitor 220 can be charged under the conditions described above. Therefore, the performance of the bootstrap circuit 105 can be significantly improved. The problems mentioned in the prior art can be effectively solved.
綜以上所述,本發明公開了一種可有效地對自舉電容220充電的自舉式電路,以提供穩定能量至電晶體MD3的源極端NS以及切換端NSW之間,且控制邏輯電路156可輕易地控制電晶體MD1的閘極端的電壓準位,使電晶體MD1的閘極端的電壓準位提升且高於輸入電壓Vin。 In summary, the present invention discloses a bootstrap circuit that can effectively charge the bootstrap capacitor 220 to provide stable energy between the source terminal N S and the switching terminal N SW of the transistor MD3, and a control logic circuit. 156 can easily control the voltage level of the gate terminal of the transistor MD1, so that the voltage level of the gate terminal of the transistor MD1 is increased and is higher than the input voltage V in .
以上所述僅為本發明的較佳實施例,凡依本發明權利要求範圍所做的均等變化與修飾,皆應屬本發明的涵蓋範圍。因此,上述公開內容應該被解釋為僅由所附權利要求的邊界限制。 The above are only preferred embodiments of the present invention, and any equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention. Accordingly, the foregoing disclosure should be construed as limited only by the boundaries of the appended claims.
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TW280967B (en) * | 1994-07-15 | 1996-07-11 | Philips Electronics Nv | |
TW541528B (en) * | 2001-12-06 | 2003-07-11 | Hynix Semiconductor Inc | Bootstrap circuit |
US20090231886A1 (en) * | 2008-03-12 | 2009-09-17 | Inventec Corporation | Power supply and bootstrap circuit thereof |
TW201025862A (en) * | 2008-12-30 | 2010-07-01 | Dongbu Hitek Co Ltd | Fast differential level shifter and boot strap driver including the same |
TW201622348A (en) * | 2014-10-10 | 2016-06-16 | 高效電源轉換公司 | High voltage zero QRR bootstrap supply |
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Publication number | Priority date | Publication date | Assignee | Title |
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TW280967B (en) * | 1994-07-15 | 1996-07-11 | Philips Electronics Nv | |
TW541528B (en) * | 2001-12-06 | 2003-07-11 | Hynix Semiconductor Inc | Bootstrap circuit |
US20090231886A1 (en) * | 2008-03-12 | 2009-09-17 | Inventec Corporation | Power supply and bootstrap circuit thereof |
TW201025862A (en) * | 2008-12-30 | 2010-07-01 | Dongbu Hitek Co Ltd | Fast differential level shifter and boot strap driver including the same |
TW201622348A (en) * | 2014-10-10 | 2016-06-16 | 高效電源轉換公司 | High voltage zero QRR bootstrap supply |
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