CN115833542A

CN115833542A - Drive control circuit and drive method for switching converter

Info

Publication number: CN115833542A
Application number: CN202211698414.7A
Authority: CN
Inventors: 吴杰
Original assignee: Jingyi Semiconductor Co ltd
Current assignee: Jingyi Semiconductor Co ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-03-21

Abstract

A drive control circuit and a drive method for a switching converter are disclosed. The driving control circuit comprises a loop control module, a lower tube driving current regulating circuit and a lower tube driving circuit. The lower tube driving current regulating circuit generates a driving current regulating signal according to a current sampling signal representing a current flowing through the lower tube and a lower tube control signal. The lower tube driving circuit generates a lower tube driving signal according to the lower tube control signal and the driving current adjusting signal. During the downtube shutdown, the drive current adjustment signal reduces the downtube drive signal from a first value to a second value if the current sampling signal is greater than the current reversal threshold. During the period of switching off the lower tube, the lower tube driving signal changes along with the current value flowing through the lower tube, so that the voltage stress of the lower tube is not too large, and the whole converter is ensured to work in a safe working area.

Description

Drive control circuit and drive method for switching converter

Technical Field

The present invention relates to electronic circuits, and more particularly, to a drive control circuit and method for a switching converter.

Background

In the design of a power chip, it is generally required to ensure that a power switch tube works in a safe working area. For example, in a BUCK switching converter, in order to prevent the problem that the lower tube is coupled by the on action of the upper tube and becomes high, which causes shoot-through, the lower tube is generally prone to be turned off by strong pull-down driving. However, in some applications, in order to pursue lower current, the BUCK switching converter is controlled to operate in a Forced Continuous operation Mode (FCCM) under light load, that is: when the inductor current is reduced to zero, the lower tube is not turned off, the output capacitor at the load end reversely charges the inductor, and the current flowing through the lower tube is reversed, namely the current flows from the drain electrode to the source electrode of the lower tube. When the reverse current reaches a certain value and the lower tube needs to be turned off, if the pull-down capability of the lower tube is too strong at the moment, the voltage stress of the lower tube is too large to meet the condition of a safe working area, and the lower tube can even be burnt in an extreme condition.

Disclosure of Invention

The present disclosure is directed to solving the above problems in the prior art, and provides a driving control circuit and method for a switching converter. The invention provides a drive control circuit, which changes the pull-down capability of the lower tube switch-off by detecting the current before the lower tube switch-off, thereby optimizing the problem.

In one aspect, the present disclosure discloses a driving control circuit of a switching converter, which includes an upper tube and a lower tube. The drive control circuit includes: the loop control module is used for receiving the voltage feedback signal and the current sampling signal and generating an upper tube control signal and a lower tube control signal according to the voltage feedback signal and the current sampling signal, wherein the voltage feedback signal represents an output voltage signal of the converter, and the current sampling signal represents current flowing through a lower tube; the lower tube driving current regulating circuit is used for receiving the current sampling signal and the lower tube control signal and generating a driving current regulating signal according to the current sampling signal and the lower tube control signal; and the lower tube driving circuit is used for receiving the lower tube control signal and the driving current adjusting signal and generating a lower tube driving signal according to the lower tube control signal and the driving current adjusting signal, wherein the lower tube driving signal is used for driving the lower tube to be switched on and off, and during the period of switching off the lower tube, if the current sampling signal is larger than the current reverse threshold value, the driving current adjusting signal reduces the lower tube driving signal from a first value to a second value.

The present disclosure in another aspect discloses a driving method applied to a lower tube of a switching converter, including: sampling a current flowing through a lower tube and generating a current sampling signal; during the lower tube turn-off period, comparing the current sampling signal with a current reverse threshold; and reducing the drive signal driving the lower tube to close from a first value to a second value if the current sampling signal is greater than the current reversal threshold.

Drawings

Fig. 1 shows a switching converter circuit schematic according to an embodiment of the present disclosure.

Fig. 2 shows a circuit schematic of the down tube drive current regulation circuit 14 and the down tube drive circuit 15 according to one embodiment of the present disclosure.

Fig. 3 shows a circuit schematic of the lower tube drive current regulation circuit 14 based on the lower tube drive circuit of fig. 2 according to yet another embodiment of the present disclosure.

Fig. 4 shows a circuit schematic of the lower tube drive current regulation circuit 14 based on the lower tube drive circuit of fig. 2 according to yet another embodiment of the present disclosure.

Fig. 5 shows a circuit schematic of the down tube drive current regulation circuit 14 and the down tube drive circuit 15 according to another embodiment of the present disclosure.

Fig. 6 shows a circuit schematic of the lower tube drive current regulation circuit 14 based on the lower tube drive circuit of fig. 5, according to yet another embodiment of the present disclosure.

Fig. 7 shows a driving method for driving a lower tube of a switching converter to be turned off according to an embodiment of the present invention.

As shown in the drawings, like reference numerals refer to like parts throughout the different views. The drawings presented herein are for purposes of illustrating the embodiments, principles, concepts and the like and are not necessarily drawn to scale.

Detailed Description

Specific embodiments of the present invention will now be described without limitation in conjunction with the accompanying drawings. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The verbs "comprising" and "having" are used herein as open-ended restrictions that neither exclude nor require the presence of unrecited features. The features recited in the dependent claims may be freely combined with each other, unless explicitly stated otherwise. The use of the terms "a" or "an" (i.e., singular forms) in defining an element throughout this document does not exclude the possibility of a plurality of such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct or may be via one or more other elements. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When referring to a voltage of a node or terminal, the voltage is considered to be the voltage between the node and a reference potential (typically ground) unless otherwise indicated. Further, when referring to the potential of a node or a terminal, the potential is considered to refer to a reference potential unless otherwise indicated. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of the logic signal may correspond to voltages or currents that may not be completely constant in the high or low states.

Fig. 1 shows a switching converter circuit schematic according to an embodiment of the present disclosure. In the embodiment shown in fig. 1, the switching converter includes a switching circuit, an output inductor L, an output capacitor Cout, and a driving control circuit. The input end of the switching circuit receives an input voltage signal VIN; the output end of the switch circuit is coupled to one end of the output inductor L. The other end of the output inductor L is coupled with the output end of the switch converter; the capacitor Cout is coupled between the output terminal of the switching converter and a reference ground to provide an output voltage signal VOUT. The on-off switching is carried out by controlling a controllable switch in the switch circuit, so that the input voltage signal VIN is converted into the output voltage signal VOUT.

In the embodiment shown in fig. 1, the switching circuit is illustrated as a switching circuit of a BUCK topology. A top tube HS and a bottom tube LS are coupled in series between the input of switch circuit 10 and ground, with the common node of top tube HS and bottom tube LS labeled switch node SW. An output inductor L is coupled between the switch node SW and the output of the switching converter. In the embodiment shown in FIG. 1, upper tubes HS and lower tubes LS are illustrated as NMOS transistors. It will be appreciated by those skilled in the art that in other embodiments, upper tubes HS and lower tubes LS may also comprise other suitable semiconductor switching device types, such as junction field effect transistors, insulated gate bipolar transistors, and double diffused metal oxide semiconductors, among others.

In the embodiment shown in fig. 1, the drive control circuit of the switching converter includes an output voltage sampling circuit 2, a lower tube current sampling circuit 3, and a drive control circuit.

In the embodiment shown in fig. 1, the output voltage sampling circuit 2 is coupled to the output terminal of the switching converter, and is configured to sample the output voltage signal VOUT and generate a voltage feedback signal VFB, where the voltage feedback signal VFB represents the output voltage signal VOUT. In one embodiment, the output voltage sampling circuit 2 includes a voltage divider formed of resistors. In other embodiments, the output voltage sampling circuit 2 may also directly sample the output voltage signal VOUT.

In the embodiment shown in fig. 1, the lower tube current sampling circuit 3 is configured to sample the current flowing through the lower tube LS and generate a current sampling signal VCS, wherein the current sampling signal VCS represents the current flowing through the lower tube LS. In one embodiment, the lower tube current sampling circuit 3 may include a sampling resistor connected in series with the lower tube LS, and the voltage on the sampling resistor may represent the current flowing through the lower tube LS. In another embodiment, the switching converter may not include the down tube current sampling circuit 3. When the lower tube LS is turned on, the voltage signal on the node SW (the voltage VSW generated by the on-resistance of the lower tube LS) represents the current flowing through the lower tube LS. That is, after the lower transistor LS is turned on, the voltage signal VSW at the node SW is the current sampling signal VCS.

With continued reference to fig. 1, in the embodiment shown in fig. 1, the drive control circuit includes a loop control module, a lower tube drive current regulation circuit 14, a lower tube drive circuit 15, and an upper tube drive circuit 16. The loop control module controls the switching converter to work in the FCCM mode in the light load mode, that is, after the inductive current is reduced to zero, the output capacitor Cout continues to discharge through the lower tube LS, and the inductive current is reversely increased. Specifically, the loop control module includes a PWM control module 11, a comparison circuit 12, and a logic circuit 13

The PWM control module 11 receives the voltage feedback signal VFB and generates an upper tube control signal CH and an inverse signal CL of the upper tube control signal CH according to the voltage feedback signal VFB. The inverted signal CL of the top-tube control signal CH is logically complementary to the top-tube control signal CH, i.e., when the top-tube control signal CH is at a logic high level, the inverted signal CL is at a logic low level, and vice versa. The top tube control signal CH is used to control the switching on and off of the top tube HS.

The comparison circuit 12 has a first input terminal, a second input terminal and an output terminal. A first input terminal of the current sampling circuit receives a current sampling signal VCS; a second input terminal thereof receives a maximum reverse current reference signal Vneg-max; the comparison circuit 12 compares the current sample signal VCS with the maximum reverse current reference signal Vneg-max and generates a reverse current indication signal RES at the output. Wherein the maximum reverse current reference signal Vneg-max represents the maximum reverse current allowed to flow through the lower tube LS. As will be understood by those skilled in the art, in one embodiment, the lower tube LS flows current from the source to the drain of the lower tube LS during the process of inductor current dropping, and the current flowing in this direction is referred to as "positive current"; when operating in FCCM mode, the output capacitor Cout will continue to discharge through the lower tube LS after the inductor current has decreased to zero, and the current will increase and flow from the drain to the source of the lower tube LS, which is called "reverse current". In one embodiment, the reverse current indication signal RES is a logic high low level signal having a first logic state (e.g., logic high) and a second logic state (e.g., logic low). In one embodiment, the reverse current indication signal RES has a first logic state when the current sampling signal VCS is less than or equal to the maximum reverse current reference signal Vneg-max; the reverse current indication signal RES has a second logic state when the current sampling signal VCS is greater than the maximum reverse current reference signal Vneg-max. In one embodiment, comparison circuit 12 comprises a voltage comparator, wherein a first input of comparison circuit 12 is an inverting input of the voltage comparator; a second input terminal of the comparison circuit 12 is a non-inverting input terminal of the voltage comparator.

The logic circuit 13 receives the inverted signal CL and the inverted current indication signal RES, and generates the down tube control signal CTL by performing a logic operation on the inverted signal CL and the inverted current indication signal RES. The lower tube control signal CTL is used to control the on and off of the lower tube LS. In one embodiment, the lower tube control signal CTL has a second logic state (e.g., logic low) when either one of the inverted signal CL and the inverted current indication signal RES has the second logic state (e.g., logic low). In one embodiment, when the lower tube control signal CTL has a first logic state, the lower tube LS is turned on; when the lower tube control signal CTL has the second logic state, the lower tube LS is turned off. In one embodiment, the logic circuit 13 comprises a logic and gate circuit.

The lower driving current adjusting circuit 14 receives the lower control signal CTL and the current sampling signal VCS, and generates a driving current adjusting signal Reg according to the lower control signal CTL and the current sampling signal VCS. The lower tube driving current adjusting circuit 14 generates a driving current adjusting signal Reg according to the value of the current sampling signal VCS during the off period of the lower tube LS. The driving current regulation signal Reg is used to regulate the driving pull-down current when the lower tube LS is turned off. As will be appreciated by those of ordinary skill in the art: the switching off of the lower tube LS requires a process with a certain switching off time. In one embodiment, the time when the lower tube control signal CTL transitions from the first logic state to the second logic state (e.g., the falling edge time) is the starting time when the lower tube starts to turn off.

In one embodiment, the drive current regulation signal Reg includes a logic high low level signal having a first logic state (e.g., logic high) and a second logic state (e.g., logic low). In one embodiment, the active state of the drive current regulation signal Reg is a second logic state (logic low). In one embodiment, the drive current regulation signal Reg is used to reduce the pull-down current when the lower tube LS is off from a first value to a second value when in an active state.

In yet another embodiment, the drive current adjustment signal Reg comprises an analog voltage signal. When the value of the current sampling signal VCS at the turn-off time of the lower tube LS is larger than the current reverse threshold (namely, the lower tube LS flows reverse current), the value of the driving current regulation signal Reg is inversely proportional to the value of the current sampling signal VCS, namely, the larger the amplitude of the current sampling signal VCS is, the smaller the driving current regulation signal Reg is, and further, the smaller the pull-down current of the lower tube is regulated.

The lower tube driving circuit 15 receives the lower tube control signal CTL and the driving current regulation signal Reg, and generates a lower tube driving signal DRVL for driving the lower tube LS to turn on and off according to the lower tube control signal CTL and the driving current regulation signal Reg. When the lower tube LS is controlled to be turned off, the value of the lower tube driving signal DRVL is adjusted by the driving current adjusting signal Reg, which will vary with the value of the current sampling signal VCS.

The upper tube driving circuit 16 receives the upper tube control signal CH, and generates an upper tube driving signal DRVH for driving the upper tube HS to turn on and off according to the upper tube control signal CH.

In the embodiment disclosed in fig. 1, the lower tube driving signal DRVL (i.e., the pull-down current for turning off the lower tube) will vary with the current value flowing through the lower tube, and when the converter operates in the FCCM mode, the pull-down current for controlling the turn-off of the lower tube is automatically reduced, so that the voltage stress of the lower tube is not too large, and the whole converter is ensured to operate in the safe operating area.

Fig. 2 further illustrates a schematic circuit diagram of the lower tube driving current regulating circuit 14 and the lower tube driving circuit 15 according to an embodiment of the present disclosure, and illustrates a schematic circuit block diagram of the PWM control module 11.

Illustratively, the lower tube drive current regulating circuit 14 includes a sample-and-hold module 141 and a comparison circuit 142. The driving current regulation signal Reg includes a first driving current regulation signal Reg1

The sample-and-hold block 141 receives the down tube control signal CTL and the current sampling signal VCS, and samples and holds the value of the current sampling signal VCS at the timing when the down tube control signal CTL changes from the first logic state to the second logic state (i.e., the starting timing when the down tube starts to be turned off), and generates a sample-and-hold signal S/H.

The comparator circuit 142 has a first input terminal, a second input terminal, and an output terminal. A first input end of the sampling hold circuit receives a sampling hold signal S/H; a second input terminal thereof receives a current reversal threshold Vth1; the comparison circuit 12 compares the sample hold signal S/H with the current inversion threshold Vth1, and generates a first drive current adjustment signal Reg1 at the output terminal. Wherein the current reversal threshold Vth1 represents a zero crossing of the current flowing through the lower tube LS. When the S/H signal is less than or equal to the current reversal threshold Vth1, the lower tube LS is represented to flow a positive current; when the sample-and-hold signal S/H is greater than the current inversion threshold Vth1, it represents that the lower tube LS flows the reverse current. The magnitude of the current reversal threshold Vth1 is smaller than the magnitude of the maximum reversal current reference signal Vneg-max. In one embodiment, the current reversal threshold Vth1 includes a voltage signal having a voltage value equal to or approximate to that of the reference ground potential. By "approximately" is meant a voltage value slightly above or below the reference ground potential, with error values typically in the millivolt range. In one embodiment, the error value is determined by the bias voltage of the comparison circuit 142. In one embodiment, the first drive current regulation signal Reg1 is used to reduce the drive signal of the lower tube LS from a first value to a second value. In one embodiment, the comparison circuit 142 comprises a voltage comparator, wherein the first input of the comparison circuit 142 is the inverting input of the voltage comparator; a second input of the comparison circuit 142 is a non-inverting input of the voltage comparator.

With continued reference to fig. 2, the lower tube driving circuit 15 includes an inverter, pull-up tubes P0 and P1, pull-down tubes N0 and N1, and a first adjustment switch tube NM1.

The first end of the pull-up tube P0 is coupled to the supply voltage VCC, the second end of the pull-up tube P0 serves as the output end of the lower tube driving circuit 15, and the control end of the pull-up tube P0 receives the lower tube control signal CTL through the phase inverter. The first end of the pull-up tube P1 is coupled to a power supply voltage VCC, the second end of the pull-up tube P1 is coupled to the second end of the pull-up tube P0, and the control end of the pull-up tube P1 receives a lower tube control signal CTL through the phase inverter. The first end of the pull-down tube N0 is coupled to the second end of the pull-up tube P0, the second end of the pull-down tube N0 is electrically connected to the reference ground, and the control end of the pull-down tube N0 receives a lower tube control signal CTL through the phase inverter. The first end of the pull-down tube N1 is coupled to the second end of the pull-up tube P1, and the control end of the pull-down tube N1 receives a lower tube control signal CTL through the phase inverter. The first end of the first adjustment switch tube NM1 is coupled to the second end of the pull-down tube N1, the second end of the first adjustment switch tube NM1 is electrically connected to the reference ground, and the control end of the first adjustment switch tube NM1 receives the first driving current adjustment signal Reg1.

When the pull-down control signal CTL is logic low, if the first driving current adjustment signal Reg1 is logic high, the pull-up transistors P0 and P1 are turned off, and the pull-down transistors N0 and N1 and the first adjustment switch transistor NM1 are turned on. The gate-source capacitance of the lower tube LS discharges through the pull-down tubes N0 and N1 and the first regulation switch tube NM1, the pull-down current is strong, the value of the pull-down current is ibase + i1, and the lower tube LS is rapidly turned off. When the lower tube control signal CTL is logic low, and at this time, if the first driving current adjustment signal Reg1 is logic low, the pull-up tubes P0 and P1 and the first adjustment switch tube NM1 are both turned off, the pull-down tubes N0 and N1 are turned on, the gate-source capacitance of the lower tube LS is only discharged through the pull-down tube N0, the pull-down current is ibase, the pull-down current is weak, and the lower tube LS will slow down the turn-off speed. Therefore, the voltage stress of the lower pipe is not large, the upper pipe and the lower pipe cannot be directly connected, and the reliability requirement of a safe working area is met. In an embodiment, the lower tube drive signal DRVL comprises a current signal. When the lower tube LS is turned off, the current direction of the lower tube driving signal DRVL is: the down tube driving signal DRVL is a pull-down current of the down tube LS, which flows from the gate of the down tube LS to the driving circuit 15 and then to the reference ground; when the lower tube LS is turned on, the current direction of the lower tube driving signal DRVL is: the current flows from the drive circuit 15 to the gate of the lower tube LS.

In another embodiment, the lower tube drive current regulation circuit 14 may also include other implementations. For example, as shown in fig. 3, the lower tube driving current regulating circuit 14 is illustrated as a combination of the comparing circuit 142 and the first flip-flop 144, and the sample-and-hold block 141 is omitted.

In the example of fig. 3, the comparison circuit 142 further includes an enable terminal EN for receiving a lower tube control signal CTL, the comparison circuit 142 being enabled during a lower tube turn-off period from a time when the lower tube control signal CTL changes from the first logic state to the second logic state. The comparison circuit 142 receives the current sampling signal VCS and the current inversion threshold Vth1, and compares the current sampling signal VCS and the current inversion threshold Vth1 to generate a first comparison signal CA1. The first flip-flop 144 receives the first comparison signal CA1 and outputs the first driving current regulation signal Reg1 when the active edge of the first comparison signal CA1 arrives. The first driving current regulation signal Reg1 is used to turn off the first regulation switch NM1 at the beginning of the active edge time of the first comparison signal CA1.

In yet another embodiment, as shown in FIG. 4, the lower tube driving current regulating circuit 14 may also include a comparison circuit 142 and an amplitude amplifying circuit 146. The comparator circuit 142 is enabled at the time when the lower control signal CTL changes from the first logic state to the second logic state. The comparison circuit 142 receives the current sampling signal VCS and the current inversion threshold Vth1, and compares the current sampling signal VCS and the current inversion threshold Vth1 to generate a first comparison signal CA1. The first comparison signal CA1 is used to enable the amplitude amplifying circuit 146. The amplitude amplifying circuit 146 receives the current sampling signal VCS when enabled, and amplifies the amplitude of the current sampling signal VCS to generate the driving current adjusting signal Reg.

In the embodiment of fig. 4, the driving current regulation signal Reg is an analog signal rather than a logic high/low signal. The driving current regulation signal Reg is sent to the control end of the first regulation switch tube NM1, and when the current sampling signal VCS is greater than the current reversal threshold Vth1, the value of the driving current regulation signal Reg changes with the value change of the current sampling signal VCS. Specifically, the method comprises the following steps: when the first comparison signal CA1 is active, the amplitude amplifying circuit 146 is enabled, and the value of the driving current adjusting signal Reg changes in accordance with the value change of the current sampling signal VCS. The higher the value of the current sampling signal VCS is, the smaller the value of the driving current regulation signal Reg is, the larger the on-resistance of the first regulation switching tube NM1 is, and the smaller the flowing current i1 is; when the first comparison signal CA1 is invalid, the amplitude amplifying circuit 146 controls the driving current adjusting signal Reg to have only one fixed voltage value for turning on the first adjusting switch NM1.

With continued reference to fig. 2, fig. 2 also illustrates a block schematic circuit diagram of the PWM control module 11 according to an embodiment of the present invention. In the example of fig. 2, the PWM control module 11 employs a constant on-time control method including an on-period control module 111, an off-period control module 112, and an RS flip-flop 113.

The on-time control module 111 is configured to generate an on-time control signal TON for controlling the on-time of the upper tube HS. The on-duration control signal TON comprises a logic signal having a high-low logic level, and in one embodiment, the upper tube HS is turned on and turned off when the on-duration control signal TON changes from a logic low to a logic high.

The turn-off duration control module 112 receives the voltage feedback signal VFB and the voltage reference signal, and generates a turn-off duration control signal TOFF according to the voltage feedback signal VFB and the voltage reference signal, wherein the voltage feedback signal VFB represents the output voltage signal VOUT of the switching converter. The off-duration control signal TOFF is used to control the off-duration of the upper tube HS. The off-period control signal TOFF includes a logic signal having a high-low logic level. In one embodiment, when the off duration control signal TOFF changes from logic low to logic high, the upper pipe HS is turned off and turned on, while the lower pipe LS is turned off.

A set terminal S of the RS flip-flop 113 receives the off-duration control signal TOFF, a reset terminal R of the RS flip-flop receives the on-duration control signal TON, the RS flip-flop outputs the tube control signal CH at a first output terminal Q, and at a second output terminal Q

And outputting an inverse signal CL of the upper tube control signal CH.

It will be appreciated by those skilled in the art that the PWM control module 11 in the example of fig. 2 is merely exemplary, and in other embodiments, the switching converter may also use other control methods to generate the upper tube control signal CH and the inverted signal CL. The PWM control module 11 may optionally include different modules according to different control methods.

Next, a detailed circuit principle of the control circuit in another embodiment of the present disclosure will be described with reference to fig. 5. Compared with the embodiment shown in fig. 2, the lower tube driving current adjusting circuit 14 further includes a comparison circuit 143, and the lower tube driving circuit 15 further includes a pair of pull-up tube P2 and pull-down tube N2 and a second adjusting switch tube NM2. The connection mode and circuit principle of the newly added components will be described next. In the example of fig. 4, the drive current adjustment signal Reg includes a first drive current adjustment signal Reg1 and a second drive current adjustment signal Reg2

The comparator circuit 143 has a first input terminal, a second input terminal, and an output terminal. A first input end of the sampling hold circuit receives a sampling hold signal S/H; a second input terminal thereof receives a second threshold Vth2; the comparison circuit 143 compares the sample hold signal S/H with the second threshold Vth2 and generates the second drive current adjustment signal Reg2 at the output terminal. Wherein, the amplitude of the second threshold Vth2 is greater than the amplitude of the current reversal threshold Vth1 and less than the amplitude of the maximum reversal current reference signal Vneg-max, that is: vth1< Vth2< Vneg-max. In one embodiment, the comparison circuit 143 comprises a voltage comparator, wherein the first input of the comparison circuit 143 is an inverting input of the voltage comparator; a second input terminal of the comparison circuit 143 is a non-inverting input terminal of the voltage comparator.

In the lower transistor driving circuit 15, a first end of the pull-up transistor P2 is coupled to the supply voltage VCC, a second end of the pull-up transistor P2 is coupled to a second end of the pull-up transistor P0, and a control end of the pull-up transistor P2 receives the lower transistor control signal CTL through the inverter. The first end of the pull-down tube N2 is coupled to the second end of the pull-up tube P2, and the control end of the pull-down tube N2 receives the lower tube control signal CTL through the inverter. A first end of the second adjustment switch tube NM2 is coupled to a second end of the pull-down tube N2, a control end of the second adjustment switch tube NM2 receives the second driving current adjustment signal Reg2, and a second end of the second adjustment switch tube NM2 is electrically connected to the reference ground.

When the lower control signal CTL is logic low, if the first driving current adjusting signal Reg1 is logic high, the pull-up transistors P0, P1 and P2 are turned off, and the pull-down transistors N0, N1 and N2 and the adjusting switch transistors NM1 and NM2 are turned on. The gate-source capacitance of the lower tube LS discharges through the pull-down tubes N0, N1 and N2 and the regulating switch tubes NM1 and NM2, the pull-down current is strong, the value of the pull-down current is ibase + i1+ i2, and the lower tube LS is rapidly turned off. When the down tube control signal CTL is logic low, and at this time Vth1< ICS < Vth2, the first driving current regulation signal Reg1 is logic low and the second driving current regulation signal Reg2 is logic high, the pull-up tubes P0, P1, and P2 and the first regulation switch tube NM1 are all turned off, the pull-down tubes N0, N1, and N2 and the second regulation switch tube NM2 are turned on, the gate-source capacitance of the down tube LS is discharged through the pull-down tubes N0, N2, and NM2, the pull-down current is ibase + i2, the pull-down current is weakened, and the down tube LS slows down the turn-off speed. When the lower tube control signal CTL is logic low, and at this time Vth2< ICS, the driving current adjusting signals Reg1 and Reg2 are both logic low, the pull-up tubes P0, P1 and P2 and the adjusting switch tubes NM1 and NM2 are all turned off, the pull-down tubes N0, N1 and N2 are turned on, the gate-source capacitance of the lower tube LS will only discharge through the pull-down tube N0, the pull-down current is further reduced to ibase, and the lower tube LS will further slow down the turn-off speed. Therefore, the overall pull-down current of the down tube driving circuit 15 is adaptively varied and inversely proportional to the sampled voltage ICS. The larger the value of the current sampling signal VCS is, the smaller the pull-down current is, the slower the turn-off of the lower tube LS is, and the better the reliability is.

It should be understood by those skilled in the art that although only three pairs of pull-up and pull-down transistors and two adjustment switch transistors NM1 and NM2 are disclosed in the embodiment shown in fig. 5, in order to better adapt the pull-down current to the variation of the current sampling signal VCS, the lower tube driving circuit 15 may include N (N is an integer greater than 3) pairs of pull-up and pull-down transistors and N-1 adjustment switch transistors, which are within the protection scope of the present disclosure.

Likewise, in another embodiment, the lower tube drive current regulation circuit 14 of fig. 5 may also include other implementations. For example, as shown in fig. 6, the lower tube driving current adjusting circuit 14 omits the sample-and-hold block 141, and is illustrated as including a comparison circuit 142, a comparison circuit 143, a first flip-flop 144, and a second flip-flop 145.

In fig. 6, each of the

comparison circuits

142 and 143 has an enable terminal EN for receiving the lower tube control signal CTL, and the

comparison circuits

142 and 143 are enabled at a timing when the lower tube control signal CTL changes from the first logic state to the second logic state. The comparison circuit 142 receives the current sampling signal VCS and the current inversion threshold Vth1, and compares the current sampling signal VCS and the current inversion threshold Vth1 to generate a first comparison signal CA1. The comparison circuit 143 receives the current sampling signal VCS and the second threshold Vth2, and compares the current sampling signal VCS and the second threshold Vth2 to generate a second comparison signal CA2. The first flip-flop 144 receives the first comparison signal CA1 and outputs the first driving current regulation signal Reg1 at the active edge time of the first comparison signal CA1. The second flip-flop 145 receives the second comparison signal CA2 and outputs the second driving current regulation signal Reg2 at the timing of the active edge of the second comparison signal CA2. The first driving current regulation signal Reg1 is also used to turn off the first regulation switch NM1 at the beginning of the active edge time of the first comparison signal CA1. The second driving current regulation signal Reg2 is also used to turn off the second regulation switch NM2 at the beginning of the active edge time of the second comparison signal CA2. The driving current regulation signal Reg includes a first driving current regulation signal Reg1 and a second driving current regulation signal Reg2.

In other embodiments, the embodiment shown in fig. 5 and the embodiment shown in fig. 4 can be combined. For example, while the value of the current i1 flowing through the first adjustment switching tube NM1 is adjusted, the value of the current i2 flowing through the second adjustment switching tube NM2 may also be adjusted by being introduced and cut off. So as not to obscure the focus of the invention, it is not shown or described in detail herein, but is within the scope of the disclosure.

Fig. 7 shows a driving method for driving a lower tube of a switching converter to be turned off according to an embodiment of the invention. The driving method can be used in the switching converter mentioned in the previous fig. 1-6, and the switching converter adopting the driving method operates in FCCM mode under light load. The shut down method comprises steps S1-S3.

Step S1, samples the current flowing through the lower tube and generates a current sampling signal VCS. In one embodiment, sampling the current flowing through the lower tube includes sampling and holding the current flowing through the lower tube at the time of the turn-off of the lower tube and generating a current sample signal VCS (i.e., the current sample signal VCS is also the aforementioned sample-and-hold signal H/S). In yet another embodiment, sampling the current flowing through the downtube includes sampling the current flowing through the downtube during shutdown of the downtube. In one embodiment, the lower pipe turn-off time refers to a starting time when the lower pipe starts to turn off, for example, a time (e.g., a falling edge time) when the lower pipe control signal CTL transitions from the first logic state to the second logic state is the lower pipe turn-off time; the lower tube turn-off period refers to a time between a start time and an end time when the lower tube starts to turn off.

And step S2, comparing the current sampling signal VCS with a current reverse threshold Vth1 during the period of the lower tube turn-off, and judging whether the current sampling signal VCS is greater than the current reverse threshold Vth1. If the current sampling signal VCS is larger than the current reverse threshold Vth1, continuing to step S3; if the current sampling signal VCS is less than the current inversion threshold Vth1, step S2 is continued.

Step S3, the lower tube driving signal DRVL is decreased from the first value to the second value. In one embodiment, the lower tube drive signal DRVL includes a drive current that drives the lower tube closed. In one embodiment, the second value is inversely proportional to the current sample signal VCS, and the larger the current sample signal VCS, the smaller the second value.

Further, in step S2, if the current sampling signal VCS is less than the current reversal threshold Vth1, the down tube driving signal DRVL is kept unchanged at the first value in addition to continuing to compare the current sampling signal VCS with the current reversal threshold Vth1.

In a further embodiment, the shut down method further comprises steps S4-S5.

Step S4, comparing the current sampling signal VCS with the second threshold signal Vth2, and determining whether the current sampling signal VCS is greater than the second threshold Vth2. If the current sampling signal VCS is greater than the second threshold Vth2, continue to step S5; if the current sampling signal VCS is less than the second threshold Vth2, step S4 is continued. In one embodiment, the second threshold Vth2 is greater than the current inversion threshold Vth1.

In step S5, the lower tube driving signal DRVL is decreased from the second value to the third value. In one embodiment, the second value is greater than the third value. In one embodiment, the third value is inversely proportional to the current sampling signal VCS, and the larger the current sampling signal VCS, the smaller the third value.

Further, in step S4, if the current sampling signal VCS is less than the second threshold Vth2, the down tube driving signal DRVL is kept unchanged at the second value in addition to continuing to compare the current sampling signal VCS with the second threshold Vth2.

It should be noted that although the above embodiments are described in detail based on BUCK converters, the control circuit and method disclosed above can also be used in other suitable topologies for preventing the upper pipe and the lower pipe from going through when the lower pipe is turned off. While the present invention has been described with reference to several exemplary embodiments, it is understood by those of ordinary skill in the relevant art that the terminology used in the embodiments disclosed is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Furthermore, various modifications in form and detail of the disclosed embodiments of the invention may occur to those skilled in the art without departing from the spirit and concept of the invention and, therefore, such modifications are intended to be included within the scope of the present invention as defined in the appended claims and their equivalents.

Claims

1. A drive control circuit for a switching converter, the switching converter including an upper tube and a lower tube, the drive control circuit comprising:

the loop control module is used for receiving a voltage feedback signal and a current sampling signal and generating an upper tube control signal and a lower tube control signal according to the voltage feedback signal and the current sampling signal, wherein the voltage feedback signal represents an output voltage signal of the switching converter, and the current sampling signal represents current flowing through a lower tube;

the lower tube driving current regulating circuit is used for receiving the current sampling signal and the lower tube control signal and generating a driving current regulating signal according to the current sampling signal and the lower tube control signal; and

and the lower tube driving circuit is used for receiving a lower tube control signal and a driving current adjusting signal and generating a lower tube driving signal according to the lower tube control signal and the driving current adjusting signal, wherein the lower tube driving signal is used for driving the lower tube to be switched on and off, and during the period of switching off the lower tube, if the current sampling signal is larger than a current reversal threshold value, the driving current adjusting signal reduces the lower tube driving signal from a first value to a second value.

2. The drive control circuit of claim 1, wherein the drive current adjustment signal decreases the down tube drive signal from a second value to a third value if the current sample signal is greater than a second threshold during the down tube turn off, wherein the second threshold is greater than the current reversal threshold.

3. The drive control circuit of claim 1, wherein the second value is inversely proportional to the current sample signal.

4. The drive control circuit of claim 1 wherein the drive current adjustment signal comprises a first drive current adjustment signal, the drive current adjustment circuit comprising:

the sampling and holding module is used for receiving the lower tube control signal and the current sampling signal, sampling and holding the value of the current sampling signal at the moment when the lower tube control signal is changed from a first logic state to a second logic state, and generating a sampling and holding signal; and

and the first comparison circuit is used for receiving the sampling and holding signal and comparing the sampling and holding signal with the current reversal threshold value so as to generate a first driving current regulating signal.

5. The drive control circuit of claim 1 wherein the drive current adjustment signal comprises a first drive current adjustment signal, the drive current adjustment circuit comprising:

the first comparison circuit is provided with a first input end, a second input end, an enable end and an output end, the first input end of the first comparison circuit receives a current sampling signal, the second input end of the first comparison circuit receives a current reverse threshold value, the enable end of the first comparison circuit receives a lower tube control signal, and the first comparison circuit compares the current sampling signal with the current reverse threshold value to generate a first comparison signal after being enabled by the lower tube control signal; and

the first flip-flop is configured to receive the first comparison signal and generate a first driving current adjustment signal when an active edge of the first comparison signal CA1 arrives.

6. The drive control circuit of claim 1, wherein the drive current adjustment signal comprises a first drive current adjustment signal, the drive current adjustment circuit further comprising:

the amplitude amplifying circuit is provided with an enabling end, an input end and an output end, the enabling end of the amplitude amplifying circuit receives a first comparison signal, the input end of the amplitude amplifying circuit receives a current sampling signal, and the amplitude amplifying circuit amplifies the amplitude of the current sampling signal and generates a first driving current adjusting signal at the output end after being enabled by the first comparison signal.

7. The drive control circuit of claim 4 wherein the drive current adjustment signal comprises a first drive current adjustment signal and a second drive current adjustment signal, the drive current adjustment circuit further comprising:

and the second comparison circuit is used for receiving the sampling and holding signal and comparing the sampling and holding signal with a second threshold value to generate a second driving current regulating signal, wherein the second threshold value is greater than the current reversal threshold value.

8. The drive control circuit of one of claims 4-6, wherein the down tube drive circuit comprises:

the first end of the first pull-up tube is coupled with a power supply voltage, the second end of the first pull-up tube is used as the output end of the lower tube driving circuit, and the control end of the first pull-up tube receives a lower tube control signal through the phase inverter;

a first end of the second pull-up tube is coupled with a power supply voltage, a second end of the second pull-up tube is coupled with a second end of the first pull-up tube, and a control end of the second pull-up tube receives a lower tube control signal through a phase inverter;

the first end of the first pull-down tube is coupled with the second end of the first pull-up tube, the second end of the first pull-down tube is electrically connected with a reference ground, and the control end of the first pull-down tube receives a lower tube control signal through the phase inverter;

a first end of the second pull-down tube is coupled with a second end of the second pull-up tube, and a control end of the second pull-down tube receives a lower tube control signal through a phase inverter; and

the first end of the first regulating switch tube is coupled to the second end of the second pull-down tube, the second end of the first regulating switch tube is electrically connected to the reference ground, and the control end of the first regulating switch tube receives the first driving current regulating signal.

9. The drive control circuit of claim 7, wherein the down tube drive circuit comprises:

a first end of the second pull-up tube is coupled with a power supply voltage, a second end of the second pull-up tube is coupled with a second end of the first pull-up tube, and a control end of the second pull-up tube receives a lower tube control signal through the phase inverter;

a first end of the third pull-up tube is coupled with a power supply voltage, a second end of the third pull-up tube is coupled with a second end of the first pull-up tube, and a control end of the third pull-up tube receives a lower tube control signal through a phase inverter;

the first end of the first pull-down tube is coupled with the second end of the first pull-up tube, the second end of the first pull-down tube is electrically connected with the reference ground, and the control end of the first pull-down tube receives a lower tube control signal through the phase inverter;

a first end of the second pull-down tube is coupled with a second end of the second pull-up tube, and a control end of the second pull-down tube receives a lower tube control signal through a phase inverter;

a first end of the third pull-down tube is coupled with a second end of the third pull-up tube, and a control end of the third pull-down tube receives a lower tube control signal through a phase inverter;

the first end of the first adjusting switch tube is coupled with the second end of the second pull-down tube, the second end of the first adjusting switch tube is electrically connected with the reference ground, and the control end of the first adjusting switch tube receives a first driving current adjusting signal; and

and a first end of the second regulating switch tube is coupled to a second end of the third pull-down tube, a second end of the second regulating switch tube is electrically connected to the reference ground, and a control end of the second regulating switch tube receives a second driving current regulating signal.

10. The drive control circuit of claim 1, wherein the loop control module comprises:

the PWM control module is used for receiving the voltage feedback signal and generating an upper tube control signal and an inverted signal of the upper tube control signal according to the voltage feedback signal;

the third comparison circuit is used for receiving the current sampling signal and the maximum reverse current reference signal, comparing the current sampling signal with the maximum reverse current reference signal and further generating a reverse current indication signal, wherein the maximum reverse current reference signal is greater than a current reverse threshold value; and

and the logic circuit is used for receiving the inverted signal and the inverted current indicating signal of the upper tube control signal and carrying out logic operation on the inverted signal and the inverted current indicating signal of the upper tube control signal to generate a lower tube control signal.

11. A driving method applied to a lower tube of a switching converter comprises the following steps:

sampling a current flowing through a lower tube and generating a current sampling signal;

during the lower tube turn-off period, comparing the current sampling signal with a current reverse threshold; and

if the current sampling signal is greater than the current reversal threshold, the drive signal that drives the lower tube closed is reduced from a first value to a second value.

12. The driving method according to claim 11, characterized in that the driving method further comprises:

during the lower tube turn-off period, comparing the current sampling signal with a second threshold value, wherein the second threshold value is greater than a current reversal threshold value; and

and if the current sampling signal is larger than the second threshold value, reducing the driving signal for driving the lower tube to be closed from the second value to a third value.