TWI663749B - Light emitting apparatus and manufacturing method thereof - Google Patents

Light emitting apparatus and manufacturing method thereof Download PDF

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TWI663749B
TWI663749B TW106144714A TW106144714A TWI663749B TW I663749 B TWI663749 B TW I663749B TW 106144714 A TW106144714 A TW 106144714A TW 106144714 A TW106144714 A TW 106144714A TW I663749 B TWI663749 B TW I663749B
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light
emitting element
layer
conductive layer
emitting
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TW201810722A (en
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謝明勳
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晶元光電股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Abstract

本發明提供一種發光裝置，包含一發光結構，發光結構包含一第一導電層、一活性層、與一第二導電層，活性層位於第一導電層上以做為一發光層，第二導電層位於活性層上；一第一金屬層，位於發光結構上並電性接觸第一導電層；一第二金屬層，位於發光結構上並電性接觸第二導電層；其中第一金屬層或第二金屬層具有一粗化表面，粗化表面的表面粗糙度介於0.5微米至5微米之間。The invention provides a light-emitting device including a light-emitting structure. The light-emitting structure includes a first conductive layer, an active layer, and a second conductive layer. The active layer is located on the first conductive layer as a light-emitting layer, and the second conductive layer A layer is located on the active layer; a first metal layer is located on the light emitting structure and electrically contacts the first conductive layer; a second metal layer is located on the light emitting structure and is electrically contacted to the second conductive layer; wherein the first metal layer or The second metal layer has a roughened surface, and the roughened surface has a surface roughness between 0.5 μm and 5 μm.

Description

發光裝置及其製作方法Light emitting device and manufacturing method thereof

本發明係一種發光元件及其製作方法以及一種發光元件陣列及其製作方法，特別是一種發光裝置及其製作方法。The invention relates to a light-emitting element and a manufacturing method thereof, and a light-emitting element array and a manufacturing method thereof, particularly a light-emitting device and a manufacturing method thereof.

習知發光二極體（LED）封裝技術係先在晶片座（sub-mount）上點膠，再將發光二極體晶片固定於晶片座上，進而形成一發光二極體元件，此步驟稱為固晶（Die Bonding）。固晶膠材主要為具導電性的銀膠或其他非導電性環氧樹脂。之後將發光二極體元件組合於電路板上。覆晶（flip chip）式的發光二極體係使二極體結構中的p型半導體導電層與n型半導體導電層，暴露於同一側，以能將陰、陽極電極製作於二極體結構的同一側上，因而可直接將設置有陰、陽極電極的發光二極體結構覆置於一錫料（solder）上。如此，能免除採用傳統金屬拉線（wire bonding）的需求。然而習知之覆晶式發光二極體仍需透過切割、固晶等封裝步驟，才能與電路板連結。因此，若覆晶式發光二極體的電極具有足夠大的接觸面積，便能夠省略習知之封裝步驟。The conventional light-emitting diode (LED) packaging technology is to first dispense on a sub-mount, and then fix the light-emitting diode wafer to the wafer holder to form a light-emitting diode element. This step is called It is die bonding. Solid crystal adhesives are mainly conductive silver adhesives or other non-conductive epoxy resins. The light emitting diode element is then combined on the circuit board. A flip chip type light emitting diode system exposes the p-type semiconductor conductive layer and the n-type semiconductor conductive layer in the diode structure to the same side, so that the cathode and anode electrodes can be fabricated on the diode structure. On the same side, the light emitting diode structure provided with the cathode and anode electrodes can be directly covered on a solder. In this way, the need to use traditional metal wire bonding can be eliminated. However, the conventional flip-chip light-emitting diodes still need to be connected to the circuit board through packaging steps such as cutting and die bonding. Therefore, if the electrode of the flip-chip light-emitting diode has a sufficiently large contact area, the conventional packaging step can be omitted.

一般傳統LED的操作電流約為數十至數百個毫安培（mA），但亮度往往不足以應付一般照明所需。若組合大量的LED以提高亮度，則LED照明元件的體積將增加而導致市場上之競爭性降低。因此，提昇單顆LED之晶粒亮度，成為必然之趨勢。然而，當LED朝向高亮度發展時，單一LED的操作電流及功率增加為傳統LED的數倍至數百倍，例如，一個高亮度的LED的操作電流約為數百毫安培至數個安培，使得LED所產生的熱問題不容忽視。LED的性能會因為”熱”而降低，例如熱效應會影響LED的發光波長，半導體特性也因熱而產生亮度衰減，更嚴重時甚至造成元件損壞。因此，高功率LED如何散熱成為LED的重要議題。Generally, the operating current of traditional LEDs is about tens to hundreds of milliamperes (mA), but the brightness is often insufficient to meet the requirements of general lighting. If a large number of LEDs are combined to increase the brightness, the volume of the LED lighting element will increase and the competition in the market will decrease. Therefore, it is an inevitable trend to increase the brightness of the crystals of a single LED. However, when LEDs are moving towards high brightness, the operating current and power of a single LED increase several times to hundreds of times that of traditional LEDs. For example, the operating current of a high brightness LED is about several hundred milliamps to several amps. Makes the heat problem that LED produces cannot be ignored. The performance of LEDs will be reduced due to "heat". For example, thermal effects will affect the light emitting wavelength of LEDs, and semiconductor characteristics will also cause brightness attenuation due to heat, and even more serious, even cause component damage. Therefore, how to dissipate heat in high-power LEDs has become an important issue for LEDs.

美國專利申請號2004/0188696以及2004/023189（為2004/0188696之分割案）中分別揭示了一種使用表面黏著技術（Surface Mount Technology, SMT）的LED封裝結構與方法，其中每一封裝結構含有一LED晶片。每一LED晶片先以覆晶的形式，藉由凸塊（bonding bump）黏著於在一晶片座（sub-mount）之前側（front side）上。在晶片座中具有預先鑿出之開孔陣列，並填以金屬以形成通道陣列（via array）。此晶片的電極可藉由此通道陣列連接至晶片座的具有錫料的後側（back side）。此通道陣列亦可作為LED晶片之散熱路徑。在每一LED晶片與次基板黏著之後，再將次基板切割，以進行後續之LED封裝。US Patent Application Nos. 2004/0188696 and 2004/023189 (the division of 2004/0188696) respectively disclose a LED package structure and method using Surface Mount Technology (SMT), where each package structure contains a LED chip. Each LED chip is first adhered to a front side of a sub-mount by means of a bonding bump in the form of a flip chip. The wafer holder has an array of pre-cut holes and is filled with metal to form a via array. The electrodes of the wafer can be connected to the back side of the wafer holder with tin by the array of channels. This channel array can also be used as a heat dissipation path for the LED chip. After each LED chip is adhered to the sub substrate, the sub substrate is cut to perform subsequent LED packaging.

然而，在美國專利申請號2004/0188696以及2004/023189中之晶片座，需鑿出填以金屬的通道陣列（via array），增加製程成本。此外，每一LED晶片黏著於晶片座的步驟，也會增加製作的複雜度。因此，若能具有一種發光二極體，不需晶片座，亦具有良好的散熱路徑，可在市場上具有優勢。However, in the wafer holders in US Patent Application Nos. 2004/0188696 and 2004/023189, a via array filled with metal needs to be cut out, which increases the manufacturing cost. In addition, the step of adhering each LED chip to the wafer holder will also increase the complexity of fabrication. Therefore, if it can have a light-emitting diode, there is no need for a chip holder, and it has a good heat dissipation path, which can have advantages in the market.

本發明揭示一種發光裝置的製作方法，其包含步驟：提供一第一載板，其具有複數第一金屬接觸；提供一基材；形成複數發光疊層以及複數溝槽於基材上，其中複數發光疊層藉由複數溝槽與彼此分離；連接複數發光疊層與第一載板；形成一封裝材料共同地位於複數發光疊層上；以及切割第一載板以及封裝材料以形成複數晶粒級的發光元件單元。The invention discloses a method for manufacturing a light-emitting device, which comprises the steps of: providing a first carrier plate having a plurality of first metal contacts; providing a substrate; forming a plurality of light-emitting stacks and a plurality of grooves on the substrate, wherein the plurality of The light emitting stack is separated from each other by a plurality of trenches; connecting the plurality of light emitting stacks with the first carrier board; forming a packaging material commonly located on the plurality of light emitting stacks; and cutting the first carrier board and the packaging material to form a plurality of crystal grains Light emitting element unit.

於本發明之一實施例中，發光裝置的製作方法更包含形成一第一波長轉換層於一第一發光疊層上，第一波長轉換層將第一發光疊層發出的光轉換為一第一光；形成一第二波長轉換層於一第二發光疊層上，第二波長轉換層將第二發光疊層發出的光轉換為一第二光；以及提供一個第三發光疊層，第三發光疊層之上方並未有任何波長轉換材料，其中第一發光疊層、第二發光疊層以及第三發光疊層發出的光為藍光，第一光為綠光且第二光為紅光。In one embodiment of the present invention, the method for manufacturing a light emitting device further includes forming a first wavelength conversion layer on a first light emitting stack. The first wavelength conversion layer converts light emitted by the first light emitting stack into a first light emitting stack. A light; forming a second wavelength conversion layer on a second light emitting stack, the second wavelength conversion layer converts the light emitted from the second light emitting stack into a second light; and providing a third light emitting stack, the first There is no wavelength conversion material above the three light-emitting stacks. The light emitted by the first, second, and third light-emitting stacks is blue, the first light is green, and the second light is red. Light.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。在圖式中，元件之形狀或厚度可擴大或縮小。需特別注意的是，圖中未繪示或描述之元件，可以是熟習此技藝之人士所知之形式。本發明所列舉之各實施例僅用以說明本發明，並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings. In the drawings, the shape or thickness of the element can be enlarged or reduced. It is important to note that components not shown or described in the figures may be in a form known to those skilled in the art. The embodiments listed in the present invention are only used to illustrate the present invention and are not intended to limit the scope of the present invention. Any obvious modification or change made by anyone to the present invention will not depart from the spirit and scope of the present invention.

參照第1A第至第1E圖，係為依照本發明實施例之一種發光元件的製作方法流程各階段所對應之剖面圖。在第1A圖中，首先形成一發光結構100，其包含一基材11、一第一導電層102以做為一包覆層、一活性層104位於第一導電層102上以作為一發光層、一第二導電層106於此活性層104上以作為另一包覆層。較佳地，如第1A圖所示，一電極或接合墊（bonding pad）107a位於第一導電層102之暴露的部分上，另一電極或接合墊107b位在第二導電層106上。電極或接合墊107a與107b之材料（例如鋁）與製作方法應為習此技藝者所熟知，在此不加贅述。此外，在一實施例中，發光結構100更包含一保護層（passivation layer）120，以保護此發光結構100。此保護層120的材料（例如二氧化矽）與製作方法亦為習此技藝者所熟知，在此加不贅述。Referring to FIGS. 1A to 1E, it is a cross-sectional view corresponding to each stage of a method of manufacturing a light emitting device according to an embodiment of the present invention. In FIG. 1A, a light-emitting structure 100 is first formed, which includes a substrate 11, a first conductive layer 102 as a cladding layer, and an active layer 104 on the first conductive layer 102 as a light-emitting layer. A second conductive layer 106 is used as another cladding layer on the active layer 104. Preferably, as shown in FIG. 1A, one electrode or bonding pad 107 a is located on the exposed portion of the first conductive layer 102, and the other electrode or bonding pad 107 b is located on the second conductive layer 106. The materials (such as aluminum) and manufacturing methods of the electrodes or the bonding pads 107a and 107b should be well known to those skilled in the art, and will not be repeated here. In addition, in one embodiment, the light emitting structure 100 further includes a passivation layer 120 to protect the light emitting structure 100. The material (such as silicon dioxide) and manufacturing method of the protective layer 120 are also well known to those skilled in the art, and will not be described in detail here.

在一實施例中，第一導電層102為一n型半導體導電層，而第二導電層106為一p型半導體導電層。n型半導體導電層102、p型半導體導電層106為任何習知或未來中可見者之半導體材料，較佳者為Ⅲ－Ⅴ（三/五）族化合物半導體，例如氮化鋁鎵銦（Alx Gay ln（ 1 － x － y ） N）或磷化鋁鎵銦（Alx Gay In（ 1-x-y ） P），其中0≦x≦1，0≦y≦1，0≦x＋y≦1，並視情況進一步被p/n型摻質所摻雜。而活性層104亦可使用習知之半導體材料與結構，例如材料可為氮化鋁鎵銦（AlxGayln（ 1 － x － y ） N）或磷化鋁鎵銦（Alx Gay ln（ 1 － x － y ） P）等，而結構可為單量子井（Single Quantum Well，SQW）、多重量子井（Multiple Quantum Well， MQW）與雙異質（Double Heterosture，DH），其發光原理與機制係為習知之技術，在此不再贅述。此外，發光結構100可藉由有機金屬化學氣相沉積（MOCVD）、分子束磊晶成長（molecular beam epitaxy， MBE）製程、或氫化物氣相磊晶成長（hydride vapor phase epitaxy，HVPE）製程等製作。In one embodiment, the first conductive layer 102 is an n-type semiconductor conductive layer, and the second conductive layer 106 is a p-type semiconductor conductive layer. The n-type semiconductor conductive layer 102 and the p-type semiconductor conductive layer 106 are any conventional or visible semiconductor materials, preferably a III-V (three / five) group compound semiconductor, such as aluminum gallium indium (Al x Ga y ln ( 1 - x - y ) N) or aluminum gallium indium phosphide (Al x Ga y In ( 1-xy ) P), where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x ＋ y ≦ 1, and optionally further doped with p / n type dopants. The active layer 104 and the semiconductor material may also be used with the conventional structure, the material may be, for example, aluminum gallium indium nitride (AlxGayln (1 - x - y ) N) or aluminum gallium indium phosphide (Al x Ga y ln (1 - x - y) P) and the like, and the structure may be a single quantum well (single quantum well, SQW), multiple quantum well (multiple quantum well, MQW) and double heterostructure (double Heterosture, DH), which emission principle and mechanism system according to the prior Known technologies are not repeated here. In addition, the light emitting structure 100 may be processed by an organic metal chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a hydride vapor phase epitaxy (HVPE) process. Production.

接著，如第1B圖所示，形成一第一介電層122於此發光結構100上。較佳地，第一介電層122為一透明介電層，且其厚度D≦20μm，藉此有效地傳導發光結構100所產生之熱。第一介電層122的材料可為二氧化矽（SiO2 ）、氮化矽（Si3 N4 ）、或是其組合，而其可藉由MOCVD或是MBE製作。Next, as shown in FIG. 1B, a first dielectric layer 122 is formed on the light emitting structure 100. Preferably, the first dielectric layer 122 is a transparent dielectric layer and has a thickness D ≦ 20 μm, thereby effectively conducting the heat generated by the light emitting structure 100. The material of the first dielectric layer 122 may be silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or a combination thereof, and it may be made by MOCVD or MBE.

之後，參見第1C圖，形成一第二介電層140於第一介電層122上。第二介電層140的材料可為二氧化矽、氮化矽、聚亞醯胺（polyimide）、 BCB（bisbenzocyclobutene）、以及光阻劑（photoresist）中選擇其一。較佳地，第二介電層140之厚度約25μm，係藉由一印刷技術而形成。After that, referring to FIG. 1C, a second dielectric layer 140 is formed on the first dielectric layer 122. The material of the second dielectric layer 140 may be one of silicon dioxide, silicon nitride, polyimide, BCB (bisbenzocyclobutene), and photoresist. Preferably, the thickness of the second dielectric layer 140 is about 25 μm, which is formed by a printing technique.

參見第1D圖，在第二介電層140形成之後，形成金屬層160，金屬層160位於發光結構100上並電性接觸第一導電層102，且部分之金屬層160位於第一介電層122上；以及形成金屬層162，金屬層162位於發光結構100上並電性接觸第二導電層106，且部分之金屬層162位於第一介電層122上。其中，第一介電層122與第二介電層140隔絕金屬層160與金屬層162。金屬層160或金屬層162的材料可選自金（Au）、鋁（Al）、銀（Ag）、其等之合金、或其他習知的金屬。較佳地，金屬層160與金屬層162係藉由一印刷技術或電鍍而共同形成。經由上述步驟，即完成發光元件10。Referring to FIG. 1D, after the second dielectric layer 140 is formed, a metal layer 160 is formed. The metal layer 160 is located on the light emitting structure 100 and electrically contacts the first conductive layer 102, and part of the metal layer 160 is located on the first dielectric layer. 122; and forming a metal layer 162, the metal layer 162 is located on the light emitting structure 100 and electrically contacts the second conductive layer 106, and a part of the metal layer 162 is located on the first dielectric layer 122. The first dielectric layer 122 and the second dielectric layer 140 isolate the metal layer 160 and the metal layer 162. The material of the metal layer 160 or the metal layer 162 may be selected from gold (Au), aluminum (Al), silver (Ag), alloys thereof, or other conventional metals. Preferably, the metal layer 160 and the metal layer 162 are jointly formed by a printing technique or electroplating. Through the above steps, the light-emitting element 10 is completed.

在一實施例中，第一介電層122為一透明介電層，而第一介電層122與金屬層160及/或金屬層162之接觸面供反射發光結構100發出之光，因而可有效提升發光元件10之光輸出強度。此外，金屬層160及/或金屬層162亦作為發光結構100之散熱路徑，當金屬層160及金屬層162具有較大的接觸面積A1、A2，也有助於有效且快速的散熱。In one embodiment, the first dielectric layer 122 is a transparent dielectric layer, and the contact surface between the first dielectric layer 122 and the metal layer 160 and / or the metal layer 162 is used for the light emitted by the reflective light-emitting structure 100, so that Effectively increase the light output intensity of the light emitting element 10. In addition, the metal layer 160 and / or the metal layer 162 also serve as a heat dissipation path of the light emitting structure 100. When the metal layer 160 and the metal layer 162 have large contact areas A1 and A2, it also contributes to effective and rapid heat dissipation.

參見第1E圖，形成如同第1D圖所示之結構之後，發光元件的製作方法更包含一移除基材11之步驟，藉以暴露出第一導電層102。基材11可以例如是一藍寶石基材或是砷化鎵基材。當基材11為藍寶石基材，可藉由準分子雷射（excimer laser）移除基材11。準分子雷射可以為一具有能量為400毫焦耳/平方公分（mJ/cm2 ）、波長為248奈米以及脈衝寬度（pulse width）為38奈秒（ns）的氟化氪（KrF）準分子雷射。在較高的溫度中，例如60℃，當準分子雷射照射在藍寶石基材上時，藍寶石基材被移除以暴露出第一導電層102。另外，當基材11為砷化鎵基材，一比例為1:35之氨水（NH4 OH）與過氧化氫（H2 O2 ）的溶液或是一比例為5:3:5之磷酸（H3 PO4 ）、過氧化氫（H2 O2 ）與水的溶液可以用於移除砷化鎵基材，藉以暴露出第一導電層102。Referring to FIG. 1E, after the structure shown in FIG. 1D is formed, the method for manufacturing the light-emitting element further includes a step of removing the substrate 11 to expose the first conductive layer 102. The substrate 11 may be, for example, a sapphire substrate or a gallium arsenide substrate. When the substrate 11 is a sapphire substrate, the substrate 11 can be removed by an excimer laser. An excimer laser can be a KrF standard with an energy of 400 millijoules per square centimeter (mJ / cm 2 ), a wavelength of 248 nanometers, and a pulse width of 38 nanoseconds (ns). Molecular laser. At higher temperatures, such as 60 ° C., when an excimer laser is irradiated on the sapphire substrate, the sapphire substrate is removed to expose the first conductive layer 102. In addition, when the substrate 11 is a gallium arsenide substrate, a ratio of 1:35 ammonia water (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) or a ratio of 5: 3: 5 phosphoric acid A solution of (H 3 PO 4 ), hydrogen peroxide (H 2 O 2 ), and water can be used to remove the gallium arsenide substrate, thereby exposing the first conductive layer 102.

移除基材11之後，發光元件的製作方法更包含粗化第一導電層102的表面102a。例如，當第一導電層102為一氮化鋁鎵銦（Alx Gay ln（ 1 － x － y ） N）層，其表面102a可以藉由蝕刻液粗化，蝕刻液可例如為氫氧化鉀（KOH）溶液。此外，當第一導電層102為一磷化鋁鎵銦（Alx Gay In（ 1-x-y ） P）層，一鹽酸（HCl）以及磷酸的溶液可用於粗化第一導電層102的表面102a，粗化時間可例如為15秒。第一導電層102的粗化表面102a可降低發生全反射的可能性，藉以增加發光元件的光取出效率。After the substrate 11 is removed, the method for manufacturing the light emitting device further includes roughening the surface 102 a of the first conductive layer 102. For example, when the first conductive layer 102 is an aluminum gallium indium (Al x Ga y ln ( 1 - x - y ) N) layer, the surface 102a thereof may be roughened by an etching solution, and the etching solution may be, for example, hydroxide Potassium (KOH) solution. In addition, when the first conductive layer 102 is an Al x Ga y In ( 1-xy ) P layer, a solution of hydrochloric acid (HCl) and phosphoric acid may be used to roughen the surface of the first conductive layer 102. 102a, the roughening time may be, for example, 15 seconds. The roughened surface 102a of the first conductive layer 102 can reduce the possibility of total reflection, thereby increasing the light extraction efficiency of the light emitting element.

第1E圖所示之發光元件10以及第1D圖所示之發光元件10a、10b、10c提供足夠大的接觸面積（較佳為至少佔據發光元件10截面積之一半），發光元件10a、10b、10c係利用錫料（solder）12直接與電路載板13連接，而不需要固晶（Die Bonding）與金屬拉線（Wire Bonding）等過程。在一實施例中，發光元件10a發出紅光（R）、發光元件10b發出綠光（G）、發光元件10c發出藍光（B），三者分別與電路載板13連接以供影像顯示之用途。The light-emitting element 10 shown in FIG. 1E and the light-emitting elements 10a, 10b, and 10c shown in FIG. 1D provide a sufficiently large contact area (preferably occupying at least a half of the cross-sectional area of the light-emitting element 10). The light-emitting elements 10a, 10b, The 10c series uses a solder 12 to directly connect to the circuit carrier board 13 without the need for processes such as die bonding and wire bonding. In one embodiment, the light-emitting element 10a emits red light (R), the light-emitting element 10b emits green light (G), and the light-emitting element 10c emits blue light (B). The three are respectively connected to the circuit substrate 13 for image display purposes. .

參照第2A圖至第2D圖，係為依照本發明實施例之一種發光元件陣列的製作方法流程各階段所對應之剖面圖。在第2A圖中，首先提供一基材21，例如一藍寶石（Sapphire）基材、砷化鎵（GaAs）基材、或是其他習此技藝者所熟知之基材與其組合。接著，在基材21上形成複數個發光結構200a、200b、與200c。發光結構200a、200b、與200c的材料與製作方法可參考第1A圖至第1D圖的發光結構100。相似地，發光結構200a、200b、與200c可藉由有機金屬化學氣相沉積（MOCVD）製程、分子束磊晶成長（molecular beam epitaxy，MBE）製程、或氫化物氣相磊晶成長（hydride vapor phase epitaxy， HVPE）製程等製作。Referring to FIG. 2A to FIG. 2D, it is a cross-sectional view corresponding to each stage of a method of manufacturing a light-emitting element array according to an embodiment of the present invention. In FIG. 2A, a substrate 21 is first provided, such as a sapphire substrate, a gallium arsenide (GaAs) substrate, or other substrates known to those skilled in the art and combinations thereof. Next, a plurality of light emitting structures 200a, 200b, and 200c are formed on the substrate 21. For materials and manufacturing methods of the light-emitting structures 200a, 200b, and 200c, reference may be made to the light-emitting structure 100 in FIGS. 1A to 1D. Similarly, the light emitting structures 200a, 200b, and 200c can be processed by an organic metal chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, or a hydride vapor epitaxial growth (hydride vapor). phase epitaxy (HVPE).

接著，如第2B圖所示，形成一介電層222a於發光結構200a上、形成一介電層222b於發光結構200b上、形成一介電層222c於發光結構200c上。較佳地，如同第1B圖所示之介電層122，介電層222a、222b、222c為一透明介電層，且其厚度D≦20μm，藉此有效地傳導發光結構200a、200b、200c所產生之熱。介電層222a、222b、222c的材料可為二氧化矽、氮化矽或其等之組合，而其可藉由MOCVD或是MBE製作。Next, as shown in FIG. 2B, a dielectric layer 222a is formed on the light emitting structure 200a, a dielectric layer 222b is formed on the light emitting structure 200b, and a dielectric layer 222c is formed on the light emitting structure 200c. Preferably, like the dielectric layer 122 shown in FIG. 1B, the dielectric layers 222a, 222b, and 222c are a transparent dielectric layer, and the thickness D ≦ 20 μm, thereby effectively conducting the light emitting structures 200a, 200b, and 200c. The heat generated. The materials of the dielectric layers 222a, 222b, and 222c can be silicon dioxide, silicon nitride, or a combination thereof, and they can be made by MOCVD or MBE.

之後，參見第2C圖，形成介電層240a於介電層222a上、形成介電層240b於介電層222b上、形成介電層240c於介電層222c上。介電層240a、240b、240c的材料可為二氧化矽、氮化矽、聚亞醯胺（polyimide）、BCB（bisbenzocyclobutene）、以及光阻劑（photoresist）中選擇其一。較佳地，如同第1C圖所示之介電層第二140，介電層240a、240b、240c之厚度分別約為25μm，且係藉由一印刷技術而形成。在一實施例中，在發光結構200a、200b、200c之間，更形成一介電層280，藉以電絕緣發光元件20a、20b、與20c（如第2D圖所示）。在此實施例中，介電層280之材料與介電層240a、240b、240c的材料相同，例如聚亞醯胺，並利用一製程（例如一印刷技術）與介電層240a、240b、240c共同形成。在另一實施例中，介電層280之材料不同於介電層240a、240b、240c的材料，且藉由不同製程形成。Then, referring to FIG. 2C, a dielectric layer 240a is formed on the dielectric layer 222a, a dielectric layer 240b is formed on the dielectric layer 222b, and a dielectric layer 240c is formed on the dielectric layer 222c. The materials of the dielectric layers 240a, 240b, and 240c may be selected from silicon dioxide, silicon nitride, polyimide, BCB (bisbenzocyclobutene), and photoresist. Preferably, as in the second dielectric layer 140 shown in FIG. 1C, the thicknesses of the dielectric layers 240a, 240b, and 240c are about 25 μm, respectively, and are formed by a printing technique. In one embodiment, a dielectric layer 280 is formed between the light-emitting structures 200a, 200b, and 200c, so as to electrically insulate the light-emitting elements 20a, 20b, and 20c (as shown in FIG. 2D). In this embodiment, the material of the dielectric layer 280 is the same as that of the dielectric layers 240a, 240b, and 240c, such as polyimide, and a process (such as a printing technology) is used with the dielectric layers 240a, 240b, and 240c Together. In another embodiment, the material of the dielectric layer 280 is different from the materials of the dielectric layers 240a, 240b, 240c, and is formed by different processes.

參見第2D圖，形成金屬層260a、260b、260c；以及形成金屬層262a、262b、262c。金屬層260a、260b、260c、262a、262b、與262c的材料可選自金（Au）、鋁（Al）、銀（Ag）或其等之合金。較佳地，金屬層260a、260b、260c、262a、262b、與262c係藉由一印刷技術或是電鍍而共同形成。經由上述步驟，即完成具有發光元件20a、20b、與20c之發光元件陣列20。Referring to FIG. 2D, metal layers 260a, 260b, and 260c are formed; and metal layers 262a, 262b, and 262c are formed. The material of the metal layers 260a, 260b, 260c, 262a, 262b, and 262c may be selected from gold (Au), aluminum (Al), silver (Ag), or alloys thereof. Preferably, the metal layers 260a, 260b, 260c, 262a, 262b, and 262c are jointly formed by a printing technique or electroplating. Through the above steps, the light-emitting element array 20 having the light-emitting elements 20a, 20b, and 20c is completed.

如第2E圖至第2F圖所示，在一實施例中，發光元件20a、20b、與20c提供足夠大的接觸面積，以利用錫料（solder）22直接與電路載板23連接。再使基材21與發光元件陣列20分離，發光元件陣列20便可作為影像顯示之用。例如，利用錫料22直接連接發光元件20a、20b、與20c與電路載板23之後，發光元件的製作方法更包含一移除基材21之步驟。基材11可以例如是一藍寶石基材，且可藉由準分子雷射（excimer laser）移除。準分子雷射可以為一具有能量為400毫焦耳/平方公分（mJ/cm2 ）、波長為248奈米以及脈衝寬度（pulse width）為38奈秒（ns）的氟化氪（KrF）準分子雷射。在較高的溫度中，例如60℃，當準分子雷射照射在藍寶石基材上時，藍寶石基材便被移除以暴露出第一導電層102。另外，當基材11為砷化鎵基材，一比例為1:35之氨水（NH4 OH）與過氧化氫（H2 O2 ）的溶液或是一比例為5:3:5之磷酸（H3 PO4 ）、過氧化氫（H2 O2 ）與水的溶液可用於移除砷化鎵基材，藉以暴露出第一導電層102。As shown in FIG. 2E to FIG. 2F, in one embodiment, the light-emitting elements 20a, 20b, and 20c provide a sufficiently large contact area to be directly connected to the circuit carrier board 23 by using a solder 22. The substrate 21 is separated from the light-emitting element array 20, and the light-emitting element array 20 can be used for image display. For example, after the tin material 22 is directly connected to the light-emitting elements 20a, 20b, and 20c and the circuit substrate 23, the method for manufacturing the light-emitting element further includes a step of removing the substrate 21. The substrate 11 may be, for example, a sapphire substrate, and may be removed by an excimer laser. An excimer laser can be a KrF standard with an energy of 400 millijoules per square centimeter (mJ / cm 2 ), a wavelength of 248 nanometers, and a pulse width of 38 nanoseconds (ns). Molecular laser. At a higher temperature, such as 60 ° C., when an excimer laser is irradiated on the sapphire substrate, the sapphire substrate is removed to expose the first conductive layer 102. In addition, when the substrate 11 is a gallium arsenide substrate, a ratio of 1:35 ammonia water (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) or a ratio of 5: 3: 5 phosphoric acid A solution of (H 3 PO 4 ), hydrogen peroxide (H 2 O 2 ), and water can be used to remove the gallium arsenide substrate, thereby exposing the first conductive layer 102.

移除基材21之後，發光裝置的製作方法更包含粗化第一導電層102的表面102a。例如，當第一導電層102為一氮化鋁鎵銦（Alx Gay ln（ 1 － x － y ） N）層，其表面102a可以藉由蝕刻液粗化，蝕刻液可例如為氫氧化鉀（KOH）溶液。此外，當第一導電層102為一磷化鋁鎵銦（Alx Gay In1-x-y P）層，一鹽酸（HCl）以及磷酸的溶液可用於粗化第一導電層102的表面102a，粗化時間可例如為15秒。第一導電層102的粗化表面102a可降低發生全反射的可能性，藉以增加發光元件的光取出效率。一實施例中，如第2G圖所示，一透明封裝材料24係用於包覆包含發光元件20a、20b、與20c之發光元件陣列20且連接電路載板23，進而形成發光元件封裝25，其中透明封裝材料24可例如為環氧樹脂或是其他習知技藝者所熟知之適合的材料。After the substrate 21 is removed, the manufacturing method of the light emitting device further includes roughening the surface 102 a of the first conductive layer 102. For example, when the first conductive layer 102 is an aluminum gallium indium (Al x Ga y ln ( 1 - x - y ) N) layer, the surface 102a thereof may be roughened by an etching solution, and the etching solution may be, for example, hydroxide Potassium (KOH) solution. Further, when the first conductive layer 102 is an aluminum gallium indium phosphide (Al x Ga y In 1- xy P) layer, a hydrochloric acid (HCl) and phosphoric acid solution may be used for surface roughening of the first conductive layer 102 is 102a, The roughening time may be, for example, 15 seconds. The roughened surface 102a of the first conductive layer 102 can reduce the possibility of total reflection, thereby increasing the light extraction efficiency of the light emitting element. In an embodiment, as shown in FIG. 2G, a transparent packaging material 24 is used to cover the light-emitting element array 20 including the light-emitting elements 20a, 20b, and 20c, and is connected to the circuit carrier board 23 to form a light-emitting element package 25. The transparent packaging material 24 can be, for example, epoxy resin or other suitable materials well known to those skilled in the art.

參照第3A圖至第3G圖，係為依照本發明實施例之一種發光裝置的製作方法流程各階段所對應之剖面圖。參見第3A圖，提供一基材21，其為單晶且包含藍寶石、砷化鎵、氮化鎵或矽；磊晶成長一第一導電層102於基材21上，第一導電層102係做為一包覆層；磊晶成長一包含多重量子井（Multiple Quantum Well, MQW）結構的活性層104於第一導電層102上，其中活性層104係作為一發光層；以及磊晶成長一第二導電層106於活性層104上，其中第二導電層106係做為另一包覆層。接著，蝕刻第一導電層102、活性層104以及第二導電層106以在基材21上形成複數藉由溝槽（圖未標）而彼此分離的發光疊層101，且每一發光疊層101中，一部分的第一導電層102是暴露的。接著，每一發光疊層101上形成有一保護層120，且保護層120覆蓋部分的第一導電層102、部分的第二導電層106以及發光疊層101的一側壁。接著，於每一第一導電層102的暴露的部位上設置一與第一導電層102電性連接的電極或接合墊107a，以及於每一第二導電層106上設置一與第二導電層106電性連接的電極或接合墊107b。Referring to FIG. 3A to FIG. 3G, it is a cross-sectional view corresponding to each stage of a method of manufacturing a light-emitting device according to an embodiment of the present invention. Referring to FIG. 3A, a substrate 21 is provided, which is single crystal and includes sapphire, gallium arsenide, gallium nitride, or silicon; epitaxial growth of a first conductive layer 102 on the substrate 21, the first conductive layer 102 is As a cladding layer; epitaxial growth; an active layer 104 including a multiple quantum well (MQW) structure on the first conductive layer 102, wherein the active layer 104 serves as a light emitting layer; and epitaxial growth. The second conductive layer 106 is on the active layer 104, and the second conductive layer 106 is used as another cladding layer. Next, the first conductive layer 102, the active layer 104, and the second conductive layer 106 are etched to form a plurality of light-emitting stacks 101 separated from each other by a trench (not shown) on the substrate 21, and each light-emitting stack In 101, a part of the first conductive layer 102 is exposed. Next, a protection layer 120 is formed on each light-emitting stack 101, and the protection layer 120 covers part of the first conductive layer 102, part of the second conductive layer 106, and a sidewall of the light-emitting stack 101. Next, an electrode or a bonding pad 107a electrically connected to the first conductive layer 102 is disposed on the exposed portion of each first conductive layer 102, and one and a second conductive layer are disposed on each second conductive layer 106. 106 The electrode or bonding pad 107b electrically connected.

之後，參見第3B圖，於每一保護層120上設置一反射層221，以及於每一保護層120上形成一覆蓋反射層221之第一介電層122。對於發光疊層101發出的光，反射層221具有一等同於或是大於80%的反射率。反射層221之材料包含金屬，例如銀、銀合金、鋁或鋁合金。在一實施例中，反射層221的材料包含混有無機粒子的高分子，其中無機粒子由金屬氧化物組成或是由具有反射率等於或是大於1.8之材料組成，反射層221的材料例如為混有氧化鈦粒子的環氧樹脂。各反射層221係完全地被各自對應的保護層120以及第一介電層122覆蓋，藉以電絕緣各反射層221與各自對應的發光疊層101。於另一實施例中，保護層120是被省略的，且反射層221是直接形成於第二導電層106上且電性連接第二導電層106。之後，如第3C圖所示，於基材21上以及溝槽之間以及於每一發光疊層101上形成一第二介電層240，且各第二介電層240暴露各自對應的電極或接合墊107a以及電極或接合墊107b。之後，於每一第二介電層240之間以及於部分的對應之第一介電層122上形成一第一金屬層260以及一第二金屬層262。第一金屬層260以及第二金屬層262係分別形成於對應的電極或接合墊107a以及電極或接合墊107b上。第一金屬層260以及第二金屬層262之材料包含金、鋁、銀或其等之合金。於一實施例中，第一金屬層260以及第二金屬層262係藉由一印刷技術或是電鍍而共同形成。After that, referring to FIG. 3B, a reflective layer 221 is disposed on each protective layer 120, and a first dielectric layer 122 is formed on each protective layer 120 to cover the reflective layer 221. For the light emitted from the light-emitting stack 101, the reflective layer 221 has a reflectivity equal to or greater than 80%. The material of the reflective layer 221 includes a metal, such as silver, a silver alloy, aluminum, or an aluminum alloy. In one embodiment, the material of the reflective layer 221 includes a polymer mixed with inorganic particles. The inorganic particles are composed of a metal oxide or a material having a reflectance equal to or greater than 1.8. The material of the reflective layer 221 is, for example, An epoxy resin mixed with titanium oxide particles. Each reflective layer 221 is completely covered by a corresponding protective layer 120 and a first dielectric layer 122, thereby electrically insulating each reflective layer 221 and a corresponding light-emitting stack 101. In another embodiment, the protective layer 120 is omitted, and the reflective layer 221 is directly formed on the second conductive layer 106 and is electrically connected to the second conductive layer 106. Then, as shown in FIG. 3C, a second dielectric layer 240 is formed on the substrate 21, between the trenches, and on each light-emitting stack 101, and each second dielectric layer 240 exposes a corresponding electrode. Or bonding pad 107a and electrode or bonding pad 107b. Thereafter, a first metal layer 260 and a second metal layer 262 are formed between each second dielectric layer 240 and on a portion of the corresponding first dielectric layer 122. The first metal layer 260 and the second metal layer 262 are formed on the corresponding electrode or bonding pad 107a and the electrode or bonding pad 107b, respectively. The material of the first metal layer 260 and the second metal layer 262 includes gold, aluminum, silver, or an alloy thereof. In one embodiment, the first metal layer 260 and the second metal layer 262 are jointly formed by a printing technique or electroplating.

如第3D圖所示，圖案化位於相鄰發光疊層101之間的第二介電層240藉以於第二介電層240裡形成凹槽，凹槽暴露一部分的基材21且將第二介電層240隔開以形成介電層240a，之後形成一不透光層290於凹槽中。於一實施例中，不透光層290作為一反射層或是一光吸收層，藉以反射或是吸收對應的發光疊層101發出的光且避免被鄰近的發光疊層101發出的光互相影響或產生串擾（crosstalk）。對於對應的發光疊層101發出的光，不透光層290具有一小於50%的穿透率（transmittance）。不透光層290的材料包含金屬或是包含混有無機粒子的高分子，其中無機粒子由金屬氧化物組成或是由具有反射率等於或是大於1.8之材料組成，反射層221的材料例如為混有氧化鈦粒子的環氧樹脂。至此，包含複數發光元件300的發光元件陣列30製作完成。如第3E圖所示，提供一電路載板23，其包含有複數位於電路載板23之上表面以及下表面的金屬接觸22以及包含有複數貫穿電路載板23的導電通道22a，其中導電通道22a可連接位於電路載板之上表面上的金屬接觸22以及位於電路載板之下表面上的金屬接觸22。於一實施例中，電路載板23包含錫料（solder）。電路載板23包含FR-4、BT （Bismaleimide-Triazine）樹脂、陶瓷或玻璃。電路載板23之厚度介於50至200微米之間以足夠支撐發光元件且依舊具有小體積。發光元件陣列30藉由對準各發光元件300的第一金屬層260與第二金屬層262至對應的金屬接觸22而直接以覆晶的形式與電路載板23連接。值得注意的是，發光元件陣列30與電路載板23之間金屬接觸22以外的區域可能形成有空隙。另外可選擇性地以填充材料填充於空隙裡以增進連結強度以及機械支撐。連接發光元件陣列30與電路載板23之後，移除發光元件陣列30的基材21。於一實施例中，基材包含藍寶石，發光疊層101包含氮化鎵，且移除基材21的方法包含於較高的溫度中，例如60℃，使用一準分子雷射照射在第一導電層102與基材21的介面，接著分離基材21與第一導電層102。準分子雷射可以為一具有能量為400毫焦耳/平方公分（mJ/cm2 ）、波長為248奈米以及脈衝寬度（pulse width）為38奈秒（ns）的氟化氪（KrF）準分子雷射。於另一實施例中，當基材21為砷化鎵基材，移除基材21的方法包含使用一比例為1:35之氨水（NH4 OH）與過氧化氫（H2 O2 ）的混和物或是一比例為5:3:5之磷酸（H3 PO4 ）、過氧化氫（H2 O2 ）與水的混和物藉以蝕刻至可以完全地移除基材21且暴露各發光元件300的第一導電層102、介電層240a以及不透光層290。As shown in FIG. 3D, the second dielectric layer 240 located between adjacent light emitting stacks 101 is patterned to form a recess in the second dielectric layer 240. The recess exposes a part of the substrate 21 and the second The dielectric layers 240 are separated to form a dielectric layer 240a, and then an opaque layer 290 is formed in the groove. In an embodiment, the opaque layer 290 serves as a reflective layer or a light absorbing layer, thereby reflecting or absorbing the light emitted by the corresponding light emitting stack 101 and avoiding mutual influence by the light emitted by the adjacent light emitting stack 101. Or produce crosstalk. For the light emitted by the corresponding light-emitting stack 101, the opaque layer 290 has a transmission of less than 50%. The material of the opaque layer 290 includes a metal or a polymer mixed with inorganic particles. The inorganic particles are composed of a metal oxide or a material having a reflectance equal to or greater than 1.8. The material of the reflective layer 221 is, for example, An epoxy resin mixed with titanium oxide particles. So far, the light-emitting element array 30 including the plurality of light-emitting elements 300 is completed. As shown in FIG. 3E, a circuit carrier board 23 is provided, which includes a plurality of metal contacts 22 located on the upper and lower surfaces of the circuit carrier board 23 and a plurality of conductive channels 22 a penetrating the circuit carrier board 23. 22a may connect the metal contacts 22 on the upper surface of the circuit carrier board and the metal contacts 22 on the lower surface of the circuit carrier board. In one embodiment, the circuit board 23 includes a solder. The circuit board 23 includes FR-4, BT (Bismaleimide-Triazine) resin, ceramic, or glass. The thickness of the circuit board 23 is between 50 and 200 micrometers to sufficiently support the light emitting element and still have a small volume. The light-emitting element array 30 is directly connected to the circuit substrate 23 in a flip-chip manner by aligning the first metal layer 260 and the second metal layer 262 to the corresponding metal contacts 22 of each light-emitting element 300. It is worth noting that voids may be formed in areas other than the metal contacts 22 between the light-emitting element array 30 and the circuit substrate 23. In addition, the gap can be optionally filled with a filler material to improve the connection strength and mechanical support. After the light-emitting element array 30 and the circuit substrate 23 are connected, the base material 21 of the light-emitting element array 30 is removed. In an embodiment, the substrate includes sapphire, the light-emitting stack 101 includes gallium nitride, and the method of removing the substrate 21 includes a higher temperature, such as 60 ° C., and irradiating the first The interface between the conductive layer 102 and the substrate 21 is then separated from the substrate 21 and the first conductive layer 102. An excimer laser can be a KrF standard with an energy of 400 millijoules per square centimeter (mJ / cm 2 ), a wavelength of 248 nanometers, and a pulse width of 38 nanoseconds (ns). Molecular laser. In another embodiment, when the substrate 21 is a gallium arsenide substrate, the method for removing the substrate 21 includes using a ratio of 1:35 ammonia water (NH 4 OH) and hydrogen peroxide (H 2 O 2 ). Or a mixture of 5: 3: 5 phosphoric acid (H 3 PO 4 ), hydrogen peroxide (H 2 O 2 ) and water, so that the substrate 21 can be completely removed and each of them is exposed. The first conductive layer 102, the dielectric layer 240a, and the opaque layer 290 of the light emitting element 300.

如第3F圖所示，移除基材21之後，發光裝置的製作方法更包括粗化第一導電層102之曓露的表面。於一實施例中，第一導電層102包含氮化鋁鎵銦（Alx Gay ln（ 1 － x － y ） N，其中0≦x, y≦0），可使用氫氧化鉀（KOH）溶液蝕刻第一導電層102曓露的表面以形成一粗化表面102a。於另一實施例中，第一導電層102包含磷化鋁鎵銦（Alx Gay In（ 1 － x － y ） P），可使用鹽酸（HCl）或是磷酸的溶液蝕刻第一導電層102曓露的表面以形成一粗化表面102a，粗化時間可例如為15秒。每一第一導電層102的粗化表面102a可降低各發光元件300內的光發生全反射的可能性，藉以增加發光元件的光取出效率。於粗化步驟之後，複數凹陷區域位於粗化表面102a且實質上被介電層240a環繞。於一實施例中，為了形成一用於顯示器的晶粒級的紅綠藍發光元件單元，本實施例之製作方法可選擇性地於發光元件300b上塗佈一第一波長轉換層294以轉換光，如第3F圖所示。例如，發光元件300b之發光疊層101，其發出之主要波長介於430奈米至470奈米之間的藍光，被轉換為第一轉換光，例如為一具有主要波長介於610奈米至690奈米之間的紅光。進一步的，一第二波長轉換層296可選擇性地塗佈在發光元件300c上藉以將發光元件300c所發出的光轉換為一第二轉換光，例如為一具有主要波長介於500奈米至570奈米之間的綠光。發光元件300a並未塗佈任何波長轉換材料，以直接自發光元件300a之粗化表面102a發出藍光。於一實施例中，第一或第二波長轉換層藉由聚集奈米級的量子點（quantum dot）或是奈米級的螢光粉以形成一具有厚度實質一致的膜，且藉由一黏結層（圖未示）連結至發光疊層101。於另一實施例中，第一或第二波長轉換層包含具有奈米級的量子點或是奈米級的螢光粉，其平均直徑或平均特徵長度介於10奈米至500奈米之間。每個奈米級的量子點或奈米級的螢光粉之長度或是特徵長度實質上小於1000奈米。奈米級的量子點包含半導體材料，例如一具有組成為Znx Cdy Mgl-x-y Se的II-ⅤI（二/六）族化合物半導體，其中x以及y可調變為使II-ⅤI（二/六）族化合物半導體光激發後發出綠或紅光。「特徵長度」定義為一螢光粉或是一量子點之任兩端點之間的最大距離。之後，將例如為環氧樹脂或是矽氧樹脂（silicone）的透明封裝材料24塗佈於發光元件陣列32之上表面以將波長轉換材料固定於發光疊層101，且作為發光元件陣列32之發光元件300a、300b、300c的光學透鏡。於另一實施例中，覆蓋發光元件300a、300b、300c的波長轉換層之材料是相同的。As shown in FIG. 3F, after the substrate 21 is removed, the manufacturing method of the light emitting device further includes roughening the exposed surface of the first conductive layer 102. In one embodiment, the first conductive layer 102 includes aluminum gallium nitride (Al x Ga y ln ( 1 - x - y ) N, where 0 ≦ x, y ≦ 0), and potassium hydroxide (KOH) may be used. The solution etches the exposed surface of the first conductive layer 102 to form a roughened surface 102a. In another embodiment, the first conductive layer 102 includes aluminum gallium indium phosphide (Al x Ga y In ( 1 - x - y ) P). The first conductive layer may be etched using a solution of hydrochloric acid (HCl) or phosphoric acid. The exposed surface may be 102 to form a roughened surface 102a. The roughening time may be, for example, 15 seconds. The roughened surface 102a of each first conductive layer 102 can reduce the possibility of total reflection of light in each light emitting element 300, thereby increasing the light extraction efficiency of the light emitting element. After the roughening step, a plurality of recessed areas are located on the roughened surface 102a and are substantially surrounded by the dielectric layer 240a. In an embodiment, in order to form a grain-level red-green-blue light-emitting element unit for a display, the manufacturing method of this embodiment may selectively apply a first wavelength conversion layer 294 on the light-emitting element 300b to convert Light, as shown in Figure 3F. For example, the light-emitting stack 101 of the light-emitting element 300b emits blue light with a main wavelength between 430 nanometers and 470 nanometers. Red light between 690 nanometers. Further, a second wavelength conversion layer 296 can be selectively coated on the light-emitting element 300c to convert the light emitted by the light-emitting element 300c into a second converted light, for example, a light having a main wavelength between 500 nm and 500 nm. Green light between 570 nm. The light emitting element 300a is not coated with any wavelength conversion material to emit blue light directly from the roughened surface 102a of the light emitting element 300a. In one embodiment, the first or second wavelength conversion layer is formed by gathering nano-scale quantum dots or nano-scale phosphors to form a film having a substantially uniform thickness, and An adhesive layer (not shown) is connected to the light emitting stack 101. In another embodiment, the first or second wavelength conversion layer includes nanometer-level quantum dots or nanometer-level phosphors, and the average diameter or average characteristic length thereof is between 10 nm and 500 nm. between. The length or characteristic length of each nano-level quantum dot or nano-level phosphor is substantially less than 1000 nanometers. Nanoscale quantum dots include semiconductor materials, such as a group II-ⅤI (two / six) compound semiconductor with a composition of Zn x Cd y Mg lxy Se, where x and y can be adjusted to make II-ⅤI (two / (F) Group compound semiconductors emit green or red light upon photoexcitation. "Feature length" is defined as the maximum distance between any two ends of a phosphor or a quantum dot. Thereafter, a transparent packaging material 24 such as epoxy resin or silicone is coated on the upper surface of the light-emitting element array 32 to fix the wavelength conversion material to the light-emitting stack 101 and used as the light-emitting element array 32. Optical lenses of the light emitting elements 300a, 300b, and 300c. In another embodiment, the materials of the wavelength conversion layers covering the light emitting elements 300a, 300b, and 300c are the same.

第4A圖為如第3F圖所示之發光元件陣列32以覆晶的形式與電路載板23連接的俯視圖。發光元件陣列32以及電路載板23兩者為具有相同或類似尺寸的晶圓形式。發光元件陣列32包含於二維空間中交錯且連續設置的複數紅綠藍發光元件群組，且如圖中虛線圈起的部位所示，每一群組包含一個發光元件300a、一個發光元件300b以及一個發光元件300c。FIG. 4A is a plan view of the light-emitting element array 32 connected to the circuit substrate 23 in a flip-chip form as shown in FIG. 3F. Both the light emitting element array 32 and the circuit carrier board 23 are in the form of wafers having the same or similar dimensions. The light-emitting element array 32 includes a plurality of red-green-blue light-emitting element groups staggered and continuously arranged in a two-dimensional space, and each group includes a light-emitting element 300a and a light-emitting element 300b, as shown by a dotted circle in the figure. And a light emitting element 300c.

最後，執行一切割（dicing）步驟同時切割發光元件陣列32以及電路載板23，形成如第3G圖所示之複數晶粒級的紅綠藍發光元件單元35，各晶粒級的紅綠藍發光元件單元35包含一發出藍光的藍色發光元件300a、一發出紅光的紅色發光元件300b以及一發出綠光的綠色發光元件300c。晶粒級的紅綠藍發光元件單元35是一種不含封裝且為一種表面黏著型的裝置，亦即，於切割步驟之後，不需要傳統的封裝步驟即可直接與一印刷電路載板黏接。透明封裝材料24係共同地覆蓋發光元件300a、300b以及300且不延伸至發光元件300a、300b以及300c之側壁。於一實施例中，切割（dicing）步驟同時切割發光元件陣列32以及電路載板23以形成複數晶粒級的紅綠藍發光元件單元，其中各晶粒級的紅綠藍發光元件單元包含複數紅綠藍發光元件群組。複數紅綠藍發光元件群組於一個紅綠藍發光元件單元中係以I*J陣列排列，其中I以及J是正整數，且I與J中至少一是大於1。I與J之比例較佳地是接近或是等於1/1、3/2、4/3或16/9。Finally, a dicing step is performed to simultaneously cut the light-emitting element array 32 and the circuit carrier board 23 to form a plurality of grain-level red-green-blue light-emitting element units 35 as shown in FIG. 3G, and each grain-level red-green-blue The light emitting element unit 35 includes a blue light emitting element 300a that emits blue light, a red light emitting element 300b that emits red light, and a green light emitting element 300c that emits green light. The die-level red-green-blue light-emitting element unit 35 is a device without a package and a surface-adhesive type, that is, after the cutting step, it can be directly bonded to a printed circuit carrier without the need for a traditional packaging step. . The transparent packaging material 24 collectively covers the light emitting elements 300a, 300b, and 300 and does not extend to the side walls of the light emitting elements 300a, 300b, and 300c. In one embodiment, the dicing step simultaneously cuts the light-emitting element array 32 and the circuit carrier board 23 to form a plurality of grain-level red-green-blue light-emitting element units, wherein each grain-level red-green-blue light-emitting element unit includes a plurality of Red green blue light emitting element group. The plurality of red-green-blue light-emitting element groups are arranged in an I * J array in a red-green-blue light-emitting element unit, where I and J are positive integers, and at least one of I and J is greater than 1. The ratio of I to J is preferably close to or equal to 1/1, 3/2, 4/3, or 16/9.

參照第4B圖，係為晶粒級的紅綠藍發光元件單元35包含如第3G圖所示之紅綠藍發光元件群組。晶粒級的紅綠藍發光元件單元35是為具有一第一長邊以及一第一短邊的第一矩形，其中第一短邊具有一第一寬度S1且第一長邊具有一大於第一寬度S1的第一長度S2。每一發光疊層101為具有一第二長邊以及一第二短邊的第二矩形，其中第二短邊具有一第二寬度d1且第二長邊具有一大於第二寬度d1的第二長度d2。發光疊層101的第二短邊實質上設置於平行於晶粒級的紅綠藍發光元件單元35的第一長邊或實質上設置於垂直於晶粒級的紅綠藍發光元件單元35的第一短邊。於一實施例中，紅綠藍發光元件單元35可作為室內顯示平板的一個像素。為了使具有對角線為40吋且像素解析度為1024*768的電視顯示全部使用發光元件像素，每一像素的面積需小於約0.64平方毫米（mm2 ）。因此，紅綠藍發光元件單元35的面積可例如為小於0.36 mm2 。第一長度S2以及第一寬度S1皆小於0.6毫米，且紅綠藍發光元件單元35的長寬比，亦即S2/S1，較佳地係小於2/1。根據本發明所揭露之實施例，第一金屬層260以及第二金屬層262之間的距離，亦即第一距離S3，受限於發光元件陣列以及電路載板於連接步驟中的對位控制。第一距離S3等於或是大於25微米（micron）且小於150微米，藉以確保製程容差且提供足夠做為導電用的接觸面積。紅綠藍發光元件單元35之其中一邊緣與紅綠藍發光元件單元35的其中一發光疊層101之間的距離，亦即第二距離S4，受限於切割步驟的容差。第二距離S4等於或是大於25微米且小於60微米，藉以確保切割步驟的容差以及維持小體積的優點。兩個相鄰發光元件之間的距離，亦即第三距離S5受限於微影蝕刻步驟，且小於50微米，或較佳地小於25微米，藉以於發光疊層101之間保留較多的面積。對於紅綠藍發光元件單元35中每一發光疊層101而言，第二寬度d1介於20至150微米之間且第二長度d2介於20至550微米之間。紅綠藍發光元件單元35的面積與發光疊層101的總面積之比例小於2或介於1.1至2之間，且較佳地係介於1.2至1.8之間。發光疊層101的面積取決於所需的亮度以及像素尺寸。值得注意的是，紅綠藍發光元件單元35的形狀亦可為四邊皆與第一寬度S1相同的正方形。於一實施例中，一像素包含兩個紅綠藍發光元件單元35，其中一個用於正常操作，另一個用於備用以防正常操作的紅綠藍發光元件單元35故障。第一寬度S1較佳地係小於0.3毫米，藉以使兩個紅綠藍發光元件單元35設置於一個像素內。本發明的優點在於，可以實現發光元件作為一平面電視的像素元件，且解析度更可以提升至像素解析度為1024*768的兩倍或是四倍。於另一實施例中，一紅綠藍發光元件單元35包含兩個紅綠藍發光元件群組，其中一個用於正常操作，另一個用於備用以防正常操作的紅綠藍發光元件群組故障。Referring to FIG. 4B, the red-green-blue light-emitting element unit 35, which is a grain level, includes a red-green-blue light-emitting element group as shown in FIG. 3G. The grain-level red-green-blue light-emitting element unit 35 is a first rectangle having a first long side and a first short side, wherein the first short side has a first width S1 and the first long side has a greater than A first length S2 of a width S1. Each light-emitting stack 101 is a second rectangle having a second long side and a second short side, wherein the second short side has a second width d1 and the second long side has a second width larger than the second width d1. Length d2. The second short side of the light-emitting stack 101 is substantially disposed on the first long side of the red-green-blue light-emitting element unit 35 parallel to the grain level or substantially on the red-green-blue light-emitting element unit 35 perpendicular to the grain level. First short side. In one embodiment, the red-green-blue light-emitting element unit 35 can be used as one pixel of an indoor display panel. In order for a TV display with a diagonal of 40 inches and a pixel resolution of 1024 * 768 to use all light-emitting element pixels, the area of each pixel needs to be less than about 0.64 square millimeters (mm 2 ). Therefore, the area of the red-green-blue light-emitting element unit 35 may be, for example, less than 0.36 mm 2 . The first length S2 and the first width S1 are both less than 0.6 mm, and the aspect ratio of the red-green-blue light-emitting element unit 35, that is, S2 / S1, is preferably less than 2/1. According to the disclosed embodiment, the distance between the first metal layer 260 and the second metal layer 262, that is, the first distance S3, is limited by the alignment control of the light-emitting element array and the circuit substrate in the connection step. . The first distance S3 is equal to or greater than 25 microns (micron) and less than 150 microns, thereby ensuring a process tolerance and providing a sufficient contact area for conducting. The distance between one edge of the red-green-blue light-emitting element unit 35 and one of the light-emitting stacks 101 of the red-green-blue light-emitting element unit 35, that is, the second distance S4, is limited by the tolerance of the cutting step. The second distance S4 is equal to or greater than 25 micrometers and less than 60 micrometers, thereby ensuring the tolerance of the cutting step and the advantage of maintaining a small volume. The distance between two adjacent light-emitting elements, that is, the third distance S5 is limited by the lithographic etching step, and is less than 50 microns, or preferably less than 25 microns, so that more of the light-emitting stack 101 is retained. area. For each light-emitting stack 101 in the red-green-blue light-emitting element unit 35, the second width d1 is between 20 and 150 microns and the second length d2 is between 20 and 550 microns. The ratio of the area of the red-green-blue light-emitting element unit 35 to the total area of the light-emitting stack 101 is less than 2 or between 1.1 and 2, and preferably between 1.2 and 1.8. The area of the light emitting stack 101 depends on the required brightness and pixel size. It is worth noting that the shape of the red-green-blue light-emitting element unit 35 may also be a square with four sides having the same width as the first width S1. In one embodiment, one pixel includes two red-green-blue light-emitting element units 35, one of which is used for normal operation and the other is used to prevent the red-green-blue light-emitting element unit 35 from malfunctioning. The first width S1 is preferably less than 0.3 mm, so that the two red-green-blue light-emitting element units 35 are disposed in one pixel. The advantage of the present invention is that the light emitting element can be implemented as a pixel element of a flat-screen television, and the resolution can be increased to twice or four times the pixel resolution of 1024 * 768. In another embodiment, a red-green-blue light-emitting element unit 35 includes two red-green-blue light-emitting element groups, one of which is used for normal operation, and the other is used for standby of the red-green-blue light-emitting element group. malfunction.

參照第5A圖至第5C圖，係為依照本發明實施例之一種晶粒級的發光元件單元，其製造方法以及結構與第3A圖至第3G圖所示之實施例以及相關之揭示內容相似，不同的地方在於，於切割步驟之前，發光元件陣列34包含複數相同的發光元件300d，如第5A圖所示。每一發光元件300d係塗佈相同或不同的波長轉換層298，波長轉換層298用於轉換對應的發光元件300d之發光疊層101發出的光，例如，將主要波長介於430奈米至470奈米之間的藍光轉換為黃光、綠光或是從光的轉換光。參照第5B圖以及第5C圖，係為切割步驟後，包含單一發光元件的晶粒級的發光元件單元36之俯視圖以及剖面圖。晶粒級的發光元件單元36的尺寸與第4B圖所示之晶粒級的紅綠藍發光元件單元35的尺寸相似或相同。晶粒級的發光元件單元36為具有一第一長邊以及一第一短邊的第一矩形，其中第一長邊具有第一長度S1，且第一短邊具有小於第一長度S1的第一寬度S6。每一發光疊層101為具有一第二長邊以及一第二短邊的第二矩形，其中第二短邊具有一第二寬度d1且第二長邊具有一大於第二寬度d1的第二長度d2。發光疊層101的第二短邊實質上設置於平行於晶粒級的紅綠藍發光元件單元36的第一短邊或實質上設置於垂直於晶粒級的紅綠藍發光元件單元36的第一長邊。於一實施例中，紅綠藍發光元件單元36是用於一室內顯示平板的的像素之其中一部分。紅綠藍發光元件單元36的面積可例如為小於0.12mm2 。第一長度S1以及第一寬度S6皆小於0.2毫米，且紅綠藍發光元件單元36的長寬比，亦即S1/S6，較佳地係小於2/1。根據本發明，第一金屬層260以及第二金屬層262之間的距離，亦即第一距離S3，受限於發光元件陣列以及電路載板於連接步驟中的對位控制。第一距離S3等於或是大於25微米且小於150微米，以確保製程容差且提供足夠做為導電用的接觸面積。紅綠藍發光元件單元36之其中一邊緣與其發光疊層101之間的距離，亦即第二距離S4，受限於切割步驟的容差。第二距離S4等於或是大於25微米且小於60微米，藉以確保切割步驟的容差以及維持小體積的優點。對於晶粒級的紅綠藍發光元件單元36中的發光疊層101而言，第二寬度d1介於20至150微米之間且第二長度d2於20至550微米之間。晶粒級的紅綠藍發光元件單元36的面積與發光疊層101的總面積比例小於2或介於1.1至2之間，且較佳地係介於1.2至1.8之間。發光疊層101的面積取決於所需的亮度以及像素尺寸。值得注意的是，紅綠藍發光元件單元36的形狀亦可為四邊皆與第一寬度S6相同的正方形。相似的，發光疊層101的形狀亦可為四邊皆與第二寬度d1相同的正方形。於一實施例中，一像素包含至少三個晶粒級的紅綠藍發光元件單元36，藉以發出藍、紅以及綠光。Referring to FIGS. 5A to 5C, it is a grain-level light-emitting element unit according to an embodiment of the present invention. The manufacturing method and structure are similar to the embodiments and related disclosures shown in FIGS. 3A to 3G. The difference is that before the cutting step, the light-emitting element array 34 includes a plurality of the same light-emitting elements 300d, as shown in FIG. 5A. Each light emitting element 300d is coated with the same or different wavelength conversion layer 298. The wavelength conversion layer 298 is used to convert light emitted from the light emitting stack 101 of the corresponding light emitting element 300d. For example, the main wavelength is between 430 nm and 470. The blue light between the nanometers is converted into yellow light, green light, or converted light from the light. 5B and 5C are a plan view and a cross-sectional view of a grain-level light-emitting element unit 36 including a single light-emitting element after the cutting step. The size of the grain-level light-emitting element unit 36 is similar to or the same as the size of the grain-level red-green-blue light-emitting element unit 35 shown in FIG. 4B. The die-level light-emitting element unit 36 is a first rectangle having a first long side and a first short side, wherein the first long side has a first length S1, and the first short side has a first length smaller than the first length S1.一 Width S6. Each light-emitting stack 101 is a second rectangle having a second long side and a second short side, wherein the second short side has a second width d1 and the second long side has a second width larger than the second width d1. Length d2. The second short side of the light-emitting stack 101 is substantially disposed on the first short side of the red-green-blue light-emitting element unit 36 parallel to the die level or substantially First long side. In one embodiment, the red-green-blue light-emitting element unit 36 is a part of the pixels used for an indoor display panel. The area of the red-green-blue light-emitting element unit 36 may be, for example, less than 0.12 mm 2 . The first length S1 and the first width S6 are both less than 0.2 mm, and the aspect ratio of the red-green-blue light-emitting element unit 36, that is, S1 / S6, is preferably less than 2/1. According to the present invention, the distance between the first metal layer 260 and the second metal layer 262, that is, the first distance S3, is limited by the alignment control of the light emitting element array and the circuit substrate in the connection step. The first distance S3 is equal to or greater than 25 micrometers and less than 150 micrometers to ensure a process tolerance and provide a sufficient contact area for conducting. The distance between one edge of the red-green-blue light-emitting element unit 36 and its light-emitting stack 101, that is, the second distance S4, is limited by the tolerance of the cutting step. The second distance S4 is equal to or greater than 25 micrometers and less than 60 micrometers, thereby ensuring the tolerance of the cutting step and the advantage of maintaining a small volume. For the light-emitting stack 101 in the grain-level red-green-blue light-emitting element unit 36, the second width d1 is between 20 and 150 microns and the second length d2 is between 20 and 550 microns. The ratio of the area of the grain-level red-green-blue light-emitting element unit 36 to the total area of the light-emitting stack 101 is less than 2 or between 1.1 and 2, and preferably between 1.2 and 1.8. The area of the light emitting stack 101 depends on the required brightness and pixel size. It is worth noting that the shape of the red-green-blue light-emitting element unit 36 may be a square with four sides having the same width as the first width S6. Similarly, the shape of the light-emitting stack 101 may be a square whose four sides are the same as the second width d1. In one embodiment, a pixel includes at least three grain-level red-green-blue light-emitting element units 36 to emit blue, red, and green light.

參照第5D圖至第5E圖，係為依照本發明實施例之一種晶粒級的發光元件單元，其製造方法以及結構與第5A圖至第5C圖所示之實施例以及相關之揭示內容相似，不同的地方在於，不透光層290可選擇性地省略。紅綠藍發光元件單元36’是直接表面黏著於一包含於一燈具的光板。發光疊層101之面積取決於所需的亮度以及光板或燈具的尺寸。對於例如小於0.3瓦之低功率的應用而言，紅綠藍發光元件單元36’的發光疊層101之面積係為100mil2 至200mil2 ，對於例如介於0.3至0.9瓦之間的中功率之應用而言，紅綠藍發光元件單元36’的發光疊層101之面積係為201 mil2 至900 mil2 ，對於例如高於0.9瓦的高功率之應用而言，紅綠藍發光元件單元36’的發光疊層101之面積係大於900 mil2 。環繞發光疊層101的介電層240a可作為將光取出晶粒級的發光元件單元36’的耦合透鏡（coupling lens）。晶粒級的發光元件單元36’的面積與發光疊層101的面積之比例等於或大於9，且較佳地係等於或大於15，藉以具有較佳的光取出效率以及光分散性。於本發明中，第一金屬層260以及第二金屬層262之間的距離，亦即第一距離S3’，受限於發光元件陣列以及電路載板於連接步驟中的對位控制。第一距離S3’等於或是大於25微米且小於150微米，藉以確保製程容差且提供足夠做為導電用的接觸面積。值得注意的是，晶粒級的發光元件單元36’的形狀亦可為四邊皆與第一寬度S6’相同的正方形。同樣的，發光疊層101的形狀亦可為四邊皆與第二寬度d1’相同的正方形。第一寬度S6’與第二寬度d1’相同或是大於第二寬度d1’的三倍，較佳地，第一寬度S6’與第二寬度d1’相同或是大於第二寬度d1’的四倍，以使晶粒級的發光元件單元36’具有較佳的光取出效率。於一實例中，介電層於發光疊層101的側壁具有不相同的厚度，因此第一寬度S6’與第二寬度d1’的第一比例（S6’/ d1’）不同於第一長度S1’與第二長度d2’的第二比例（S1’/ d2’），以達到於操作時，俯視晶粒級的發光元件單元36’，其具有不對稱的光場的特性。此外，第一比例至少為第二比例的兩倍，或較佳地係為第二比例的四倍。Referring to FIGS. 5D to 5E, it is a grain-level light-emitting element unit according to an embodiment of the present invention. The manufacturing method and structure are similar to the embodiments and related disclosures shown in FIGS. 5A to 5C. The difference is that the opaque layer 290 can be selectively omitted. The red-green-blue light-emitting element unit 36 'is directly adhered to a light plate included in a lamp. The area of the light emitting stack 101 depends on the required brightness and the size of the light plate or lamp. For applications such as less than 0.3 watts of low power, the area of the light emitting element RGB unit 36 'of the light emitting stack 101 is based 100mil 2 to 200mil 2, for example, in a power range between 0.3 to 0.9 watts In terms of application, the area of the light-emitting stack 101 of the red-green-blue light-emitting element unit 36 ′ is 201 mil 2 to 900 mil 2. For high-power applications such as higher than 0.9 watts, the red-green-blue light-emitting element unit 36 The area of the light-emitting stack 101 is greater than 900 mil 2 . The dielectric layer 240 a surrounding the light-emitting stack 101 can serve as a coupling lens for extracting light from the light-emitting element unit 36 ′ at the grain level. The ratio of the area of the die-level light-emitting element unit 36 ′ to the area of the light-emitting stack 101 is equal to or greater than 9, and preferably equal to or greater than 15, so as to have better light extraction efficiency and light dispersion. In the present invention, the distance between the first metal layer 260 and the second metal layer 262, that is, the first distance S3 ′, is limited by the alignment control of the light-emitting element array and the circuit substrate in the connection step. The first distance S3 'is equal to or greater than 25 micrometers and less than 150 micrometers, thereby ensuring a process tolerance and providing a sufficient contact area for conducting. It is worth noting that the shape of the light-emitting element unit 36 ′ at the grain level may be a square with four sides having the same width as the first width S6 ′. Similarly, the shape of the light-emitting stack 101 may be a square with four sides having the same width as the second width d1 ′. The first width S6 'is the same as the second width d1' or is three times larger than the second width d1 '. Preferably, the first width S6' is the same as the second width d1 'or larger than the fourth width d1'. So that the light-emitting element unit 36 'at the grain level has better light extraction efficiency. In an example, the dielectric layer has different thicknesses on the sidewalls of the light-emitting stack 101, so the first ratio (S6 '/ d1') of the first width S6 'and the second width d1' is different from the first length S1 The second ratio (S1 '/ d2') to the second length d2 'is such that during operation, the grain-level light-emitting element unit 36' is viewed from the bottom, and it has an asymmetric light field characteristic. In addition, the first ratio is at least twice the second ratio, or preferably four times the second ratio.

參照第6A圖，係為依照本發明實施例之一晶粒級的紅綠藍發光元件單元65的剖面圖，其製造方法以及結構與第3A圖至第3G圖所示之實施例以及相關之揭示內容相似，不同的地方在於，一填充材料680係填充於包含發光元件300a’、300b’以及300c’的發光元件陣列32’以及電路載板23之間的空隙，藉以提高兩者的連接強度以及提供電路載板以及發光元件之間的電流路徑。填充材料680包含異方導電膠（anisotropic conductive film，ACF），其具有在發光元件陣列32’與電路載板23之間以垂直路徑傳導電流以及在發光元件陣列32’ 與電路載板23之間以平行於發光元件陣列32’或電路載板的橫向路徑絕緣電流的能力。填充材料680係於連接發光元件陣列至電路載板23之前塗佈於電路載板23上。於一實施例中，第一金屬層260’以及第二金屬層262’皆未接觸電路載板23的金屬接觸22。填充材料680係位於第一金屬層260’、第二金屬層262’ 與金屬接觸22之間，藉以在第一金屬層260’、第二金屬層262’ 以及金屬接觸22之間傳導電流。第一金屬層260’以及第二金屬層262’係經圖案化，因此在面對金屬接觸22的表面為一具有複數凹部以及凸部的粗化表面。故，發光元件陣列與電路載板的接觸面積增加，發光元件陣列與電路載板的連接強度亦提升。複數凹部以及凸部具有規則形狀或是不規則形狀，且表面粗糙度（Ra）係介於0.5至5微米之間。使用異方導電膠作為填充材料的的優點在於第一金屬層260’與第二金屬層262’之間的距離，即如第4B圖所示之第一距離S3，可小於25微米。6A is a cross-sectional view of a grain-level red-green-blue light-emitting element unit 65 according to an embodiment of the present invention. The manufacturing method and structure are similar to the embodiments shown in FIGS. 3A to 3G and related The disclosure is similar, except that a filling material 680 fills the gap between the light-emitting element array 32 'including the light-emitting elements 300a', 300b ', and 300c' and the circuit carrier board 23, thereby improving the connection strength between the two And provide a current path between the circuit board and the light emitting element. The filling material 680 includes an anisotropic conductive film (ACF), which has a vertical path for conducting current between the light-emitting element array 32 ′ and the circuit substrate 23 and between the light-emitting element array 32 ′ and the circuit substrate 23. Ability to insulate current with a lateral path parallel to the light emitting element array 32 'or the circuit carrier board. The filling material 680 is coated on the circuit carrier board 23 before connecting the light emitting element array to the circuit carrier board 23. In one embodiment, neither the first metal layer 260 'nor the second metal layer 262' contacts the metal contact 22 of the circuit carrier board 23. The filling material 680 is located between the first metal layer 260 ', the second metal layer 262', and the metal contact 22, thereby conducting current between the first metal layer 260 ', the second metal layer 262', and the metal contact 22. Since the first metal layer 260 'and the second metal layer 262' are patterned, the surface facing the metal contact 22 is a roughened surface having a plurality of concave portions and convex portions. Therefore, the contact area between the light-emitting element array and the circuit substrate increases, and the connection strength of the light-emitting element array and the circuit substrate also increases. The plurality of concave portions and convex portions have a regular shape or an irregular shape, and the surface roughness (Ra) is between 0.5 and 5 microns. The advantage of using the anisotropic conductive adhesive as the filling material is that the distance between the first metal layer 260 'and the second metal layer 262', that is, the first distance S3 as shown in FIG. 4B, can be less than 25 microns.

第6B圖係為第6A圖所示之發光元件陣列32’中的單顆發光元件300d’ 之示意圖。填充材料680以及第一金屬層260’與第二金屬層262’之圖案化的表面亦可以應用於如第5A圖至第5C圖所示之實施例，藉以形成如第6B圖所示之結構。填充材料680係填充於發光元件300d’以及電路載板23之間的空隙，以提高兩者的連接強度以及提供電路載板與發光元件之間的電流路徑。填充材料680包含異方導電膠（anisotropic conductive film，ACF），其具有在發光元件300d’與電路載板23之間以垂直路徑傳導電流以及在發光元件300d’與電路載板23之間以平行於發光元件300d’或電路載板的橫向路徑絕緣電流的能力。填充材料680係於連接發光元件陣列至電路載板23之前塗佈於電路載板23上。於一實施例中，第一金屬層260’以及第二金屬層262’皆未接觸電路載板23的金屬接觸22。填充材料680係位於第一金屬層260’、第二金屬層262’ 與金屬接觸22之間，藉以在第一金屬層260’ 、第二金屬層262’以及金屬接觸22之間傳導電流。第一金屬層260’以及第二金屬層262’係經圖案化，因此在面對金屬接觸22的表面上有複數凹部以及凸部。故，發光元件與電路載板的接觸面積增加，發光元件與電路載板的連接強度亦提升。複數凹部以及凸部具有規則形狀或是不規則形狀，且表面粗糙度（Ra）係介於0.5至5微米之間。同樣地，填充材料680以及第一金屬層260’與第二金屬層262’之圖案化的表面亦可以應用於上述如第5E圖所示之實施例，以形成如第6C圖所示之結構。Fig. 6B is a schematic diagram of a single light-emitting element 300d 'in the light-emitting element array 32' shown in Fig. 6A. The filling material 680 and the patterned surfaces of the first metal layer 260 'and the second metal layer 262' can also be applied to the embodiments shown in Figs. 5A to 5C to form the structure shown in Fig. 6B. . The filling material 680 fills the gap between the light emitting element 300d 'and the circuit carrier board 23 to improve the connection strength between the two and provide a current path between the circuit carrier board and the light emitting element. The filling material 680 includes an anisotropic conductive film (ACF), which has a vertical path for conducting current between the light-emitting element 300d 'and the circuit substrate 23 and a parallel between the light-emitting element 300d' and the circuit substrate 23 The ability to insulate current in the lateral path of the light emitting element 300d 'or the circuit board. The filling material 680 is coated on the circuit carrier board 23 before connecting the light emitting element array to the circuit carrier board 23. In one embodiment, neither the first metal layer 260 'nor the second metal layer 262' contacts the metal contact 22 of the circuit carrier board 23. The filler material 680 is located between the first metal layer 260 ', the second metal layer 262', and the metal contact 22, thereby conducting a current between the first metal layer 260 ', the second metal layer 262', and the metal contact 22. Since the first metal layer 260 'and the second metal layer 262' are patterned, there are a plurality of concave portions and convex portions on the surface facing the metal contact 22. Therefore, the contact area between the light emitting element and the circuit carrier board is increased, and the connection strength between the light emitting element and the circuit carrier board is also improved. The plurality of concave portions and convex portions have a regular shape or an irregular shape, and the surface roughness (Ra) is between 0.5 and 5 microns. Similarly, the filling material 680 and the patterned surfaces of the first metal layer 260 'and the second metal layer 262' can also be applied to the embodiment shown in FIG. 5E to form the structure shown in FIG. 6C. .

參照第7A圖至第7G圖，係為依照本發明實施例之一種發光裝置的製作方法流程各階段所對應之剖面圖，其中第7A圖至第7D圖之步驟以及結構與第2A圖至第2D圖所示之實施例以及相關之揭示內容相似，第7F圖至第7G圖之步驟以及結構與第3E圖至第3F圖所示之實施例以及相關之揭示內容相似，不同的地方在於，如第7C圖所示，介電層240a、240b、240c、280係為一光阻劑，例如為正光阻劑或是負光阻劑；如第7D圖至第7E圖所示，於形成金屬層260a、260b、260c以及形成金屬層262a、262b、262c之後，所述的製作方法更包含移除介電層240a、240b、240c、280，因此形成空隙於兩相鄰的發光元件之間以及單一發光元件之金屬層之間；如第7F圖至第7G圖所示，移除基材21之後，兩相鄰的發光元件藉由空隙以彼此分離，且所述的製作方法更包括粗化第一導電層102曓露的表面以形成一粗化表面102a，粗化的方法如前所述，在此便不再贅述。於一實施例中，為了形成一用於顯示或照明的晶粒級（chip-scale）的紅綠藍發光元件，其製作方法可選擇性地於發光元件300b上塗佈一第一波長轉換層294，如第7G圖所示，以將發光元件300b所發出的光轉換為一第一轉換光。進一步的，一第二波長轉換層296可選擇性地塗佈在發光元件300c上藉以將發光元件300c所發出的光轉換為一第二轉換光。發光元件300a並未塗佈任何波長轉換材料，以直接自發光元件300a之粗化表面102a發出藍光。各轉換層的形成方式以及材料如前所述，在此不再贅述。第7H圖係為依照本發明實施例之晶粒級的紅綠藍發光元件單元包含如第7G圖所示之紅綠藍發光元件群組之俯視圖，紅綠藍發光元件單元37之第一寬度S1、第一長度S2、第二長度d2、第一距離S3、第二距離S4、第二寬度d1、第三距離S5如第4B圖所示之實施例以及相關之揭示內容所述，在此不再贅述，不同的地方在於，發光疊層101並未被介電層240a以及不透光層290環繞。於形成第一波長轉換層294以及第二波長轉換層296之後，不需塗佈前述實施例之透明封裝材料24，直接執行切割（dicing）步驟以直接切割電路載板23而不需經由切割發光元件陣列32，形成複數晶粒級的紅綠藍發光元件單元。參照第7I圖以及第7J圖，係為切割步驟後，包含單一發光元件的晶粒級的發光元件單元37之剖面圖以及俯視圖。晶粒級的發光元件單元37之第一長度S1、第一寬度S6、第二寬度d1、第二長度d2、第一距離S3以及第二距離S4如圖5B所示之實施例以及相關之揭示內容所述，在此不再贅述，不同的地方在於，發光疊層101、第一金屬層260以及第二金屬層262之的側壁並未有介電層240a以及不透光層290；此外，波長轉換層298上並未有透明封裝材料24。7A to 7G are cross-sectional views corresponding to each stage of a method for manufacturing a light-emitting device according to an embodiment of the present invention. The steps and structures of FIGS. 7A to 7D are the same as FIG. 2A to FIG. The embodiment shown in FIG. 2D and related disclosure are similar. The steps and structures of FIGS. 7F to 7G are similar to the embodiment shown in FIGS. 3E to 3F and related disclosure. The difference is that: As shown in FIG. 7C, the dielectric layers 240a, 240b, 240c, and 280 are a photoresist, such as a positive photoresist or a negative photoresist; as shown in FIGS. 7D to 7E, a metal is formed. After the layers 260a, 260b, and 260c and the metal layers 262a, 262b, and 262c are formed, the manufacturing method further includes removing the dielectric layers 240a, 240b, 240c, and 280, so that a gap is formed between two adjacent light-emitting elements and Between the metal layers of a single light-emitting element; as shown in FIGS. 7F to 7G, after removing the substrate 21, two adjacent light-emitting elements are separated from each other by a gap, and the manufacturing method further includes roughening. The exposed surface of the first conductive layer 102 forms a roughened surface 10 2a, the coarsening method is as described above, and is not repeated here. In an embodiment, in order to form a chip-scale red-green-blue light-emitting element for display or illumination, a manufacturing method thereof may selectively coat a first wavelength conversion layer on the light-emitting element 300b. 294. As shown in FIG. 7G, the light emitted from the light emitting element 300b is converted into a first converted light. Further, a second wavelength conversion layer 296 may be selectively coated on the light emitting element 300c, so as to convert the light emitted by the light emitting element 300c into a second converted light. The light emitting element 300a is not coated with any wavelength conversion material to emit blue light directly from the roughened surface 102a of the light emitting element 300a. The formation method and material of each conversion layer are as described above, and are not repeated here. FIG. 7H is a top view of a red-green-blue-light-emitting element unit at a grain level according to an embodiment of the present invention including a red-green-blue light-emitting element group as shown in FIG. 7G; a first width of the red-green-blue light-emitting element unit 37; S1, the first length S2, the second length d2, the first distance S3, the second distance S4, the second width d1, and the third distance S5 are as described in the embodiment shown in FIG. 4B and the related disclosure, here No need to go into details, the difference is that the light emitting stack 101 is not surrounded by the dielectric layer 240a and the opaque layer 290. After the first wavelength conversion layer 294 and the second wavelength conversion layer 296 are formed, the transparent packaging material 24 of the foregoing embodiment is not coated, and a dicing step is directly performed to directly cut the circuit carrier board 23 without cutting and emitting light. The element array 32 forms red-green-blue light-emitting element units of a plurality of crystal grain levels. 7I and 7J are a cross-sectional view and a top view of a grain-level light-emitting element unit 37 including a single light-emitting element after the cutting step. The embodiment of the first length S1, the first width S6, the second width d1, the second length d2, the first distance S3, and the second distance S4 of the die-level light-emitting element unit 37 and related disclosure are shown in FIG. 5B. The content is not repeated here. The difference is that the sidewalls of the light-emitting stack 101, the first metal layer 260, and the second metal layer 262 do not have the dielectric layer 240a and the opaque layer 290. In addition, There is no transparent packaging material 24 on the wavelength conversion layer 298.

參照第8A圖，係為依照本發明實施例之一種顯示模組76，其包含複數位於第二電路載板73上的晶粒級的紅綠藍發光元件單元65。例如，任兩個相鄰的晶粒級的紅綠藍發光元件單元65是由一間距彼此分離或是無縫地設置而使兩者互相接觸。第二電路載板73包含電路72，電路72是與紅綠藍發光元件單元65之各發光元件電性連接，藉以獨立控制每一紅綠藍發光元件單元65中的藍、紅以及綠色發光元件。於一實施例中，顯示模組76包含M列以及N行的晶粒級的紅綠藍發光元件單元65以用於一具有X*Y像素解析度的顯示器，其中M/N = 1/1、3/2、4/3或16/9，X=a*M，Y=b*N，且a以及b皆為等於或大於2的正整數。顯示模組76於一平方英吋之面積中，包含超過500個的紅綠藍發光元件單元65。也就是說，顯示模組76於一平方英吋之面積中，包含超過1500個發光疊層101。於另一實施例中，每一晶粒級的紅綠藍發光元件單元包含複數紅綠藍發光元件群組，且每一群組如之前所述，包含一藍色發光元件、一紅色發光元件以及一綠色發光元件。複數紅綠藍發光元件群組於一個晶粒級的紅綠藍發光元件單元中係以I*J陣列排列，其中I以及J是正整數，且I與J中至少一是大於1。I與J之比例較佳地是接近或是等於1/1、3/2、4/3或16/9。於一晶粒級的紅綠藍發光元件單元中，分別來自於兩相鄰的紅綠藍發光元件群組的兩相鄰的發光疊層之間的距離，實質上等於分別來自於兩相鄰的晶粒級的紅綠藍發光元件單元之兩相鄰的發光疊層之間的距離。顯示模組76包含M列以及N行的晶粒級的紅綠藍發光元件單元65以用於一具有X*Y像素解析度的顯示器，其中M /N = 1/1、3/2、4/3或16/9，X=a*M*I，Y=b*N*J，且a以及b皆為等於或大於2的正整數。顯示模組76於一平方英吋之面積中，包含超過500個的紅綠藍發光元件群組。也就是說，顯示模組76於一平方英吋之面積中，包含超過1500個發光疊層101。每一紅綠藍發光元件單元以及紅綠藍發光元件單元中的每一發光元件皆可藉由電路載板23以及第二電路載板73上形成的電路獨立驅動。第二電路載板73的材料班還FR-4、BT （Bismaleimide-Triazine） 樹脂、陶瓷或是玻璃。第8B圖係為依照本發明實施例之一種照明模組78的示意圖。照明模組78包括複數位於第二電路載板73上的晶粒級的發光元件單元66。依據施加的驅動電壓，晶粒級的發光元件單元66可藉由第二電路載板73上的電路以串聯或是並聯方式連接。於一實施例中，照明模組78係被設置於一如第9所示之燈泡80內。燈泡80進一步包含一覆蓋照明模組78的光學透鏡82，一具有一連接表面且照明模組78是位於連接表面的散熱槽85，一與散熱槽85連接的連結部87，以及一與連結部87連接且與照明模組78電性連接的電連接器88。Referring to FIG. 8A, a display module 76 according to an embodiment of the present invention includes a plurality of grain-level red-green-blue light-emitting element units 65 located on a second circuit carrier board 73. For example, any two adjacent red-green-blue light-emitting element units 65 at the grain level are separated from each other by a pitch or are arranged seamlessly so that the two are in contact with each other. The second circuit carrier board 73 includes a circuit 72, which is electrically connected to each light-emitting element of the red-green-blue light-emitting element unit 65, thereby independently controlling the blue, red, and green light-emitting elements in each of the red-green-blue light-emitting element units 65. . In an embodiment, the display module 76 includes M columns and N rows of grain-level red-green-blue light-emitting element units 65 for a display with X * Y pixel resolution, where M / N = 1/1 , 3/2, 4/3, or 16/9, X = a * M, Y = b * N, and a and b are positive integers equal to or greater than 2. The display module 76 includes more than 500 red-green-blue light-emitting element units 65 in one square inch. That is, the display module 76 includes more than 1500 light-emitting stacks 101 in a square inch area. In another embodiment, the red-green-blue light-emitting element units of each die level include a plurality of red-green-blue light-emitting element groups, and each group includes a blue light-emitting element and a red light-emitting element as described above. And a green light emitting element. The plurality of red-green-blue light-emitting element groups are arranged in a grain-level red-green-blue light-emitting element unit in an I * J array, where I and J are positive integers, and at least one of I and J is greater than 1. The ratio of I to J is preferably close to or equal to 1/1, 3/2, 4/3, or 16/9. In a grain-level red-green-blue light-emitting element unit, the distance between two adjacent light-emitting stacks from two adjacent red-green-blue light-emitting element groups is substantially equal to that from two adjacent The distance between two adjacent light-emitting stacks of a red-green-blue light-emitting element unit of a grain level. The display module 76 includes M-row and N-row grain-level red-green-blue light-emitting element units 65 for a display with X * Y pixel resolution, where M / N = 1/1, 3/2, 4 / 3 or 16/9, X = a * M * I, Y = b * N * J, and a and b are positive integers equal to or greater than 2. The display module 76 includes more than 500 red-green-blue light-emitting element groups in an area of one square inch. That is, the display module 76 includes more than 1500 light-emitting stacks 101 in a square inch area. Each of the red-green-blue light-emitting element units and each of the red-green-blue light-emitting element units can be independently driven by a circuit formed on the circuit carrier board 23 and the second circuit carrier board 73. Material classes of the second circuit carrier board 73 are also FR-4, BT (Bismaleimide-Triazine) resin, ceramic, or glass. FIG. 8B is a schematic diagram of a lighting module 78 according to an embodiment of the present invention. The lighting module 78 includes a plurality of die-level light-emitting element units 66 located on the second circuit carrier board 73. Depending on the applied driving voltage, the die-level light-emitting element units 66 may be connected in series or in parallel through the circuits on the second circuit carrier board 73. In one embodiment, the lighting module 78 is disposed in a light bulb 80 as shown in FIG. 9. The light bulb 80 further includes an optical lens 82 covering the lighting module 78, a heat dissipation groove 85 having a connection surface and the lighting module 78 is located on the connection surface, a connection portion 87 connected to the heat dissipation groove 85, and a connection portion 87 is an electrical connector 88 connected to and electrically connected to the lighting module 78.

以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. When the scope of the patent of the present invention cannot be limited, That is, any equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.

100、200a、200b、與200c‧‧‧發光結構 100, 200a, 200b, and 200c‧‧‧ light-emitting structures

11、21‧‧‧基材 11, 21‧‧‧ substrate

102‧‧‧第一導電層 102‧‧‧first conductive layer

104‧‧‧活性層 104‧‧‧active layer

106‧‧‧第二導電層 106‧‧‧Second conductive layer

107a、107b‧‧‧電極或接合墊 107a, 107b‧‧‧ electrode or bonding pad

120‧‧‧保護層 120‧‧‧ protective layer

122‧‧‧第一介電層 122‧‧‧first dielectric layer

140、240‧‧‧第二介電層 140, 240‧‧‧Second dielectric layer

222a、222b、222c、240a、240b、240c、280‧‧‧介電層 222a, 222b, 222c, 240a, 240b, 240c, 280‧‧‧ Dielectric layers

160、260a、260b、260c、162、262a、262b、262c‧‧‧金屬層 160, 260a, 260b, 260c, 162, 262a, 262b, 262c‧‧‧ metal layer

20、30、32、32’‧‧‧發光元件陣列 20, 30, 32, 32 ’‧‧‧ light emitting element array

21‧‧‧基材 21‧‧‧ substrate

22‧‧‧錫料 22‧‧‧ Tin

13、23‧‧‧電路載板 13, 23‧‧‧Circuit Carrier Board

24‧‧‧透明封裝材料 24‧‧‧ transparent packaging material

25‧‧‧發光元件封裝 25‧‧‧Light emitting element package

10、10a、10b、10c、20a、20b、20c、300、300a、300b、300c、300d、300a’、300b’、300c’、300d’‧‧‧發光元件 10, 10a, 10b, 10c, 20a, 20b, 20c, 300, 300a, 300b, 300c, 300d, 300a ’, 300b’, 300c ’, 300d’ ‧‧‧ light-emitting element

102a‧‧‧表面 102a‧‧‧ surface

101‧‧‧發光疊層 101‧‧‧light emitting stack

221‧‧‧反射層 221‧‧‧Reflective layer

260、260’‧‧‧第一金屬層 260、260’‧‧‧first metal layer

262、262’‧‧‧第二金屬層 262, 262’‧‧‧ second metal layer

290‧‧‧不透光層 290‧‧‧opaque layer

22‧‧‧金屬接觸 22‧‧‧ metal contact

22a‧‧‧導電通道 22a‧‧‧ conductive channel

294‧‧‧第一波長轉換層 294‧‧‧first wavelength conversion layer

296‧‧‧第二波長轉換層 296‧‧‧Second wavelength conversion layer

35、36、36’、65、66、37‧‧‧紅綠藍發光元件單元 35, 36, 36 ’, 65, 66, 37‧‧‧ red, green and blue light emitting element units

S1、S6’‧‧‧第一寬度 S1, S6’‧‧‧ first width

S2‧‧‧第一長度 S2‧‧‧first length

d1、d1’‧‧‧第二寬度 d1, d1’‧‧‧ second width

d2‧‧‧第二長度 d2‧‧‧second length

S3、S3’‧‧‧第一距離 S3, S3’‧‧‧ the first distance

S4‧‧‧第二距離 S4‧‧‧Second Distance

S5‧‧‧第三距離 S5‧‧‧ Third distance

298‧‧‧波長轉換層 298‧‧‧wavelength conversion layer

S1‧‧‧第一長度 S1‧‧‧first length

S6‧‧‧第一寬度 S6‧‧‧first width

680‧‧‧填充材料 680‧‧‧filler

76‧‧‧顯示模組 76‧‧‧Display Module

73‧‧‧第二電路載板 73‧‧‧Second circuit carrier board

72‧‧‧電路 72‧‧‧circuit

78‧‧‧照明模組 78‧‧‧lighting module

80‧‧‧燈泡 80‧‧‧ bulb

82‧‧‧光學透鏡 82‧‧‧optical lens

85‧‧‧散熱槽 85‧‧‧heat sink

87‧‧‧連結部 87‧‧‧Connection Department

88‧‧‧電連接器 88‧‧‧electrical connector

第1A圖至第1E圖係為依照本發明實施例之發光元件製作方法的示意圖；1A to 1E are schematic diagrams of a method for manufacturing a light emitting device according to an embodiment of the present invention;

第1F圖係為本發明實施例之發光元件之應用示意圖；FIG. 1F is a schematic diagram of an application of a light emitting element according to an embodiment of the present invention;

第2A圖至第2D圖係為依照本發明實施例之發光元件陣列製作方法的示意圖；2A to 2D are schematic diagrams of a method for manufacturing a light emitting element array according to an embodiment of the present invention;

第2E圖係為依照本發明實施例之發光元件陣列與電路板連結之示意圖；FIG. 2E is a schematic diagram showing the connection between a light emitting element array and a circuit board according to an embodiment of the present invention;

第2F圖係為依照本發明實施例之具有粗化表面之第一導電層的發光元件陣列之示意圖；FIG. 2F is a schematic diagram of a light emitting element array having a first conductive layer with a roughened surface according to an embodiment of the present invention;

第2G圖係為依照本發明實施例之發光元件陣列之封裝示意圖；Figure 2G is a schematic diagram of a package of a light emitting element array according to an embodiment of the present invention;

第3A圖至第3G圖係為依照本發明實施例之發光裝置的製作方法流程各階段所對應之剖面圖；FIG. 3A to FIG. 3G are cross-sectional views corresponding to each stage of a method of manufacturing a light-emitting device according to an embodiment of the present invention;

第4A圖係為如第3F圖所示之發光元件陣列以覆晶的形式與電路載板連接的俯視圖；FIG. 4A is a top view of the light-emitting element array shown in FIG. 3F connected to a circuit substrate in the form of a flip chip;

第4B圖係為依照本發明實施例之晶粒級的紅綠藍發光元件單元包含如第3G圖所示之紅綠藍發光元件群組之俯視圖；FIG. 4B is a top view of a grain-level red-green-blue light-emitting element unit including a red-green-blue light-emitting element group shown in FIG. 3G according to an embodiment of the present invention; FIG.

第5A圖係為依照本發明實施例之發光元件陣列以覆晶的形式與電路載板連接的俯視圖；FIG. 5A is a top view of a light-emitting element array connected to a circuit carrier board in the form of a flip chip according to an embodiment of the present invention; FIG.

第5B圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之俯視圖；FIG. 5B is a top view of a grain-level light-emitting element unit of a single light-emitting element according to an embodiment of the present invention; FIG.

第5C圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之剖面圖；FIG. 5C is a cross-sectional view of a grain-level light-emitting element unit of a single light-emitting element according to an embodiment of the present invention; FIG.

第5D圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之俯視圖；FIG. 5D is a top view of a grain-level light-emitting element unit of a single light-emitting element according to an embodiment of the present invention; FIG.

第5E圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之剖面圖；FIG. 5E is a cross-sectional view of a grain-level light-emitting element unit of a single light-emitting element according to an embodiment of the present invention; FIG.

第6A圖係為依照本發明實施例之晶粒級的紅綠藍發光元件單元的剖面圖FIG. 6A is a cross-sectional view of a grain-level red-green-blue light-emitting element unit according to an embodiment of the present invention;

第6B圖係為第6A圖所示之發光元件陣列中的單顆發光元件之示意圖；FIG. 6B is a schematic diagram of a single light-emitting element in the light-emitting element array shown in FIG. 6A; FIG.

第6C圖係為依照本發明實施例之發光元件陣列中的單顆發光元件之示意圖；FIG. 6C is a schematic diagram of a single light-emitting element in a light-emitting element array according to an embodiment of the present invention; FIG.

第7A圖至第7G圖係為依照本發明實施例之一種發光裝置的製作方法流程各階段所對應之剖面圖；7A to 7G are cross-sectional views corresponding to each stage of a manufacturing method process of a light-emitting device according to an embodiment of the present invention;

第7H圖係為依照本發明實施例之晶粒級的紅綠藍發光元件單元包含如圖7G所示之紅綠藍發光元件群組之俯視圖；FIG. 7H is a top view of a grain-level red-green-blue light-emitting element unit including a red-green-blue light-emitting element group shown in FIG. 7G according to an embodiment of the present invention; FIG.

第7I圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之剖面圖；FIG. 7I is a cross-sectional view of a grain-level light-emitting element unit of a single light-emitting element according to an embodiment of the present invention; FIG.

第7J圖係為依照本發明實施例之單一發光元件的晶粒級的發光元件單元之俯視圖；FIG. 7J is a top view of a grain-level light-emitting element unit of a single light-emitting element according to an embodiment of the present invention; FIG.

第8A圖係為依照本發明實施例之顯示模組之示意圖；FIG. 8A is a schematic diagram of a display module according to an embodiment of the present invention; FIG.

第8B圖係為依照本發明實施例之顯示模組之示意圖；以及FIG. 8B is a schematic diagram of a display module according to an embodiment of the present invention; and

第9圖係為依照本發明實施例之燈泡元件分解圖。FIG. 9 is an exploded view of a light bulb element according to an embodiment of the present invention.

Claims (10)

一種發光元件，包含：一第一半導體導電層；一第二半導體導電層；一活性層位於該第一半導體導電層與該第二半導體導電層之間；一第二電極位於該第二半導體導電層之上，並與該第二半導體導電層電性連接；一第一金屬層與該第一半導體導電層電性連接；一第二金屬層覆蓋該第二電極並與該第二半導體導電層電性連接，該第二金屬層包含一第一部分、一第二部分位於該第一部份之上、以及一第三部分位於該第二部分之上；以及一介電層位於該第一金屬層與該第二金屬層之間，具有一上表面與該第一金屬層與該第二金屬層大體上共平面；其中，該發光元件具有一粗化上表面，該粗化上表面與該第二電極位於該活性層的相對側，且該粗化上表面未被藍寶石覆蓋，其中，該第一部分、該第二部分及該第三部分中至少兩者之寬度互不相同，該第三部分的寬度大於該第二電極的寬度。A light-emitting element includes: a first semiconductor conductive layer; a second semiconductor conductive layer; an active layer between the first semiconductor conductive layer and the second semiconductor conductive layer; a second electrode located on the second semiconductor conductive layer Layer, and is electrically connected to the second semiconductor conductive layer; a first metal layer is electrically connected to the first semiconductor conductive layer; a second metal layer covers the second electrode and is in contact with the second semiconductor conductive layer For electrical connection, the second metal layer includes a first portion, a second portion on the first portion, and a third portion on the second portion; and a dielectric layer on the first metal Between the layer and the second metal layer, an upper surface is substantially coplanar with the first metal layer and the second metal layer; wherein the light emitting element has a roughened upper surface, and the roughened upper surface and the The second electrode is located on the opposite side of the active layer, and the roughened upper surface is not covered by sapphire, wherein at least two of the first portion, the second portion, and the third portion have different widths from each other, and the third portion section A width greater than the width of the second electrode. 如請求項1所述之發光元件，更包含一第一電極位於該第一半導體導電層之上，並與該第一半導體導電層電性連接。The light-emitting device according to claim 1, further comprising a first electrode located on the first semiconductor conductive layer and electrically connected to the first semiconductor conductive layer. 如請求項2所述之發光元件，其中，該第一金屬層覆蓋該第一電極，該第一金屬層的最大寬度大於該第一電極的最大寬度。The light-emitting device according to claim 2, wherein the first metal layer covers the first electrode, and a maximum width of the first metal layer is larger than a maximum width of the first electrode. 如請求項1所述之發光元件，其中，該介電層直接接觸該第一金屬層與該第二金屬層之一側壁。The light-emitting device according to claim 1, wherein the dielectric layer directly contacts a sidewall of the first metal layer and the second metal layer. 如請求項1所述之發光元件，更包含一封裝材料覆蓋該粗化的上表面。The light-emitting element according to claim 1, further comprising a packaging material covering the roughened upper surface. 如請求項1所述之發光元件，更包含一保護層位於該第二金屬層與該第二半導體導電層之間，並覆蓋該第二半導體導電層以及該活性層的側壁。The light-emitting element according to claim 1, further comprising a protective layer between the second metal layer and the second semiconductor conductive layer, and covering the second semiconductor conductive layer and the sidewall of the active layer. 如請求項6所述之發光元件，更包含一反射層位於該保護層上。The light-emitting element according to claim 6, further comprising a reflective layer on the protective layer. 如請求項1所述之發光元件，更包含一波長轉換層覆蓋該粗化的上表面。The light-emitting element according to claim 1, further comprising a wavelength conversion layer covering the roughened upper surface. 如請求項8所述之發光元件，其中該波長轉換層的材料包含量子點。The light-emitting element according to claim 8, wherein the material of the wavelength conversion layer includes quantum dots. 如請求項8所述之發光元件，更包含一透明封裝材料覆蓋該波長轉換層。The light-emitting element according to claim 8, further comprising a transparent packaging material covering the wavelength conversion layer.
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