TWI663696B - 於半導體裝置中形成為金屬線互連之凸塊連結 - Google Patents
於半導體裝置中形成為金屬線互連之凸塊連結 Download PDFInfo
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- TWI663696B TWI663696B TW104116554A TW104116554A TWI663696B TW I663696 B TWI663696 B TW I663696B TW 104116554 A TW104116554 A TW 104116554A TW 104116554 A TW104116554 A TW 104116554A TW I663696 B TWI663696 B TW I663696B
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Abstract
本發明揭示一種半導體功率晶片,其具有形成於一半導體晶粒上之一半導體功率裝置;其中該半導體功率裝置包括:一導電接觸元件陣列;一鈍化層,其形成於該複數個導電接觸元件上方,該鈍化層包括複數個該等導電接觸元件上方之鈍化開口;及一導電凸塊陣列,其包含一或多個互連凸塊,其中每一互連凸塊形成於該鈍化層上方並延伸至該等鈍化開口中之至少兩者中且與至少兩個下伏導電接觸元件接觸,以藉此提供該至少兩個下伏導電接觸元件之間的一導電耦合。
Description
本申請案主張於2014年5月22日提出申請之第62/002,164號美國臨時申請案之權益,該美國臨時申請案之全文併入本文中。
本發明係關於半導體裝置(例如,功率FET或其他半導體功率裝置),且更特定而言係關於使用充當單獨金屬線之間的互連之凸塊連結進行之至一引線框架之一半導體功率裝置之製作。
半導體功率裝置通常在高電流密度下操作,且因此,需要具有足夠低接觸電阻之載流導體來充分地處置去往及來自裝置之電流。然而,在半導體功率裝置之製作期間存在對金屬沈積厚度之限制。此金屬沈積厚度限制使必須在半導體功率裝置(例如,功率場效電晶體(功率FET))之前側及背側兩者上沈積金屬導體成為必需。但必須使用裝置之功率元件之背側觸點(例如,汲極)需要大量處理來消除半導體基板之串聯電阻,藉此給最終半導體功率產品添加顯著成本。
因此,期望減少製造一半導體功率裝置之處理步驟,且藉此減少其製造成本。
根據一實施例,一種半導體功率晶片可包括形成於一半導體晶粒上之一半導體功率裝置;其中該半導體功率裝置包括:一導電接觸
元件陣列;一鈍化層,其形成於該複數個導電接觸元件上方,該鈍化層包括複數個該等導電接觸元件上方之鈍化開口;及一導電凸塊陣列,其包含一或多個互連凸塊,其中每一互連凸塊形成於該鈍化層上方並延伸至該等鈍化開口中之至少兩者中且與至少兩個下伏導電接觸元件接觸,以藉此提供該至少兩個下伏導電接觸元件之間的一導電耦合。
根據又一實施例,該導電接觸元件陣列可包括至少一個閘極接觸元件、至少一個源極接觸元件及至少一個汲極接觸元件。根據又一實施例,該導電接觸元件陣列可包括平行配置之複數個細長接觸條帶。根據又一實施例,複數個鈍化開口可配置於每一源極接觸元件及汲極接觸元件上方。根據又一實施例,該一或多個互連凸塊可包括提供至少兩個經電隔離源極區之間的一導電耦合之至少一個源極互連凸塊。根據又一實施例,該一或多個互連凸塊可包括提供至少兩個經電隔離汲極區之間的一導電耦合之至少一個汲極互連凸塊。根據又一實施例,該半導體功率晶片可進一步包括一引線框架,該引線框架耦合至該導電凸塊陣列,使得該一或多個互連凸塊提供該導電接觸元件陣列之至少一部分與該引線框架之間的一導電耦合。根據又一實施例,該半導體功率裝置可僅包括一單個金屬互連層,該單個金屬互連層包含該導電接觸元件陣列。根據又一實施例,該導電凸塊陣列可包含一或多個非互連凸塊,每一非互連凸塊延伸成僅與一單個下伏導電觸點接觸。根據又一實施例,該導電凸塊陣列可僅包含互連凸塊。
根據另一實施例,一種半導體功率裝置可包括如上文所闡述之一半導體功率晶片且可進一步包括:一引線框架,其具有包括閘極、源極及汲極引線指狀物之一區域,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以連接至該至少一個閘極接觸元件、該複數個源極接觸元件及該複數個汲極接觸元件中之每一者;及
一外殼,其環繞該半導體功率晶片及該引線框架。
根據再一實施例,一種半導體功率裝置可包括至少一第一半導體功率晶片及一第二半導體功率晶片(每一半導體功率晶片如上文所闡述而形成)且可進一步包括:一引線框架,其具有一第一區域及一第二區域,第一區域及第二區域中之每一者包括閘極、源極及汲極引線指狀物,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以分別連接至該第一半導體晶片及該第二半導體晶片之該至少一個閘極接觸元件、該複數個源極接觸元件及該複數個汲極接觸元件中之每一者;及一外殼,其環繞該第一半導體功率晶片及該第二半導體功率晶片以及該引線框架。
根據再一實施例,一種半導體裝置可包括如上文所闡述之一半導體功率晶片且進一步包括:另一晶片;一引線框架,其具有包括閘極、源極及汲極引線指狀物之一第一區域及經組態以用於導線連結該另一晶片之一第二區域,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以連接至該半導體功率晶片之該至少一個閘極接觸元件、該複數個源極接觸元件及該複數個汲極接觸元件中之每一者;及一外殼,其環繞該半導體功率晶片、該另一晶片及該引線框架。
根據又一實施例,該另一晶片可為可操作以控制該半導體功率晶片之一微控制器晶片。根據又一實施例,該另一晶片可為可操作以控制該半導體功率晶片之一脈衝寬度調變晶片。根據又一實施例,可以覆晶方式安裝該另一晶片。根據又一實施例,該引線框架可經設計以提供該另一晶片與該半導體功率晶片之間的連接。
根據再一實施例,一種半導體裝置可包括至少一第一半導體功率晶片及一第二半導體功率晶片(每一半導體功率晶片如上文所闡述而形成)且進一步包括:一第三晶片;一引線框架,其具有一第一區
域及一第二區域及經組態以用於導線連結該另一晶片之一第三區域,第一區域及第二區域中之每一者包括閘極、源極及汲極引線指狀物,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以分別連接至該第一半導體晶片及該第二半導體晶片之該至少一個閘極接觸元件、該複數個源極接觸元件及該複數個汲極接觸元件中之每一者;及一外殼,其環繞該第一半導體功率晶片及該第二半導體功率晶片、該第三晶片及該引線框架。
根據又一實施例,該第三晶片可為可操作以控制該半導體功率晶片之一微控制器晶片。根據又一實施例,該第三晶片可為可操作以控制該半導體功率晶片之一脈衝寬度調變晶片。根據又一實施例,可以覆晶方式安裝該第三晶片。
根據又一實施例,該引線框架可經設計以提供該第三晶片與該第一半導體功率晶片及該第二半導體功率晶片之間的連接。
根據再一實施例,一種半導體功率裝置可包括:一外殼;一半導體功率裝置,其包括以覆晶組態配置於該外殼內之一半導體晶粒及一引線框架,其中該半導體晶粒包括一導電接觸元件陣列及形成於該複數個導電接觸元件上方之一鈍化層,該導電接觸元件陣列包括至少一個閘極接觸元件、至少一個源極接觸元件及至少一個汲極接觸元件,該鈍化層包括複數個該等導電接觸元件上方之鈍化開口;一導電凸塊陣列,其包含一或多個互連凸塊,其中每一互連凸塊形成於該鈍化層上方並延伸至該等鈍化開口中之至少兩者中且與至少兩個下伏導電接觸元件接觸,以藉此提供該至少兩個下伏導電接觸元件之間的一導電耦合,且其中該引線框架具有包括閘極、源極及汲極引線指狀物之一區域,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以連接至該至少一個閘極接觸元件、該複數個源極接觸元件及該複數個汲極接觸元件中之每一者。
根據又一實施例,該導電接觸元件陣列可包括平行配置之複數個細長接觸條帶。根據又一實施例,複數個鈍化開口可配置於每一源極接觸元件及汲極接觸元件上方。根據又一實施例,該一或多個互連凸塊可包括提供至少兩個經電隔離源極區之間的一導電耦合之至少一個源極互連凸塊。根據又一實施例,該一或多個互連凸塊可包括提供至少兩個經電隔離汲極區之間的一導電耦合之至少一個汲極互連凸塊。
10‧‧‧半導體晶粒
12‧‧‧鈍化開口/開口
12a‧‧‧鈍化開口/鈍化層開口
12b‧‧‧鈍化開口/鈍化層開口
12c‧‧‧鈍化開口/鈍化層開口
12d‧‧‧鈍化開口/鈍化層開口
12e‧‧‧鈍化開口/鈍化層開口
12f‧‧‧鈍化開口/鈍化層開口
14‧‧‧導電凸塊
20‧‧‧引線框架
102‧‧‧功率半導體晶粒/晶粒/半導體晶粒
104‧‧‧引線框架
110A‧‧‧閘極金屬接觸區/金屬接觸區/閘極球形凸塊/閘極金屬2
線
110B‧‧‧汲極金屬接觸區/金屬接觸區/汲極球形凸塊/汲極金屬2線
110C‧‧‧源極金屬接觸區/金屬接觸區/源極球形凸塊/源極金屬2線
120‧‧‧凸塊
120’‧‧‧凸塊
120A‧‧‧球形凸塊
120A’‧‧‧細長凸塊
120B‧‧‧球形凸塊
120B’‧‧‧細長凸塊
120C‧‧‧球形凸塊
120C’‧‧‧細長凸塊
130B‧‧‧汲極金屬1線
130C‧‧‧源極金屬1線
140‧‧‧導電通體/導通體
150‧‧‧鈍化層
152‧‧‧鈍化開口
200‧‧‧球形凸塊/凸塊/非互連凸塊
200A‧‧‧凸塊
200a’‧‧‧互連凸塊
200B’‧‧‧汲極互連凸塊
200C’‧‧‧源極互連凸塊
200c’‧‧‧互連凸塊
200e’‧‧‧互連凸塊
210‧‧‧單金屬互連層式半導體裝置/裝置/半導體功率裝置
230A‧‧‧閘極金屬線/金屬線
230B‧‧‧汲極金屬線/金屬線/單獨汲極金屬線/汲極金屬1線
230C‧‧‧源極金屬線/金屬線/單獨源極金屬線/單獨下伏源極金屬1線/源極金屬1線
240‧‧‧半導體晶粒
250‧‧‧鈍化層
252‧‧‧鈍化開口
260‧‧‧鈍化開口
510‧‧‧引線框架
530‧‧‧晶片/功率電晶體晶片/第二晶片
540‧‧‧元件符號/支撐結構
560‧‧‧連結導線
570‧‧‧接腳/外部接腳/元件符號/單獨接腳/指定接腳
610‧‧‧引線框架
620‧‧‧第一晶片/微控制器晶片
650‧‧‧連結墊
710‧‧‧引線框架/外部接腳
720‧‧‧電晶體晶片/功率電晶體晶片
730‧‧‧電晶體晶片/功率電晶體晶片
740‧‧‧連結導線
750‧‧‧連結導線
810‧‧‧引線框架
820‧‧‧控制器晶片/微控制器晶片/晶片
830‧‧‧功率電晶體晶片/晶片/功率電晶體/電晶體
840‧‧‧功率電晶體晶片/晶片/功率電晶體/電晶體/場效電晶體
910‧‧‧部件/較暗陰影區域
920‧‧‧部件/較亮綠色區域
930‧‧‧編號
940‧‧‧小墊
1010‧‧‧垂直線
1020‧‧‧橢圓形件/凸塊
1030‧‧‧正方形/開口
1040‧‧‧橢圓形/凸塊
1050‧‧‧連接墊
1110‧‧‧大連接區域
1120‧‧‧大連接區域
圖1A、圖1B、圖1C展示具有鈍化開口、焊料凸塊之一陣列及引線框架之一習用半導體晶粒;圖2A、圖2B展示一習用功率電晶體晶粒及相關聯引線框架;圖3及圖4展示功率電晶體晶粒上之凸塊之習用配置;圖5展示以覆晶技術安裝於一引線框架上之一習用功率電晶體晶粒之沿著圖3及圖4之線5-5之一剖面圖;圖6展示一習用功率電晶體晶粒之金屬層之一俯視圖;圖7A、圖7B、圖7C展示根據各種實施例之具有鈍化開口、相關聯焊料凸塊之一陣列及引線框架之一半導體晶粒;圖8展示根據各種實施例之一功率電晶體晶片之一俯視圖;圖9展示沿著圖8之線9-9之一剖面圖;圖10至圖12展示根據某些實施例之引線框架以及功率電晶體之實例;圖13及圖14展示根據某些實施例之一引線框架及功率電晶體晶片配置;圖15展示根據再一實施例之一功率電晶體;圖16及圖17展示一微控制器晶片及以覆晶技術在一引線框架上之放置;
圖18展示根據一實施例之一引線框架之一相片;圖19展示根據一實施例之具有經安裝晶片之一引線框架之一相片;圖20展示根據一實施例之呈俯視圖及仰視圖之多晶粒積體電路之一相片;圖21展示經設計以接納如圖20中所展示之一積體電路之一印刷電路板之一例示性佈局。
如在於2011年11月3日提出申請且公開為US 2012/0126406之同在申請中之申請案13/288,108(在下文中稱為「‘108申請案」)(該申請案之全部內容以引用方式併入本文中)中所揭示,一半導體功率晶片可具有一半導體晶粒,該半導體晶粒具有製作於其一基板上之一功率裝置,其中功率裝置藉由一凸塊連結(例如,球形凸塊或條形凸塊)陣列來導電地連接至一對應引線框架。舉例而言,一半導體功率晶片可具有一半導體晶粒,該半導體晶粒具有製作於其一基板上之一功率裝置,其中該功率裝置具有配置於該半導體晶粒之頂部上之複數個閘極金屬接觸區、源極金屬接觸區及汲極金屬接觸區。可將複數個球形凸塊或一條形凸塊安置於每一金屬接觸區上,且一引線框架具有包括閘極、源極及汲極引線指狀物之一區域,該等閘極、源極及汲極引線指狀物與該複數個球形凸塊或該條形凸塊相匹配以連接至金屬接觸區中之每一者。
如在‘108申請案中所論述,使用一凸塊或條塊陣列來分佈半導體功率裝置之元件與一厚得多的引線框架之間的電流消除對一單獨背側觸點及後續處理步驟之需要。該凸塊或條塊陣列可包括以一「凸出條塊」組態配置於半導體元件中之每一者上之一單個條形凸塊或複數個球形凸塊。然後可使用覆晶球連結技術將半導體功率裝置附接至一引
線框架。此產生半導體功率裝置之較低處理及製造成本以及一較小外觀尺寸。不需要低電阻基板且消除了一磊晶矽生長步驟。可在一外殼內將此一經安裝功率裝置組合並連接至一第二晶片,其中該第二晶片可包括一微控制器或脈衝寬度調變控制器。
本發明提供對‘108申請案中所揭示之概念之進一步發明性改良。舉例而言,本發明提供用於形成凸塊連結(「凸塊」)之一方法,該等凸塊連結不僅允許將半導體裝置連接至引線框架,而且亦充當單獨製作金屬線之間的互連。此外,該等凸塊可用以將複數個引線框架跡線互連至一單個製作金屬線。在相關現有技術之一論述之後,在下文中論述此等概念。
圖1A展示具有形成於一鈍化層中之鈍化開口12之一陣列之一半導體晶粒10之一大體示意性平面圖,每一鈍化開口12通往一下伏金屬接觸區(例如,閘極、源極或汲極金屬接觸區)。圖1B展示具有形成於每一鈍化開口12中之導電凸塊14的圖1A之半導體晶粒10。圖1C展示一引線框架20,該引線框架具有待連接至圖1B中所展示之凸塊14之一對應圖案,藉此形成半導體晶粒10之下伏金屬接觸區與引線框架20之間的觸點。
圖2A及圖2B分別展示(例如)根據‘108申請案之一半導體功率裝置之一示意性平面圖及一對應引線框架之一平面圖。如圖2A中所展示,一功率半導體晶粒102可包括一閘極(G)金屬接觸區110A、汲極(D)金屬接觸區110B及源極(S)金屬接觸區110C。細長金屬接觸區110可稱為「指狀物」。可藉由沈積於(舉例而言)第二金屬層之頂部上之互連金屬層之頂部上之一經圖案化金屬層形成凸塊金屬指狀物110。舉例而言,可將源極區及汲極區連接至一第一金屬層上之金屬流道,然後一第二金屬層可形成較寬金屬流道,該等較寬金屬流道將係將沈積頂部觸點之凸塊金屬之位置。
如圖2B中所展示,具有一導電框架及引線指狀物之一對應引線框架104經調適以依一「覆晶」組態經由配置於各種金屬接觸區110A、110B及110C上之複數個導電凸塊而耦合至半導體功率裝置,如下文所闡述。以一「最終狀態」繪示圖2B中所展示之引線框架104,換言之,已移除指狀物之間的任何支撐接頭。
圖3展示形成於圖2A之晶粒102上之半導體功率裝置,其中球形凸塊120A、120B及120C分別形成於金屬接觸區110A、110B及110C上。球形凸塊可包括焊料球形凸塊、導電環氧樹脂球形凸塊等等。可以一「覆晶」組態將引線框架104配置於半導體晶粒102上方,其中引線框架104之指狀物接觸半導體裝置上之各別球形凸塊120A、120B及120C。因此,一閘極引線指狀物連接至閘極球形凸塊110A,汲極引線指狀物連接至汲極球形凸塊110B且源極引線指狀物連接至源極球形凸塊110C,例如,如‘108申請案中所闡述。
圖4展示形成於圖2A之晶粒102上之半導體功率裝置,其中細長凸塊120A’、120B’及120C’(作為圖3中所展示之球形凸塊之一替代方案)分別形成於金屬接觸區110A、110B及110C上。可以如上文所論述之一類似方式將引線框架104耦合至細長凸塊120A’、120B’及120C’。
圖5係透過圖3或圖4中之線「5-5」所截取之經組裝引線框架與半導體功率裝置之一剖面圖。如所展示,半導體功率裝置包含形成於包含源極金屬1線130C(以及並未在此視圖中展示之汲極金屬1線及閘極金屬1線)之一第一金屬層上方之一第二金屬層(包含源極金屬2線110C、汲極金屬2線110B及閘極金屬2線110A),其中第二金屬層之源極金屬2線110C藉由導電通體140連接至下伏於該第二金屬層之源極金屬1線130C。形成於第二金屬層上方之一鈍化層150包含鈍化開口152,凸塊120或120’透過該等鈍化開口延伸成與第二金屬層之各別下伏金屬接觸區(在此視圖中,源極金屬2線110C)接觸。最後,將引線
框架104配置成與凸塊120或120’接觸,藉此將該引線框架導電地連接至半導體功率裝置。
圖6展示圖5之實例性雙金屬層式半導體功率裝置之一示意性平面圖,該示意性平面圖展示第一金屬層上方之第二金屬層之配置且展示第一金屬層之源極金屬1線130C及汲極金屬1線130B兩者。圖6中並未展示連接各別金屬1層及金屬2層之導通體140。
圖7A至圖7C展示根據各種實施例使用凸塊來互連半導體裝置之單獨金屬接觸區/線,同時提供至引線框架之連接之一實例。圖7A展示具有形成於一鈍化層中之鈍化開口12之一陣列之一半導體晶粒10之一示意性平面圖,每一開口通往一下伏金屬接觸區(例如,如在上文中關於圖1A所論述)。在半導體內,可不連接下伏於開口12之金屬層。因此,習用裝置將需要一額外金屬層。根據各種實施例,可避免此等額外層。
圖7B展示圖1A之半導體晶粒10,其中球形凸塊200形成於某些鈍化開口12中,且互連凸塊200a’、200c’、200e’形成於其他鈍化開口12a至12f中且在鈍化層上方延伸以連接兩個或兩個以上下伏金屬接觸區。因此,互連凸塊200a’透過鈍化層開口12a及12b連接兩個金屬層。互連凸塊200c’透過鈍化層開口12c及12d連接兩個金屬層,且互連凸塊200e’透過鈍化層開口12e及12f連接兩個金屬層。根據其他實施例,其他組態係可能的且一互連凸塊200’亦可連接兩個以上下伏金屬層。
圖7C展示一引線框架20,該引線框架具有待連接至凸塊200及200’之一對應圖案,藉此形成半導體晶粒10之下伏金屬接觸區與引線框架20之間的觸點。每一互連凸塊200’可連接任何適合數目個下伏金屬接觸區,例如,兩個、三個、四個或更多接觸區。此外,一特定組態可包含互連凸塊200’及非互連凸塊200(例如,圖7B中所展示之球
形凸塊)兩者,或可僅包含互連凸塊200’。
因此,互連凸塊200’可在可替換一個金屬互連層之凸塊層中提供路由。因此,在某些實施例中,半導體裝置可僅需要一單個金屬互連層,而非包含於圖5及圖6之設計中之兩個金屬層,其中減少一金屬層可減少製作成本。此外,如與圖5及圖6之設計相比,此等互連凸塊200’之使用可提供具有較低電阻之一「頂部金屬層」。
圖8展示根據一項實例性實施例之一單金屬互連層式半導體裝置210(例如,一功率FET裝置)上之互連凸塊200’之一實例性配置之一示意性平面圖。如所展示,裝置210包含一單個金屬互連層,該金屬互連層包含一閘極金屬線230A、汲極金屬線230B及源極金屬線230C。一凸塊200A經由一對應鈍化開口260形成於閘極金屬線230A上方並與閘極金屬線230A連接。可取決於各別金屬線230A、230B、230C之大小而在大小上調適鈍化開口260。複數個汲極互連凸塊200B’經形成以經由各別鈍化開口互連單獨汲極金屬線230B,且複數個源極互連凸塊200C’經形成以經由各別鈍化開口互連單獨源極金屬線230C。
圖9係透過圖8中所展示之線「9-9」所截取的圖8之半導體功率裝置210之一剖面圖,且該剖面圖展示以一覆晶安裝組態組裝至半導體功率裝置210之一引線框架104。如所展示,半導體功率裝置210包含一單個金屬互連層,該金屬互連層包含形成於一半導體晶粒240上之源極金屬1線230C、汲極金屬1線230B及閘極金屬2線(未經展示)。形成於金屬互連層上方之一鈍化層250包含鈍化開口252,源極互連凸塊200C’透過該等鈍化開口延伸成與多個單獨下伏源極金屬1線230C接觸,使得每一源極互連凸塊200C’將多個源極金屬1線230C連接至引線框架,藉此在凸塊層中提供路由,並允許消除一第二金屬互連層,如上文所闡述。
圖10展示安裝於如上文所闡釋之一引線框架510上之一晶片530
之一第一實例。引線框架可具有複數個外部接腳570,其在所展示之實例中具有8個接腳。所展示之功率電晶體晶片530使用用於汲極連接之四個接腳570及用於源極連接之三個接腳570。一單個接腳用於閘極連接。出於安裝目的且在囊封之前,引線框架可包括複數個支撐連接,該等支撐連接中之三個支撐連接藉由元件符號540參考。用於外部連接之接腳570可為單獨接腳或形成如圖10中所展示之一經連接接腳群組。因此,在一群組內此等接腳之間的任一支撐連接可保持。此外根據其他實施例,較寬接腳可用於源極汲極連接以支援一較高電流。
特定控制電路應用(特定而言微控制器應用)需要對功率電晶體之控制,舉例而言,切換模式電力供應控制器、降壓轉換器或馬達控制應用。因此此等應用通常使用單獨離散功率電晶體。根據各種實施例,一脈衝寬度調變器或甚至一微控制器可與如上文所闡述之一功率電晶體封裝在一起。
圖11展示一引線框架610之一實例,該引線框架可支撐以習用連結技術耦合至引線框架610之一第一晶片620(舉例而言,一微控制器晶片)及包括如上文所闡述之一個功率電晶體且使用上文所提及之覆晶凸塊連結技術安裝至該引線框架之一第二晶片530。元件符號570同樣指示引線框架510之一外部接腳。此外在圖11中展示具有複數個支撐連接之引線框架610,該等支撐連接中之四個支撐連接藉由元件符號540指示。如上文所提及,在將裝置封圍於一外殼中之前切除此等支撐結構以消除框架中及至指定接腳570之恰當連接中之任何非想要短路。如所展示,可在引線框架610上之適當連接點處(例如使用連結導線560)將第一晶片620互連至源極、汲極及閘極指狀物中之至少一者。在第一晶片620使用單獨接腳570以各自連接至一連結墊650時,引線框架之用於第二晶片之區段可同樣將多個接腳570連接至每一源
極及汲極連接以提供一低電阻並支援高電流。然而,根據各種實施例,其他外部接腳(舉例而言,較寬接腳)可用於第二晶片530之源極及/或汲極觸點。如上文所提及,第一晶片520可為可操作以與一功率電晶體直接介接之一脈衝寬度調變裝置、一控制器或一微控制器。為此,此等裝置具有能夠直接驅動功率電晶體之閘極之積體驅動器。
圖12展示包括一引線框架710之再一實施例,該引線框架具有藉由標準導線連結而連接之一微控制器晶片620及以如上文所闡釋之覆晶技術安裝之兩個功率電晶體晶片720及730。右側之區段包括兩個功率電晶體。此處,與圖11相比,提供額外外部接腳710以經由連結導線750與經互連源極-汲極區段310耦合。兩個電晶體晶片720、730之任一源極、汲極及/或閘極可經由微控制器晶片620之一連結導線740連接至一連結墊650,如圖12中所例示性展示。此外,圖12展示將在囊封之前被移除之複數個支撐結構540。
圖13展示包括一引線框架810之再一實施例,該引線框架具有一微控制器晶片820或適合的任何其他控制單元以及兩個功率電晶體晶片830及840。在此實施例中,以如上文所闡釋之覆晶技術安裝所有晶片。如在此實施例中可見,根本不使用連結導線。因此,亦以覆晶技術設計控制器晶片820。引線框架810用以提供微控制器晶片820與兩個功率電晶體830及840之間的互連。控制器晶片820使用一再分佈層且然後經凸塊連接至引線框架810。然後將其放置於引線框架上並蝕刻該引線框架以提供路由。
如在圖13中可見,在此實施例中,功率電晶體840係功率電晶體830之大小的兩倍。對於某些應用而言,下部FET(其中其源極連接至接地)係與供應電壓Vin耦合之上部FET的兩倍。舉例而言,在一切換模式電力供應器中此一應用可使用一供應電壓12V及0.8至2.5輸出電壓Vout。然而,可挑選FET之其他尺寸且圖13僅展示一個可能配置。
圖14僅單獨展示圖13之引線框架810,其中最後曝露於經封裝積體電路中之部件910比該引線框架之其他部件920的陰影暗。因此,僅將較暗陰影區域910向下焊接於一印刷電路板上。較亮綠色區域920仍係引線框架,但其僅曝露於其中各別晶粒將翻轉至其上之封裝內部,或其用於路由信號,特定而言用於微控制器晶片820。
因此,各別連接指狀物之細長條帶及部件用以針對功率電晶體830及840提供適合於攜載大電流之一大外部連接區域,其中針對微控制器晶片820提供小正方形連接墊。編號930展示至各別電晶體830及840之閘極連接以及至控制器晶片820之各別連接。該閘極連接亦可透過在此處與控制器晶片820相關聯之各別小墊940而外部接達。
圖15展示可如何以覆晶技術將一功率電晶體晶片830安裝並連接於一封裝內之另一實例。垂直線1010係製作金屬1線,橢圓1020、1040係凸塊且較小正方形1030係鈍化開口。因此,圖15展示在一個可能配置中凸塊如何互連個別金屬1線。如在此實施例中可見,與汲極或源極指狀物相關聯之每一凸塊1020連接多個指狀物(舉例而言,5個指狀物),其中凸塊1040僅使用一單個開口1030來連接至各別閘極指狀物。然後將此晶片830向上翻轉至如圖13中所展示之一相關聯引線框架810之條帶上。
圖16展示僅展示有連接墊1050之一微控制器晶片820之一仰視圖。圖17展示具有放置於引線框架上之微控制器的圖13之一經放大區段。類似於圖17中所展示,晶片820至840經指示配置於引線框架810下方。
圖18展示在安裝之前一引線框架本身之一實際圖片。區域係經曝露以用於外部連接。圖19展示具有翻轉並安裝於其上之3個半導體晶片之引線框架。圖20展示兩個最終積體電路封裝之一俯視圖,其中與一硬幣相比,一個晶片已經倒置。圖21展示如在一各別CAD程式中
所展示之一印刷電路板之一例示性設計。如可見,提供大連接區域1110及1120以連接至經提供用於下部FET 840之源極及汲極之引線框架區域。
如圖13至圖20之實施例中所展示之控制器晶片及功率電晶體之原理配置亦可應用至如圖11中所展示之一控制器及一單個功率電晶體。各種圖中所展示之實施例並不限於場效電晶體,而且亦可用於任何類型之雙極電晶體結構。
儘管已參考本發明之實例性實施例來繪示、闡述及界定本發明之實施例,但此等參考並不暗示對本發明之一限制,且不應推斷出存在此限制。所揭示之標的物能夠在形式及功能上具有大量修改、變更及等效形式,熟悉此項技術者將會想到此等修改、變更及等效形式並受益於本發明。
Claims (26)
- 一種設備,其包括:一導電接觸元件陣列;一鈍化層,其形成於該複數個導電接觸元件上方,該鈍化層包括複數個該等導電接觸元件上方之多個鈍化開口;一導電凸塊陣列,其包含一或多個互連凸塊,其中每一互連凸塊形成於該鈍化層上方並延伸至該等鈍化開口中之至少兩者中且與至少兩個下伏導電接觸元件接觸,以藉此提供該至少兩個下伏導電接觸元件之間的一導電耦合;一前側汲極連接;一前側源極連接,其與該前側汲極連接在相同之一源極金屬胞元內;及僅一單個金屬互連層,其包含該導電接觸元件陣列;其中該前側源極連接及該前側汲極連接由一相同導電凸塊覆蓋。
- 如請求項1之設備,其中該導電接觸元件陣列包括至少一個閘極接觸元件、至少一個源極接觸元件及至少一個汲極接觸元件。
- 如請求項1之設備,其中該導電接觸元件陣列包括平行配置之複數個細長的接觸條帶。
- 如請求項2之設備,其中複數個鈍化開口係配置在每一源極接觸元件及每一汲極接觸元件上。
- 如請求項1之設備,其中該一或多個互連凸塊包括提供經電隔離的至少兩個源極區之間的一導電耦合之至少一個源極互連凸塊。
- 如請求項1之設備,其中該一或多個互連凸塊包括提供經電隔離的至少兩個汲極區之間的一導電耦合之至少一個汲極互連凸塊。
- 如請求項1之設備,其進一步包括一引線框架,該引線框架耦合至該導電凸塊陣列,使得該一或多個互連凸塊提供該導電接觸元件陣列之至少一部分與該引線框架之間的一導電耦合。
- 如請求項1之設備,其中該導電凸塊陣列包含一或多個非互連凸塊,每一非互連凸塊延伸成僅與一單個下伏導電觸點接觸。
- 如請求項1之設備,其中該導電凸塊陣列包含兩個或更多個互連凸塊且僅包含多個互連凸塊。
- 如請求項2之設備,其進一步包括:一引線框架,其具有包括閘極、源極及汲極引線指狀物之一區域,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以連接至該至少一個閘極接觸元件、複數個源極接觸元件及複數個汲極接觸元件中之每一者,及一外殼,其環繞該半導體功率晶片及該引線框架。
- 如請求項2之設備,其進一步包括:另一晶片;一引線框架,其具有包括閘極、源極及汲極引線指狀物之一第一區域及一第二區域,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以連接至該半導體功率晶片之該至少一個閘極接觸元件、複數個源極接觸元件及複數個汲極接觸元件中之每一者,該第二區域經組態用於導線連結或覆晶耦合該另一晶片,及一外殼,其環繞一半導體功率晶片、該另一晶片及該引線框架。
- 如請求項11之設備,其中該另一晶片係可操作以控制該半導體功率晶片之一微控制器晶片。
- 如請求項11之設備,其中該另一晶片係可操作以控制該半導體功率晶片之一脈衝寬度調變晶片。
- 如請求項11之設備,其中該另一晶片以覆晶方式安裝。
- 如請求項14之設備,其中該引線框架經設計以提供該另一晶片與該半導體功率晶片之間的連接。
- 一種半導體功率裝置,其包括至少一第一半導體功率晶片及至少一第二半導體功率晶片,如請求項2之設備形成每一半導體功率晶片,該半導體功率裝置進一步包括:一引線框架,其具有一第一區域及一第二區域,第一區域及第二區域之每一者包括閘極、源極及汲極引線指狀物,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以分別連接至該第一半導體功率晶片及該第二半導體功率晶片之該至少一個閘極接觸元件、該複數個源極接觸元件及該複數個汲極接觸元件中之每一者,及一外殼,其環繞該第一半導體功率晶片及該第二半導體功率晶片及該引線框架。
- 一種設備,其包括至少一第一半導體功率晶片及一第二半導體功率晶片,如請求項2形成每一半導體功率晶片,其進一步包括:一第三晶片;一引線框架,其具有一第一區域及一第二區域及經組態以用於導線連結該第三晶片之一第三區域,第一區域及第二區域之每一者包括閘極、源極及汲極引線指狀物,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以分別連接至該第一半導體晶片及該第二半導體晶片之該至少一個閘極接觸元件、複數個源極接觸元件及複數個汲極接觸元件中之每一者,及一外殼,其環繞該第一半導體功率晶片及該第二半導體功率晶片、該第三晶片及該引線框架。
- 如請求項17之設備,其中該第三晶片係可操作以控制該半導體功率晶片之一微控制器晶片。
- 如請求項17之設備,其中該第三晶片係可操作以控制該半導體功率晶片之一脈衝寬度調變晶片。
- 如請求項17之設備,其中該第三晶片以覆晶方式安裝。
- 如請求項20之設備,其中該引線框架經設計以提供該第三晶片與該第一半導體功率晶片及該第二半導體功率晶片之間的連接。
- 一種設備,其包括:一外殼;一引線框架,其以覆晶組態配置於該外殼內;一導電接觸元件陣列,其包括至少一個閘極接觸元件、至少一個源極接觸元件及至少一個汲極接觸元件,及一鈍化層,其形成於該複數個導電接觸元件上方,該鈍化層包括複數個該等導電接觸元件上方之多個鈍化開口;僅一單個金屬互連層,其包含該導電接觸元件陣列;一導電凸塊陣列,其包含一或多個互連凸塊,其中每一互連凸塊形成於該鈍化層上方並延伸至該等鈍化開口中之至少兩者中且與至少兩個下伏導電接觸元件接觸,以藉此提供該至少兩個下伏導電接觸元件之間的一導電耦合;一前側汲極連接;一前側源極連接,其與該前側汲極連接在相同之一源極金屬胞元內;及其中該前側源極連接及該前側汲極連接由一相同導電凸塊覆蓋且其中該引線框架具有包括閘極、源極及汲極引線指狀物之一區域,該等閘極、源極及汲極引線指狀物經調適以與該導電凸塊陣列相匹配以連接至該至少一個閘極接觸元件、複數個源極接觸元件及複數個汲極接觸元件中之每一者。
- 如請求項22之設備,其中該導電接觸元件陣列包括平行配置之複數個細長的接觸條帶。
- 如請求項22之設備,其中複數個鈍化開口係配置在每一源極接觸元件及每一汲極接觸元件上。
- 如請求項22之設備,其中該一或多個互連凸塊包括提供經電隔離的至少兩個源極區之間的一導電耦合之至少一個源極互連凸塊。
- 如請求項22之設備,其中該一或多個互連凸塊包括提供經電隔離的至少兩個汲極區之間的一導電耦合之至少一個汲極互連凸塊。
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US10163773B1 (en) | 2017-08-11 | 2018-12-25 | General Electric Company | Electronics package having a self-aligning interconnect assembly and method of making same |
US10847483B2 (en) | 2018-08-29 | 2020-11-24 | Texas Instruments Incorporated | Integrated circuits with conductive bumps having a profile with a wave pattern |
US10833036B2 (en) * | 2018-12-27 | 2020-11-10 | Texas Instruments Incorporated | Interconnect for electronic device |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050023670A1 (en) * | 2003-07-31 | 2005-02-03 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
US7560808B2 (en) * | 2005-10-19 | 2009-07-14 | Texas Instruments Incorporated | Chip scale power LDMOS device |
TW201232704A (en) * | 2010-11-18 | 2012-08-01 | Microchip Tech Inc | Using bump bonding to distribute current flow on a semiconductor power device |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150722A (en) | 1994-11-02 | 2000-11-21 | Texas Instruments Incorporated | Ldmos transistor with thick copper interconnect |
US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
DE19613409B4 (de) * | 1996-04-03 | 2005-11-17 | Texas Instruments Deutschland Gmbh | Leistungsbauelementanordnung |
US6927491B1 (en) | 1998-12-04 | 2005-08-09 | Nec Corporation | Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board |
US6645791B2 (en) * | 2001-04-23 | 2003-11-11 | Fairchild Semiconductor | Semiconductor die package including carrier with mask |
US6969909B2 (en) | 2002-12-20 | 2005-11-29 | Vlt, Inc. | Flip chip FET device |
JP4130668B2 (ja) | 2004-08-05 | 2008-08-06 | 富士通株式会社 | 基体の加工方法 |
JP2006128543A (ja) * | 2004-11-01 | 2006-05-18 | Nec Electronics Corp | 電子デバイスの製造方法 |
JP4357434B2 (ja) * | 2005-02-25 | 2009-11-04 | 株式会社東芝 | 半導体装置の製造方法 |
US7944048B2 (en) * | 2006-08-09 | 2011-05-17 | Monolithic Power Systems, Inc. | Chip scale package for power devices and method for making the same |
JP2009170747A (ja) * | 2008-01-18 | 2009-07-30 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2011100932A (ja) * | 2009-11-09 | 2011-05-19 | Toshiba Corp | 半導体パッケージ及びdc−dcコンバータ |
JP5457292B2 (ja) * | 2010-07-12 | 2014-04-02 | パナソニック株式会社 | 窒化物半導体装置 |
CN102110691A (zh) * | 2010-12-03 | 2011-06-29 | 杭州矽力杰半导体技术有限公司 | 一种功率场效应晶体管及其布图方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050023670A1 (en) * | 2003-07-31 | 2005-02-03 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
US7560808B2 (en) * | 2005-10-19 | 2009-07-14 | Texas Instruments Incorporated | Chip scale power LDMOS device |
TW201232704A (en) * | 2010-11-18 | 2012-08-01 | Microchip Tech Inc | Using bump bonding to distribute current flow on a semiconductor power device |
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