TWI660412B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI660412B
TWI660412B TW106113247A TW106113247A TWI660412B TW I660412 B TWI660412 B TW I660412B TW 106113247 A TW106113247 A TW 106113247A TW 106113247 A TW106113247 A TW 106113247A TW I660412 B TWI660412 B TW I660412B
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Taiwan
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gate
contact plug
forming
source
stack
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TW106113247A
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TW201816859A (zh
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廖志騰
邱意為
陳璽中
蔡嘉慶
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台灣積體電路製造股份有限公司
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Abstract

一種半導體裝置的形成方法，包括：形成虛設閘極堆疊於半導體區上方；形成閘極間隔物於虛設閘極堆疊的側壁上；移除虛設閘極堆疊以形成開口；形成替代閘極堆疊於開口中；凹蝕替代閘極堆疊以形成凹槽；以導電材料填充凹槽；以及實行平坦化以移除閘極間隔物上方之導電材料的多餘部分。導電材料的剩餘部分形成閘極接觸插塞。閘極接觸插塞的頂部齊平於第一閘極間隔物的頂部。

Description

半導體裝置及其形成方法
本發明之實施例係關於半導體裝置及其形成方法。
隨著積體電路的尺寸變得越來越小，相應的形成製程也變得越來越困難，且可能出現傳統上不會出現的問題。例如，在鰭式場效應電晶體(Fin Field-Effect Transistors,FinFET)的形成中，金屬閘極與相鄰的源極和汲極區可能會彼此電氣短路。金屬閘極的接觸插塞亦可能短接至源極和汲極區之相鄰的接觸插塞。
此外，鰭式場效應電晶體(FinFET)的形成可涉及虛設多晶矽閘極的形成，在後續製程中移除虛設多晶矽閘極，以及以取代金屬閘極填充虛設多晶矽閘極所留下的凹槽。然而，由於虛設多晶矽閘極變得非常窄，故可會能因為虛設多晶矽閘極的不完全移除而留下多晶矽殘留物，進而導致裝置性能的劣化。
根據本發明的一些實施例，提供一種半導體裝置的形成方法，包括：形成虛設閘極堆疊於半導體區上方；形成 閘極間隔物於虛設閘極堆疊的側壁上；移除虛設閘極堆疊以形成開口；形成替代閘極堆疊於開口中；凹蝕替代閘極堆疊以形成凹槽；以導電材料填充凹槽；以及實行平坦化以移除閘極間隔物上方之導電材料的多餘部分。導電材料的剩餘部分形成閘極接觸插塞。閘極接觸插塞的頂部齊平於第一閘極間隔物的頂部。
根據本發明的一些實施例，提供一種半導體裝置的形成方法，包括：形成虛設閘極堆疊於半導體鰭的頂面及側壁上；形成閘極間隔物，其具有複數個側壁，該些側壁接觸虛設閘極堆疊的側壁；形成源極/汲極區於虛設閘極堆疊的一側上；形成層間介電質以覆蓋源極/汲極區；移除虛設閘極堆疊以形成開口於閘極間隔物之間；以替代閘極堆疊填充開口的底部；以及形成閘極接觸插塞以填充該開口的頂部。閘極接觸插塞位於閘極間隔物的複數個頂部之間。
根據本發明的一些實施例，提供一種半導體裝置，包括：半導體區；位於半導體區上方之閘極堆疊；位於閘極堆疊的一側之源極/汲極區；位於閘極堆疊的側壁上之第一閘極間隔物及第二閘極間隔物。位於閘極堆疊上方之閘極接觸插塞，其中閘極接觸插塞介於第一閘極間隔物與第二閘極間隔物之間，且第一閘極間隔物及第二閘極間隔物的頂部齊平於閘極接觸插塞的頂部。
2‧‧‧半導體晶圓
14‧‧‧特徵
16‧‧‧特徵
22'‧‧‧特徵
24'‧‧‧特徵
20‧‧‧半導體基底
20A‧‧‧半導體鰭
22‧‧‧虛設閘極介電層
22'‧‧‧虛設閘極介電層
24'‧‧‧虛設閘極電極層
24‧‧‧虛設閘極電極層
26‧‧‧底部抗反射塗層
28‧‧‧圖案化光阻
30‧‧‧虛設閘極堆疊
32‧‧‧閘極間隔物
32A‧‧‧層
32B‧‧‧層
36‧‧‧源極/汲極區
38‧‧‧隔離區
38A‧‧‧頂表面
40‧‧‧接觸蝕刻停止層
42‧‧‧層間介電質
44‧‧‧腔室
46‧‧‧過濾器
48‧‧‧凹槽
49‧‧‧閘極間隔物層
50‧‧‧閘極間隔物
52‧‧‧閘極堆疊
54‧‧‧界面介電層
56‧‧‧高介電常數閘極介電質
58‧‧‧取代閘電極
60‧‧‧硬罩幕
62‧‧‧犧牲介電層
64‧‧‧圖案化光阻
66‧‧‧接觸開口
68‧‧‧源極/汲極矽化物區
70‧‧‧源極/汲極接觸插塞
72‧‧‧開口
72'‧‧‧虛線
74‧‧‧閘極接觸插塞
74'‧‧‧閘極接觸插塞
76‧‧‧蝕刻停止層
78‧‧‧層間介電質(ILD)
80‧‧‧接觸間隔物
82‧‧‧源/汲接觸插塞
84‧‧‧蝕刻停止層
86‧‧‧介電層
88‧‧‧導電通孔
90‧‧‧介層窗開口
92‧‧‧通孔
94‧‧‧通孔間隔物
96‧‧‧金屬線
112‧‧‧罩幕堆疊
212‧‧‧罩幕堆疊
312‧‧‧罩幕堆疊
412‧‧‧罩幕堆疊
122‧‧‧特徵
124‧‧‧特徵
114‧‧‧特徵
116‧‧‧特徵
118‧‧‧層
124‧‧‧虛設閘極電極層
224‧‧‧虛設閘極電極層
324‧‧‧虛設閘極電極層
424‧‧‧虛設閘極電極層
122‧‧‧虛設閘極介電層
222‧‧‧虛設閘極介電層
322‧‧‧虛設閘極介電層
422‧‧‧虛設閘極介電層
422‧‧‧特徵
424‧‧‧特徵
414‧‧‧特徵
416‧‧‧特徵
100‧‧‧標準裝置區
200‧‧‧高壓裝置區
300‧‧‧長通道裝置區
400‧‧‧輸入-輸出裝置區
500‧‧‧流程圖
502‧‧‧步驟
504‧‧‧步驟
506‧‧‧步驟
508‧‧‧步驟
510‧‧‧步驟
512‧‧‧步驟
514‧‧‧步驟
516‧‧‧步驟
518‧‧‧步驟
520‧‧‧步驟
522‧‧‧步驟
524‧‧‧步驟
W112‧‧‧寬度
W212‧‧‧寬度
W312‧‧‧寬度
W412‧‧‧寬度
W112’‧‧‧寬度
W212’‧‧‧寬度
W312’‧‧‧寬度
W412’‧‧‧寬度
α‧‧‧角度
α1‧‧‧角度
α2‧‧‧角度
α3‧‧‧角度
α4‧‧‧角度
β1‧‧‧傾斜角度
β2‧‧‧傾斜角度
HMG‧‧‧高度
HMG1‧‧‧高度
HMG2‧‧‧高度
HMG3‧‧‧高度
HMG4‧‧‧高度
V‧‧‧體積
V1‧‧‧體積
V2‧‧‧體積
V3‧‧‧體積
V4‧‧‧體積
以下將配合所附圖式詳述本揭露之實施例，應注意的是，依照工業上的標準實施，以下圖示並未按照比例繪 製，事實上，可能任意的放大或縮小元件的尺寸以便清楚表現出本揭露的特徵。而在說明書及圖式中，除了特別說明外，同樣或類似的元件將以類似的符號表示。
第1-4、5A-5B、6-12、13A-13B、14-23圖顯示根據一些實施例，形成電晶體之中間階段的剖面圖。
第24圖顯示根據一些實施例，形成電晶體的流程圖。
以下提供許多不同的實施方法或是例子來實行各種實施例之不同特徵。以下描述具體的元件及其排列的例子以闡述本揭露。當然這些僅是例子且不該以此限定本揭露的範圍。例如，在描述中提及第一個元件形成一第二個元件上時，其可以包括第一個元件與第二個元件直接接觸的實施例，也可以包括有其他元件形成於第一個與第二個元件之間的實施例，其中第一個元件與第二個元件並未直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。
再者，與空間相關的用詞，像是“在…下方”、“下方”、“較低的”、“上方”、“較高的”等，這些關係詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係。這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖示中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。
根據各種例示性實施例，提供具有金屬閘極和接觸插塞的電晶體及其形成方法。根據一些實施例，顯示形成電晶體、金屬閘極及接觸插塞的中間階段。在此討論一些實施例的一些變化。在各個視圖和說明性實施例中，相似的參考標號用於表示相似的元件。
第1圖至第23圖顯示根據本發明一些實施例，形成電晶體之中間階段的剖面圖。第1圖至第23圖中所示之步驟也用圖表顯示在第24圖所示之流程圖500中。說明性實施例使用鰭式場效電晶體(Fin Field-Effect Transistor,FinFET)的形成作為實例。本發明的概念容易適用於平面電晶體。
請參照第1圖，提供半導體基底20，其為半導體晶圓2的一部分。根據本發明一些實施例，半導體基底20包括矽晶體。在半導體基底20中亦可包括其它常用的材料，例如碳、鍺、鎵、硼、砷、氮、銦、磷等。基底20亦可為包括III-V族化合物半導體或矽鍺之化合物基底。
半導體基底20包括多個區域之部分，其中將形成不同類型的電晶體。根據一些實施例，多個區域包括標準裝置區100、高壓(High-Voltage,HV)裝置區200、長通道裝置區300及輸入-輸出(Input-Output,IO)裝置區400。標準裝置區100可用於形成核心/邏輯電晶體。高壓(HV)裝置區200可用於形成高壓(HV)電晶體。長通道裝置區300可用於形成具有長通道的電晶體，且輸入-輸出(IO)裝置區400可用於形成輸入-輸出(IO)電晶體。核心電晶體可供應有低的正電源電壓(positive power supply voltage)，例如：低於約1.0伏特 (volt)。高壓(HV)電晶體可供應有並配置以承受高的正電源電壓，其高於裝置區100中之裝置的正電源電壓。例如，高壓(HV)裝置區200的電源電壓可為介於約1.5V和約3.3V之間。
根據本發明一些實施例，基底20包括半導體鰭20A，其為相鄰於隔離區上方的部分。第5B圖顯示例示性鰭20A，其說明半導體鰭20A高於相鄰的隔離區38，且隔離區38可為淺溝槽隔離(Shallow Trench Isolation,STI)區。應注意的是，儘管為了簡單起見，區域100、200、300和400中的鰭係顯示為彼此相連，但實際上，不同裝置區中的鰭係彼此分離。
請回頭參照第1圖，形成虛設閘極介電層22於基底20上方。虛設閘極介電層22可由氧化矽所形成。根據一些實施例，虛設閘極電極層24形成在虛設閘極介電層22上方，且可由多晶矽所形成。
根據一些示例性實施例，罩幕堆疊112、212、312和412分別形成在裝置區100、200、300和400中，且分別具有寬度W112、W212、W312和W412，其關係為W412>W312>W212>W112。罩幕堆疊112可包括層114、116和118，其可由氧化矽、氮化矽、矽碳氮化物、矽碳氮氧化物等所形成。罩幕堆疊212、312和412具有與罩幕堆疊112相同的層。
形成底部抗反射塗層(Bottom Anti-Reflective Coating,BARC)26在虛設閘極電極層24上，並填充罩幕堆疊112、212、312和412之間的空間。根據一些實施例，底部抗反射塗層(BARC)26係由諸如SiON的介電材料所形成。可填充底部抗反射塗層(BARC)26以覆蓋罩幕堆疊112、212、312 和412，或者可具有與層118的頂表面齊平或更高的頂表面。圖案化光阻28形成在底部抗反射塗層(BARC)26上方，並覆蓋罩幕堆疊212、312和412，從而使罩幕堆疊112未被覆蓋。
請參照第2圖，使用光阻28作為蝕刻罩幕並對底部抗反射塗層(BARC)26進行圖案化。因此，暴露出罩幕堆疊112的側壁。接著，實行修整步驟(trimming step)，其中修整為各向同性(isotropic)，且可為濕蝕刻製程或乾蝕刻製程。相應的步驟在第24圖所示之流程圖中顯示為步驟502。根據一些實施例，藉由濕蝕刻製程並使用包括HF、去離子水、NH4OH、H2O2、異丙醇(Isopropanol,IPA)。或者，藉由乾蝕刻製程並使用包括HBr、SO2或CF4的蝕刻氣體來實行修整。根據一些實施例，作為修整的結果，罩幕堆疊112具有小於約0.9×W112的寬度W112'。
接著，如第3圖所示，移除底部抗反射塗層(BARC)26和光阻28。可使用各向同性蝕刻來實行另一修整製程以進一步修整罩幕堆疊112、212、312和412的寬度。相應的步驟在第24圖所示之流程圖中也顯示為步驟502。蝕刻劑可與第2圖所示之修整所使用的蝕刻劑相同(或不同)。結果，如第2圖所示，寬度W112”、W212’、W312’和W412’分別小於寬度W112’、W212、W312和W412的約90%。
請參照第4圖，使用罩幕堆疊112、212、312和412作為蝕刻罩幕來蝕刻虛設閘極電極層24和虛設閘極介電層22(第3圖)。經蝕刻的虛設閘極電極層24之剩餘部分為虛設閘極電極層124、224、324和424。經蝕刻的虛設閘極介電層22之 剩餘部分分別為虛設閘極介電層122、222、322和422。相應的步驟在第24圖所示之流程圖中顯示為步驟504。在此步驟期間，蝕刻穿過虛設閘極介電層22(圖3)，並露出半導體鰭20A。虛設閘極介電層122、222、322和422的側壁也被露出。如第3圖所示，罩幕層118可被消耗。
通過如第1圖至第4圖所示之製程，將虛設閘極電極層124、224、324和424的寬度調整並縮小至期望值，這導致有利地降低所得電晶體之臨界尺寸(Critical Dimension,CD，閘極寬度)，特別是標準電晶體和高壓(HV)電晶體。根據本發明一些實施例，虛設閘極電極層124、224、324和424的寬度之比例可為W112'：W212'：W312'：W412'為1.0：1.0~1.3：1.3~1.6：4.0~4.5。
第5A/5B圖至第23圖中之隨後示出的製程步驟顯示用於形成電晶體的中間步驟。用於形成一個電晶體之流程圖被示出，其中流程圖可代表裝置區100之標準電晶體、裝置區200之高壓(HV)電晶體、裝置區300之長通道電晶體及裝置區400之輸入-輸出(IO)電晶體的流程圖。因此，第5A圖所示之元件代表如第4圖所示之罩幕堆疊和相應的底層虛設閘極電極層及虛設閘極介電層，其取決於所欲形成之電晶體的類型。例如，當欲形成標準電晶體時，第5A圖中的特徵22'、24'、14和16分別代表第4圖中的特徵122、124、114和116。相似地，當欲形成輸入-輸出(IO)電晶體時，第5A圖中的特徵22'、24'、14和16分別代表第4圖中的特徵422、424、414和416。如第5A圖所示，虛設閘極介電層22'和虛設閘極電極層24'具有延伸於 半導體鰭20A的頂表面和側壁上之側壁部分(使用虛線示出)。在隨後的討論中，特徵22'、24'、14和16統稱為虛設閘極堆疊30。
第5B圖顯示第5A圖所示之結構的剖面圖，其中該剖面圖係從第5A圖之平面交叉線5B-5B所獲得。第5B圖顯示半導體鰭20A突出並高於淺溝槽隔離(STI)區38的頂表面38A，且虛設閘極堆疊30延伸於半導體鰭20A的頂表面和側壁上。
第6圖顯示閘極間隔物32之形成，其形成在虛設閘極堆疊的側壁上。相應的步驟在第24圖所示之流程圖中顯示為步驟506。根據本發明一些實施例，閘極間隔物32包括複數個層，例如層32A及位於層32A上之層32B。雖然未示出，但可包括更多的層於閘極間隔物32中。閘極間隔物32的材料包括氧化矽、氮化矽、氮氧化矽、矽碳氮氧化物等。例如，層32A和32B可由不同的材料所形成。或者，層32A和32B包括具有不同組成(具有不同百分比)的相同元素(例如：矽和氮)。根據一些實施例，閘極間隔物32可與半導體鰭20A的頂表面和側壁接觸。
請參照第7圖，形成源極/汲極區36。相應的步驟在第24圖所示之流程圖中顯示為步驟508。根據本發明一些實施例，源極/汲極區36的形成包括蝕刻半導體鰭20A未被虛設閘極堆疊30和閘極間隔物32覆蓋的部分，並實行磊晶以在所得的凹陷中生長磊晶區。根據一些示例性實施例，當欲形成n型FinFET時，源極/汲極區36包括矽磷(SiP)或磷摻雜矽碳(SiCP)。當欲形成p型FinFET時，源極/汲極區36可包括SiGe和諸如硼或 銦的p型摻雜，其可被原位(in-situ)摻雜於磊晶期間。可實行或可不實行佈植以將n型(用於n型FinFET)或p型摻質(用於p型FinFET)摻雜至磊晶區中。根據替代實施例，藉由植入半導體鰭20A來實行源極/汲極區36的形成。
第8圖顯示接觸蝕刻停止層(Contact Etch Stop Layer,CESL)40及位於接觸蝕刻停止層(CESL)40上之層間介電質(Inter-Layer Dielectric,ILD)42之形成。相應的步驟在第24圖所示之流程圖中顯示為步驟510。根據一些實施例，在形成接觸蝕刻停止層(CESL)40之前，形成緩衝氧化層(未示出)於源極和汲極區36上。緩衝氧化層可由氧化矽所形成，且接觸蝕刻停止層(CESL)40可由氮化矽、碳氮化矽等所形成。可使用例如原子層沉積(Atomic Layer Deposition,ALD)來形成緩衝氧化層和接觸蝕刻停止層(CESL)40。層間介電質(ILD)42可使用例如可流動化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)並由可流動的氧化物所形成。層間介電質(ILD)42亦可包括磷矽酸鹽玻璃(Phospho-Silicate glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)，四乙基正矽酸鹽(Tetra Ethyl Ortho Silicate,TEOS)氧化物等。可實行諸如化學機械研磨(Chemical Mechanical Polish,CMP)的平坦化以使虛設閘極堆疊30、閘極間隔物32、接觸蝕刻停止層(CESL)40和層間介電質(ILD)的頂表面齊平。
如第9及10圖所示，接著，移除虛設閘極堆疊30。 相應的步驟在第24圖所示之流程圖中顯示為步驟512。首先，移除罩幕層14及16，且所得的結構如第9圖所示。可使用例如含氟製程氣體(例如：CF4/O2/N2、NF3/O2、SF6或SF6/O2)或使用H3PO4溶液來移除罩幕層14和16。接著，實行步驟以蝕刻形成於虛設閘極電極層24'上的氧化層，其可為自然氧化層。可使用NF3及NH3實行氧化物的移除，當暴露在RF下時，NF3及NH3彼此反應以形成NH4F，其用於蝕刻氧化矽(當加熱至例如約40℃時)以產生(NH4)2SiF6及水。(NH4)2SiF6為固體，且當例如在高於約100℃的溫度下退火時，產生SiF4、NH3及HF之氣體，其藉由泵(未示出)從腔室44排出。
第9圖進一步顯示根據本發明一些實施例，虛設閘極電極層24'的蝕刻。置放晶圓2於腔室44中，並引入製程氣體NF3和H2，且從NF3產生電漿，NF3與H2(與產生的電漿)反應以形成H(氫)自由基和F(氟)自由基。離子亦從製程氣體中產生。第9圖顯示由字母“R”所表示之自由基，且正離子和負離子分別由“+”和“-”符號所表示。過濾器46(其可為選擇性調控裝置)可用以濾掉離子，同時允許自由基通過過濾器46以到達晶圓2。氟自由基與矽(虛設閘極電極層24')反應以產生SiH4和H2之氣體，其藉由泵(未示出)從腔室44排出。在虛設閘極電極層24'的蝕刻期間，氟自由基並非定向的，且不具有撞擊效應(bombardment effect)。因此，虛設閘極電極層24'的底角部分被完全蝕刻而沒有留下殘餘物。
如第10圖所示，在移除虛設閘極電極層24'之後，使用例如NF3/NH3或HF移除虛設閘極介電層22'，使得半導體鰭 20A的頂面和側壁被暴露並形成凹槽48。有利地，由於虛設閘極介電層22(第2圖及第3圖)的蝕刻穿過(etch-through)，故虛設閘極介電層不會留在閘極間隔物32的正下方。因此，閘極間隔物32的正下方不會形成底切(undercut)，其中，如果形成底切，可能會以用於形成替代閘極之隨後沉積的金屬來填充，且可能產生洩漏/短路路徑。因此，虛設閘極介電層22的蝕刻穿過有利地移除了洩漏/短路路徑。
第11及12圖顯示根據一些實施例，閘極間隔物50的形成。相應的步驟在第24圖所示之流程圖中顯示為步驟514。根據替代實施例，跳過第11和12圖所示的步驟。請參照第11圖，例如使用共形沉積方法(諸如原子層沉積(ALD)或化學氣相沉積(CVD))以形成閘極間隔物層49。因此，閘極間隔物層49的水平部分和垂直部分的厚度彼此接近，例如，其差異小於約20%或10%之水平部分的厚度。根據本揭露一些實施例，閘極間隔物層由氮化矽、碳氮化矽、氮氧化矽或另一介電材料所形成，其可不同於閘極間隔物32的材料和接觸蝕刻停止層(CESL)40及層間介電質(ILD)42的材料。閘極間隔物50的形成有利地將隨後形成的金屬閘極與源極/汲極區36彼此遠離地隔開，並降低它們之間的洩漏和電氣短路的可能性。
請參照第12圖，實行各向異性蝕刻以移除閘極間隔物層49的水平部分，留下閘極間隔物50於閘極間隔物32的側壁上。
如第13A圖所示，接著，形成替代閘極堆疊52於凹槽48中，並延伸於半導體鰭20A的頂面和側壁上。相應的步驟 在第24圖所示之流程圖中顯示為步驟516。閘極堆疊52可包括界面介電層54、高介電常數(high-k)閘極介電質56和取代閘電極58。根據本發明一些實施例，界面介電層54係透過熱氧化或化學氧化所形成之氧化矽層，在此期間半導體鰭20A的表層被氧化。高介電常數介電層56可具有大於7或大於20的介電常數值。示例性的高介電常數介電材料包括氧化鉿、氧化鋯、氧化鑭等。替代閘極電極58可為由同質導電材料所形成的單層。或者，替代閘極電極58可為複合層，其包括由TiN、氮化鈦矽(TSN)，TaSiN、WN、TiAl、TiAlN、TaC、TaN、鋁、鎢或其組合所形成的複數層。高介電常數介電層56和閘極電極58的形成可包括原子層沉積(ALD)、物理氣相沉積(PVD)、金屬有機化學氣相沉積(Metal-Organic Chemical Vapor Deposition,MOCVD)及/或其他合適的方法。實行諸如化學機械研磨(CMP)的平坦化以移除多餘的閘極堆疊52。
形成硬罩幕60於替代閘極堆疊52上方。根據本發明一些實施例，回蝕平坦化的閘極堆疊52，且在由閘極堆疊52的蝕刻部分所留下的凹槽中形成硬罩幕60。硬罩幕60的形成包括沉積步驟和平坦化步驟以移除閘極間隔物32和層間介電質(ILD)42上方的多餘沉積材料。例如，硬罩幕60可由氮化矽所形成。
第13B圖示意地顯示物理性地形成於晶圓上之金屬閘極的輪廓。可以觀察到，替代閘極電極58可具有突出邊緣部分上方之中間部分之輪廓。因此，如第13B圖所示，頂面在剖面圖中形成角度α。如在前段中所討論，所示的電晶體可代 表標準電晶體、高壓(HV)電晶體、長通道電晶體和輸入-輸出(IO)電晶體。由於閘極電極的不同寬度，這些電晶體的輪廓可為彼此不同。舉例而言，假設當所示的電晶體為標準電晶體、高壓(HV)電晶體、長通道電晶體或輸入-輸出(IO)電晶體時，角度α分別等於α1、α2、α3或α4，則比例α1：α2：α3：α4可為1.0：1.7~1.8：1.9~2.0：2.0~2.1。
閘極堆疊52的高度HMG係從硬罩幕60的頂部測量至淺溝槽隔離(STI)區38(第5B圖)的頂面38A。假設當所示的電晶體為標準電晶體、高壓(HV)電晶體、長通道電晶體或輸入-輸出(IO)電晶體時，高度HMG分別等於高度HMG1、高度HMG2、高度HMG3或高度HMG4，則比例HMG1：HMG2：HMG3：HMG4可為1.0：1.0~1.1：0.9~1.0：1.0~1.1。
當所示的電晶體為標準電晶體、高壓(HV)電晶體、長通道電晶體或輸入-輸出(IO)電晶體時，閘極堆疊52的體積V可分別表示為V1、V2、V3或V4。根據本發明一些實施例，比例V1：V2：V3：V4可為1.0：0.9~0.98：30~38：42~48。
閘極間隔物55的側壁的傾斜角度β1可為小於約89度，且閘極間隔物32的側壁的傾斜角度β2亦可為小於約89度。根據本發明一些實施例，閘極堆疊52的邊緣大抵上是直的，因此傾斜角度β1和β2為接近90度。
第14圖至第16圖顯示下源極/汲極接觸插塞的形成。相應的步驟在第24圖所示之流程圖中顯示為步驟518。請參照第14圖，形成犧牲介電層62，接著施用圖案化光阻64。犧牲介電層62由不同於層間介電質(ILD)42的介電材料所形成。 舉例而言，犧牲介電層62可由選自用於形成層間介電質(ILD)42之相同的候選介電材料所形成，而它們仍係由不同的材料所形成。接著，如第15圖所示，蝕刻犧牲介電層62、層間介電質(ILD)42和接觸蝕刻停止層(CESL)40以形成接觸開口66。接著，例如透過自對準矽化製程以形成源極/汲極矽化物區68。應當理解的是，可形成源極/汲極接觸開口66於單一微影製程中，或可於雙重圖案化製程中使用兩個微影製程以形成源極/漏極接觸開口66。其中，在替代閘極堆疊52的左側上之源極/汲極接觸開口66的圖案係位於第一微影罩幕中，且在替代閘極堆疊52的右側上之源極/汲極接觸開口66的圖案係位於第二微影罩幕中。接著移除光阻64。
請參照第16圖，以導電材料填充接觸開口66，接著進行平坦化製程，因此形成源極/汲極接觸插塞70。根據一些實施例，源極/汲極接觸插塞70包括由鈦、氮化鈦、鉭或氮化鉭所形成之導電阻障層，以及位於擴散阻擋層上方之諸如鎢、鋁、銅等之金屬。根據替代實施例，接觸插塞70係由單層所形成，其係由諸如鎢或合金之同質材料所形成。
第17圖至第19圖顯示閘極接觸插塞的形成。相應的步驟在第24圖所示之流程圖中顯示為步驟520。請參照第17圖，使用微影罩幕(未示出)來實行光微影製程以蝕刻穿過犧牲介電層62。接著移除硬罩幕60並形成開口72。根據本發明一些實施例，開口72的形成包括各向異性蝕刻以蝕刻穿過犧牲介電層62，以及各向同性蝕刻(乾或濕)以移除硬罩幕60。因此，露出閘極間隔物50的側壁。在未形成閘極間隔物50的實施例 中，閘極間隔物32的側壁暴露於開口72。選擇用於蝕刻犧牲介電層62和硬罩幕60的蝕刻劑，使得閘極間隔物50和32大抵上不被蝕刻。根據本發明之替代實施例，開口72較硬罩幕60窄，因此留下硬罩幕60的一些邊緣部分，其中使用虛線72'顯示相應的開口72和硬罩幕60。
請參照第18圖，沉積導電材料74，其中形成單層或複合層(包括複數個導電層)。閘極接觸插塞74的材料和結構可選自與接觸插塞70相同的候選材料及結構。接著，實行諸如化學機械研磨(CMP)的平坦化步驟以移除犧牲介電層62及導電材料70位於犧牲介電層62內部及上方之部分。因此，如第19圖所示，形成閘極接觸插塞74。亦降低源極/汲極接觸插塞70。
閘極接觸插塞74'和源極/汲極接觸插塞70具有頂面，其與閘極間隔物32和層間介電質(ILD)42的頂面大抵上為共面。此外，閘極間隔物50(或如果沒有形成閘極間隔物50，則為閘極間隔物32)延伸以接觸閘極接觸插塞74'的側壁。或者，根據一些實施例，閘極接觸插塞74'的側壁和閘極堆疊52的側壁接觸相應之閘極間隔物50(或32)的相同側壁。因此，閘極間隔物50和32將閘極接觸插塞74'與源極/汲極接觸插塞70分離。閘極間隔物50的增加有利地降低閘極接觸插塞74'和源極/汲極接觸插塞70之間的洩漏或電氣短路的可能性。
根據其中硬罩幕60未被完全移除的替代實施例，藉由硬罩幕60的剩餘部分將閘極接觸插塞74'與一或兩個閘極間隔物32分離，其中硬罩幕60的頂面亦與閘極間隔物32和層間介電質(ILD)42的頂面為共面。根據這些實施例，虛線顯示閘極接觸插塞74'的側壁。
第20圖顯示蝕刻停止層76、層間介電質(ILD)78和蝕刻停止層76及層間介電質(ILD)78中之源/汲接觸插塞82的形成。蝕刻停止層76可以包括碳化矽、氮氧化矽、碳氮化矽等。層間介電質(ILD)78可包括選自以下之材料：磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、氟摻雜矽玻璃(Fluorine-doped Silicon Glass,FSG)、四乙氧基矽烷(tetraethoxysilane,TEOS)或其它非多孔低介電常數(low-k)介電材料。可使用諸如化學氣相沉積(CVD)的沉積方法來形成蝕刻停止層76。可使用旋轉塗佈、可流動化學氣相沉積(FCVD)等來形成層間介電質(ILD)78，或者，可使用諸如電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition,PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition,LPCVD)等沉積方法來形成形成層間介電質(ILD)78。
蝕刻層間介電質(ILD)78及蝕刻停止層76以形成開口(被82和80佔據)。可使用例如反應離子蝕刻(Reactive Ion Etch,RIE)來實行蝕刻。在隨後的步驟中，形成接觸間隔物80。接觸間隔物80可以由選自SiN、SiON、SiCN、SiOCN、AlON、AlN、上述之組合及/或其多層之介電材料所形成。形成方法大抵上可與閘極間隔物50的形成相同，其包括毯覆性沉積和各向異性蝕刻。接著，例如透過沉積和平坦化以形成接觸插塞82。相應的步驟在第24圖所示之流程圖中顯示為步驟522。
第21圖顯示蝕刻停止層84、介電層86、導電通孔88和介層窗開口90的形成。可使用與蝕刻停止層76及層間介電質(ILD)78相似(或不同)的材料及相似的方法以分別形成蝕刻停止層84和介電層86。通孔88可包括由鈦、氮化鈦、鉭或氮化鉭所形成之阻障層，以及位於阻障層上方之諸如銅、鎢等之導電材料。藉由蝕刻層76、78、84和86以形成開口90。
接著，如第22圖所示，填充開口90以形成通孔92，其可由與通孔88相似的材料所形成。相應的步驟在第24圖所示之流程圖中顯示為步驟524。通孔間隔物94可形成於通孔88及/或90的側壁上，用於減少洩漏或電氣短路。第23圖顯示底部金屬化層的形成，其包括金屬線96。
本發明的實施例具有一些有利的特徵。透過罩幕堆疊的修整，減小了一些電晶體的寬度，並減小了相應電晶體的尺寸。虛設閘極介電質的蝕刻穿過降低了由形成在閘極間隔物下方的底切所引起之電氣短路和洩漏的可能性。在由虛設閘極堆疊留下的凹陷中形成額外的閘極間隔物亦有利地降低電氣短路和洩漏。使用自由基的虛設閘極電極之蝕刻導致更好的移除而不留下殘餘物。此外，接觸間隔物的形成亦降低了閘極接觸插塞與源極/汲極接觸插塞之間短路的可能性。
根據本發明的一些實施例，提供一種半導體裝置的形成方法，包括：形成虛設閘極堆疊於半導體區上方；形成閘極間隔物於虛設閘極堆疊的側壁上；移除虛設閘極堆疊以形成開口；形成替代閘極堆疊於開口中；凹蝕替代閘極堆疊以形成凹槽；以導電材料填充凹槽；以及實行平坦化以移除閘極間 隔物上方之導電材料的多餘部分。導電材料的剩餘部分形成閘極接觸插塞。閘極接觸插塞的頂部齊平於第一閘極間隔物的頂部。
根據本發明的一些實施例，提供一種半導體裝置的形成方法，包括：形成虛設閘極堆疊於半導體鰭的頂面及側壁上；形成閘極間隔物，其具有複數個側壁，該些側壁接觸虛設閘極堆疊的側壁；形成源極/汲極區於虛設閘極堆疊的一側上；形成層間介電質以覆蓋源極/汲極區；移除虛設閘極堆疊以形成開口於閘極間隔物之間；以替代閘極堆疊填充開口的底部；以及形成閘極接觸插塞以填充該開口的頂部。閘極接觸插塞位於閘極間隔物的複數個頂部之間。
根據本發明的一些實施例，提供一種半導體裝置，包括：半導體區；位於半導體區上方之閘極堆疊；位於閘極堆疊的一側之源極/汲極區；位於閘極堆疊的側壁上之第一閘極間隔物及第二閘極間隔物。位於閘極堆疊上方之閘極接觸插塞，其中閘極接觸插塞介於第一閘極間隔物與第二閘極間隔物之間，且第一閘極間隔物及第二閘極間隔物的頂部齊平於閘極接觸插塞的頂部。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以更佳的了解本揭露的各個方面。本技術領域中具有通常知識者應該可理解，他們可以很容易的以本揭露為基礎來設計或修飾其它製程及結構，並以此達到相同的目的及/或達到與本揭露介紹的實施例相同的優點。本技術領域中具有通常知識者也應該了解這些相等的結構並不會背離 本揭露的發明精神與範圍。本揭露可以作各種改變、置換、修改而不會背離本揭露的發明精神與範圍。

Claims (13)

  1. 一種半導體裝置的形成方法，包括：形成具有不同寬度之一第一罩幕堆疊及一第二罩幕堆疊；形成一光阻以覆蓋該第二罩幕堆疊；修整該第一罩幕堆疊的一第一寬度；移除該光阻；進一步修整該第一罩幕堆疊的該第一寬度，並同時修整該第二罩幕堆疊的一第二寬度；使用該第一罩幕堆疊及該第二罩幕堆疊作為一蝕刻罩幕，以蝕刻一虛設閘極電極層及一虛設閘極介電層，以成為一虛設閘極堆疊於一半導體區上方；形成一第一閘極間隔物於該虛設閘極堆疊的側壁上；移除該虛設閘極堆疊以形成一開口；形成一替代閘極堆疊於該開口中；凹蝕該替代閘極堆疊以形成一凹槽；以一導電材料填充該凹槽；以及實行一平坦化以移除該第一閘極間隔物上方之該導電材料的多餘部分，其中該導電材料的剩餘部分形成一閘極接觸插塞，其中該閘極接觸插塞的頂部齊平於該第一閘極間隔物的頂部。
  2. 如專利申請範圍第1項所述之半導體裝置的形成方法，其中實行該平坦化直到暴露該第一閘極間隔物。
  3. 如專利申請範圍第1項所述之半導體裝置的形成方法，其中該虛設閘極堆疊的移除包括：從一含氟製程氣體中產生一電漿；從該電漿中濾掉離子並留下一氟自由基；以及使用該氟自由基蝕刻該虛設閘極堆疊的一多晶矽層。
  4. 如專利申請範圍第1項所述之半導體裝置的形成方法，其中形成該虛設閘極堆疊於該半導體區上方包括：蝕刻一虛設閘極電極層以露出一虛設閘極介電層；以及蝕刻穿過(etching-through)該虛設閘極介電層以暴露該半導體區。
  5. 如專利申請範圍第1-4項任一項所述之半導體裝置的形成方法，更包括：在移除該虛設閘極堆疊以形成該開口之後，形成一第二閘極間隔物於該開口中，其中該第二閘極間隔物具有接觸該第一閘極間隔物之一第一側壁，以及接觸該閘極接觸插塞的側壁之一第二側壁。
  6. 一種半導體裝置的形成方法，包括：形成一虛設閘極堆疊於一半導體鰭的一頂面及一側壁上；形成複數個第一閘極間隔物，其具有複數個側壁，該些側壁接觸該虛設閘極堆疊的側壁；形成一源極/汲極區於該虛設閘極堆疊的一側上；形成一層間介電質以覆蓋該源極/汲極區；移除該虛設閘極堆疊以形成一開口於該些第一閘極間隔物之間；以一替代閘極堆疊填充該開口的一底部；以及形成一閘極接觸插塞以填充該開口的一頂部，其中該閘極接觸插塞位於該些第一閘極間隔物的複數個頂部之間，且其中該閘極接觸插塞的形成包括：形成一犧牲介電層於該層間介電質上方；蝕刻該犧牲介電層以形成一額外的開口於該層間介電質中；填充一金屬材料於該額外的開口及該開口的該頂部之中；以及移除該犧牲介電層及填充於該額外的開口之該金屬材料的一部份。
  7. 如專利申請範圍第6項所述之半導體裝置的形成方法，其中該閘極接觸插塞係由以下步驟所形成：蝕刻該替代閘極堆疊的一頂部以形成一凹槽於該些第一閘極間隔物的該些頂部之間；以一硬罩幕層填充該凹槽；移除該硬罩幕層以恢復(regenerate)該凹槽；以一導電材料填充該凹槽；以及實行一平坦化以移除該導電材料的多餘部分，且該導電材料的剩餘部分形成該閘極接觸插塞。
  8. 如專利申請範圍第6項所述之半導體裝置的形成方法，更包括：蝕刻該層間介電質以形成一源極/汲極接觸開口，且該源極/汲極區暴露於該源極/汲極接觸開口；形成一源極/汲極接觸插塞以填充該源極/汲極接觸開口，其中當該源極/汲極接觸開口形成時，沉積該閘極接觸插塞的一相同材料於該源極/汲極接觸插塞上方並接觸該源極/汲極接觸插塞；以及移除沉積於該源極/汲極接觸插塞上方並接觸該源極/汲極接觸插塞之該閘極接觸插塞的該相同材料的一部份。
  9. 如專利申請範圍第6-8項任一項所述之半導體裝置的形成方法，更包括：在移除該虛設閘極堆疊以形成該開口之後，形成一第二閘極間隔物於該開口中，其中該第二閘極間隔物具有接觸該第一閘極間隔物的側壁之一第一側壁，以及接觸該閘極接觸插塞的側壁之一第二側壁。
  10. 一種半導體裝置，包括：一半導體區；一閘極堆疊，位於該半導體區上方；一源極/汲極區，位於該閘極堆疊的一側；一第一閘極間隔物及一第二閘極間隔物，位於該閘極堆疊的側壁上；以及一閘極接觸插塞，位於該閘極堆疊上方，其中該閘極接觸插塞介於該第一閘極間隔物與該第二閘極間隔物之間，且該第一閘極間隔物及該第二閘極間隔物的頂部齊平於該閘極接觸插塞的頂部。
  11. 如專利申請範圍第10項所述之半導體裝置，其中該閘極接觸插塞接觸該第一閘極間隔物及該第二閘極間隔物的側壁，且該閘極堆疊的相對側壁接觸該第一閘極間隔物及該第二閘極間隔物的側壁；其中在該裝置的剖面圖中，該閘極接觸插塞的側壁垂直對齊於該閘極堆疊的側壁。
  12. 如專利申請範圍第10項所述之半導體裝置，更包括：一第一源極/汲極接觸插塞，位於該源極/汲極區上方並電性連接該源極/汲極區，其中該第一源極/汲極接觸插塞包括一頂面，其大抵上與該第一閘極間隔物及該第二閘極間隔物的頂面為共面；一蝕刻停止層，位於該第一源極/汲極接觸插塞及該閘極接觸插塞上方；一介電層，位於該蝕刻停止層上方；一第二源極/汲極接觸插塞，位於該第一源極/汲極接觸插塞上方並接觸該第一源極/汲極接觸插塞，其中該第二源極/汲極接觸插塞位於該蝕刻停止層及該介電層之中；以及一介電接觸間隔物，其圍繞並接觸該第二源極/汲極接觸插塞。
  13. 如專利申請範圍第10項所述之半導體裝置，更包括：一第三閘極間隔物及一第四閘極間隔物，且該第一閘極間隔物及該第二閘極間隔物介於該第三閘極間隔物及該第四閘極間隔物之間，其中該第三閘極間隔物包括：一第一層，具有一L型；以及一第二層，位於該第一層的一水平腳(horizontal leg)之正上方。
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