TWI660224B - Pixel array - Google Patents
Pixel array Download PDFInfo
- Publication number
- TWI660224B TWI660224B TW107108336A TW107108336A TWI660224B TW I660224 B TWI660224 B TW I660224B TW 107108336 A TW107108336 A TW 107108336A TW 107108336 A TW107108336 A TW 107108336A TW I660224 B TWI660224 B TW I660224B
- Authority
- TW
- Taiwan
- Prior art keywords
- electrode
- pixel
- active element
- electrically connected
- data line
- Prior art date
Links
Landscapes
- Liquid Crystal (AREA)
Abstract
一種畫素陣列包括一閘極線、一第一資料線、一第二資料線、一第一畫素結構、一第二畫素結構、一第一導線、一第一連接電極與一第二連接電極。第一畫素結構包含電性連接至閘極線與第一資料線的第一畫素電極與第二畫素電極、以及與第一畫素電極至少部分重疊設置的第一共通電極。第二畫素結構包含電性連接至閘極線與第二資料線的第三畫素電極與第四畫素電極、以及與第三畫素電極至少部分重疊設置的第二共通電極。第一導線與第一畫素結構重疊設置，未與第二畫素結構重疊設置。第一連接電極電性連接第一導線、第一共通電極以及第二畫素電極。第二連接電極電性連接第二共通電極以及第四畫素電極。A pixel array includes a gate line, a first data line, a second data line, a first pixel structure, a second pixel structure, a first wire, a first connection electrode, and a second Connect the electrodes. The first pixel structure includes a first pixel electrode and a second pixel electrode electrically connected to the gate line and the first data line, and a first common electrode disposed at least partially overlapping the first pixel electrode. The second pixel structure includes a third pixel electrode and a fourth pixel electrode electrically connected to the gate line and the second data line, and a second common electrode disposed at least partially overlapping the third pixel electrode. The first wire is disposed overlapping the first pixel structure and is not disposed overlapping the second pixel structure. The first connection electrode is electrically connected to the first lead, the first common electrode, and the second pixel electrode. The second connection electrode is electrically connected to the second common electrode and the fourth pixel electrode.
Description
本發明係關於一種顯示技術，特別是一種畫素陣列。The invention relates to a display technology, in particular to a pixel array.
在液晶顯示面板中，受限於液晶分子本身的光學特性，在不同視角觀看下可能發生色偏的現象，此種現象通常被稱為側視偏白（color washout）。一般來說，為改善顯示面板的側視角偏白的現象，一般會將各子畫素劃分為兩個區域，並搭配適當的電路驅動架構以使各子畫素的兩個區域之畫素電壓不同，以使各子畫素的兩個區域可以顯示不同的亮度。In a liquid crystal display panel, due to the optical characteristics of the liquid crystal molecules, color shift may occur under different viewing angles. This phenomenon is often referred to as color washout. Generally, in order to improve the phenomenon that the side viewing angle of the display panel is white, each sub-pixel is generally divided into two regions, and an appropriate circuit driving architecture is used to make the pixel voltage of the two regions of each sub-pixel. Different so that the two areas of each sub-pixel can display different brightness.
目前為達到改善側視角偏白的畫素結構設計中，面臨連接不同層別之導電線路的貫穿孔結構不僅製程步驟繁複，同時也限制了畫素結構的開口率。因此，目前亟需一種能解決上述問題方法。In the current pixel structure design for improving the whiteness of the side viewing angle, the through-hole structure facing conductive layers of different layers is not only complicated in manufacturing steps, but also limits the aperture ratio of the pixel structure. Therefore, there is an urgent need for a method that can solve the above problems.
本發明一實施例提出一種畫素陣列，畫素陣列包括第一閘極線、第一資料線、第二資料線、第一畫素結構、第二畫素結構、第一導線、第一連接電極及第二連接電極。第一資料線與第二資料線與第一閘極線交錯設置。第一資料線位於第一畫素結構與第二畫素結構之間。第一畫素結構包括第一主動元件、第二主動元件、第一畫素電極、第二畫素電極、第一共通電極及第一分享主動元件。其中，第一主動元件與第二主動元件電性連接第一閘極線與第一資料線。第一畫素電極與第二畫素電極分別電性連接第一主動元件與第二主動元件。第一共通電極與第一畫素電極至少部分重疊設置。第一分享主動元件電性連接第二畫素電極。第二畫素結構包括第三主動元件、第四主動元件、第三畫素電極、第四畫素電極、第二共通電極及第二分享主動元件。其中，第三主動元件與第四主動元件電性連接第一閘極線與第二資料線。第三畫素電極與第四畫素電極分別電性連接第三主動元件與第四主動元件。第二共通電極與第三畫素電極至少部分重疊設置。第二分享主動元件電性連接第四畫素電極。第一導線與第一畫素電極和第二畫素電極重疊設置。第一連接電極電性連接第一共通電極、第一導線以及第一分享主動元件。第二連接電極電性連接第二共通電極以及第二分享主動元件。An embodiment of the present invention provides a pixel array. The pixel array includes a first gate line, a first data line, a second data line, a first pixel structure, a second pixel structure, a first wire, and a first connection. An electrode and a second connection electrode. The first data line and the second data line are staggered with the first gate line. The first data line is located between the first pixel structure and the second pixel structure. The first pixel structure includes a first active element, a second active element, a first pixel electrode, a second pixel electrode, a first common electrode, and a first shared active element. The first active element and the second active element are electrically connected to the first gate line and the first data line. The first pixel electrode and the second pixel electrode are electrically connected to the first active element and the second active element, respectively. The first common electrode and the first pixel electrode are at least partially overlapped. The first sharing active element is electrically connected to the second pixel electrode. The second pixel structure includes a third active element, a fourth active element, a third pixel electrode, a fourth pixel electrode, a second common electrode, and a second shared active element. The third active element and the fourth active element are electrically connected to the first gate line and the second data line. The third pixel electrode and the fourth pixel electrode are electrically connected to the third active element and the fourth active element, respectively. The second common electrode and the third pixel electrode are at least partially overlapped. The second sharing active element is electrically connected to the fourth pixel electrode. The first lead is disposed overlapping the first pixel electrode and the second pixel electrode. The first connection electrode is electrically connected to the first common electrode, the first lead, and the first shared active element. The second connection electrode is electrically connected to the second common electrode and the second shared active element.
綜上所述，本發明實施例所提供的畫素陣列，其利用導線（例如第一導線）作為畫素陣列沿著第一方向電性連接的線路，而各畫素結構的共通電極作為畫素陣列沿著第二方向電性連接的線路，藉由導線（例如第一導線）、連接電極（例如第一連接電極）以及各畫素結構的共通電極的網狀架構，而無須於每一畫素結構中設置導線（例如第一導線）。在一些實施例中，導線（例如第一導線）、連接電極（例如第一連接電極）以及各畫素結構的共通電極和分享主動元件係經由同一貫穿孔而彼此電性連接，不需形成額外的貫穿孔來使導線（例如第一導線）、連接電極（例如第一連接電極）以及各畫素結構的共通電極和分享主動元件電性連接，如此不僅節省製程步驟還可增加畫素陣列的開口率。在一些實施例中，導線（第一導線）的材料可以是單一金屬材料或是合金材料，因此阻抗較低，進而可改善水平串擾（H-crosstalk）的問題。In summary, the pixel array provided by the embodiment of the present invention uses a wire (such as a first wire) as a line electrically connected to the pixel array along the first direction, and a common electrode of each pixel structure is used as a picture. The pixel array is electrically connected along the second direction by a wire (such as the first wire), a connection electrode (such as the first connection electrode), and a network structure of the common electrodes of each pixel structure, without the need for each A lead (such as a first lead) is provided in the pixel structure. In some embodiments, the lead (eg, the first lead), the connection electrode (eg, the first connection electrode), and the common electrode and the shared active element of each pixel structure are electrically connected to each other through the same through hole, without forming an additional Through holes to electrically connect wires (such as the first wire), connection electrodes (such as the first connection electrode), common electrodes of each pixel structure, and share active components, so that not only can save process steps but also increase the pixel array Opening rate. In some embodiments, the material of the conductive line (the first conductive line) may be a single metal material or an alloy material, so the impedance is low, and the problem of H-crosstalk can be improved.
為便於清楚說明，以下述及之“第一”、“第二”、“第三”等次序用語係用於將元件、區域、部分與另一個相同或相似的元件、區域、部分區分開來，而非用以限定特定的元件、區域、部分。For the sake of clarity, the terms “first”, “second”, and “third” in the following order are used to distinguish an element, region, or part from another element, region, or part that is the same or similar. , Not to limit specific components, areas, or sections.
圖1A為本發明一實施例的畫素陣列的俯視示意圖。圖1B為圖1A的局部示意圖。圖2是沿著圖1B之剖線X-X的剖面示意圖。請參閱圖1A及圖1B。畫素陣列100包括至少一閘極線GL（如圖1A所繪示的GL1）、多條資料線DL（如圖1A所繪示的第一資料線DL1、第二資料線DL2與第四資料線DL4）、複數個畫素結構PX（如圖1A所繪示的第一畫素結構PX1與第二畫素結構PX2）、至少一導線110（如圖1A所繪示的第一導線110a）、複數個連接電極120（如圖1A所繪示的第一連接電極120a及第二連接電極120b）。FIG. 1A is a schematic top view of a pixel array according to an embodiment of the present invention. FIG. 1B is a partial schematic diagram of FIG. 1A. Fig. 2 is a schematic cross-sectional view taken along the line X-X of Fig. 1B. Please refer to FIG. 1A and FIG. 1B. The pixel array 100 includes at least one gate line GL (GL1 shown in FIG. 1A), a plurality of data lines DL (first data line DL1, second data line DL2, and fourth data shown in FIG. 1A). Line DL4), a plurality of pixel structures PX (the first pixel structure PX1 and the second pixel structure PX2 shown in FIG. 1A), at least one wire 110 (the first wire 110a shown in FIG. 1A) And a plurality of connection electrodes 120 (the first connection electrode 120a and the second connection electrode 120b shown in FIG. 1A).
請參閱圖1A、圖1B及圖2。在本實施例中，多條資料線DL沿著第一方向D1延伸設置於基板SUB上且彼此間隔配置；閘極線GL沿著第二方向D2延伸設置於基板SUB上；其中第一方向D1與第二方向D2相交，閘極線GL與多條資料線DL於基板SUB上交織出網狀的結構。在本實施例中，第一方向D1與第二方向D2可實質上互相垂直，但不以此為限。閘極線GL與多條資料線DL可分別由兩不同的圖案化導電層所構成，但不以此為限。Please refer to FIG. 1A, FIG. 1B and FIG. 2. In this embodiment, a plurality of data lines DL are extended on the substrate SUB along the first direction D1 and are spaced from each other; the gate lines GL are extended on the substrate SUB along the second direction D2; wherein the first direction D1 Intersecting with the second direction D2, the gate line GL and the plurality of data lines DL are interwoven with each other on the substrate SUB to form a mesh structure. In this embodiment, the first direction D1 and the second direction D2 may be substantially perpendicular to each other, but not limited thereto. The gate line GL and the plurality of data lines DL may be respectively composed of two different patterned conductive layers, but are not limited thereto.
為了便於說明，在本實施例中，圖1A係繪示出畫素陣列100的其中二個畫素結構PX（第一畫素結構PX1和第二畫素結構PX2）作為示例來說明，此非對本發明實施例的限定。For ease of description, in this embodiment, FIG. 1A illustrates two pixel structures PX (the first pixel structure PX1 and the second pixel structure PX2) of the pixel array 100 as an example. Limitations on the embodiments of the present invention.
在本實施例中，第一畫素結構PX1與第二畫素結構PX2係沿著第二方向D2相鄰設置。換言之，第一畫素結構PX1與第二畫素結構PX2係為畫素陣列100中之其中一列（row）的其中二個畫素結構PX。第一資料線DL1位於第一畫素結構PX1與第二畫素結構PX2之間，第一資料線DL1與第四資料線DL4設置於第一畫素結構PX1的相對兩側，且第二畫素結構PX2位於第一資料線DL1與第二資料線DL2之間。In this embodiment, the first pixel structure PX1 and the second pixel structure PX2 are disposed adjacently along the second direction D2. In other words, the first pixel structure PX1 and the second pixel structure PX2 are two pixel structures PX in one row of the pixel array 100. The first data line DL1 is located between the first pixel structure PX1 and the second pixel structure PX2, the first data line DL1 and the fourth data line DL4 are disposed on opposite sides of the first pixel structure PX1, and the second picture The element structure PX2 is located between the first data line DL1 and the second data line DL2.
請參閱圖1A及圖1B，第一畫素結構PX1包括第一主動元件TFT1、第二主動元件TFT2、第一畫素電極PE1、第二畫素電極PE2、共通電極CE11、第一分享主動元件SW1。第二畫素結構PX2包括第三主動元件TFT3、第四主動元件TFT4、第三畫素電極PE3、第四畫素電極PE4、共通電極CE21、第二分享主動元件SW2。第一閘極線GL1通過第一畫素結構PX1與第二畫素結構PX2；第一閘極線GL1位於第一畫素電極PE1與第二畫素電極PE2之間、以及位於第三畫素電極PE3與第四畫素電極PE4之間。1A and 1B, the first pixel structure PX1 includes a first active element TFT1, a second active element TFT2, a first pixel electrode PE1, a second pixel electrode PE2, a common electrode CE11, and a first shared active element. SW1. The second pixel structure PX2 includes a third active element TFT3, a fourth active element TFT4, a third pixel electrode PE3, a fourth pixel electrode PE4, a common electrode CE21, and a second shared active element SW2. The first gate line GL1 passes through the first pixel structure PX1 and the second pixel structure PX2; the first gate line GL1 is located between the first pixel electrode PE1 and the second pixel electrode PE2, and the third pixel Between the electrode PE3 and the fourth pixel electrode PE4.
共通電極CE11與第一畫素電極PE1至少部分重疊設置，也就是說，共通電極CE11可以與第一畫素電極PE1部分重疊或完全重疊設置。第一主動元件TFT1與第二主動元件TFT2電性連接第一閘極線GL1與第一資料線DL1。第一主動元件TFT1的源極SE1電性連接第一資料線DL1，第一主動元件TFT1的汲極DE1電性連接第一畫素電極PE1，第一主動元件TFT1的閘極GE1電性連接第一閘極線GL1，且第一主動元件TFT1的通道層CH1位於閘極GE1以及源極SE1和汲極DE1之間。第二主動元件TFT2的源極SE2電性連接第一資料線DL1，第二主動元件TFT2的汲極DE2電性連接第二畫素電極PE2，第二主動元件TFT2的閘極GE2電性連接第一閘極線GL1，且第二主動元件TFT2的通道層CH2位於閘極GE2以及源極SE2和汲極DE2之間。第一分享主動元件SW1的源極SWS1電性連接第二主動元件TFT2的汲極DE2及第二畫素電極PE2，第一分享主動元件SW1的汲極SWD1電性連接第一導線110a、第一連接電極120a及共通電極CE11，第一分享主動元件SW1的閘極SWG1電性連接至第一閘極線GL1，且第一分享主動元件SW1的通道層SWCH1位於閘極SWG1以及源極SWS1和汲極SWD1之間。於一實施態樣中，畫素結構PX1可以更包括共通電極CE12，且共通電極CE12與第二畫素電極PE2至少部分重疊。The common electrode CE11 is at least partially overlapped with the first pixel electrode PE1, that is, the common electrode CE11 may be partially overlapped or completely overlapped with the first pixel electrode PE1. The first active element TFT1 and the second active element TFT2 are electrically connected to the first gate line GL1 and the first data line DL1. The source SE1 of the first active element TFT1 is electrically connected to the first data line DL1, the drain DE1 of the first active element TFT1 is electrically connected to the first pixel electrode PE1, and the gate GE1 of the first active element TFT1 is electrically connected to the first A gate line GL1, and a channel layer CH1 of the first active element TFT1 is located between the gate electrode GE1 and the source electrode SE1 and the drain electrode DE1. The source electrode SE2 of the second active element TFT2 is electrically connected to the first data line DL1, the drain electrode DE2 of the second active element TFT2 is electrically connected to the second pixel electrode PE2, and the gate electrode GE2 of the second active element TFT2 is electrically connected to the first A gate line GL1, and a channel layer CH2 of the second active element TFT2 is located between the gate electrode GE2 and the source electrode SE2 and the drain electrode DE2. The source SWS1 of the first sharing active element SW1 is electrically connected to the drain DE2 of the second active element TFT2 and the second pixel electrode PE2, and the drain SWD1 of the first sharing active element SW1 is electrically connected to the first wire 110a and the first The connection electrode 120a and the common electrode CE11, the gate SWG1 of the first shared active element SW1 is electrically connected to the first gate line GL1, and the channel layer SWCH1 of the first shared active element SW1 is located at the gate SWG1 and the source SWS1 and the drain Between poles SWD1. In an embodiment, the pixel structure PX1 may further include a common electrode CE12, and the common electrode CE12 and the second pixel electrode PE2 at least partially overlap.
共通電極CE21與第三畫素電極PE3至少部分重疊設置，也就是說，共通電極CE21可以與第三畫素電極PE3部分重疊或完全重疊設置。第三主動元件TFT3與第四主動元件TFT4電性連接第一閘極線GL1與第二資料線DL2。第三主動元件TFT3的源極SE3電性連接第二資料線DL2，第三主動元件TFT3的汲極DE3電性連接第三畫素電極PE3，第三主動元件TFT3的閘極GE3電性連接第一閘極線GL1，且第三主動元件TFT3的通道層CH3位於閘極GE3以及源極SE3和汲極DE3之間。第四主動元件TFT4的源極SE4電性連接第二資料線DL2，第四主動元件TFT4的汲極DE4電性連接第四畫素電極PE4，第四主動元件TFT4的閘極GE4電性連接第一閘極線GL1，且第四主動元件TFT4的通道層CH4位於閘極GE4以及源極SE4和汲極DE4之間。第二分享主動元件SW2的源極SWS2電性連接第四主動元件TFT4的汲極電極DE4及第四畫素電極PE4，第二分享主動元件SW2的汲極SWD2電性連接第二連接電極120b及共通電極CE21，第二分享主動元件SW2的閘極SWG2電性連接第一閘極線GL1，且第二分享主動元件SW2的通道層SWCH2位於閘極SWG2以及源極SWS2和汲極SWD2之間。於一實施態樣中，第二畫素結構PX2可以更包括共通電極CE22，且共通電極CE22與第四畫素電極PE4至少部分重疊。The common electrode CE21 and the third pixel electrode PE3 are at least partially overlapped, that is, the common electrode CE21 may be partially overlapped or completely overlapped with the third pixel electrode PE3. The third active element TFT3 and the fourth active element TFT4 are electrically connected to the first gate line GL1 and the second data line DL2. The source SE3 of the third active element TFT3 is electrically connected to the second data line DL2, the drain DE3 of the third active element TFT3 is electrically connected to the third pixel electrode PE3, and the gate GE3 of the third active element TFT3 is electrically connected to the first A gate line GL1 and a channel layer CH3 of the third active element TFT3 are located between the gate electrode GE3 and the source electrode SE3 and the drain electrode DE3. The source SE4 of the fourth active element TFT4 is electrically connected to the second data line DL2, the drain DE4 of the fourth active element TFT4 is electrically connected to the fourth pixel electrode PE4, and the gate GE4 of the fourth active element TFT4 is electrically connected to the first A gate line GL1, and a channel layer CH4 of the fourth active element TFT4 is located between the gate GE4 and the source SE4 and the drain DE4. The source SWS2 of the second shared active element SW2 is electrically connected to the drain electrode DE4 and the fourth pixel electrode PE4 of the fourth active element TFT4, and the drain SWD2 of the second shared active element SW2 is electrically connected to the second connection electrode 120b and The common electrode CE21, the gate SWG2 of the second shared active element SW2 is electrically connected to the first gate line GL1, and the channel layer SWCH2 of the second shared active element SW2 is located between the gate SWG2 and the source SWS2 and the drain SWD2. In an embodiment, the second pixel structure PX2 may further include a common electrode CE22, and the common electrode CE22 and the fourth pixel electrode PE4 at least partially overlap.
在本實施例中，第一導線110a與第一畫素結構PX1重疊設置且未與第二畫素結構PX2重疊設置。也就是說，第一導線110a與第一畫素電極PE1和第二畫素電極PE2重疊設置。第一連接電極120a與對應於第一導線110a的畫素結構PX1的共通電極CE11電性連接、以及與第一導線110a、和第一分享主動元件SW1電性連接。第二連接電極120b與未對應於第一導線110a的畫素結構PX2的共通電極CE21電性連接、以及與第二分享主動元件SW2電性連接。In this embodiment, the first conductive line 110a is disposed overlapping the first pixel structure PX1 and is not disposed overlapping the second pixel structure PX2. That is, the first conductive line 110a is disposed to overlap the first pixel electrode PE1 and the second pixel electrode PE2. The first connection electrode 120a is electrically connected to the common electrode CE11 of the pixel structure PX1 corresponding to the first wire 110a, and is electrically connected to the first wire 110a and the first shared active element SW1. The second connection electrode 120b is electrically connected to the common electrode CE21 of the pixel structure PX2 that does not correspond to the first wire 110a, and is electrically connected to the second shared active element SW2.
於一實施態樣中，如圖1所繪示，對應畫素陣列100中之其中一列的多個畫素結構PX的共通電極CE11與共通電極CE21沿著第二方向彼此電性相連；共通電極CE12與共通電極CE22沿著第二方向彼此電性相連。In an embodiment, as shown in FIG. 1, the common electrode CE11 and the common electrode CE21 corresponding to the pixel structures PX of one of the columns in the pixel array 100 are electrically connected to each other along the second direction; the common electrode CE12 and common electrode CE22 are electrically connected to each other along the second direction.
第一導線110a通過畫素陣列100中之其中一行（column）的多個畫素結構PX且電性連接此些畫素結構PX的共通電極。如圖1所繪示，於此實施例中，第一導線110a係對應於畫素結構PX1所屬的該行的多個畫素結構，第一導線110a的沿著第一方向D1電性連接畫素結構PX1所屬的共通電極CE11。於一實施態樣中，第一導線110a係經由對應於畫素結構PX1所屬的貫穿孔H1與共通電極CE11電性連接，後文會再詳述貫穿孔H1的實施態樣。The first wire 110a passes through a plurality of pixel structures PX in one row of the pixel array 100 and is electrically connected to a common electrode of the pixel structures PX. As shown in FIG. 1, in this embodiment, the first conductive line 110 a corresponds to a plurality of pixel structures of the row to which the pixel structure PX1 belongs, and the first conductive line 110 a is electrically connected along the first direction D1. The common electrode CE11 to which the element structure PX1 belongs. In an embodiment, the first lead 110a is electrically connected to the common electrode CE11 through the through hole H1 corresponding to the pixel structure PX1, and the embodiment of the through hole H1 will be described in detail later.
於一實施態樣中，第一導線110a實質上與資料線DL為同一材料層所形成。此外，在畫素陣列100的垂直投影方向Z上，第一導線110a與各資料線DL不重疊。In one embodiment, the first conductive line 110a is formed of substantially the same material layer as the data line DL. In addition, in the vertical projection direction Z of the pixel array 100, the first conductive lines 110a and the data lines DL do not overlap.
第一連接電極120a對應於第一導線110a所通過的畫素結構PX1。第一連接電極120a電性連接第一導線110a、此畫素結構PX1的共通電極CE11及第一分享主動元件SW1。於一實施態樣中，第一連接電極120a係經由對應於畫素結構PX1的貫穿孔H1與共通電極CE11及第一導線110a電性連接，後文會再詳述貫穿孔H1的實施態樣。The first connection electrode 120a corresponds to the pixel structure PX1 through which the first wire 110a passes. The first connection electrode 120a is electrically connected to the first lead 110a, the common electrode CE11 of the pixel structure PX1, and the first shared active element SW1. In one embodiment, the first connection electrode 120a is electrically connected to the common electrode CE11 and the first lead 110a through the through hole H1 corresponding to the pixel structure PX1. The embodiment of the through hole H1 will be described in detail later. .
第二連接電極120b對應於第一導線110a未通過的該行的畫素結構PX2。第二連接電極120b與畫素結構PX2的共通電極CE21及第二分享主動元件SW2。於一實施態樣中，第二連接電極120b係經由對應於畫素結構PX2的接觸孔W1與共通電極CE21電性連接，後文會再詳述接觸孔W1的實施態樣。The second connection electrode 120b corresponds to the pixel structure PX2 of the row through which the first wire 110a does not pass. The second connection electrode 120b and the common electrode CE21 of the pixel structure PX2 and the second shared active element SW2. In one embodiment, the second connection electrode 120b is electrically connected to the common electrode CE21 via the contact hole W1 corresponding to the pixel structure PX2. The implementation of the contact hole W1 will be described in detail later.
如前所述，第一導線110a沿著第一方向D1延伸且透過第一連接電極120a電性連接畫素陣列100中之至少一行的至少一畫素結構PX（如第一畫素結構PX1的共通電極CE11）；而對應畫素陣列100中之至少一列的多個畫素結構PX的各共通電極沿著第二方向D2彼此電性相連（例如是，共通電極CE11電性連接共通電極CE21，而共通電極CE12電性連接共通電極CE22），如此，第一導線110a、第一連接電極120a及各共通電極（如共通電極CE11、共通電極CE12、共通電極CE21、共通電極CE22）電性連接至一參考電壓。透過適當地調整施加於第一導線110a的參考電壓，使得各畫素結構PX之對應不同畫素電極的液晶分子的傾倒角度不同，以改善面板的視角。此外，第一導線110a、第一連接電極120a、第一畫素結構PX1的共通電極CE11及第一分享主動元件SW1係經由同一貫穿孔（畫素結構PX1的第一區PX11的貫穿孔H1）而彼此電性連接，如此可以改善畫素陣列的開口率。在一些實施例中，第一導線110a的材料可以是單一金屬材料或是合金材料，因此阻抗較低，進而可改善水平串擾（H-crosstalk）的問題。As described above, the first conductive line 110a extends along the first direction D1 and is electrically connected to at least one pixel structure PX of at least one row in the pixel array 100 through the first connection electrode 120a (such as the first pixel structure PX1). (Common electrode CE11); and the common electrodes corresponding to the plurality of pixel structures PX in at least one column of the pixel array 100 are electrically connected to each other along the second direction D2 (for example, the common electrode CE11 is electrically connected to the common electrode CE21, The common electrode CE12 is electrically connected to the common electrode CE22). In this way, the first lead 110a, the first connection electrode 120a, and each common electrode (such as the common electrode CE11, the common electrode CE12, the common electrode CE21, and the common electrode CE22) are electrically connected to A reference voltage. By appropriately adjusting the reference voltage applied to the first lead 110a, the tilt angles of the liquid crystal molecules corresponding to different pixel electrodes of each pixel structure PX are different to improve the viewing angle of the panel. In addition, the first lead 110a, the first connection electrode 120a, the common electrode CE11 of the first pixel structure PX1, and the first shared active element SW1 pass through the same through hole (the through hole H1 of the first region PX11 of the pixel structure PX1). And they are electrically connected to each other, so that the aperture ratio of the pixel array can be improved. In some embodiments, the material of the first wire 110a may be a single metal material or an alloy material, so the impedance is low, and the problem of horizontal crosstalk (H-crosstalk) can be improved.
請參見圖2，圖2是沿著圖1B之剖線X-X的剖面示意圖。於一實施例中，共通電極CE11位於基板SUB上，第一絕緣層130a位於共通電極CE11上，第一導線110a位於第一絕緣層130a上，第二絕緣層130b位於第一導線110a上，第一連接電極120a位於第二絕緣層130b上。換而言之，第一絕緣層130a位於共通電極CE11與第一導線110a之間，且第二絕緣層130b位於第一導線110a與第一連接電極120a之間。貫穿孔H1對應共通電極CE11與第一導線110a設置。貫穿孔H1位於第一絕緣層130a與第二絕緣層130b中，且貫穿第一絕緣層130a與第二絕緣層130b。貫穿孔H1暴露出畫素結構PX1的部分的共通電極CE11以及部分的第一導線110a。於此，第一連接電極120a由第二絕緣層130b的上表面沿著貫穿孔H1的側壁而延伸至貫穿孔H1底部以接觸暴露於貫穿孔H1底部的共通電極CE11，且沿著貫穿孔H1的側壁而以接觸暴露於貫穿孔H1的側壁的第一導線110a。亦即，第一連接電極120a設置於貫穿孔H1中，以電性連接共通電極CE11和第一導線110a。Please refer to FIG. 2, which is a schematic cross-sectional view taken along the line X-X of FIG. 1B. In one embodiment, the common electrode CE11 is located on the substrate SUB, the first insulating layer 130a is located on the common electrode CE11, the first conductive line 110a is located on the first insulating layer 130a, and the second insulating layer 130b is located on the first conductive line 110a. A connection electrode 120a is located on the second insulating layer 130b. In other words, the first insulating layer 130a is located between the common electrode CE11 and the first lead 110a, and the second insulating layer 130b is located between the first lead 110a and the first connection electrode 120a. The through hole H1 is provided corresponding to the common electrode CE11 and the first lead 110a. The through hole H1 is located in the first insulating layer 130a and the second insulating layer 130b, and penetrates the first insulating layer 130a and the second insulating layer 130b. The through hole H1 exposes a part of the common electrode CE11 of the pixel structure PX1 and a part of the first conductive line 110a. Here, the first connection electrode 120a extends from the upper surface of the second insulating layer 130b along the sidewall of the through-hole H1 to the bottom of the through-hole H1 to contact the common electrode CE11 exposed at the bottom of the through-hole H1, and along the through-hole H1 To contact the first conductive line 110a exposed to the sidewall of the through hole H1. That is, the first connection electrode 120a is disposed in the through-hole H1 to electrically connect the common electrode CE11 and the first lead 110a.
於其中一實施態樣中，第一絕緣層130a可包括位於第一分享主動元件SW1的閘極電極上的閘極絕緣層（Gate insulator layer，GI）及間隔在第一分享主動元件SW1的閘極SWG1與源極SWS1/汲極SWD1之間的層間絕緣層（Interlayer dielectric，ILD）。第二絕緣層130b可包括位於第一分享主動元件SW1的源極SWS1/汲極SWD1上的平坦層，例如但不限於鈍化層（Passivation layer，PL）或介面層（Interfacial layer，IL）等。In one embodiment, the first insulating layer 130a may include a gate insulator layer (GI) on the gate electrode of the first sharing active element SW1 and a gate spaced between the first sharing active element SW1. Interlayer dielectric (ILD) between the electrode SWG1 and the source SWS1 / drain SWD1. The second insulating layer 130b may include a flat layer on the source SWS1 / drain SWD1 of the first shared active device SW1, such as but not limited to a passivation layer (PL) or an interfacial layer (IL).
於另一實施例中，接觸孔W1可以開設於第二連接電極120b及共通電極CE21之間的膜層。於一實施態樣中，接觸孔W1位於第一絕緣層130a與第二絕緣層130b中，且接觸孔W1暴露出畫素結構PX2的部分的共通電極CE21、第二分享主動元件SW2之部分的汲極SWD2。於此，第二連接電極120b由第二絕緣層130b的上表面沿著接觸孔W1的側壁而延伸至接觸孔W1底部以接觸暴露於接觸孔W1底部的共通電極CE21。亦即，第二連接電極120b設置於接觸孔W1中，以電性連接共通電極CE21和第二分享主動元件SW2。In another embodiment, the contact hole W1 may be formed in a film layer between the second connection electrode 120b and the common electrode CE21. In one embodiment, the contact hole W1 is located in the first insulating layer 130a and the second insulating layer 130b, and the contact hole W1 exposes the common electrode CE21 of the pixel structure PX2 and the portion of the second shared active element SW2. Drain SWD2. Here, the second connection electrode 120b extends from the upper surface of the second insulating layer 130b along the sidewall of the contact hole W1 to the bottom of the contact hole W1 to contact the common electrode CE21 exposed at the bottom of the contact hole W1. That is, the second connection electrode 120b is disposed in the contact hole W1 to electrically connect the common electrode CE21 and the second shared active element SW2.
於另一實施例中，畫素陣列200可以包括複數個導線110。為了便於說明，圖3係繪示出畫素陣列200的其中之三個畫素結構PX，並且下方以第一畫素結構PX1、第二畫素結構PX2、第三畫素結構PX3、第一閘極線GL1、第一資料線DL1、第二資料線DL2、第三資料線DL3、第四資料線DL4、第一導線110a、第二導線110b、第一連接電極120a、第二連接電極120b及第三連接電極120c作為示例來說明，此非對本發明實施例的限定。於此，第一畫素結構PX1、第二畫素結構PX2、第一閘極線GL1、第一資料線DL1、第二資料線DL2、第三資料線DL4、第一導線110a、第一連接電極120a及第二連接電極120b的連接關係及結構大致上相同於前述實施例，故相同或相似之處不再贅述。In another embodiment, the pixel array 200 may include a plurality of conductive lines 110. For ease of description, FIG. 3 illustrates three pixel structures PX of the pixel array 200, and the first pixel structure PX1, the second pixel structure PX2, the third pixel structure PX3, and the first pixel structure 200 are shown below. Gate line GL1, first data line DL1, second data line DL2, third data line DL3, fourth data line DL4, first wire 110a, second wire 110b, first connection electrode 120a, second connection electrode 120b The third connection electrode 120c is described as an example, which is not a limitation on the embodiment of the present invention. Here, the first pixel structure PX1, the second pixel structure PX2, the first gate line GL1, the first data line DL1, the second data line DL2, the third data line DL4, the first wire 110a, and the first connection The connection relationship and structure of the electrode 120a and the second connection electrode 120b are substantially the same as those of the foregoing embodiment, and therefore the same or similar portions are not described again.
在本實施例中，第一畫素結構PX1、第二畫素結構PX2及第三畫素結構PX3係沿著第二方向D2相鄰設置。換言之，第一畫素結構PX1、第二畫素結構PX2及第三畫素結構PX3係為畫素陣列200中之其中一列的其中三個畫素結構PX。第一資料線DL1位於第一畫素結構PX1與第二畫素結構PX2之間，第二資料線DL2位於第二畫素結構PX2與第三畫素結構PX3之間，第一資料線DL1與第四資料線DL4設置於第一畫素結構PX1的相對兩側，且第三畫素結構PX3位於第二資料線DL2與第三資料線DL3之間。In this embodiment, the first pixel structure PX1, the second pixel structure PX2, and the third pixel structure PX3 are disposed adjacently along the second direction D2. In other words, the first pixel structure PX1, the second pixel structure PX2, and the third pixel structure PX3 are three pixel structures PX of one of the columns in the pixel array 200. The first data line DL1 is located between the first pixel structure PX1 and the second pixel structure PX2, the second data line DL2 is located between the second pixel structure PX2 and the third pixel structure PX3, and the first data line DL1 and The fourth data line DL4 is disposed on opposite sides of the first pixel structure PX1, and the third pixel structure PX3 is located between the second data line DL2 and the third data line DL3.
第三畫素結構PX3包括第五主動元件TFT5、第六主動元件TFT6、第五畫素電極PE5、第六畫素電極PE6、共通電極CE31與第三分享主動元件SW3。第一閘極線GL1通過第三畫素結構PX3，並且第五畫素電極PE5與第六畫素電極PE6分別設置於第一閘極線GL1的相對兩側。The third pixel structure PX3 includes a fifth active element TFT5, a sixth active element TFT6, a fifth pixel electrode PE5, a sixth pixel electrode PE6, a common electrode CE31, and a third shared active element SW3. The first gate line GL1 passes through the third pixel structure PX3, and the fifth pixel electrode PE5 and the sixth pixel electrode PE6 are respectively disposed on opposite sides of the first gate line GL1.
共通電極CE31與第五畫素電極PE5至少部分重疊設置，也就是說，共通電極CE31可以與第五畫素電極PE5部分重疊或完全重疊設置。第五主動元件TFT5與第六主動元件TFT6電性連接第一閘極線GL1與第三資料線DL3。關於第五主動元件TFT5與第六主動元件TFT6與第一閘極線GL1、第三資料線DL3、第五畫素電極PE5和第六畫素電極PE6的連接方式，請參考前述的第一主動元件TFT1、第二主動元件TFT2、第三主動元件TFT3與第四主動元件TFT4，在此不再詳述。第三分享主動元件SW3電性連接於第一閘極線GL1、第二導線110b與第六畫素電極PE6。關於第三分享主動元件SW3與第一閘極線GL1、第二導線110b和第六畫素電極PE6的連接方式，請參考前述的第一分享主動元件SW1以及第二分享主動元件SW2，在此不再詳述。於一實施態樣中，第三畫素結構PX3可以更包括共通電極CE32，且共通電極CE32與第六畫素電極PE6至少部分重疊。The common electrode CE31 and the fifth pixel electrode PE5 are at least partially overlapped, that is, the common electrode CE31 may be partially overlapped or completely overlapped with the fifth pixel electrode PE5. The fifth active device TFT5 and the sixth active device TFT6 are electrically connected to the first gate line GL1 and the third data line DL3. For the connection methods of the fifth active device TFT5 and the sixth active device TFT6 with the first gate line GL1, the third data line DL3, the fifth pixel electrode PE5, and the sixth pixel electrode PE6, please refer to the aforementioned first active device. The element TFT1, the second active element TFT2, the third active element TFT3, and the fourth active element TFT4 are not described in detail here. The third sharing active element SW3 is electrically connected to the first gate line GL1, the second wire 110b, and the sixth pixel electrode PE6. For the connection of the third sharing active element SW3 to the first gate line GL1, the second wire 110b, and the sixth pixel electrode PE6, please refer to the aforementioned first sharing active element SW1 and the second sharing active element SW2, here No more details. In an embodiment, the third pixel structure PX3 may further include a common electrode CE32, and the common electrode CE32 and the sixth pixel electrode PE6 at least partially overlap.
在本實施例中，第二導線110b與第三畫素結構PX3重疊設置。也就是說，第二導線110b與第五畫素電極PE5和第六畫素電極PE6重疊設置。第二導線110b與對應於第二導線110b的畫素結構PX3的共通電極CE31電性連接。更詳而言之，第二導線110b電性連接共通電極CE31與第三分享主動元件SW3。In this embodiment, the second conductive line 110b and the third pixel structure PX3 are overlapped and disposed. That is, the second lead 110b is disposed to overlap the fifth pixel electrode PE5 and the sixth pixel electrode PE6. The second lead 110b is electrically connected to the common electrode CE31 of the pixel structure PX3 corresponding to the second lead 110b. More specifically, the second wire 110b is electrically connected to the common electrode CE31 and the third shared active element SW3.
於一實施態樣中，第二導線110b實質上與第一導線110a、第一資料線DL1、第二資料線DL2、第三資料線DL3和第四資料線DL3為同一材料層所形成。此外，在畫素陣列200的垂直投影方向Z上，第二導線110b與各資料線DL及第一導線110a不重疊。In one embodiment, the second conductive line 110b is substantially formed with the first conductive line 110a, the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL3. In addition, in the vertical projection direction Z of the pixel array 200, the second conductive line 110b does not overlap with each data line DL and the first conductive line 110a.
第三連接電極120c對應於第二導線110b所通過的該行（column）的第三畫素結構PX3。第三連接電極120c電性連接第二導線110b、第三畫素結構PX3的共通電極CE31以及第三分享主動元件SW3。於一實施態樣中，第三連接電極120c係經由對應於第三畫素結構PX3的貫穿孔H2與共通電極CE31及第二導線110b電性連接。The third connection electrode 120c corresponds to the third pixel structure PX3 of the column through which the second wire 110b passes. The third connection electrode 120c is electrically connected to the second wire 110b, the common electrode CE31 of the third pixel structure PX3, and the third shared active element SW3. In one embodiment, the third connection electrode 120c is electrically connected to the common electrode CE31 and the second wire 110b through the through hole H2 corresponding to the third pixel structure PX3.
於一實施態樣中，貫穿孔H2的實施態樣可以是與貫穿孔H1類似的結構來實現。也就是說，貫穿孔H2位於第一絕緣層130a與第二絕緣層130b中，且貫穿第一絕緣層130a與第二絕緣層130b。貫穿孔H2暴露出第三畫素結構PX3部分的共通電極CE31以及部分的第二導線110b。於此，第三連接電極120c由第二絕緣層130b的上表面沿著貫穿孔H2的側壁而延伸至貫穿孔H2底部以接觸暴露於貫穿孔H2底部的共通電極CE31，且沿著貫穿孔H2的側壁而以接觸暴露於貫穿孔H2的側壁的第二導線110b。亦即，第三連接電極120c設置於貫穿孔H2中，以電性連接共通電極CE31和第二導線110b。In an implementation form, the implementation form of the through-hole H2 may be implemented by a structure similar to the through-hole H1. That is, the through hole H2 is located in the first insulating layer 130a and the second insulating layer 130b, and penetrates the first insulating layer 130a and the second insulating layer 130b. The through-hole H2 exposes a common electrode CE31 in a portion of the third pixel structure PX3 and a portion of the second conductive line 110b. Here, the third connection electrode 120c extends from the upper surface of the second insulating layer 130b along the sidewall of the through-hole H2 to the bottom of the through-hole H2 to contact the common electrode CE31 exposed at the bottom of the through-hole H2, and along the through-hole H2 The second conductive line 110b is exposed to the sidewall of the through hole H2. That is, the third connection electrode 120c is disposed in the through hole H2 to electrically connect the common electrode CE31 and the second lead 110b.
如前所述，第一導線110a沿著第一方向D1延伸且電性連接畫素陣列200中之其中一行的至少一畫素結構PX（如第一畫素結構PX1的共通電極CE11），第二導線110b沿著第一方向D1延伸且電性連接畫素陣列200中之另一行的至少一畫素結構PX（如第三畫素結構PX3的一共通電極CE31），對應畫素陣列200中之至少一列的多個畫素結構PX的共通電極沿著第二方向D2彼此電性相連（如共通電極CE11、共通電極CE21與共通電極CE31電性連接，而共通電極CE12、共通電極CE22與共通電極CE32電性連接），如此，第一導線110a、第一連接電極120a、第二導線110b、第三連接電極120c及各共通電極（如共通電極CE11、共通電極CE12、共通電極CE21、共通電極CE22、共通電極CE31、共通電極CE32）電性連接至一參考電壓。透過適當地調整施加於第一導線110a及第二導線110b的參考電壓，使得各畫素結構PX之對應不同畫素電極的液晶分子的傾倒角度不同，以改善面板的視角。此外，第一導線110a、第一連接電極120a、第一畫素結構PX1的共通電極CE11及第一分享主動元件SW1係經由同一貫穿孔H1而彼此電性連接；第二導線110b、第三連接電極120c、第三畫素結構PX3的共通電極CE31及第三分享主動元件SW3係經由同一貫穿孔H2而彼此電性連接，如此可以改善畫素陣列的開口率。在一些實施例中，第一導線110a、第二導線110b的材料可以是單一金屬材料或是合金材料，因此阻抗較低，進而可改善水平串擾（H-crosstalk）的問題。As described above, the first wire 110a extends along the first direction D1 and is electrically connected to at least one pixel structure PX (such as the common electrode CE11 of the first pixel structure PX1) of one of the rows in the pixel array 200. The two wires 110b extend along the first direction D1 and are electrically connected to at least one pixel structure PX (such as a common electrode CE31 of the third pixel structure PX3) of another row in the pixel array 200, corresponding to the pixel array 200. The common electrodes of multiple pixel structures PX in at least one column are electrically connected to each other along the second direction D2 (for example, the common electrode CE11, the common electrode CE21, and the common electrode CE31 are electrically connected, and the common electrode CE12, the common electrode CE22, and the common electrode The electrode CE32 is electrically connected). In this way, the first lead 110a, the first connection electrode 120a, the second lead 110b, the third connection electrode 120c, and the common electrodes (such as the common electrode CE11, the common electrode CE12, the common electrode CE21, and the common electrode) CE22, common electrode CE31, and common electrode CE32) are electrically connected to a reference voltage. By appropriately adjusting the reference voltages applied to the first lead 110a and the second lead 110b, the tilt angles of the liquid crystal molecules corresponding to different pixel electrodes of each pixel structure PX are different to improve the viewing angle of the panel. In addition, the first lead 110a, the first connection electrode 120a, the common electrode CE11 of the first pixel structure PX1, and the first shared active element SW1 are electrically connected to each other through the same through-hole H1; the second lead 110b and the third connection The electrode 120c, the common electrode CE31 of the third pixel structure PX3, and the third shared active element SW3 are electrically connected to each other through the same through hole H2, so that the aperture ratio of the pixel array can be improved. In some embodiments, the material of the first conductive line 110a and the second conductive line 110b may be a single metal material or an alloy material, so the impedance is low, and the problem of horizontal crosstalk (H-crosstalk) can be improved.
於又一實施例中，為了便於說明，圖4係繪示出畫素陣列300的其中之四個畫素結構PX，並且下方以第一畫素結構PX1、第二畫素結構PX2、第三畫素結構PX3、第四畫素結構PX4、第一閘極線GL1、第二閘極線GL2、第一資料線DL1、第二資料線DL2、第四資料線DL4、第一導線110a、第一連接電極120a、第二連接電極120b、第三連接電極120c及第四連接電極120d作為示例來說明，此非對本發明實施例的限定。於此，第一畫素結構PX1、第二畫素結構PX2、第一閘極線GL1、第一資料線DL1、第二資料線DL2、第四資料線DL4、第一導線110a、第一連接電極120a及第二連接電極120b的連接關係及結構大致上相同於前述實施例，故相同或相似之處不再贅述。In another embodiment, for convenience of explanation, FIG. 4 illustrates four pixel structures PX of the pixel array 300, and the first pixel structure PX1, the second pixel structure PX2, and the third pixel structure are shown below. Pixel structure PX3, fourth pixel structure PX4, first gate line GL1, second gate line GL2, first data line DL1, second data line DL2, fourth data line DL4, first wire 110a, first The one connection electrode 120a, the second connection electrode 120b, the third connection electrode 120c, and the fourth connection electrode 120d are described as examples, which is not a limitation on the embodiment of the present invention. Here, the first pixel structure PX1, the second pixel structure PX2, the first gate line GL1, the first data line DL1, the second data line DL2, the fourth data line DL4, the first wire 110a, and the first connection The connection relationship and structure of the electrode 120a and the second connection electrode 120b are substantially the same as those of the foregoing embodiment, and therefore the same or similar portions are not described again.
在本實施例中，第一畫素結構PX1與第二畫素結構PX2沿著第二方向D2相鄰設置於同一列，第三畫素結構PX3與第四畫素結構PX4係沿第二方向D2相鄰設置於同一列。第一畫素結構PX1與第三畫素結構PX3沿著第一方向D1相鄰設置於同一行，第二畫素結構PX2與第四畫素結構PX4係沿著第一方向D1相鄰設置於同一行。換言之，第一畫素結構PX1與第二畫素結構PX2係為畫素陣列300中之其中一列的其中二個畫素結構PX，第三畫素結構PX3與第四畫素結構PX4係為畫素陣列300中之其中另一列的其中二個畫素結構PX；且，第一畫素結構PX1與第三畫素結構PX3係為畫素陣列300中之其中一行的其中二個畫素結構PX，第二畫素結構PX2與第四畫素結構PX4係為畫素陣列300中之其中另一行的其中二個畫素結構PX。第一資料線DL1係位於第一畫素結構PX1與第二畫素結構PX2之間以及位於第三畫素結構PX3與第四畫素結構PX4之間。第一資料線DL1與第四資料線DL4設置於第一畫素結構PX1的相對兩側以及設置於第三畫素結構PX3的相對兩側。第一資料線DL1與第二資料線DL2設置於第二畫素結構PX2的相對兩側以及設置於第四畫素結構PX4的相對兩側。In this embodiment, the first pixel structure PX1 and the second pixel structure PX2 are adjacently arranged in the same column along the second direction D2, and the third pixel structure PX3 and the fourth pixel structure PX4 are along the second direction. D2 is adjacently arranged in the same column. The first pixel structure PX1 and the third pixel structure PX3 are adjacently arranged in the same row along the first direction D1, and the second pixel structure PX2 and the fourth pixel structure PX4 are adjacently arranged along the first direction D1 The same line. In other words, the first pixel structure PX1 and the second pixel structure PX2 are two pixel structures PX of one of the columns in the pixel array 300, and the third pixel structure PX3 and the fourth pixel structure PX4 are pictures. Two pixel structures PX of the other column in the pixel array 300; and the first pixel structure PX1 and the third pixel structure PX3 are two pixel structures PX of one row in the pixel array 300 The second pixel structure PX2 and the fourth pixel structure PX4 are two pixel structures PX of another row in the pixel array 300. The first data line DL1 is located between the first pixel structure PX1 and the second pixel structure PX2 and between the third pixel structure PX3 and the fourth pixel structure PX4. The first data line DL1 and the fourth data line DL4 are disposed on opposite sides of the first pixel structure PX1 and on opposite sides of the third pixel structure PX3. The first data line DL1 and the second data line DL2 are disposed on opposite sides of the second pixel structure PX2 and on opposite sides of the fourth pixel structure PX4.
第三畫素結構PX3包括第五主動元件TFT5、第六主動元件TFT6、第五畫素電極PE5、第六畫素電極PE6、共通電極CE31與第三分享主動元件SW3。第四畫素結構PX4包括第七主動元件TFT7、第八主動元件TFT8、第七畫素電極PE7、第八畫素電極PE8、共通電極CE41、第四分享主動元件SW4。第二閘極線GL2通過第三畫素結構PX3與第四畫素結構PX4；第二閘極線GL2位於第五畫素電極PE5與第六畫素電極PE6之間、以及位於第七畫素電極PE7與第八畫素電極PE8之間。The third pixel structure PX3 includes a fifth active element TFT5, a sixth active element TFT6, a fifth pixel electrode PE5, a sixth pixel electrode PE6, a common electrode CE31, and a third shared active element SW3. The fourth pixel structure PX4 includes a seventh active element TFT7, an eighth active element TFT8, a seventh pixel electrode PE7, an eighth pixel electrode PE8, a common electrode CE41, and a fourth shared active element SW4. The second gate line GL2 passes through the third pixel structure PX3 and the fourth pixel structure PX4; the second gate line GL2 is located between the fifth pixel electrode PE5 and the sixth pixel electrode PE6 and the seventh pixel Between the electrode PE7 and the eighth pixel electrode PE8.
共通電極CE31與第五畫素電極PE5至少部分重疊設置，也就是說，共通電極CE31可以與第五畫素電極PE5部分重疊或完全重疊設置。第五主動元件TFT5與第六主動元件TFT6電性連接第二閘極線GL2與第一資料線DL1。關於第五主動元件TFT5與第六主動元件TFT6與第二閘極線GL2與第一資料線DL1、第五畫素電極PE5和第六畫素電極PE6的連接方式，請參考前述圖1A之實施例的第一主動元件TFT1、第二主動元件TFT2，在此不再詳述。第三分享主動元件SW3電性連接於第二閘極線GL2、第一導線110a與第六畫素電極PE6。關於第三分享主動元件SW3與第二閘極線GL2、第一導線110a與第六畫素電極PE6的連接方式，請參考前述圖1A之實施例的第一分享主動元件SW1，在此不再詳述。The common electrode CE31 and the fifth pixel electrode PE5 are at least partially overlapped, that is, the common electrode CE31 may be partially overlapped or completely overlapped with the fifth pixel electrode PE5. The fifth active device TFT5 and the sixth active device TFT6 are electrically connected to the second gate line GL2 and the first data line DL1. For the connection methods of the fifth active element TFT5, the sixth active element TFT6, the second gate line GL2, the first data line DL1, the fifth pixel electrode PE5, and the sixth pixel electrode PE6, please refer to the implementation of FIG. 1A described above. The first active element TFT1 and the second active element TFT2 are not described in detail here. The third sharing active element SW3 is electrically connected to the second gate line GL2, the first wire 110a, and the sixth pixel electrode PE6. Regarding the connection method of the third sharing active element SW3 and the second gate line GL2, the first wire 110a and the sixth pixel electrode PE6, please refer to the first sharing active element SW1 in the embodiment of FIG. 1A described above, and will not be repeated here. Elaborate.
共通電極CE41與第七畫素電極PE7至少部分重疊設置，也就是說，共通電極CE41可以與第七畫素電極PE7部分重疊或完全重疊設置。第七動元件TFT7與第八主動元件TFT8電性連接第二閘極線GL2與第二資料線DL2。關於第七動元件TFT7與第八主動元件TFT8與第二閘極線GL2與第二資料線DL2、第七畫素電極PE7和第八畫素電極PE8的連接方式，請參考前述圖1A之實施例的第三主動元件TFT3、第四主動元件TFT4，在此不再詳述。第四分享主動元件SW4電性連接於第二閘極線GL2與共通電極CE41。關於第四分享主動元件SW4與第二閘極線GL2與共通電極CE41的連接方式，請參考前述圖1A之實施例的第二分享主動元件SW2，在此不再詳述。The common electrode CE41 and the seventh pixel electrode PE7 are at least partially overlapped, that is, the common electrode CE41 may be partially overlapped or completely overlapped with the seventh pixel electrode PE7. The seventh moving element TFT7 and the eighth active element TFT8 are electrically connected to the second gate line GL2 and the second data line DL2. For the connection of the seventh moving element TFT7, the eighth active element TFT8, the second gate line GL2, the second data line DL2, the seventh pixel electrode PE7, and the eighth pixel electrode PE8, please refer to the implementation of FIG. 1A described above. The third active element TFT3 and the fourth active element TFT4 are not described in detail here. The fourth sharing active element SW4 is electrically connected to the second gate line GL2 and the common electrode CE41. Regarding the connection method of the fourth shared active element SW4, the second gate line GL2, and the common electrode CE41, please refer to the second shared active element SW2 in the embodiment of FIG. 1A described above, which will not be described in detail here.
於一實施態樣中，第三畫素結構PX3可以更包括共通電極CE32，且共通電極CE32與第六畫素電極PE6至少部分重疊。In an embodiment, the third pixel structure PX3 may further include a common electrode CE32, and the common electrode CE32 and the sixth pixel electrode PE6 at least partially overlap.
於一實施態樣中，第四畫素結構PX4可以更包括共通電極CE42，且共通電極CE42與第八畫素電極PE8至少部分重疊。In an embodiment, the fourth pixel structure PX4 may further include a common electrode CE42, and the common electrode CE42 and the eighth pixel electrode PE8 at least partially overlap.
在本實施例中，如圖4所繪示，對應畫素陣列300中之其中一列的第一畫素結構PX1與第一畫素結構PX2的共通電極CE11與共通電極CE21彼此電性相連，以及共通電極CE12與共通電極CE22彼此電性相連。對應畫素陣列300中之另一列的第三畫素結構PX3與第四畫素結構PX4的共通電極CE31與共通電極CE41彼此電性相連，以及共通電極CE32與共通電極CE42彼此電性相連。In this embodiment, as shown in FIG. 4, the common electrode CE11 and the common electrode CE21 of the first pixel structure PX1 and the first pixel structure PX2 corresponding to one of the columns in the pixel array 300 are electrically connected to each other, and The common electrode CE12 and the common electrode CE22 are electrically connected to each other. The common electrode CE31 and the common electrode CE41 of the third pixel structure PX3 and the fourth pixel structure PX4 corresponding to another column in the pixel array 300 are electrically connected to each other, and the common electrode CE32 and the common electrode CE42 are electrically connected to each other.
第一導線110a通過畫素陣列300中之同一行的第一畫素結構PX1及第三畫素結構PX3。第一連接電極120a藉由對應的貫穿孔H1將第一導線110a與第一畫素結構PX1的共通電極CE11和第一分享主動元件SW1電性連接。第三連接電極120c藉由對應的貫穿孔H2 將第一導線110a與第三畫素結構PX3的共通電極CE31和第三分享主動元件SW3電性連接。The first wire 110a passes through the first pixel structure PX1 and the third pixel structure PX3 in the same row in the pixel array 300. The first connection electrode 120a electrically connects the first lead 110a with the common electrode CE11 of the first pixel structure PX1 and the first shared active element SW1 through the corresponding through hole H1. The third connection electrode 120c electrically connects the first lead 110a with the common electrode CE31 of the third pixel structure PX3 and the third shared active element SW3 through the corresponding through hole H2.
第二連接電極120b與第四連接電極120d對應於第一導線110a未通過的第二畫素結構PX2與第四畫素結構PX4。第二連接電極120b直接連接第二畫素結構PX2的共通電極CE21及第二分享主動元件SW2；第四連接電極120d直接連接第四畫素結構PX4的共通電極CE41及第四分享主動元件SW4。於一實施態樣中，第二連接電極120b係經由對應於第二畫素結構PX2的接觸孔W1與共通電極CE21電性連接。第四連接電極120d係經由對應於第四畫素結構PX4的接觸孔W2與共通電極CE41電性連接。於一實施態樣中，接觸孔W2的實施態樣可以是與未被任一導線110通過的接觸孔W1類似的結構來實現。The second connection electrode 120b and the fourth connection electrode 120d correspond to the second pixel structure PX2 and the fourth pixel structure PX4 that the first wire 110a has not passed. The second connection electrode 120b is directly connected to the common electrode CE21 of the second pixel structure PX2 and the second shared active element SW2; the fourth connection electrode 120d is directly connected to the common electrode CE41 of the fourth pixel structure PX4 and the fourth shared active element SW4. In one embodiment, the second connection electrode 120b is electrically connected to the common electrode CE21 through the contact hole W1 corresponding to the second pixel structure PX2. The fourth connection electrode 120d is electrically connected to the common electrode CE41 via a contact hole W2 corresponding to the fourth pixel structure PX4. In an embodiment, the embodiment of the contact hole W2 may be implemented by a structure similar to the contact hole W1 that is not passed by any of the wires 110.
於此，第一導線110a沿著第一方向D1延伸且電性連接畫素陣列300中之同一行的第一畫素結構PX1的共通電極CE11及第三畫素結構PX3的共通電極CE31；而對應畫素陣列300中之同一列的多個畫素結構PX的各共通電極沿著第二方向D2彼此電性連接（如共通電極CE11與共通電極CE21電性連接、共通電極CE12與共通電極CE22電性連接、共通電極CE31與共通電極CE41電性連接、共通電極CE32與共通電極CE42電性連接）。如此，第一導線110a、第一連接電極120a、第二連接電極120b、第三連接電極120c、第四連接電極120d及各共通電極（如CE11、CE12、CE21、CE22、CE31、CE32、CE41、CE42）電性連接至一參考電壓。透過適當地調整施加於第一導線110a的參考電壓，使得各畫素結構PX之對應不同畫素電極的液晶分子的傾倒角度不同，以改善面板的視角。此外，由於第一導線110a、第一連接電極120a、第一畫素結構PX1的共通電極CE11及第一分享主動元件SW1係經由同一貫穿孔H1而彼此電性連接；第一導線110a、第三連接電極120c、第三畫素結構PX3的共通電極CE31及第三分享主動元件SW3係經由同一貫穿孔H2而彼此電性連接，如此可以改善畫素陣列的開口率。在一些實施例中，第一導線110a的材料可以是單一金屬材料或是合金材料，因此阻抗較低，進而可改善水平串擾（H-crosstalk）的問題。Here, the first wire 110a extends along the first direction D1 and is electrically connected to the common electrode CE11 of the first pixel structure PX1 and the common electrode CE31 of the third pixel structure PX3 in the same row in the pixel array 300; and The common electrodes corresponding to a plurality of pixel structures PX in the same column in the pixel array 300 are electrically connected to each other along the second direction D2 (eg, the common electrode CE11 and the common electrode CE21 are electrically connected, the common electrode CE12 and the common electrode CE22 are electrically connected to each other). Electrically connected, the common electrode CE31 is electrically connected to the common electrode CE41, and the common electrode CE32 is electrically connected to the common electrode CE42). In this way, the first lead 110a, the first connection electrode 120a, the second connection electrode 120b, the third connection electrode 120c, the fourth connection electrode 120d, and the common electrodes (such as CE11, CE12, CE21, CE22, CE31, CE32, CE41, CE42) is electrically connected to a reference voltage. By appropriately adjusting the reference voltage applied to the first lead 110a, the tilt angles of the liquid crystal molecules corresponding to different pixel electrodes of each pixel structure PX are different to improve the viewing angle of the panel. In addition, the first lead 110a, the first connection electrode 120a, the common electrode CE11 of the first pixel structure PX1, and the first shared active element SW1 are electrically connected to each other through the same through-hole H1; the first lead 110a, the third The connection electrode 120c, the common electrode CE31 of the third pixel structure PX3, and the third shared active element SW3 are electrically connected to each other through the same through hole H2, so that the aperture ratio of the pixel array can be improved. In some embodiments, the material of the first wire 110a may be a single metal material or an alloy material, so the impedance is low, and the problem of horizontal crosstalk (H-crosstalk) can be improved.
於一實施例中，畫素陣列更包括複數個電極線140，此些電極線140分別電性連接各連接電極120且位於資料線DL上。舉例而言，如圖3所繪示，畫素陣列200可以更包括第一電極線140a、第二電極線140b及第三電極線140c。第一電極線140a連接第一連接電極120a且位於第四資料線DL4上。第二電極線140b連接第二連接電極120b且位於第一資料線DL1上。第三電極線140c連接第三連接電極120c且位於第二資料線DL2上。舉另一例而言，如圖4所繪示，畫素陣列300可以更包括第一電極線140a、第二電極線140b、第三電極線140c及第四電極線140d。第一電極線140a連接第一連接電極120a且位於第四資料線DL4上。第二電極線140b連接第二連接電極120b且位於第一資料線DL1上。第三電極線140c連接第三連接電極120c且位於第四資料線DL4上。第四電極線140d連接第四連接電極120d且位於第一資料線DL1上。In one embodiment, the pixel array further includes a plurality of electrode lines 140, and these electrode lines 140 are electrically connected to the connection electrodes 120 and located on the data line DL, respectively. For example, as shown in FIG. 3, the pixel array 200 may further include a first electrode line 140a, a second electrode line 140b, and a third electrode line 140c. The first electrode line 140a is connected to the first connection electrode 120a and is located on the fourth data line DL4. The second electrode line 140b is connected to the second connection electrode 120b and is located on the first data line DL1. The third electrode line 140c is connected to the third connection electrode 120c and is located on the second data line DL2. For another example, as shown in FIG. 4, the pixel array 300 may further include a first electrode line 140 a, a second electrode line 140 b, a third electrode line 140 c, and a fourth electrode line 140 d. The first electrode line 140a is connected to the first connection electrode 120a and is located on the fourth data line DL4. The second electrode line 140b is connected to the second connection electrode 120b and is located on the first data line DL1. The third electrode line 140c is connected to the third connection electrode 120c and is located on the fourth data line DL4. The fourth electrode line 140d is connected to the fourth connection electrode 120d and is located on the first data line DL1.
於一實施態樣中，此些電極線140實質上與畫素電極屬於同一層的導電層，因此其可透過同一道製程來共同形成。於一實施態樣中，此述同一層的導電層的材料例如為透明導電材料（氧化銦錫，indium tin oxide，ITO），但不以此為限。此外，在畫素陣列200、畫素陣列300的垂直投影方向Z上，各電極線140與各畫素電極不重疊。In one embodiment, these electrode lines 140 are substantially the same conductive layer as the pixel electrode, so they can be formed together through the same process. In an embodiment, the material of the conductive layer of the same layer is, for example, a transparent conductive material (indium tin oxide, ITO), but is not limited thereto. In addition, in the vertical projection direction Z of the pixel array 200 and the pixel array 300, each electrode line 140 does not overlap each pixel electrode.
於一實施例中，畫素陣列可以包括多個導線110，此些導線110可以間隔一行畫素結構或是間隔多行的畫素結構而設置。換言之，對應設置有導線110的該行的畫素結構，其相鄰行的畫素結構上並未設置有導線110。舉例而言，如圖3所繪示，第一導線110a係對應於畫素結構PX1所屬的該行的多個畫素結構PX，第二導線110b係對應於畫素結構PX3所屬的該行的多個畫素結構PX，而畫素結構PX2所屬的該行的多個畫素結構PX並未設置導線110。In one embodiment, the pixel array may include a plurality of conductive lines 110, and the conductive lines 110 may be arranged at a pixel structure of one row or a pixel structure of multiple rows. In other words, the pixel structure of the row corresponding to the conducting wire 110 is not provided with the conducting wire 110 on the pixel structure of the adjacent row. For example, as shown in FIG. 3, the first wire 110a corresponds to a plurality of pixel structures PX of the row to which the pixel structure PX1 belongs, and the second wire 110b corresponds to the pixel structure of the row to which the pixel structure PX3 belongs. There are multiple pixel structures PX, and the multiple pixel structures PX of the row to which the pixel structure PX2 belongs are not provided with the conductive lines 110.
於一實施例中，畫素陣列400的導線110可以是對應紅色畫素結構或是藍色畫素結構。於一實施態樣中，如圖5所繪示，當畫素陣列400的複數個畫素結構PX係為紅色畫素結構、綠色畫素結構以及藍色畫素結構以條狀排列（RGB stripe排列），此些紅色畫素結構、綠色畫素結構、藍色畫素結構分別各屬一行時，各導線110可以對應藍色畫素結構所屬的該行的各畫素結構PX，因此，這些導線110的數量係對應畫素陣列400的其中三分之一數量行。於另一實施態樣中，如圖6所繪示，當畫素陣列500的複數個畫素結構PX為紅色畫素結構、綠色畫素結構以及藍色畫素結構以條狀排列（RGB stripe排列），這些紅色畫素結構、綠色畫素結構、藍色畫素結構分別各屬一行時，各導線110可以對應藍色畫素結構所屬的該行的各畫素結構PX以及紅色畫素結構所屬的該行的各畫素結構PX，因此，這些導線110的數量係對應畫素陣列500的其中三分之二數量行。於另一實施態樣中，如圖7所繪示，當畫素陣列600的複數個畫素結構PX係為RGBW排列，且藍色畫素結構及紅色畫素結構同屬一行，且綠色畫素結構及白色畫素結構同屬一行時，各導線110可以對應藍色畫素結構及紅色畫素結構所屬的該行的各畫素結構PX。於此，此些導線110的數量係對應畫素陣列100的其中二分之一數量行。In one embodiment, the conductive lines 110 of the pixel array 400 may correspond to a red pixel structure or a blue pixel structure. In an embodiment, as shown in FIG. 5, when the pixel structure PX of the pixel array 400 is a red pixel structure, a green pixel structure, and a blue pixel structure are arranged in stripes (RGB stripe Arrangement), when the red pixel structure, the green pixel structure, and the blue pixel structure belong to a row, each lead line 110 may correspond to each pixel structure PX of the row to which the blue pixel structure belongs, and therefore, these The number of the conductive lines 110 corresponds to one third of the number of rows of the pixel array 400. In another embodiment, as shown in FIG. 6, when the pixel structure PX of the pixel array 500 is a red pixel structure, a green pixel structure, and a blue pixel structure are arranged in a stripe (RGB stripe Arrangement), when each of the red pixel structure, the green pixel structure, and the blue pixel structure belongs to a row, each wire 110 may correspond to the pixel structure PX and the red pixel structure of the row to which the blue pixel structure belongs. The pixel structure PX of the corresponding row belongs to two-thirds of the pixel array 500. In another embodiment, as shown in FIG. 7, when a plurality of pixel structures PX of the pixel array 600 are arranged in RGBW, and the blue pixel structure and the red pixel structure belong to a row, and the green picture When the pixel structure and the white pixel structure belong to the same row, each lead line 110 may correspond to each pixel structure PX of the row to which the blue pixel structure and the red pixel structure belong. Here, the number of the conductive lines 110 corresponds to a half of the number of rows of the pixel array 100.
此外，請再參考圖1A。於一實施例中，在基板SUB的一垂直投影方向Z上，第一畫素電極PE1與第一資料線DL1和第四資料線DL4部分重疊，第三畫素電極PE3與第一資料線DL1和第二資料線DL2部分重疊，亦即，第一畫素電極PE1和第三畫素電極PE3與第一資料線DL1之間不具有間隙。同樣地，第二畫素電極PE2與第一資料線DL1和第四資料線DL4部分重疊，第四畫素電極PE4與第一資料線DL1和第二資料線DL2部分重疊。於其他實施例中，如圖3所繪示，在基板SUB的一垂直投影方向Z上，第一畫素電極PE1與第一資料線DL1和第四資料線DL4不重疊，第三畫素電極PE3與第一資料線DL1和第二資料線DL2不重疊，以及第五畫素電極PE5與第二資料線DL2和第三資料線DL3不重疊；而第二畫素電極PE2與第一資料線DL1和第四資料線DL4部分重疊，第四畫素電極PE4與第一資料線DL1和第二資料線DL2部分重疊，以及第六畫素電極PE6與第二資料線DL2和第三資料線DL3部分重疊。In addition, please refer to FIG. 1A again. In an embodiment, in a vertical projection direction Z of the substrate SUB, the first pixel electrode PE1 partially overlaps the first data line DL1 and the fourth data line DL4, and the third pixel electrode PE3 and the first data line DL1 Partially overlaps the second data line DL2, that is, there is no gap between the first and third pixel electrodes PE1 and PE3 and the first data line DL1. Similarly, the second pixel electrode PE2 partially overlaps the first and fourth data lines DL1 and DL4, and the fourth pixel electrode PE4 partially overlaps the first and second data lines DL1 and DL2. In other embodiments, as shown in FIG. 3, in a vertical projection direction Z of the substrate SUB, the first pixel electrode PE1 does not overlap the first data line DL1 and the fourth data line DL4, and the third pixel electrode PE3 does not overlap the first data line DL1 and the second data line DL2, and the fifth pixel electrode PE5 does not overlap the second data line DL2 and the third data line DL3; and the second pixel electrode PE2 and the first data line DL1 and the fourth data line DL4 partially overlap, the fourth pixel electrode PE4 partially overlaps the first data line DL1 and the second data line DL2, and the sixth pixel electrode PE6 and the second data line DL2 and the third data line DL3 Partial overlap.
再者，於一實施例中，共通電極可以具有至少一支條。請參考圖1A與圖8，為了方便說明起見，圖8為圖1A的畫素電極與共通電極的局部俯視示意圖，圖8中僅繪示第一畫素電極PE1、第二畫素電極PE2、共通電極CE11及共通電極CE12，並且省略了第一閘極線GL1、第一資料線DL1、第一主動元件TFT1、第二主動元件TFT2等構件。請參閱圖1A及圖8，對應第一畫素結構PX1的共通電極CE11具有支條CE11a，而對應第一畫素結構PX1的共通電極CE12具有支條CE12a，第一畫素電極PE1與第二畫素電極PE2分別具有至少兩個配向區，在本實施例中第一畫素電極PE1包含四個配向區DM1~DM4，第二畫素電極PE2包含四個配向區DM5~DM8。共通電極CE11的支條CE11a對應設置配向區DM1~DM4的交界處，而共通電極CE12的支條CE12a對應設置配向區DM5~DM8的交界處。對應第二畫素結構PX2的共通電極CE21具有支條CE21a，而對應第二畫素結構PX2的共通電極CE22具有支條CE22a，第三畫素電極PE3與第四畫素電極PE4分別具有至少兩個配向區，在本實施例中第三畫素電極PE3包含四個配向區DM9~DM12，第四畫素電極PE4包含四個配向區DM13~DM16。共通電極CE21的支條CE21a對應設置配向區DM9~DM12的交界處，而共通電極CE22的支條CE22a對應設置配向區DM13~DM16的交界處。在基板SUB的一垂直投影方向Z上，如圖1A所繪示，第一導線110a的垂直投影係與支條CE11a的垂直投影和支條CE12a的垂直投影重疊。因此，第一導線110a並不會影響第一畫素結構PX1的開口率。Furthermore, in an embodiment, the common electrode may have at least one bar. Please refer to FIG. 1A and FIG. 8. For the convenience of description, FIG. 8 is a schematic partial plan view of the pixel electrode and the common electrode of FIG. 1A. In FIG. 8, only the first pixel electrode PE1 and the second pixel electrode PE2 are shown. , Common electrode CE11 and common electrode CE12, and components such as the first gate line GL1, the first data line DL1, the first active element TFT1, and the second active element TFT2 are omitted. 1A and FIG. 8, the common electrode CE11 corresponding to the first pixel structure PX1 has a branch CE11a, and the common electrode CE12 corresponding to the first pixel structure PX1 has a branch CE12a, and the first pixel electrode PE1 and the second pixel The pixel electrode PE2 has at least two alignment regions. In this embodiment, the first pixel electrode PE1 includes four alignment regions DM1 to DM4, and the second pixel electrode PE2 includes four alignment regions DM5 to DM8. The branches CE11a of the common electrode CE11 correspond to the junctions of the alignment regions DM1 to DM4, and the branches CE12a of the common electrode CE12 correspond to the junctions of the alignment regions DM5 to DM8. The common electrode CE21 corresponding to the second pixel structure PX2 has branches CE21a, and the common electrode CE22 corresponding to the second pixel structure PX2 has branches CE22a. The third pixel electrode PE3 and the fourth pixel electrode PE4 have at least two In this embodiment, the third pixel electrode PE3 includes four alignment regions DM9 to DM12, and the fourth pixel electrode PE4 includes four alignment regions DM13 to DM16. The branches CE21a of the common electrode CE21 correspond to the junctions of the alignment regions DM9 to DM12, and the branches CE22a of the common electrode CE22 correspond to the junctions of the alignment regions DM13 to DM16. In a vertical projection direction Z of the substrate SUB, as shown in FIG. 1A, the vertical projection system of the first wire 110 a overlaps with the vertical projection of the branch CE11 a and the vertical projection of the branch CE12 a. Therefore, the first conductive line 110a does not affect the aperture ratio of the first pixel structure PX1.
於一實施例中，畫素結構的主動元件的閘極、分享主動元件的閘極、共通電極CE與閘極線GL屬於同一層的導電層，因此可以透過同一道製程來共同形成。於一實施態樣中，此述同一層的導電層的材料可以是單一金屬材料或是合金材料，但不以此為限。In one embodiment, the gates of the active elements of the pixel structure, the gates sharing the active elements, the common electrode CE, and the gate line GL belong to the same conductive layer, so they can be formed together through the same process. In an embodiment, the material of the conductive layer of the same layer may be a single metal material or an alloy material, but is not limited thereto.
於再一實施例中，畫素結構的主動元件的源極/汲極、分享主動元件的源極/汲極、導線110與資料線DL都屬於同一層的導電層，因此其可透過同一道製程來共同形成。於一實施態樣中，此述同一層的導電層的材料可以是單一金屬材料或是合金材料，但不以此為限。In yet another embodiment, the source / drain of the active element with the pixel structure, the source / drain of the active element sharing the active element, the wire 110 and the data line DL all belong to the same conductive layer, so they can pass through the same channel. Process to come together. In an embodiment, the material of the conductive layer of the same layer may be a single metal material or an alloy material, but is not limited thereto.
於又一實施例中，連接電極120、畫素電極PE以及電極線140都屬於同一層的導電層，因此其可透過同一道製程來共同形成。於一實施態樣中，此述同一層的導電層的材料可以是透明導電材料，但不以此為限。In another embodiment, the connection electrode 120, the pixel electrode PE, and the electrode line 140 all belong to the same conductive layer, so they can be formed together through the same process. In an embodiment, the material of the conductive layer of the same layer may be a transparent conductive material, but is not limited thereto.
綜上所述，本發明實施例之所提供的畫素陣列，其利用導線（例如第一導線）作為畫素陣列之沿著第一方向電性連接的線路，而各畫素結構的共通電極作為畫素陣列之沿著第二方向電性連接的線路，因此，導線（例如第一導線）、連接電極（例如第一連接電極）以及各畫素結構的共通電極電性連接至一參考電壓，而無須於每一畫素結構設計電性連接至一參考電壓之導線。在一些實施例中，導線（例如第一導線）、連接電極（例如第一連接電極）以及各畫素結構的共通電極和分享主動元件係經由同一貫穿孔而彼此電性連接，因此，不需形成額外的貫穿孔來使導線（例如第一導線）、連接電極（例如第一連接電極）、以及各畫素結構的共通電極和分享主動元件電性連接，如此不僅節省製程步驟還可增加各畫素結構的開口率。在一些實施例中，導線（例如第一導線）的材料可以是單一金屬材料或是合金材料，因此阻抗較低，進而可改善水平串擾（H-crosstalk）的問題。To sum up, the pixel array provided by the embodiment of the present invention uses a wire (such as a first wire) as a line of the pixel array electrically connected along the first direction, and a common electrode of each pixel structure As the pixel array is electrically connected along the second direction, therefore, the lead (such as the first lead), the connection electrode (such as the first connection electrode), and the common electrode of each pixel structure are electrically connected to a reference voltage. Without having to design a lead electrically connected to a reference voltage in each pixel structure. In some embodiments, the lead (eg, the first lead), the connection electrode (eg, the first connection electrode), and the common electrode and the shared active element of each pixel structure are electrically connected to each other through the same through hole. Therefore, there is no need to An additional through hole is formed to electrically connect the lead (such as the first lead), the connection electrode (such as the first connection electrode), the common electrode of each pixel structure, and the shared active device, so that not only the process steps can be saved, but also various The aperture ratio of the pixel structure. In some embodiments, the material of the conductive line (such as the first conductive line) may be a single metal material or an alloy material, so the impedance is low, and the H-crosstalk problem may be improved.
雖然本發明的技術內容已經以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神所作些許之更動與潤飾，皆應涵蓋於本發明的範疇內，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the technical content of the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art and making some changes and retouching without departing from the spirit of the present invention should be covered by the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.
100、200、300、400、500、600‧‧‧畫素陣列100, 200, 300, 400, 500, 600‧‧‧ pixel array
110‧‧‧導線 110‧‧‧Wire
110a‧‧‧第一導線 110a‧‧‧first lead
110b‧‧‧第二導線 110b‧‧‧Second Lead
120‧‧‧連接電極 120‧‧‧ connecting electrode
120a‧‧‧第一連接電極 120a‧‧‧first connection electrode
120b‧‧‧ 第二連接電極 120b‧‧‧ Second connection electrode
120c‧‧‧第三連接電極 120c‧‧‧third connection electrode
120d‧‧‧第四連接電極 120d‧‧‧Fourth connection electrode
130‧‧‧絕緣層 130‧‧‧ Insulation
130a‧‧‧第一絕緣層 130a‧‧‧First insulation layer
130b‧‧‧第二絕緣層 130b‧‧‧Second insulation layer
140‧‧‧ 電極線 140‧‧‧ electrode wire
140a‧‧‧第一電極線 140a‧‧‧First electrode wire
140b‧‧‧ 第二電極線 140b‧‧‧ Second electrode wire
140c‧‧‧第三電極線 140c‧‧‧Third electrode wire
140d‧‧‧ 第四電極線 140d‧‧‧ Fourth electrode wire
CE11、CE12、CE21、CE22、CE31、CE32、CE41、CE42‧‧‧共通電極 CE11, CE12, CE21, CE22, CE31, CE32, CE41, CE42‧‧‧Common electrodes
CE11a、CE12a、CE21a、CE22a‧‧‧支條 CE11a, CE12a, CE21a, CE22a
CH1、CH2、CH3、CH4‧‧‧通道層 CH1, CH2, CH3, CH4‧‧‧ Channel layer
DL‧‧‧資料線 DL‧‧‧Data Line
DL1‧‧‧第一資料線 DL1‧‧‧The first data line
DL2‧‧‧第二資料線 DL2‧‧‧Second Data Line
DL3‧‧‧第三資料線 DL3‧‧‧Third Data Line
DL4‧‧‧第四資料線 DL4‧‧‧ Fourth Data Line
D1‧‧‧第一方向 D1‧‧‧ first direction
D2‧‧‧第二方向 D2‧‧‧ Second direction
DM1~DM16‧‧‧配向區 DM1 ~ DM16‧‧‧Alignment area
DE1、DE2、DE3、DE4、SWD1、SWD2‧‧‧汲極 DE1, DE2, DE3, DE4, SWD1, SWD2‧‧‧ Drain
GL‧‧‧閘極線 GL‧‧‧Gate line
GL1‧‧‧第一閘極線 GL1‧‧‧First Gate Line
GL2‧‧‧第二閘極線 GL2‧‧‧Second Gate Line
GE1、GE2、GE3、GE4、SWG1、SWG2‧‧‧閘極 GE1, GE2, GE3, GE4, SWG1, SWG2‧‧‧Gate
H1、H2‧‧‧貫穿孔 H1, H2‧‧‧ through holes
PX‧‧‧畫素結構 PX‧‧‧Pixel Structure
PX1、PX2、PX3、PX4‧‧‧第一至第四畫素結構 PX1, PX2, PX3, PX4 ‧‧‧ first to fourth pixel structure
PE1、PE2、PE3、PE4、PE5、 PE6、PE7、PE8‧‧‧第一至第八畫素電極 PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8‧‧‧ first to eighth pixel electrodes
TFT1、TFT2、TFT3、TFT4、TFT5、 TFT6、TFT7、TFT8‧‧‧主動元件 TFT1, TFT2, TFT3, TFT4, TFT5, TFT6, TFT7, TFT8‧‧‧
SE1、SE2、SE3、SE4、SWS1、SWS2‧‧‧源極 SE1, SE2, SE3, SE4, SWS1, SWS2‧‧‧ source
SUB‧‧‧基板 SUB‧‧‧ substrate
SW1、SW2、SW3、SW4‧‧‧分享主動元件 SW1, SW2, SW3, SW4‧‧‧ share active components
SWCH1、SWCH2‧‧‧通道層 SWCH1, SWCH2‧‧‧Channel layer
W1、W2‧‧‧接觸孔 W1, W2‧‧‧ contact holes
X-X‧‧‧剖面線 X-X‧‧‧ section line
Z‧‧‧ 垂直投影方向 Z‧‧‧ vertical projection direction
圖1A為本發明一實施例的畫素陣列的俯視示意圖。 圖1B為圖1A的局部示意圖。 圖2是沿著圖1B之剖線X-X的剖面示意圖。 圖3為本發明另一實施例的畫素陣列的俯視示意圖。 圖4為本發明又一實施例的畫素陣列的俯視示意圖。 圖5為本發明又一實施例的畫素陣列的簡單俯視示意圖。 圖6為本發明又一實施例的畫素陣列的簡單俯視示意圖。 圖7為本發明又一實施例的畫素陣列的簡單俯視示意圖。 圖8為圖1A的畫素電極與共通電極的局部俯視示意圖。FIG. 1A is a schematic top view of a pixel array according to an embodiment of the present invention. FIG. 1B is a partial schematic diagram of FIG. 1A. Fig. 2 is a schematic cross-sectional view taken along the line X-X of Fig. 1B. FIG. 3 is a schematic top view of a pixel array according to another embodiment of the present invention. FIG. 4 is a schematic top view of a pixel array according to another embodiment of the present invention. FIG. 5 is a schematic plan view of a pixel array according to another embodiment of the present invention. FIG. 6 is a schematic plan view of a pixel array according to another embodiment of the present invention. FIG. 7 is a schematic plan view of a pixel array according to another embodiment of the present invention. FIG. 8 is a schematic partial plan view of the pixel electrode and the common electrode of FIG. 1A.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107108336A TWI660224B (en) | 2018-03-12 | 2018-03-12 | Pixel array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107108336A TWI660224B (en) | 2018-03-12 | 2018-03-12 | Pixel array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI660224B true TWI660224B (en) | 2019-05-21 |
| TW201939138A TW201939138A (en) | 2019-10-01 |
Family
ID=67348005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107108336A TWI660224B (en) | 2018-03-12 | 2018-03-12 | Pixel array |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI660224B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111402832A (en) * | 2019-12-04 | 2020-07-10 | 友达光电股份有限公司 | Pixel structure and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201142779A (en) * | 2010-05-27 | 2011-12-01 | Au Optronics Corp | Pixel structure and display panel having the same |
| TW201537273A (en) * | 2014-03-26 | 2015-10-01 | Au Optronics Corp | Pixel structure |
| TW201719257A (en) * | 2015-11-19 | 2017-06-01 | 友達光電股份有限公司 | Pixel unit and pixel array |
| TWI609219B (en) * | 2017-02-10 | 2017-12-21 | 友達光電股份有限公司 | Pixel unit, pixel-array structure, and display panel |
-
2018
- 2018-03-12 TW TW107108336A patent/TWI660224B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201142779A (en) * | 2010-05-27 | 2011-12-01 | Au Optronics Corp | Pixel structure and display panel having the same |
| TW201537273A (en) * | 2014-03-26 | 2015-10-01 | Au Optronics Corp | Pixel structure |
| TW201719257A (en) * | 2015-11-19 | 2017-06-01 | 友達光電股份有限公司 | Pixel unit and pixel array |
| TWI609219B (en) * | 2017-02-10 | 2017-12-21 | 友達光電股份有限公司 | Pixel unit, pixel-array structure, and display panel |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111402832A (en) * | 2019-12-04 | 2020-07-10 | 友达光电股份有限公司 | Pixel structure and display panel |
| TWI716211B (en) * | 2019-12-04 | 2021-01-11 | 友達光電股份有限公司 | Pixel structure and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201939138A (en) | 2019-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10108055B2 (en) | Curved liquid crystal display | |
| US10558095B2 (en) | Liquid crystal display with reduced color mixing | |
| TWI511303B (en) | Array substrate of liquid crystal display | |
| CN103309093B (en) | Liquid crystal indicator | |
| TWI468829B (en) | Pixel array | |
| JP2020532755A (en) | Array boards, display panels, display devices | |
| TWI567468B (en) | Pixel unit and pixel array | |
| TW201300916A (en) | Pixel structure and driving method thereof | |
| CN104345500A (en) | Liquid crystal display | |
| WO2020118759A1 (en) | Array substrate | |
| CN104062819B (en) | Display panel | |
| KR102043578B1 (en) | Array substrates, liquid crystal display panels, and liquid crystal display devices | |
| KR102426595B1 (en) | Liquid crystal display device | |
| TWI338805B (en) | Transflective liquid crystal display panel and pixel structure thereof | |
| JP2022552766A (en) | Pixel structure, array substrate and display panel | |
| TWI570492B (en) | Pixel structure | |
| TWI567462B (en) | Pixel structure and pixel array | |
| TWI660224B (en) | Pixel array | |
| TWI514058B (en) | Pixel array | |
| US11099442B2 (en) | Display device | |
| KR102497664B1 (en) | Liquid crystal display device | |
| CN111754873A (en) | Display panel and display device | |
| CN107688263A (en) | Display panel | |
| TWI406072B (en) | Pixel structure, active device array, display panel, and display apparatus | |
| TWI643001B (en) | Display panel |