TWI648844B - 薄膜電晶體及其製造方法 - Google Patents

薄膜電晶體及其製造方法 Download PDF

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TWI648844B
TWI648844B TW106138318A TW106138318A TWI648844B TW I648844 B TWI648844 B TW I648844B TW 106138318 A TW106138318 A TW 106138318A TW 106138318 A TW106138318 A TW 106138318A TW I648844 B TWI648844 B TW I648844B
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Taiwan
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film transistor
dielectric layer
thin film
gate dielectric
semiconductor layer
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TW106138318A
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TW201919210A (zh
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Tai-Jui Wang
王泰瑞
Yung-Hui Yeh
葉永輝
Jui-Wen Yang
楊瑞紋
Hsiao-Chiang Yao
姚曉強
Chun-Hung Chu
朱俊鴻
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Industrial Technology Research Institute
財團法人工業技術研究院
Intellectual Property Innovation Corporation
創智智權管理顧問股份有限公司
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Priority to TW106138318A priority Critical patent/TWI648844B/zh
Priority to CN201711396621.6A priority patent/CN109755323B/zh
Priority to US15/913,897 priority patent/US10644167B2/en
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Publication of TWI648844B publication Critical patent/TWI648844B/zh
Publication of TW201919210A publication Critical patent/TW201919210A/zh

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Abstract

一種薄膜電晶體，其包括可撓性基板、半導體層、第一閘極以及第一閘介電層。半導體層位於可撓性基板上。第一閘極位於可撓性基板上且對應於半導體層的部份區域。第一閘介電層位於第一閘極與半導體層之間。第一閘介電層與半導體層接觸，且第一閘介電層的氫原子濃度小於6.5╳10 20原子數/立方公分。一種製造此薄膜電晶體的製造方法亦被提出。

Description

薄膜電晶體及其製造方法
本發明是有關於一種薄膜電晶體及其製造方法。
隨著電子技術的高度發展，電子產品不斷推陳出新。電子產品為了可應用於不同領域，可撓曲、輕薄以及外型不受限的特性逐漸受到重視。
就目前市面上已公開販售的可撓式電子產品而言，其大多為具有固定曲率的彎曲式（bendable）產品。為了達到折疊式（foldable）產品的目標，小撓曲半徑的可撓式電子產品是未來的大挑戰。因此，如何使具有小撓曲半徑的可撓式電子產品仍具有良好的製造良率（yield）及產品可靠度（reliability），實已成目前亟欲解決的課題。
本發明之一實施例提供一種薄膜電晶體，其閘介電層的氫原子濃度小於6.5╳10 20原子數/立方公分而可以提升薄膜電晶體的可靠度。
本發明之一實施例提供一種薄膜電晶體的製造方法，其閘介電層的氫原子濃度小於6.5╳10 20原子數/立方公分而可以提升薄膜電晶體的可靠度。
本發明一實施例的薄膜電晶體，其包括可撓性基板、半導體層、第一閘極以及第一閘介電層。半導體層位於可撓性基板上。第一閘極位於可撓性基板上且對應於半導體層的部份區域。第一閘介電層位於第一閘極與半導體層之間。第一閘介電層與半導體層接觸，且第一閘介電層的氫原子濃度小於6.5╳10 20原子數/立方公分。
本發明一實施例的薄膜電晶體的製造方法，其包括以下步驟。於可撓性基板上形成半導體層。於半導體層上形成第一閘介電層，第一閘介電層與半導體層接觸，且第一閘介電層的氫原子濃度小於6.5╳10 20原子數/立方公分。於第一閘介電層上形成對應於半導體層的部份區域的第一閘極。
為讓本發明更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1E是依照本發明的第一實施例的一種薄膜電晶體的製造方法的剖面示意圖。
請參照圖1A，提供可撓性基板110。可撓性基板110的材質可例如為聚亞醯胺（polyimide；PI）、聚碳酸酯（polycarbonate；PC）、聚醚碸（polyethersulfone；PES）、聚丙烯酸酯（polyacrylate；PA）、聚原冰烯（polynorbornene；PNB）、聚乙烯對苯二甲酸酯（polyethylene terephthalate；PET）、聚醚醚酮（polyetheretherketone；PEEK）、聚萘二甲酸乙二醇酯（polyethylene naphthalate；PEN）或聚醚亞醯胺（polyetherimide；PEI）等可撓性材料，於本發明不限於此。
在一些實施例中，在形成後續的膜層之前，可以先在可撓性基板110上形成緩衝層120。緩衝層120可為單層薄膜或是由多層薄膜所構成之疊層，本實施例不限定緩衝層120的層數、材質或形成方式。當緩衝層120是由多層薄膜所構成之疊層時，緩衝層120例如是由有機薄膜與無機薄膜交替堆疊所構成之疊層，或者，緩衝層120亦可以是由多層無機薄膜堆疊所構成之疊層。當緩衝層120是由多層無機薄膜堆疊所構成之疊層時，緩衝層120可為氮化矽（silicon nitride；SiN x）與氧化矽（Silicon oxide；SiO x）交替堆疊的疊層。緩衝層120可以具有良好的接合力或較低的水氣穿透率（vapor water transmission rate；VWTR），以提升薄膜電晶體100的可靠性（reliability）。緩衝層120也可以具有良好的隔熱性，以在形成後續的膜層的製程中，降低可能因升溫而對可撓性基板110所造成的影響。
接著，在可撓性基板110上形成半導體層130。舉例而言，可以先藉由化學氣相層積法（Chemical Vapor Deposition；CVD）以及微影蝕刻製程等類似的沉積以及圖案化製程，以在可撓性基板110上形成圖案化的非晶矽薄膜。接著，可以藉由雷射結晶化（laser crystallization）或準分子雷射退火（Excimer Laser Annealing；ELA）製程以使非晶矽薄膜成為多晶矽薄膜，並使用雷射對非晶矽膜進行掃描使其重新結晶而成為具有多晶矽的半導體層130，這種形成多晶矽的技術可以稱為低溫多晶矽（low temperature poly-Silicon；LTPS）製程。一般而言，藉由低溫多晶矽製程可以在較低（如：攝氏600度以下）的製程溫度中完成半導體層130的全部製程，因而可以在半導體層130的製造過程中使可撓性基板110仍具有良好的穩定度或性質。
在一些實施例中，還可以包括進行離子佈植（Ion Implantation）製程（未繪示），以使半導體層130中具有摻雜離子，而且依照摻雜離子的種類不同，可形成具有N型或P型摻雜的通道區130b（channel region）。
請參考圖1B，在可撓性基板110上形成半導體層130之後，於半導體層130上形成第一閘介電層140。第一閘介電層140可以藉由沉積製程所形成。第一閘介電層140共形（conformal）覆蓋於半導體層130上且直接接觸半導體層130。在本實施例中，第一閘介電層140可以是將氫氣、矽烷（如：甲矽烷（Silane；SiH 4））、載氣（惰性氣體；如氦氣（He））以及氧氣/含氮氣體（如：一氧化二氮（dinitrogen monoxide；N 2O）或氨氣（NH 3））相混合後，以電漿增強化學氣相沉積法（Plasma-Enhanced Chemical Vapor Deposition；PECVD）所形成具有氫原子摻雜的氧化矽層、氮化矽層或氮氧化矽（silicon oxynitride；SiON）層。
在形成第一閘介電層140的電漿增強化學氣相沉積法製程中，其惰性氣體流量與總氣體流量的比值可以為0.5至0.7，以使所形成的第一閘介電層140的氫原子濃度小於6.5╳10 20原子數/立方公分（Atoms/cm 3）。在本實施例中，惰性氣體可以為氦氣（He），但本發明不限於此。在其他實施例中，惰性氣體也可以為氦氣、氖氣（Ne）、氬氣（Ar）、氪氣（Kr）、氙氣（Xe）、氡氣（Rn）或上述氣體的組合。除此之外，在前述的電漿增強化學氣相沉積法製程中，可以藉由調整其他的製程參數（recipe）（如：射頻（radio frequency；Rf）功率），而可以在形成第一閘介電層140的過程中具有良好的鍍率（deposition rate）（如：2.5至3.5 Å/sec）且具有良好的膜質（film quality）。
接著，請參照圖1C，於第一閘介電層140上形成第一閘極150，其中第一閘極150位於半導體層130的通道區130b的正上方。第一閘極150可藉由沉積以及圖案化製程等其他適宜製程形成，於本實施例不限定第一閘極150材質或形成方式，惟第一閘極150需具有可傳遞電子訊號的導電性質。
隨後，以第一閘介電層140作為罩幕（mask）進行離子佈植製程（未繪示），以於半導體層130的相對兩端形成彼此分離的源極區130a與汲極區130c，其中源極區130a與汲極區130c的離子佈植製程例如是以適當能量的離子佈植，如砷（As）、磷（P）、硼（B）等離子作摻雜離子，以形成P型或N型的源極區130a與汲極區130c。
接著，請參照圖1D，在半導體層130中形成源極區130a與汲極區130c之後，於第一閘介電層140上形成絕緣層160，以覆蓋部分的第一閘介電層140以及位於第一閘介電層140上的第一閘極150。絕緣層160可藉由沉積製程、塗佈製程或其他適宜製程形成，且可為單層薄膜或是由多層薄膜所構成之疊層，於本實施例不限定絕緣層160的層數、材質或形成方式，惟絕緣層160需具有電性絕緣的性質。
在本實施例中，絕緣層160共形覆蓋第一閘介電層140以及第一閘極150，但本發明不限於此。在一些實施例中，絕緣層160例如可以藉由研磨製程（polishing process）而可以具有平坦的表面，以使後續形成於絕緣層160上的其他膜層可以位於絕緣層160的平坦表面上。
隨後，可以藉由蝕刻製程（etching process）或雷射鑽孔製程（laser drilling process），以於絕緣層160上形成多個開口160a、160b。第一開口160a貫穿絕緣層160以及第一閘介電層140，以暴露出部分的源極區130a與部分的汲極區130c。第二開口160b貫穿絕緣層160，以暴露出部分的第一閘極150。
接著，請參照圖1E，可以藉由沉積製程及/或電鍍製程等適宜的製程在開口160a、160b中填入導電物質，以形成多個導通孔（conductive via）170a、170b。位於第一開口160a內的第一導通孔170a電性連接於源極區130a與汲極區130c，且對應於源極區130a的第一導通孔170a可以為源極S，對應於汲極區130c的第一導通孔170a可以為汲極D。位於第二開口160b內的第二導通孔170b電性連接於第一閘極150。
在本實施例中，填入開口160a、160b內的導電物質可以進一步覆蓋於絕緣層160上。隨後，例如可以藉由微影及蝕刻製程以使覆蓋於絕緣層160上的導電物質圖案化，以形成圖案化導電層170。
經過上述製程後即可大致上完成本實施例的薄膜電晶體100的製作。上述的薄膜電晶體100包括可撓性基板110、半導體層130、第一閘極150、第一閘介電層140、源極以及汲極。半導體層130位於可撓性基板110上且具有源極區130a、通道區130b以及汲極區130c，其中通道區130b位於源極區130a與汲極區130c之間。源極S以及汲極D分別耦接於半導體層130的源極區130a以及汲極區130c。第一閘極150位於可撓性基板110上且對應於半導體層130的通道區130b。第一閘介電層140位於第一閘極150與半導體層130之間，第一閘介電層140與半導體層130接觸，且第一閘介電層140的氫原子濃度小於6.5╳10 20原子數/立方公分。
在矽質薄膜中，可以藉由氫原子的摻雜而使矽原子與氫原子產生矽氫鍵結（Si-H bonding），以降低矽質膜層內矽原子的懸鍵（dangling bond）數量。在一般電子元件中，若其所包括的電晶體受到撓曲應力之後，可能會因為閘介電層內的矽氫鍵的鍵結斷鍵而使電晶體產生的電性缺陷（如：臨界電壓（threshold voltage；Vth）的改變）。因此，在本實施例的薄膜電晶體100中，可以藉由降低第一閘介電層140的氫原子濃度，以對應地降低第一閘介電層140內的矽氫鍵鍵結數量。如此一來，在薄膜電晶體100受到撓曲應力之後，可以降低因為第一閘介電層140內的矽氫鍵的鍵結斷鍵而使薄膜電晶體100產生電性缺陷的可能。舉例而言，在本實施例中，由於第一閘介電層140的氫原子濃度小於6.5╳10 20原子數/立方公分，而可以使薄膜電晶體100在撓曲半徑至少為1釐米（millimeter；mm）的小撓曲徑條件之下，相較於未撓曲的薄膜電晶體100的臨界電壓飄移量（threshold voltage Variation），經撓曲後的薄膜電晶體100的臨界電壓飄移量差值在0.05伏特（Volt；V）以下，即對於薄膜電晶體100的臨界電壓飄移量不會具有太大的變化。
在本實施例中，半導體層130位於可撓性基板110與第一閘極150之間。換句話說，本實施例的薄膜電晶體100為上閘極（top gate）結構，但本發明不限於此。
在本實施例中，半導體層130藉由前述的低溫多晶矽製程所形成。換句話說，半導體層130的材質可以包括晶矽材料及/或部分未結晶成晶矽的非晶矽材料，但本發明不限於此。
圖2是依照本發明的第二實施例的一種薄膜電晶體的剖面示意圖。請參考圖1E與圖2，本實施例的薄膜電晶體200與圖1E的薄膜電晶體100的差異在於：薄膜電晶體200更包括位於第一閘極150以及第一閘介電層140之間的第二閘介電層180，且第二閘介電層180的氫原子濃度可以大於6.5╳10 20原子數/立方公分。
圖3A至圖3B是依照本發明的第三實施例的一種薄膜電晶體的製造方法的剖面示意圖。請參考圖3A與圖3B，本實施例的薄膜電晶體300的製造方法與圖1A至圖1E的實施例的薄膜電晶體100的製造方法類似，差異在於：在形成緩衝層120之前，先在可撓性基板110上形成第二閘極190。第二閘極190的形成方式可以類似於前述實施例中的第一閘極150的形成方式，故於此不加以贅述。絕緣層160上的部分開口（未繪示）可以貫穿絕緣層160、第一閘介電層140以及緩衝層120，以在填入導電物質後形成連接於圖案化導電層170與第二閘極190的第三導通孔170c。除此之外，其餘的製作流程大致與圖1D至圖1H相同或相似，故於此不加以贅述。
請參考圖1E與3B，本實施例的薄膜電晶體300與圖1E的薄膜電晶體100的差異在於：在可撓性基板110與半導體層130之間具有第二閘極190。第一閘極150與第二閘極190可以接收/傳送相同或相似的電子訊號。換句話說，本實施例的薄膜電晶體300為雙閘極（dual gate）結構。
圖4是依照本發明的第四實施例的一種薄膜電晶體的剖面示意圖。請參考圖3B與圖4，本實施例的薄膜電晶體400與圖3B的薄膜電晶體300的差異在於：薄膜電晶體400更包括位於第一閘極150以及第一閘介電層140之間的第二閘介電層180，且第二閘介電層180的氫原子濃度可以大於6.5╳10 20原子數/立方公分。
圖5A至圖5E是依照本發明的第五實施例的一種薄膜電晶體的製造方法的剖面示意圖。請同時參考圖5A至圖5E及圖1A至圖1E，在本實施例中，薄膜電晶體500的製造方法與薄膜電晶體100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能，並省略描述。
請參照圖5A，提供可撓性基板110。並且，在形成後續的膜層之前，可以選擇性地先在可撓性基板110上形成緩衝層120。接著，在可撓性基板110上形成第一閘極550。在本實施例中，第一閘極550的材質或形成方式可以相同或相似於前述實施例的第一閘極150，故於此不加以贅述。
接著，請參照圖5B，在形成第一閘極550之後，於第一閘極550上形成具有氫原子摻雜的第一閘介電層540，且第一閘介電層540的氫原子濃度小於6.5╳10 20原子數/立方公分。在本實施例中，第一閘介電層540的材質或形成方式可以相同或相似於前述實施例的第一閘介電層140，故於此不加以贅述。
接著，請參照圖5C，在形成第一閘介電層540之後，藉由低溫多晶矽製程以形成半導體層530。半導體層530位於第一閘介電層540上且與第一閘介電層540直接接觸。隨後，半導體層530可以藉由區域性的離子佈植佈植製程，以形成具有不同摻雜的源極區530a、通道區530b與汲極區530c。在本實施例中，半導體層530的材質或形成方式可以相同或相似於前述實施例的半導體層130，故於此不加以贅述。
接著，請參照圖5D，在形成半導體層530之後，於半導體層530上形成絕緣層560，以覆蓋部分的第一閘介電層540以及位於第一閘介電層540上的半導體層530。隨後，於絕緣層560上形成多個第一開口560a，以暴露出部分的源極區530a與部分的汲極區530c。在本實施例中，絕緣層560的材質或形成方式可以相同或相似於前述實施例的絕緣層160，且第一開口560a的形成方式可以相同或相似於前述實施例的第一開口160a，故於此不加以贅述。
接著，請參照圖5E，在第一開口560a中填入導電物質，以形成多個第一導通孔570a。對應於源極區130a的第一導通孔570a可以為源極S，對應於汲極區530c的第一導通孔570a可以為汲極D。填入第一開口560a內的導電物質可以進一步覆蓋於絕緣層560上，並可將覆蓋於絕緣層560上的導電物質圖案化，以形成圖案化導電層570。在本實施例中，第一導通孔570a及圖案化導電層570的材質或形成方式可以相同或相似於前述實施例的第一導通孔170a及圖案化導電層170，故於此不加以贅述。
經過上述製程後即可大致上完成本實施例的薄膜電晶體500的製作。本實施例的薄膜電晶體500與圖1E的薄膜電晶體100的差異在於：第一閘極550位於可撓性基板110與半導體層530之間。換句話說，本實施例的薄膜電晶體500為下閘極（bottom gate）結構。
圖6是依照本發明的第六實施例的一種薄膜電晶體的剖面示意圖。請參考圖5與圖6，本實施例的薄膜電晶體600與圖5的薄膜電晶體500的差異在於：薄膜電晶體600更包括位於第一閘極550以及第一閘介電層540之間的第二閘介電層580。在本實施例中，第二閘介電層580的材質或形成方式可以相同或相似於前述實施例的第二閘介電層180，故於此不加以贅述。
圖7是依照本發明的第七實施例的一種薄膜電晶體的剖面示意圖。請參考圖5與圖7，本實施例的薄膜電晶體700與圖5的薄膜電晶體500的差異在於：部分的圖案化導電層570對應於半導體層530的通道區530b而可作為第二閘極590。第一閘極550與第二閘極590可以接收/傳送相同或相似的電子訊號。換句話說，本實施例的薄膜電晶體700為雙閘極結構。除此之外，相較於前述實施例的絕緣層560，本實施例的絕緣層760可以具有較薄的厚度。
圖8是依照本發明的第八實施例的一種薄膜電晶體的剖面示意圖。請參考圖7與圖8，本實施例的薄膜電晶體800與圖7的薄膜電晶體700的差異在於：薄膜電晶體800更包括位於第一閘極550以及第一閘介電層540之間的第二閘介電層580。 測試例
以下列測試例作為說明本發明實施例的薄膜電晶體可以在高撓曲條件之下，對於薄膜電晶體的臨界電壓飄移量不會具有太大的變化，特別以下列測試例作為說明。然而，這些測試例均不用以具體限制本發明之範疇。
請同時參考圖9及圖10。圖9繪示本發明的比較例的薄膜電晶體的輸出特性（transfer characteristics）曲線圖。圖10繪示本發明的測試例的薄膜電晶體的輸出特性曲線圖。比較例的薄膜電晶體與測試例的薄膜電晶體在結構上皆為類似於圖1E中具有上閘極（top gate）結構的薄膜電晶體100，差別僅在於測試例的薄膜電晶體的第一閘介電層的氫原子濃度小於6.5╳10 20原子數/立方公分。
具體而言，在圖9及圖10中分別顯示了比較例的薄膜電晶體及測試例的薄膜電晶體在源極與汲極間具有-0.1伏特以及-10.1伏特的汲極偏壓（drain bias；於圖示中以V DS表示）下，量測撓曲前及撓曲後的同一薄膜電晶體，在對閘極施加不同的閘極偏壓（gate bias；於圖示中以V GS表示）下源極與汲極間所對應產生的電流（drain current；於圖示中以I DS表示）。在圖9及圖10中，橫軸為閘極偏壓值（單位：伏特），縱軸為對應產生的電流值（單位：安培），實線為撓曲前的薄膜電晶體在-0.1伏特的汲極偏壓下對閘極施加不同的閘極偏壓下對應產生的電流值曲線，虛線為撓曲前薄膜電晶體在-10.1伏特的汲極偏壓下對閘極施加不同的閘極偏壓下對應產生的電流值曲線，點線為撓曲後薄膜電晶體在-0.1伏特的汲極偏壓下對閘極施加不同的閘極偏壓下對應產生的電流值曲線，虛點線為撓曲後薄膜電晶體在-10.1伏特的汲極偏壓下對閘極施加不同的閘極偏壓下對應產生的電流值曲線。
在圖9中，撓曲前及撓曲後的比較例的薄膜電晶體的臨界電壓的差值約為0.4伏特。在圖10中，撓曲前及撓曲後的測試例的薄膜電晶體的臨界電壓的差值小於為0.04伏特。也就是說，測試例的薄膜電晶體具有較佳的可靠度。
綜上所述，本發明一實施例的薄膜電晶體其與半導體層相接觸的閘介電層的氫原子濃度小於6.5╳10 20原子數/立方公分，而可以對應地降低閘介電層內的矽氫鍵鍵結數量。因此，在薄膜電晶體受到撓曲應力之後，可以降低因閘介電層內的矽氫鍵的鍵結斷鍵而使薄膜電晶體產生電性缺陷的可能，而可以提升薄膜電晶體的可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200、300、400、500、600、700、800‧‧‧薄膜電晶體
110‧‧‧可撓性基板
120‧‧‧緩衝層
130、530‧‧‧半導體層
130a、530a‧‧‧源極區
130b、530b‧‧‧通道區
130c、530c‧‧‧汲極區
140、540‧‧‧第一閘介電層
150、550‧‧‧第一閘極
160、560、760‧‧‧絕緣層
160a‧‧‧第一開口
160b‧‧‧第二開口
170a‧‧‧第一導通孔
170b‧‧‧第二導通孔
170c‧‧‧第三導通孔
170‧‧‧圖案化導電層
190、590‧‧‧第二閘極
180、580‧‧‧第二閘介電層
S‧‧‧源極
D‧‧‧汲極
圖1A至圖1E是依照本發明的第一實施例的一種薄膜電晶體的製造方法的剖面示意圖。 圖2是依照本發明的第二實施例的一種薄膜電晶體的剖面示意圖。 圖3A至圖3B是依照本發明的第三實施例的一種薄膜電晶體的製造方法的剖面示意圖。 圖4是依照本發明的第四實施例的一種薄膜電晶體的剖面示意圖。 圖5A至圖5E是依照本發明的第五實施例的一種薄膜電晶體的製造方法的剖面示意圖。 圖6是依照本發明的第六實施例的一種薄膜電晶體的剖面示意圖。 圖7是依照本發明的第七實施例的一種薄膜電晶體的剖面示意圖。 圖8是依照本發明的第八實施例的一種薄膜電晶體的剖面示意圖。 圖9繪示本發明的比較例的薄膜電晶體的輸出特性曲線圖。 圖10繪示本發明的測試例的薄膜電晶體的輸出特性曲線圖。

Claims (21)

  1. 一種薄膜電晶體，包括：一可撓性基板；一半導體層，位於該可撓性基板上；一第一閘極，位於該可撓性基板上且對應於該半導體層的部份區域；以及一第一閘介電層，位於該第一閘極與該半導體層之間，該第一閘介電層與該半導體層接觸，且該第一閘介電層的氫原子濃度小於6.5×1020原子數/立方公分，但該第一閘介電層的氫原子濃度不包括5.2×1016~5.2×1018原子數/立方公分。
  2. 如申請專利範圍第1項所述的薄膜電晶體，其中該可撓性基板的可撓曲半徑大於或等於1釐米。
  3. 如申請專利範圍第1項所述的薄膜電晶體，其中該半導體層位於該可撓性基板與該第一閘極之間。
  4. 如申請專利範圍第1項所述的薄膜電晶體，其中該第一閘極位於該可撓性基板與該半導體層之間。
  5. 如申請專利範圍第1項所述的薄膜電晶體，其中該薄膜電晶體更包括一第二閘介電層，位於該第一閘極以及該第一閘介電層之間，且該第二閘介電層的氫原子濃度大於6.5×1020原子數/立方公分。
  6. 如申請專利範圍第1項所述的薄膜電晶體，其中該薄膜電晶體更包括一第二閘極，其中該半導體層位於該第一閘極與該該第二閘極之間。
  7. 如申請專利範圍第1項所述的薄膜電晶體，其中該第一閘介電層的材質包括矽的氧化物、矽的氮化物或上述之組合。
  8. 如申請專利範圍第1項所述的薄膜電晶體，其中該半導體層的材質包括多晶矽材料。
  9. 如申請專利範圍第1項所述的薄膜電晶體，更包括：分別耦接於該半導體層相對兩端的一源極以及一汲極。
  10. 一種薄膜電晶體的製造方法，包括：於一可撓性基板上形成一半導體層；於該半導體層上形成一第一閘介電層，該第一閘介電層與該半導體層接觸，且該第一閘介電層的氫原子濃度小於6.5×1020原子數/立方公分，但該第一閘介電層的氫原子濃度不包括5.2×1016~5.2×1018原子數/立方公分；以及於該第一閘介電層上形成對應於該半導體層的部份區域的一第一閘極。
  11. 如申請專利範圍第10項所述的薄膜電晶體的製造方法，更包括：於形成該第一閘極之前，於該第一閘介電層上形成第二閘介電層，其氫原子濃度大於6.5×1020原子數/立方公分，且該第一閘極形成於該第二閘介電層上。
  12. 如申請專利範圍第10項所述的薄膜電晶體的製造方法，更包括：於形成該半導體層之前，於該可撓性基板上形成一第二閘極，且該半導體層形成於該第二閘極上。
  13. 如申請專利範圍第10項所述的薄膜電晶體的製造方法，其中該第一閘介電層的形成方法包括電漿增強化學氣相沉積法，其惰性氣體流量與總製程氣體流量的比值為0.5至0.7。
  14. 如申請專利範圍第10項所述的薄膜電晶體的製造方法，其中該第一閘介電層的形成速率為2.5至3.5Å/sec。
  15. 如申請專利範圍第10項所述的薄膜電晶體的製造方法，更包括：形成分別耦接於該半導體層相對兩端的一源極以及一汲極。
  16. 一種薄膜電晶體的製造方法，包括：於一可撓性基板上形成一第一閘極；於該第一閘極上形成一第一閘介電層，且該第一閘介電層的氫原子濃度小於6.5×1020原子數/立方公分，但該第一閘介電層的氫原子濃度不包括5.2×1016~5.2×1018原子數/立方公分；以及於該第一閘介電層上形成一半導體層，其中與該第一閘介電層接觸，且該第一閘極對應於該半導體層的部份區域。
  17. 如申請專利範圍第16項所述的薄膜電晶體的製造方法，更包括：於形成該第一閘介電層之前，於該第一閘極上形成第二閘介電層，其氫原子濃度大於6.5×1020原子數/立方公分，且該第一閘介電層形成於該第二閘介電層上。
  18. 如申請專利範圍第16項所述的薄膜電晶體的製造方法，更包括：於該半導體層上形成一第二閘極。
  19. 如申請專利範圍第16項所述的薄膜電晶體的製造方法，其中該第一閘介電層的形成方法包括電漿輔助化學氣相沉積法，其惰性氣體流量與總製程氣體流量的比值為0.5至0.7。
  20. 如申請專利範圍第16項所述的薄膜電晶體的製造方法，其中該第一閘介電層的形成速率為2.5至3.5Å/sec。
  21. 如申請專利範圍第16項所述的薄膜電晶體的製造方法，更包括：形成分別耦接於該半導體層相對兩端的一源極以及一汲極。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101540342A (zh) * 2008-03-18 2009-09-23 株式会社半导体能源研究所 薄膜晶体管及显示装置
TW201220432A (en) * 2010-11-01 2012-05-16 Ind Tech Res Inst Active device and manufacturing method thereof
CN102790095A (zh) * 2011-05-19 2012-11-21 株式会社半导体能源研究所 制造半导体器件的方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1020920B1 (en) 1999-01-11 2010-06-02 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a driver TFT and a pixel TFT on a common substrate
US8441049B2 (en) * 2003-07-16 2013-05-14 Samsung Display Co., Ltd. Flat panel display device comprising polysilicon thin film transistor and method of manufacturing the same
JP3966274B2 (ja) * 2003-12-04 2007-08-29 トヨタ自動車株式会社 操舵制御装置
TWI281586B (en) 2005-09-13 2007-05-21 Ind Tech Res Inst Pixel array
KR101400699B1 (ko) * 2007-05-18 2014-05-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판 및 반도체 장치 및 그 제조 방법
US8390150B2 (en) * 2008-07-15 2013-03-05 Fisher-Rosemount Systems, Inc. Field device interface with network protection mechanism
WO2010042410A2 (en) * 2008-10-07 2010-04-15 Applied Materials, Inc. Apparatus for efficient removal of halogen residues from etched substrates
TWI343129B (en) 2008-11-24 2011-06-01 Ind Tech Res Inst Thin film transistor
CN101752424B (zh) 2008-12-17 2011-10-26 财团法人工业技术研究院 薄膜晶体管
CN101478005B (zh) * 2009-02-13 2010-06-09 北京大学深圳研究生院 一种金属氧化物薄膜晶体管及其制作方法
EP2517245B1 (en) 2009-12-25 2019-07-24 Semiconductor Energy Laboratory Co. Ltd. Semiconductor device
WO2011145484A1 (en) 2010-05-21 2011-11-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JPWO2012043338A1 (ja) 2010-09-28 2014-02-06 凸版印刷株式会社 薄膜トランジスタ及びその製造方法、薄膜トランジスタを備える画像表示装置
JP6204917B2 (ja) 2011-10-07 2017-09-27 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ アルゴンガス希釈によるシリコン含有層を堆積するための方法
KR102083380B1 (ko) * 2012-01-25 2020-03-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
JP6134230B2 (ja) 2012-08-31 2017-05-24 株式会社神戸製鋼所 薄膜トランジスタおよび表示装置
US8921209B2 (en) * 2012-09-12 2014-12-30 International Business Machines Corporation Defect free strained silicon on insulator (SSOI) substrates
TWI613709B (zh) 2013-02-20 2018-02-01 財團法人工業技術研究院 半導體元件結構及其製造方法與應用其之畫素結構
TWI555150B (zh) 2014-05-27 2016-10-21 財團法人工業技術研究院 電子元件及其製法
JP6337732B2 (ja) 2014-10-09 2018-06-06 富士通株式会社 電源回路
US10083989B2 (en) 2015-12-10 2018-09-25 Industrial Technology Research Institute Semiconductor device
TWI578505B (zh) 2015-12-10 2017-04-11 財團法人工業技術研究院 半導體元件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101540342A (zh) * 2008-03-18 2009-09-23 株式会社半导体能源研究所 薄膜晶体管及显示装置
TW201220432A (en) * 2010-11-01 2012-05-16 Ind Tech Res Inst Active device and manufacturing method thereof
CN102790095A (zh) * 2011-05-19 2012-11-21 株式会社半导体能源研究所 制造半导体器件的方法

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