TWI646522B - Display system and application processor for portable device - Google Patents
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
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Abstract
一種在顯示面板上顯示影像資料的攜帶型裝置的顯示系統的應用處理器,所述應用處理器包含:控制器,經組態以獲得自顯示驅動器積體電路接收的資料傳輸時序控制信號的頻率,且基於所獲得的所述頻率而產生用於調整與所述顯示驅動器積體電路的操作時鐘信號相關的頻率的頻率控制信號;傳輸器,經組態以將所產生的所述頻率控制信號傳輸至所述顯示驅動器積體電路;以及頻率計算電路,包括:偵測器,經組態以自所述顯示驅動器積體電路接收所述資料傳輸時序控制信號;以及頻率計算器,經組態以計算所接收的所述資料傳輸時序控制信號的所述頻率。 An application processor of a display system of a portable device for displaying image data on a display panel, the application processor comprising: a controller configured to obtain a frequency of a data transmission timing control signal received from a display driver integrated circuit Generating a frequency control signal for adjusting a frequency associated with an operational clock signal of the display driver integrated circuit based on the obtained frequency; a transmitter configured to generate the frequency control signal Transmitting to the display driver integrated circuit; and frequency calculation circuit, comprising: a detector configured to receive the data transmission timing control signal from the display driver integrated circuit; and a frequency calculator configured The frequency of the received data transmission timing control signal is calculated.
Description
本申請案主張2013年7月11日申請的美國臨時專利申請案第61/845,183號的權益,主張2013年10月8日在韓國智慧財產局(KIPO)申請的韓國專利申請案第10-2013-0120011號的優先權,且主張2014年6月30日在韓國智慧財產局(KIPO)申請的韓國專利申請案第10-2014-0080512號的優先權,所述專利申請案中的每一者的全部內容特此以引用的方式併入本文中。 This application claims the benefit of U.S. Provisional Patent Application No. 61/845,183, filed on Jul. 11, 2013, and claims the Korean Patent Application No. 10-2013, filed on the Korean Intellectual Property Office (KIPO) on October 8, 2013. Priority of -0120011, and the priority of Korean Patent Application No. 10-2014-0080512, filed on June 30, 2014 in the Korean Intellectual Property Office (KIPO), each of which is incorporated herein by reference. The entire contents of this disclosure are hereby incorporated by reference.
根據例示性實施例的設備及方法是關於主機,且更特定言之,是關於用於基於自顯示驅動器積體電路(integrated circuit,IC)輸出的資料傳輸時序控制信號而控制顯示驅動器IC的操作時鐘信號的頻率的主機、包含所述主機的系統以及操作所述系統的方法。 An apparatus and method according to an exemplary embodiment is related to a host, and more particularly, to an operation of controlling a display driver IC based on a data transfer timing control signal output from a display driver integrated circuit (IC). A host of frequencies of clock signals, a system including the host, and a method of operating the system.
包含液晶顯示器(liquid crystal display,LCD)面板的行動裝置在各種模式(包含視訊模式或命令模式)中驅動LCD面板。行動產業處理器介面顯示器串列介面(Mobile Industry Processor Interface Display Serial Interface,MIPI® DSI)是攜帶型電子裝置的先前技術的顯示標準。 A mobile device including a liquid crystal display (LCD) panel drives the LCD panel in various modes, including video mode or command mode. The Mobile Industry Processor Interface Display Serial Interface (MIPI® DSI) is a prior art display standard for portable electronic devices.
MIPI支援兩種顯示模式,即,視訊模式以及命令模式。在命令模式中,藉由撕裂效應(tearing effect,TE)信號而控制自主機的畫面資料傳輸的開始。在視訊模式中,即時地將畫面資料自主機傳輸至面板。 MIPI supports two display modes, namely, video mode and command mode. In the command mode, the start of picture data transmission from the host is controlled by a tearing effect (TE) signal. In the video mode, the picture data is transferred from the host to the panel in real time.
當在顯示面板上顯示靜態影像時,顯示驅動器IC週期性地自顯示驅動器IC中所包含的畫面緩衝器讀取靜態影像,且在顯示面板上顯示靜態影像,此稱為面板自行再新(self-refresh)。此時,顯示驅動器IC使用自電阻器-電容器(resistor-capacitor,RC)振盪器輸出的時鐘信號而執行面板自行再新。因為RC振盪器對溫度變化敏感,所以時鐘信號的頻率可能出現偏差。此偏差導致電磁干擾(electromagnetic interference,EMI),所述EMI會干擾其他裝置(諸如,觸碰螢幕、觸控筆等)的操作頻率。 When a still image is displayed on the display panel, the display driver IC periodically reads the still image from the picture buffer included in the display driver IC, and displays the still image on the display panel, which is called the panel self-renew (self -refresh). At this time, the display driver IC performs the panel self-renew using the clock signal output from the resistor-capacitor (RC) oscillator. Because the RC oscillator is sensitive to temperature changes, the frequency of the clock signal may vary. This deviation causes electromagnetic interference (EMI), which can interfere with the operating frequency of other devices such as touch screens, styluses, and the like.
當顯示驅動器IC在命令模式中將TE信號傳輸至主機時,主機基於TE信號而將畫面資料傳輸至顯示驅動器IC。TE信號用於防止撕裂或螢幕撕裂。撕裂或螢幕撕裂是在對應於至少兩個不同畫面的影像資料同時顯示於顯示面板上的單個螢幕上時顯 現的視覺假影。 When the display driver IC transmits the TE signal to the host in the command mode, the host transmits the picture data to the display driver IC based on the TE signal. The TE signal is used to prevent tearing or tearing of the screen. Tearing or screen tearing is displayed when image data corresponding to at least two different images are simultaneously displayed on a single screen on the display panel The current visual artifacts.
一或多個例示性實施例可克服以上缺點及上文未描述的其他缺點。然而,應理解,一或多個例示性實施例並非為克服上文所述的缺點所需,且可能不克服上文所述的問題中的任一者。 One or more exemplary embodiments may overcome the above disadvantages and other disadvantages not described above. However, it should be understood that one or more exemplary embodiments are not required to overcome the disadvantages described above, and may not overcome any of the problems described.
根據例示性實施例的態樣,提供一種用於在顯示面板上驅動影像資料的顯示的顯示驅動器積體電路(display driver integrated circuit,DDI),所述DDI包含:控制信號產生器,經組態以基於操作時鐘信號而產生控制信號,且將所產生的所述控制信號傳輸至外部裝置;接收器,經組態以回應於所傳輸的所述控制信號而自所述外部裝置接收第一頻率控制信號;以及控制器,經組態以基於所接收的所述第一頻率控制信號而輸出第二頻率控制信號以調整與所述操作時鐘信號相關的頻率。 According to an aspect of the exemplary embodiments, a display driver integrated circuit (DDI) for driving display of image data on a display panel is provided, the DDI comprising: a control signal generator configured Generating a control signal based on the operational clock signal and transmitting the generated control signal to an external device; the receiver being configured to receive the first frequency from the external device in response to the transmitted control signal a control signal; and a controller configured to output a second frequency control signal based on the received first frequency control signal to adjust a frequency associated with the operational clock signal.
所述控制信號可為撕裂效應信號,且所述接收器可經組態以回應於所傳輸的所述控制信號而自所述外部裝置接收所述影像資料。 The control signal can be a tear effect signal, and the receiver can be configured to receive the image data from the external device in response to the transmitted control signal.
所述DDI可更包含:振盪器,經組態以將所述操作時鐘信號輸出至所述控制信號產生器,其中所述控制器可經組態以將所述第二頻率控制信號輸出至所述振盪器以調整所述操作時鐘信號的頻率。 The DDI can further include an oscillator configured to output the operational clock signal to the control signal generator, wherein the controller can be configured to output the second frequency control signal to the The oscillator is tuned to adjust the frequency of the operational clock signal.
所述控制器可經組態以將所述第二頻率控制信號輸出至 所述控制信號產生器;且所述控制信號產生器可經組態以根據所輸出的所述第二頻率控制信號以及所述操作時鐘信號而調整所產生的所述控制信號的頻率。 The controller can be configured to output the second frequency control signal to The control signal generator; and the control signal generator is configurable to adjust a frequency of the generated control signal based on the outputted second frequency control signal and the operational clock signal.
所述控制信號產生器可經組態以根據所述操作時鐘信號的有偏差的頻率與所產生的所述控制信號的所述頻率之間的比率而調整所產生的所述控制信號的所述頻率。 The control signal generator can be configured to adjust the resulting of the generated control signal based on a ratio between a biased frequency of the operational clock signal and the frequency of the generated control signal frequency.
所述接收器可為行動產業處理器介面(MIPI)接收器。 The receiver can be a Mobile Industry Processor Interface (MIPI) receiver.
所述DDI可更包含:影像處理器,經組態以將所述影像資料輸出至所述顯示面板,其中所述處理器可經組態以回應於所傳輸的所述控制信號而自所述外部裝置接收所述影像資料。 The DDI can further include: an image processor configured to output the image material to the display panel, wherein the processor can be configured to respond to the transmitted control signal from the The external device receives the image data.
所述DDI可更包含:畫面緩衝器,經組態以緩衝所述影像資料,其中所述控制器可經組態以控制將所接收的所述影像資料寫入至所述畫面緩衝器,且根據所述操作時鐘信號而控制自所述畫面緩衝器讀取所接收的所述影像資料以輸出至所述顯示面板。 The DDI can further include: a picture buffer configured to buffer the image material, wherein the controller can be configured to control writing the received image data to the picture buffer, and And controlling the read image data from the picture buffer to be output to the display panel according to the operation clock signal.
根據另一例示性實施例的態樣,提供一種在顯示面板上顯示影像資料的攜帶型裝置的顯示系統的應用處理器,所述應用處理器包含:控制器,經組態以獲得自顯示驅動器積體電路(DDI)接收的資料傳輸時序控制信號的頻率,且基於所獲得的所述頻率而產生用於調整與所述DDI的操作時鐘信號相關的頻率的頻率控制信號;傳輸器,經組態以將所產生的所述頻率控制信號傳輸至所述DDI;以及頻率計算電路,包含:偵測器,經組態以自所述 DDI接收所述資料傳輸時序控制信號;以及頻率計算器,經組態以計算所接收的所述資料傳輸時序控制信號的頻率。 In accordance with an aspect of another exemplary embodiment, an application processor of a display system of a portable device that displays image data on a display panel is provided, the application processor including: a controller configured to obtain a self-display driver a data received by the integrated circuit (DDI) transmits a frequency of the timing control signal, and based on the obtained frequency, generates a frequency control signal for adjusting a frequency associated with the operational clock signal of the DDI; Transmitting the generated frequency control signal to the DDI; and frequency calculation circuitry, comprising: a detector configured to self-described The DDI receives the data transmission timing control signal; and a frequency calculator configured to calculate a frequency of the received data transmission timing control signal.
所述頻率計算器可經組態以將所計算的所述頻率輸出至所述控制器。 The frequency calculator can be configured to output the calculated frequency to the controller.
所述頻率計算電路可更包含:頻率比較器,經組態以判定所計算的所述頻率是否處於所述DDI的預定操作頻率範圍內,根據所述判定而產生控制信號,且將所產生的所述控制信號輸出至所述控制器。 The frequency calculation circuit may further include: a frequency comparator configured to determine whether the calculated frequency is within a predetermined operating frequency range of the DDI, generate a control signal according to the determination, and generate the generated signal The control signal is output to the controller.
所述頻率比較器可回應於所計算的所述頻率低於所述預定操作頻率範圍而產生第一控制信號,回應於所計算的所述頻率處於所述預定操作頻率範圍內而產生第二控制信號,且回應於所計算的所述頻率高於所述預定操作頻率範圍而產生第三控制信號,而作為所述控制信號。 The frequency comparator may generate a first control signal in response to the calculated frequency being lower than the predetermined operating frequency range, and generate a second control in response to the calculated frequency being within the predetermined operating frequency range And generating a third control signal as the control signal in response to the calculated frequency being higher than the predetermined operating frequency range.
所述頻率計算電路可更包含:頻率計數器,經組態以基於參考時鐘信號而判定所接收的所述資料傳輸時序控制信號的週期的計數值,其中所述頻率計算器可經組態以基於所判定的所述計數值而計算所接收的所述資料傳輸時序控制信號的所述頻率。 The frequency calculation circuit can further include: a frequency counter configured to determine a count value of a period of the received data transmission timing control signal based on the reference clock signal, wherein the frequency calculator can be configured to be based on The frequency of the received data transmission timing control signal is calculated by the determined count value.
所述偵測器可包含:邊緣偵測器,經組態以基於所接收的所述資料傳輸時序控制信號的上升邊緣或下降邊緣而偵測所接收的所述資料傳輸時序控制信號的所述週期。 The detector can include an edge detector configured to detect the received data transmission timing control signal based on the received rising edge or falling edge of the data transmission timing control signal cycle.
所述頻率計算電路可更包含:分頻器,經組態以按照預定因數來對所述參考時鐘信號進行分頻,其中所述頻率計數器可 經組態以基於所分頻的所述參考時鐘信號而判定所述計數值。 The frequency calculation circuit can further include: a frequency divider configured to divide the reference clock signal by a predetermined factor, wherein the frequency counter can The configuration is configured to determine the count value based on the divided reference clock signal.
根據另一例示性實施例的態樣,提供一種控制顯示器的操作時鐘信號的頻率的方法,所述方法包含:藉由主機而自顯示驅動器積體電路(DDI)接收信號;基於參考時鐘信號而計算所接收的所述信號的頻率;基於所計算的所述頻率而產生用於調整與所述DDI的操作時鐘信號相關的頻率的頻率控制信號;以及將所產生的所述頻率控制信號傳輸至所述DDI。 In accordance with an aspect of another exemplary embodiment, a method of controlling a frequency of an operational clock signal of a display, the method comprising: receiving a signal from a display driver integrated circuit (DDI) by a host; based on a reference clock signal Calculating a frequency of the received signal; generating a frequency control signal for adjusting a frequency associated with an operational clock signal of the DDI based on the calculated frequency; and transmitting the generated frequency control signal to The DDI.
所述產生所述頻率控制信號可包含回應於所計算的所述頻率處於所述DDI的預定操作頻率範圍外而產生所述頻率控制信號。 The generating the frequency control signal can include generating the frequency control signal in response to the calculated frequency being outside a predetermined operating frequency range of the DDI.
所述方法可更包含:回應於所接收的所述信號而將影像資料傳輸至所述DDI,其中所接收的所述信號為撕裂效應信號。 The method can further include transmitting image data to the DDI in response to the received signal, wherein the received signal is a tear effect signal.
所述計算所述頻率可包含:基於所述參考時鐘信號而判定所接收的所述信號的週期的計數值;以及基於所判定的所述計數值而計算所接收的所述信號的所述頻率。 The calculating the frequency may include determining a count value of a period of the received signal based on the reference clock signal; and calculating the frequency of the received signal based on the determined count value .
根據另一例示性實施例的態樣,提供一種控制顯示器的操作時鐘信號的頻率的方法,所述方法包含:藉由DDI基於操作時鐘信號而產生控制信號;將所產生的所述控制信號傳輸至主機;回應於所傳輸的所述控制信號而自所述主機接收第一頻率控制信號;以及基於所接收的所述第一頻率控制信號而調整所述控制信號的頻率。 According to another aspect of an exemplary embodiment, there is provided a method of controlling a frequency of an operation clock signal of a display, the method comprising: generating a control signal based on an operation clock signal by DDI; transmitting the generated control signal Receiving a first frequency control signal from the host in response to the transmitted control signal; and adjusting a frequency of the control signal based on the received first frequency control signal.
所述調整所述控制信號的所述頻率可包含藉由調整所述 操作時鐘信號的頻率而調整所述控制信號的所述頻率。 The adjusting the frequency of the control signal may include adjusting the The frequency of the control signal is adjusted by operating the frequency of the clock signal.
所述調整所述控制信號的所述頻率可包含根據所述操作時鐘信號的有偏差的頻率與所述控制信號的所述頻率之間的比率而調整所述控制信號的所述頻率。 The adjusting the frequency of the control signal can include adjusting the frequency of the control signal based on a ratio between a frequency of the deviation of the operational clock signal and the frequency of the control signal.
所述控制信號可為撕裂效應信號。 The control signal can be a tear effect signal.
根據另一例示性實施例的態樣,提供一種顯示影像資料的顯示系統,所述顯示系統包含:應用處理器,包含:第一控制器,經組態以自頻率計算電路獲得由顯示驅動器積體電路(DDI)提供的信號的頻率,且基於所獲得的所述頻率而產生用於調整與所述DDI的操作時鐘信號相關的頻率的第一頻率控制信號,以及傳輸器,經組態以將所產生的所述第一頻率控制信號傳輸至所述DDI;所述頻率計算電路,經組態以自所述DDI接收所述信號,基於參考時鐘信號而計算所接收的所述信號的所述頻率,且將所計算的所述頻率提供至所述第一控制器;以及所述DDI,經組態以驅動顯示面板上的所述影像資料的顯示,所述DDI包含:控制信號產生器,經組態以基於所述操作時鐘信號而產生所述信號,且將所產生的所述信號提供至所述應用處理器以及所述頻率計算電路;接收器,經組態以回應於所提供的所述信號而自所述應用處理器接收所述第一頻率控制信號;以及第二控制器,經組態以基於所接收的所述第一頻率控制信號而輸出第二頻率控制信號以調整與所述操作時鐘信號相關的所述頻率。 In accordance with an aspect of another exemplary embodiment, a display system for displaying image data is provided, the display system comprising: an application processor, comprising: a first controller configured to obtain a display driver product from a frequency calculation circuit a frequency of a signal provided by a body circuit (DDI), and based on the obtained frequency, a first frequency control signal for adjusting a frequency associated with an operational clock signal of the DDI, and a transmitter configured to Transmitting the generated first frequency control signal to the DDI; the frequency calculation circuit configured to receive the signal from the DDI, calculate a received signal based on a reference clock signal a frequency, and providing the calculated frequency to the first controller; and the DDI configured to drive display of the image material on a display panel, the DDI comprising: a control signal generator Configuring to generate the signal based on the operational clock signal and to provide the generated signal to the application processor and the frequency calculation circuit; a receiver, Configuring to receive the first frequency control signal from the application processor in response to the provided signal; and a second controller configured to output based on the received first frequency control signal A second frequency control signal is to adjust the frequency associated with the operational clock signal.
所述顯示系統可為攜帶型裝置,且所述應用處理器可為主機。 The display system can be a portable device, and the application processor can be a host.
所述顯示系統可更包含所述顯示面板,所述顯示面板包含經組態以自觸控筆接收輸入的觸碰螢幕。 The display system can further include the display panel, the display panel including a touch screen configured to receive input from a stylus.
所述信號可為撕裂效應信號。 The signal can be a tear effect signal.
所述DDI可包含:振盪器,經組態以輸出所述操作時鐘信號,其中所述DDI可經組態以根據所述第二頻率控制信號而調整所述操作時鐘信號的頻率。 The DDI can include an oscillator configured to output the operational clock signal, wherein the DDI can be configured to adjust a frequency of the operational clock signal in accordance with the second frequency control signal.
所述DDI可經組態以根據所述第二頻率控制信號以及所述操作時鐘信號而調整所產生的所述信號的頻率。 The DDI can be configured to adjust the frequency of the generated signal based on the second frequency control signal and the operational clock signal.
所述DDI可經組態以根據所述操作時鐘信號的有偏差的頻率與所產生的所述信號的所述頻率之間的比率而調整所產生的所述信號的所述頻率。 The DDI can be configured to adjust the frequency of the generated signal based on a ratio between a biased frequency of the operational clock signal and the frequency of the generated signal.
根據另一例示性實施例的態樣,提供一種在顯示面板上顯示影像資料的攜帶型裝置的顯示系統的應用處理器,所述應用處理器包含:控制器,經組態以獲得自顯示驅動器積體電路(DDI)接收的信號的頻率,且基於所獲得的所述頻率而產生用於調整與所述DDI的操作時鐘信號相關的頻率的頻率控制信號;以及傳輸器,經組態以將所產生的所述頻率控制信號傳輸至所述DDI。 In accordance with an aspect of another exemplary embodiment, an application processor of a display system of a portable device that displays image data on a display panel is provided, the application processor including: a controller configured to obtain a self-display driver a frequency of a signal received by the integrated circuit (DDI), and based on the obtained frequency, generating a frequency control signal for adjusting a frequency associated with an operational clock signal of the DDI; and a transmitter configured to The generated frequency control signal is transmitted to the DDI.
所接收的所述信號可為撕裂效應信號,且所述控制器可經組態以控制所述傳輸器回應於所接收的所述撕裂效應信號而將所述影像資料傳輸至所述DDI。 The received signal can be a tearing effect signal, and the controller can be configured to control the transmitter to transmit the image data to the DDI in response to the received tearing effect signal .
所述控制器可經組態以回應於所獲得的所述頻率處於所述DDI的預定操作頻率範圍外而產生所述頻率控制信號。 The controller can be configured to generate the frequency control signal in response to the obtained frequency being outside a predetermined operating frequency range of the DDI.
所述應用處理器可更包含:頻率計算電路,經組態以自所述DDI接收所述信號,且基於參考時鐘信號而計算所接收的所述信號的所述頻率,其中所述控制器可經組態以基於所計算的所述頻率而產生所述頻率控制信號。 The application processor can further include: a frequency calculation circuit configured to receive the signal from the DDI and calculate the frequency of the received signal based on a reference clock signal, wherein the controller can The frequency control signal is configured to generate based on the calculated frequency.
所述頻率計算電路可包含:頻率計數器,經組態以基於所述參考時鐘信號而判定所接收的所述信號的週期的計數值;以及頻率計算器,經組態以基於所判定的所述計數值而計算所接收的所述信號的所述頻率。 The frequency calculation circuit can include a frequency counter configured to determine a count value of a period of the received signal based on the reference clock signal, and a frequency calculator configured to be based on the determined The frequency of the received signal is calculated by counting the value.
所述頻率計算電路可更包含:邊緣偵測器,經組態以基於所接收的所述信號的上升邊緣或下降邊緣而偵測所接收的所述信號的所述週期。 The frequency calculation circuit can further include an edge detector configured to detect the period of the received signal based on the received rising edge or falling edge of the signal.
所述頻率計算電路可更包含:分頻器,經組態以按照預定因數來對所述參考時鐘信號進行分頻;且所述頻率計數器可經組態以基於所分頻的所述參考時鐘信號來判定所述計數值。 The frequency calculation circuit can further include: a frequency divider configured to divide the reference clock signal by a predetermined factor; and the frequency counter can be configured to be based on the divided reference clock A signal is used to determine the count value.
所述頻率計算電路可更包含:頻率比較器,經組態以判定所計算的所述頻率是否處於所述DDI的預定操作頻率範圍內,且根據所述判定而將控制信號輸出至所述控制器;且所述控制器可根據所輸出的所述控制信號而產生所述頻率控制信號。 The frequency calculation circuit may further include: a frequency comparator configured to determine whether the calculated frequency is within a predetermined operating frequency range of the DDI, and outputting a control signal to the control according to the determining And the controller may generate the frequency control signal according to the outputted control signal.
所述頻率比較器可回應於所計算的所述頻率小於所述預定操作頻率範圍而輸出第一中斷信號,且回應於所計算的所述頻 率大於所述預定操作頻率範圍而輸出第三中斷信號,而作為所述控制信號,且所述控制器可產生所述頻率控制信號以回應於所輸出的所述第一中斷信號或所輸出的所述第三中斷信號而調整所述頻率。 The frequency comparator may output a first interrupt signal in response to the calculated frequency being less than the predetermined operating frequency range, and responsive to the calculated frequency The rate is greater than the predetermined operating frequency range and outputs a third interrupt signal as the control signal, and the controller may generate the frequency control signal in response to the outputted first interrupt signal or the output The third interrupt signal adjusts the frequency.
所述控制器可為CPU。 The controller can be a CPU.
所述控制器可為影像處理電路。 The controller can be an image processing circuit.
10‧‧‧介面 10‧‧‧ interface
11‧‧‧介面 11‧‧‧ interface
11a‧‧‧專屬傳輸線 11a‧‧‧ exclusive transmission line
12‧‧‧介面 12‧‧‧ interface
100、100A、100B、100C‧‧‧系統 100, 100A, 100B, 100C‧‧‧ systems
200、200A、200B‧‧‧主機 200, 200A, 200B‧‧‧ host
201‧‧‧匯流排 201‧‧‧ busbar
210‧‧‧中央處理單元 210‧‧‧Central Processing Unit
220‧‧‧唯讀記憶體 220‧‧‧Read-only memory
230‧‧‧記憶體控制器 230‧‧‧ memory controller
240‧‧‧相機介面 240‧‧‧ camera interface
250、250A、250B、250C、250D、250E、250F‧‧‧頻率計算電路 250, 250A, 250B, 250C, 250D, 250E, 250F‧‧‧ frequency calculation circuit
251‧‧‧邊緣偵測器 251‧‧‧Edge detector
252‧‧‧邊緣偵測電路 252‧‧‧Edge detection circuit
252-1‧‧‧及閘 252-1‧‧‧ and gate
252-2‧‧‧反相器 252-2‧‧‧Inverter
252-3‧‧‧邊緣偵測器 252-3‧‧‧Edge detector
253‧‧‧分頻器 253‧‧‧divider
255‧‧‧頻率計數器 255‧‧‧frequency counter
256‧‧‧頻率計算器 256‧‧‧frequency calculator
257‧‧‧頻率比較電路 257‧‧‧ frequency comparison circuit
260‧‧‧影像處理電路 260‧‧‧Image Processing Circuit
270、270A‧‧‧傳輸介面 270, 270A‧‧‧ transmission interface
290‧‧‧介面 290‧‧" interface
300、300A、300B‧‧‧顯示驅動器積體電路 300, 300A, 300B‧‧‧ display driver integrated circuit
310、310A‧‧‧接收介面 310, 310A‧‧‧ receiving interface
320、320A、320B‧‧‧控制電路 320, 320A, 320B‧‧‧ control circuit
325‧‧‧畫面緩衝器 325‧‧‧ Picture buffer
330‧‧‧振盪器 330‧‧‧Oscillator
340、340A‧‧‧時序控制器 340, 340A‧‧‧ timing controller
342‧‧‧時序控制信號產生器 342‧‧‧Sequence Control Signal Generator
344‧‧‧影像處理電路 344‧‧‧Image Processing Circuit
350‧‧‧驅動電路區塊 350‧‧‧Drive Circuit Blocks
400‧‧‧顯示面板 400‧‧‧ display panel
500‧‧‧外部記憶體 500‧‧‧External memory
600‧‧‧相機 600‧‧‧ camera
700‧‧‧頻率計算積體電路 700‧‧‧Frequency calculation integrated circuit
CLK‧‧‧專屬時鐘信號 CLK‧‧‧ exclusive clock signal
CNT‧‧‧計數值 CNT‧‧‧ count value
DET‧‧‧偵測信號 DET‧‧‧Detection signal
DTE‧‧‧運算結果 DTE‧‧‧ operation results
fcnt、fcnt1、fcnt2、fcnt3‧‧‧頻率 Fcnt, fcnt1, fcnt2, fcnt3‧‧‧ frequency
fref、frefd‧‧‧參考時鐘信號 Fref, frefd‧‧‧ reference clock signal
FTF、FTFa‧‧‧第二週期 FTF, FTFa‧‧‧ second cycle
FW‧‧‧頻率窗 FW‧‧‧ frequency window
HCLK‧‧‧時鐘信號 HCLK‧‧‧ clock signal
HIW、HIWa‧‧‧高週期寬度 HIW, HIWa‧‧‧ high cycle width
ifc‧‧‧內部時鐘信號 Ifc‧‧‧ internal clock signal
INT‧‧‧中斷 INT‧‧‧ interrupt
LIW、LIWa‧‧‧低週期寬度 LIW, LIWa‧‧‧Low cycle width
RTR、RTRa‧‧‧第一週期 RTR, RTRa‧‧‧ first cycle
S110、S120、S130、S140‧‧‧操作 S110, S120, S130, S140‧‧‧ operations
TE‧‧‧資料傳輸時序控制信號 TE‧‧‧ data transmission timing control signal
X-OSC‧‧‧晶體振盪器 X-OSC‧‧‧ crystal oscillator
藉由參看附圖詳細描述本發明概念的例示性實施例,本發明概念的以上及其他特徵及優點將變得更顯而易見。 The above and other features and advantages of the present invention will become more apparent from the detailed description of the exemplary embodiments.
圖1為根據例示性實施例的系統的方塊圖。 FIG. 1 is a block diagram of a system in accordance with an exemplary embodiment.
圖2為根據例示性實施例的頻率計算電路的方塊圖。 2 is a block diagram of a frequency calculation circuit in accordance with an exemplary embodiment.
圖3為根據另一例示性實施例的頻率計算電路的方塊圖。 FIG. 3 is a block diagram of a frequency calculation circuit in accordance with another exemplary embodiment.
圖4為根據例示性實施例的頻率計算電路的操作的時序圖。 4 is a timing diagram of the operation of a frequency calculation circuit, in accordance with an exemplary embodiment.
圖5A及圖5B為根據另一例示性實施例的頻率計算電路的操作的時序圖。 5A and 5B are timing diagrams of operations of a frequency calculation circuit, in accordance with another exemplary embodiment.
圖6為根據又一例示性實施例的頻率計算電路的方塊圖。 FIG. 6 is a block diagram of a frequency calculation circuit in accordance with still another exemplary embodiment.
圖7為圖6所說明的頻率計算電路的操作的時序圖。 Figure 7 is a timing diagram of the operation of the frequency calculation circuit illustrated in Figure 6.
圖8為根據又一例示性實施例的頻率計算電路的方塊圖。 FIG. 8 is a block diagram of a frequency calculation circuit in accordance with still another exemplary embodiment.
圖9為根據另一例示性實施例的頻率計算電路的方塊圖。 FIG. 9 is a block diagram of a frequency calculation circuit in accordance with another exemplary embodiment.
圖10為圖9所說明的頻率計算電路的操作的時序圖。 FIG. 10 is a timing chart showing the operation of the frequency calculation circuit illustrated in FIG.
圖11為根據又一例示性實施例的頻率計算電路的方塊圖。 11 is a block diagram of a frequency calculation circuit in accordance with yet another exemplary embodiment.
圖12為根據例示性實施例的對系統進行操作的方法的流程圖。 12 is a flow chart of a method of operating a system, in accordance with an illustrative embodiment.
圖13為根據另一例示性實施例的系統的方塊圖。 FIG. 13 is a block diagram of a system in accordance with another exemplary embodiment.
圖14為根據又一例示性實施例的系統的方塊圖。 Figure 14 is a block diagram of a system in accordance with yet another exemplary embodiment.
圖15為根據又一例示性實施例的系統的方塊圖。 Figure 15 is a block diagram of a system in accordance with yet another exemplary embodiment.
將在下文參看附圖來更全面地描述例示性實施例。然而,例示性實施例可按照許多不同形式來體現且不應解釋為限於本文所闡述的例示性實施例。實情為,提供此等例示性實施例,以使得本揭露將為全面且完整的,且將向熟習此項技術者完全傳達本發明概念的範疇。在諸圖中,為了清楚起見,可能誇示了層以及區域的大小以及相對大小。相似參考數字在全文中表示相似元件。 The illustrative embodiments are described more fully hereinafter with reference to the drawings. However, the illustrative embodiments may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these illustrative embodiments are provided so that this disclosure will be thorough and complete, and the scope of the inventive concept will be fully conveyed by those skilled in the art. In the figures, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals indicate like elements throughout.
應理解,當一元件被稱為「連接至」或「耦接至」另一元件時,所述元件可直接連接至或耦接至所述另一元件,或可存在介入元件。相比而言,當一元件被稱為「直接連接至」或「直接耦接至」另一元件時,不存在介入元件。如本文中所使用,術語「及/或」包含相關聯的所列出項目中的一或多者的任何以及所有組合且可縮寫為「/」。 It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element or the intervening element can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, the intervening element is absent. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items and can be abbreviated as "/".
應理解,儘管本文中可使用術語「第一」、「第二」等來描述各種元件,但此等元件不應受此等術語限制。此等術語僅用 於區分一個元件與另一元件。舉例而言,第一信號可稱為第二信號,且類似地,第二信號可稱為第一信號,而不偏離本揭露的教示。 It will be understood that, although the terms "first", "second", and the like may be used herein to describe various elements, such elements are not limited by the terms. These terms are used only To distinguish one component from another. For example, a first signal could be referred to as a second signal, and similarly, a second signal could be referred to as a first signal without departing from the teachings of the present disclosure.
本文中所使用的術語是出於描述例示性實施例的目的,且不意欲限制本發明概念。如本文中所使用,單數形式「一個」以及「所述」意欲亦包含複數形式,除非上下文另有清楚指示。應進一步理解,術語「包括」或「包含」在用於本說明書中時指定所敍述的特徵、區域、整體、步驟、操作、元件及/或組件的存在,但不排除一或多個其他特徵、區域、整體、步驟、操作、元件、組件及/或其群組的存在或添加。 The terminology used herein is for the purpose of describing the exemplary embodiments and is not intended to limit the inventive concept. As used herein, the singular and " It is to be understood that the terms "comprises" or "comprises" or "an" The presence or addition of, regions, integers, steps, operations, components, components, and/or groups thereof.
除非另有定義,否則本文中所使用的所有術語(包含技術以及科學術語)具有與一般熟習例示性實施例所屬技術者通常所理解者相同的含義。應進一步理解,術語(諸如,常用字典中所定義的術語)應被解釋為具有與其在相關技術及/或本申請案的背景中的含義一致的含義,且不應以理想化或過度正式的意義來解釋,除非本文中明確地如此定義。 All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the related art and/or the application, and should not be idealized or overly formal. Meaning is explained unless it is explicitly defined as such.
圖1為根據例示性實施例的系統100的方塊圖。參看圖1,系統100包含主機200、顯示驅動器IC(DDI)300、顯示面板400、外部記憶體500以及相機600。 FIG. 1 is a block diagram of a system 100 in accordance with an illustrative embodiment. Referring to FIG. 1, system 100 includes a host 200, a display driver IC (DDI) 300, a display panel 400, an external memory 500, and a camera 600.
系統100可實施為蜂巢式電話、智慧型電話、平板型裝置、個人電腦(PC)、攜帶型裝置、多媒體播放器、行動網際網絡裝置(mobile internet device,MID)、物聯網(Internet of things,IoT) 裝置、萬聯網(Internet of everything,IoE)裝置、可穿戴電腦、智慧型裝置等。 The system 100 can be implemented as a cellular phone, a smart phone, a tablet device, a personal computer (PC), a portable device, a multimedia player, a mobile internet device (MID), and an Internet of Things (Internet of Things, IoT) Devices, Internet of Things (IoE) devices, wearable computers, smart devices, and the like.
舉例而言,當系統100支援行動產業處理器介面(MIPI®)時,系統100亦可支援面板自行再新(PSR)。PSR為在顯示面板400上週期性地顯示DDI 300的畫面緩衝器325中所儲存的靜態影像資料的操作。 For example, when the system 100 supports the Mobile Industry Processor Interface (MIPI®), the System 100 can also support Panel Renewal (PSR). The PSR is an operation of periodically displaying still image data stored in the picture buffer 325 of the DDI 300 on the display panel 400.
在一或多個例示性實施例中,系統100可支援MIPI命令模式及/或MIPI視訊模式(其支援PSR)。然而,應理解一或多個其他例示性實施例不限於此。舉例而言,根據另一例示性實施例,系統100可包含支援嵌入式顯示埠(embedded DisplayPort,eDP)標準的介面。 In one or more exemplary embodiments, system 100 can support MIPI command mode and/or MIPI video mode (which supports PSR). However, it should be understood that one or more other exemplary embodiments are not limited thereto. For example, in accordance with another exemplary embodiment, system 100 can include an interface that supports an embedded display port (eDP) standard.
主機200可自DDI 300接收資料傳輸時序控制信號TE,使用參考時鐘信號「fref」來計算資料傳輸時序控制信號TE的頻率,基於計算結果而產生用於調整DDI 300的操作時鐘信號的頻率的第一頻率控制信號,且將第一頻率控制信號輸出至DDI 300。 The host 200 can receive the data transmission timing control signal TE from the DDI 300, calculate the frequency of the data transmission timing control signal TE using the reference clock signal "fref", and generate a frequency for adjusting the frequency of the operation clock signal of the DDI 300 based on the calculation result. A frequency control signal and outputting the first frequency control signal to the DDI 300.
此外,每當將影像資料(例如,靜態影像資料或動態影像資料)傳輸至DDI 300,主機便可基於或使用傳輸時序控制信號TE而將影像資料傳輸至DDI 300。 In addition, whenever image data (eg, still image data or motion picture data) is transmitted to the DDI 300, the host can transmit the image data to the DDI 300 based on or using the transmission timing control signal TE.
換言之,傳輸時序控制信號TE控制自主機200至DDI 300的影像資料的傳輸時序。因此,資料傳輸時序控制信號TE可為用於MIPI中的撕裂效應(TE)信號。且,當主機200回應於自DDI 300輸出以防止TE的特定信號而將影像資料傳輸至DDI 300時, 可認為特定信號作為傳輸時序控制信號TE而操作,而無關於主機200與DDI 300之間的介面的類型。雖然在本例示性實施例中,主機200接收資料傳輸時序控制信號TE(諸如,撕裂效應TE信號),但應理解一或多個其他例示性實施例不限於此,且主機200可自DDI 300接收任何信號或控制信號,所接收的信號的頻率是基於DDI 300的操作時鐘信號。 In other words, the transmission timing control signal TE controls the transmission timing of the image data from the host 200 to the DDI 300. Therefore, the data transmission timing control signal TE can be a tear effect (TE) signal for use in the MIPI. And, when the host 200 transmits the image data to the DDI 300 in response to the output from the DDI 300 to prevent the specific signal of the TE, The particular signal can be considered to operate as the transmission timing control signal TE, regardless of the type of interface between the host 200 and the DDI 300. Although in the present exemplary embodiment, the host 200 receives the data transmission timing control signal TE (such as a tear effect TE signal), it should be understood that one or more other exemplary embodiments are not limited thereto, and the host 200 is self-DDI 300 receives any signal or control signal, the frequency of which is based on the operational clock signal of the DDI 300.
主機200可實施為積體電路(IC)、系統晶片(SoC)、處理器、應用處理器(application processor,AP)、行動AP等。主機200可包含中央處理單元(CPU)210、唯讀記憶體(ROM)220、記憶體控制器230、相機介面(interface,I/F)240、頻率計算電路250、影像處理電路260以及傳輸介面(transmit interface,TX I/F)270。 The host 200 can be implemented as an integrated circuit (IC), a system chip (SoC), a processor, an application processor (AP), a mobile AP, and the like. The host 200 can include a central processing unit (CPU) 210, a read only memory (ROM) 220, a memory controller 230, a camera interface (I/F) 240, a frequency calculation circuit 250, an image processing circuit 260, and a transmission interface. (transmit interface, TX I/F) 270.
CPU 210可經由匯流排201而控制元件220、230、240、250、260及270中的至少一者的操作。CPU 210可包含至少一個核心。CPU 210可在開機期間執行自外部記憶體500輸出的作業系統(operating system,OS)。根據OS的控制,CPU 210可產生用於調整DDI 300的操作時鐘信號的頻率的第一頻率控制信號,且可經由TX I/F 270而將第一頻率控制信號傳輸至DDI 300。 The CPU 210 can control the operation of at least one of the components 220, 230, 240, 250, 260, and 270 via the bus bar 201. The CPU 210 can include at least one core. The CPU 210 can execute an operating system (OS) output from the external memory 500 during power-on. According to the control of the OS, the CPU 210 may generate a first frequency control signal for adjusting the frequency of the operation clock signal of the DDI 300, and may transmit the first frequency control signal to the DDI 300 via the TX I/F 270.
換言之,當有必要或判定要調整DDI 300的操作時鐘信號的頻率時,主機200可將第一頻率控制信號傳輸至DDI 300。第一頻率控制信號可按照命令的形式來傳輸至DDI 300,且可經由傳輸影像資料的傳輸線而傳輸至DDI 300。 In other words, the host 200 can transmit the first frequency control signal to the DDI 300 when it is necessary or determined that the frequency of the operational clock signal of the DDI 300 is to be adjusted. The first frequency control signal can be transmitted to the DDI 300 in the form of a command and can be transmitted to the DDI 300 via a transmission line that transmits the image data.
ROM 220可儲存由CPU 210使用的程式碼及/或資料。 The ROM 220 can store code and/or data used by the CPU 210.
記憶體控制器230可將資料儲存於外部記憶體500中,且可自外部記憶體500讀取資料。舉例而言,記憶體控制器230可為動態隨機存取記憶體(DRAM)控制器以及快閃式記憶體控制器的集合。因此,外部記憶體500可為DRAM及快閃記憶體的集合。 The memory controller 230 can store data in the external memory 500 and can read data from the external memory 500. For example, the memory controller 230 can be a collection of dynamic random access memory (DRAM) controllers and flash memory controllers. Therefore, the external memory 500 can be a collection of DRAM and flash memory.
相機I/F 240可接收由相機600攝取的影像資料,且將影像資料傳輸至記憶體控制器230及/或影像處理電路260。當系統100支援MIPI時,相機600以及相機I/F 240可使用相機串列介面(camera serial interface,CSI)(例如,CSI-2)而彼此通信。相機600可使用低電壓差分發信(low-voltage differential signaling,LVDS)而將影像資料傳輸至相機I/F 240。 The camera I/F 240 can receive image data captured by the camera 600 and transmit the image data to the memory controller 230 and/or the image processing circuit 260. When system 100 supports MIPI, camera 600 and camera I/F 240 can communicate with one another using a camera serial interface (CSI) (eg, CSI-2). Camera 600 can transmit image data to camera I/F 240 using low-voltage differential signaling (LVDS).
頻率計算電路250可自DDI 300接收資料傳輸時序控制信號TE,使用自晶體振盪器X-OSC輸出的與時鐘信號相關的參考時鐘信號「fref」而計算資料傳輸時序控制信號TE的頻率,且經由匯流排201而將計算結果傳輸至CPU 210。CPU 210可藉由使用計算結果來產生用於調整DDI 300的操作時鐘信號的頻率的第一頻率控制信號而作為控制電路操作。 The frequency calculation circuit 250 can receive the data transmission timing control signal TE from the DDI 300, and calculate the frequency of the data transmission timing control signal TE using the reference clock signal "fref" associated with the clock signal output from the crystal oscillator X-OSC, and The bus 201 transmits the calculation result to the CPU 210. The CPU 210 can operate as a control circuit by using the calculation result to generate a first frequency control signal for adjusting the frequency of the operation clock signal of the DDI 300.
雖然在本例示性實施例中,頻率計算電路250計算資料傳輸時序控制信號TE的頻率fcnt,但應理解,在一或多個其他例示性實施例中,CPU 210可計算資料傳輸時序控制信號TE的頻率fcnt。舉例而言,在此狀況下,頻率計算電路250可使用參考時鐘 信號fref或frefd而對資料傳輸時序控制信號TE的週期進行計數,產生對應於計數結果的計數值CNT,且將計數值CNT提供至CPU 210。CPU 210可接著使用計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt。 Although in the present exemplary embodiment, the frequency calculation circuit 250 calculates the frequency fcnt of the data transmission timing control signal TE, it should be understood that in one or more other exemplary embodiments, the CPU 210 may calculate the data transmission timing control signal TE. The frequency fcnt. For example, in this case, the frequency calculation circuit 250 can use the reference clock The period of the data transfer timing control signal TE is counted by the signal fref or frefd, a count value CNT corresponding to the count result is generated, and the count value CNT is supplied to the CPU 210. The CPU 210 can then calculate the frequency fcnt of the data transmission timing control signal TE using the count value CNT.
雖然在一或多個其他例示性實施例中,主機200可包含用於產生第一頻率控制信號的獨立控制電路,但產生用於調整DDI 300的操作時鐘信號的頻率的控制信號的電路在本文中被稱為控制電路(例如,CPU 210)。 Although in one or more other exemplary embodiments, host 200 may include an independent control circuit for generating a first frequency control signal, circuitry for generating a control signal for adjusting the frequency of the operational clock signal of DDI 300 is in this document It is called a control circuit (for example, CPU 210).
影像處理電路260處理且控制待傳輸至DDI 300的影像資料及/或命令資料。命令資料包含第一頻率控制信號。影像資料及/或命令資料可按照MIPI中所定義的資料封包的形式來傳輸。然而,應理解一或多個其他例示性實施例不限於此。舉例而言,根據另一例示性實施例,影像資料及/或命令資料可按照eDP標準或高速串列介面標準中所定義的資料格式來傳輸。 Image processing circuitry 260 processes and controls the image data and/or command material to be transmitted to DDI 300. The command data contains the first frequency control signal. Image data and/or command data may be transmitted in the form of data packets as defined in MIPI. However, it should be understood that one or more other exemplary embodiments are not limited thereto. For example, according to another exemplary embodiment, image data and/or command material may be transmitted in accordance with a data format defined in an eDP standard or a high speed serial interface standard.
TX I/F 270可與DDI 300的接收介面(receive interface,RX I/F)310通信。影像資料及/或命令資料可經由影像處理電路260以及TX I/F 270而自主機200傳輸至DDI 300。TX I/F 270可使用與自晶體振盪器X-OSC輸出的時鐘信號fref相關、基於fref或等效於fref的時鐘信號來傳輸影像資料。 The TX I/F 270 can communicate with the receive interface (RX I/F) 310 of the DDI 300. The image data and/or command data may be transmitted from the host 200 to the DDI 300 via the image processing circuit 260 and the TX I/F 270. The TX I/F 270 can transmit image data using a fref or fref-based clock signal associated with the clock signal fref output from the crystal oscillator X-OSC.
介面10連接於主機200與DDI 300之間。舉例而言,介面10可經實施以支援MIPI、eDP、高速串列介面等。 The interface 10 is connected between the host 200 and the DDI 300. For example, interface 10 can be implemented to support MIPI, eDP, high speed serial interface, and the like.
DDI 300可基於自主機200傳輸的影像資料及/或命令資 料而處理影像資料,且可將所處理的影像資料傳輸至顯示面板400。此時,DDI 300可使用畫面緩衝器325中所儲存的影像資料而執行PSR。 The DDI 300 can be based on image data and/or commands transmitted from the host 200. The image data is processed and the processed image data can be transmitted to the display panel 400. At this time, the DDI 300 can perform the PSR using the image material stored in the picture buffer 325.
DDI 300可回應於自主機200傳輸的第一頻率控制信號而調整DDI 300的操作時鐘信號的頻率。操作時鐘信號的頻率可為用於DDI 300的操作的各種操作時鐘信號中的每一者的頻率。 The DDI 300 can adjust the frequency of the operational clock signal of the DDI 300 in response to the first frequency control signal transmitted from the host 200. The frequency at which the clock signal is operated may be the frequency of each of the various operational clock signals used for operation of DDI 300.
舉例而言,操作時鐘信號可為自DDI 300內所實施的振盪器330輸出的內部時鐘信號「ifc」。此時,振盪器330的內部時鐘信號ifc可參與資料傳輸時序控制信號TE的產生以及用於PSR的控制信號的產生。DDI 300可實施為行動DDI。DDI 300包含RX I/F 310、控制電路320、畫面緩衝器325、振盪器330、時序控制器340以及驅動電路區塊350。 For example, the operational clock signal can be an internal clock signal "ifc" output from oscillator 330 implemented in DDI 300. At this time, the internal clock signal ifc of the oscillator 330 can participate in the generation of the data transmission timing control signal TE and the generation of the control signal for the PSR. The DDI 300 can be implemented as an action DDI. The DDI 300 includes an RX I/F 310, a control circuit 320, a picture buffer 325, an oscillator 330, a timing controller 340, and a drive circuit block 350.
RX I/F 310可將自主機200的TX I/F 270傳輸的影像資料及/或命令資料轉換為適用於DDI 300的格式。舉例而言,當RX I/F 310支援MIPI時,RX I/F 310可令經由介面10而接收的時鐘信號傳遞至控制電路320,且可使用時鐘信號而自影像資料(例如,資料封包)恢復資料、資料啟用信號以及同步信號(例如,垂直同步信號以及水平同步信號)。 The RX I/F 310 can convert image data and/or command data transmitted from the TX I/F 270 of the host 200 into a format suitable for the DDI 300. For example, when the RX I/F 310 supports the MIPI, the RX I/F 310 can transmit the clock signal received via the interface 10 to the control circuit 320, and can use the clock signal from the image data (eg, data packet). Resume data, data enable signals, and sync signals (for example, vertical sync signals and horizontal sync signals).
控制電路320可基於自RX I/F 310輸出的一或多個控制信號而控制畫面緩衝器325、振盪器330及/或時序控制器340的操作。 Control circuit 320 can control the operation of picture buffer 325, oscillator 330, and/or timing controller 340 based on one or more control signals output from RX I/F 310.
在一或多個例示性實施例中,當RX I/F 310接收用於控 制DDI 300的操作時鐘信號的頻率的第一頻率控制信號(或命令)且將其輸出至控制電路320時,控制電路320可基於第一頻率控制信號而產生第二頻率控制信號。舉例而言,當按照命令的形式來傳輸第一頻率控制信號時,第二頻率控制信號可為經解碼的命令。振盪器330可回應於第二頻率控制信號而調整(例如,增大或減小)內部時鐘信號ifc的頻率。 In one or more exemplary embodiments, when RX I/F 310 is received for control When the DDI 300 operates the first frequency control signal (or command) of the frequency of the clock signal and outputs it to the control circuit 320, the control circuit 320 can generate the second frequency control signal based on the first frequency control signal. For example, when the first frequency control signal is transmitted in the form of a command, the second frequency control signal may be a decoded command. The oscillator 330 can adjust (eg, increase or decrease) the frequency of the internal clock signal ifc in response to the second frequency control signal.
此時,時序控制信號產生器342可使用經頻率調整的內部時鐘信號ifc而調整資料傳輸時序控制信號TE的頻率,且可將頻率已被調整的資料傳輸時序控制信號TE輸出至主機200。 At this time, the timing control signal generator 342 can adjust the frequency of the data transmission timing control signal TE using the frequency-adjusted internal clock signal ifc, and can output the data transmission timing control signal TE whose frequency has been adjusted to the host 200.
在一或多個其他例示性實施例中,當RX I/F 310接收用於控制DDI 300的操作時鐘信號的頻率的第一頻率控制信號且將其輸出至控制電路320時,控制電路320可直接使用與第一頻率控制信號相關的第二頻率控制信號來控制時序控制信號產生器342。舉例而言,在此狀況下,控制電路320可控制時序控制信號產生器342藉由調整內部時鐘信號ifc的頻率與資料傳輸時序控制信號TE的頻率之間的比率來調整(例如,增大或減小)資料傳輸時序控制信號TE的頻率,而振盪器330並不調整(例如,增大或減小)內部時鐘信號ifc的頻率。此處,所述比率可儲存於(例如)時序控制信號產生器342的暫存器中。舉例而言,在此狀況下,若內部時鐘信號ifc的頻率發生偏差而兩倍於原始頻率,則可藉由調整資料傳輸時序控制信號TE的雙態觸變循環(例如,自每8個循環的內部時鐘信號中的一個循環的資料傳輸時序控制信號TE 調整為每16個循環的內部時鐘信號中的一個循環的資料傳輸時序控制信號TE)來調整比率。 In one or more other exemplary embodiments, when the RX I/F 310 receives the first frequency control signal for controlling the frequency of the operation clock signal of the DDI 300 and outputs it to the control circuit 320, the control circuit 320 may The timing control signal generator 342 is controlled directly using the second frequency control signal associated with the first frequency control signal. For example, in this case, the control circuit 320 can control the timing control signal generator 342 to adjust (for example, increase or increase) by adjusting the ratio between the frequency of the internal clock signal ifc and the frequency of the data transmission timing control signal TE. The frequency of the data transmission timing control signal TE is reduced, and the oscillator 330 does not adjust (eg, increase or decrease) the frequency of the internal clock signal ifc. Here, the ratio may be stored in, for example, a register of the timing control signal generator 342. For example, in this case, if the frequency of the internal clock signal ifc is different from the original frequency, the two-state thixotropic cycle of the data transmission timing control signal TE can be adjusted (for example, from every 8 cycles) a cyclic data transmission timing control signal TE in the internal clock signal The ratio is adjusted by adjusting the data transmission timing control signal TE) of one cycle of the internal clock signal every 16 cycles.
根據另一例示性實施例,振盪器330可使用第二頻率控制信號來調整(例如,增大或減小)內部時鐘信號ifc的頻率,且控制電路320可直接使用第二頻率控制信號來控制時序控制信號產生器342。舉例而言,在此狀況下,控制電路320可控制時序控制信號產生器342藉由調整經調整的內部時鐘信號ifc的頻率(由振盪器330調整)與資料傳輸時序控制信號TE的頻率之間的比率來調整(例如,增大或減小)資料傳輸時序控制信號TE的頻率。 According to another exemplary embodiment, the oscillator 330 may use a second frequency control signal to adjust (eg, increase or decrease) the frequency of the internal clock signal ifc, and the control circuit 320 may directly control using the second frequency control signal. Timing control signal generator 342. For example, in this case, the control circuit 320 can control the timing control signal generator 342 to adjust the frequency of the adjusted internal clock signal ifc (adjusted by the oscillator 330) to the frequency of the data transmission timing control signal TE. The ratio is adjusted (eg, increased or decreased) by the frequency of the data transmission timing control signal TE.
時序控制信號產生器342可回應於第二頻率控制信號而調整(例如,增大或減小)資料傳輸時序控制信號TE的頻率,且可將頻率已被調整的資料傳輸時序控制信號TE輸出至主機200。舉例而言,當DDI 300支援MIPI時,時序控制信號產生器342可實施為TE信號產生器。 The timing control signal generator 342 can adjust (eg, increase or decrease) the frequency of the data transmission timing control signal TE in response to the second frequency control signal, and can output the data transmission timing control signal TE whose frequency has been adjusted to Host 200. For example, when DDI 300 supports MIPI, timing control signal generator 342 can be implemented as a TE signal generator.
控制電路320可使用寫入控制信號而將由RX I/F 310接收且自RX I/F 310輸出的影像資料寫入至畫面緩衝器325。寫入控制信號為用於將影像資料寫入至畫面緩衝器325的信號。控制電路320亦可使用根據振盪器330的內部時鐘信號ifc而產生的讀取控制信號而自畫面緩衝器325讀取影像資料,且將影像資料傳輸至時序控制器340中所包含的影像處理電路344。 The control circuit 320 can write the image data received by the RX I/F 310 and output from the RX I/F 310 to the picture buffer 325 using the write control signal. The write control signal is a signal for writing image data to the picture buffer 325. The control circuit 320 can also read the image data from the picture buffer 325 using the read control signal generated according to the internal clock signal ifc of the oscillator 330, and transmit the image data to the image processing circuit included in the timing controller 340. 344.
影像處理電路344使用振盪器330的內部時鐘信號ifc而處理自控制電路320輸出的影像資料,且將對應於處理結果的顯 示資料以及顯示資料的同步信號(例如,垂直同步信號、水平同步信號以及資料啟用信號)輸出至驅動電路區塊350。 The image processing circuit 344 processes the image data output from the control circuit 320 using the internal clock signal ifc of the oscillator 330, and will display the image corresponding to the processing result. The display data and the synchronization signals (for example, the vertical synchronization signal, the horizontal synchronization signal, and the data enable signal) of the display data are output to the drive circuit block 350.
驅動電路區塊350可根據自影像處理電路344輸出的顯示資料以及同步信號而將顯示資料驅動至顯示面板400。此外,應理解,驅動電路區塊350可包含至少一個源極驅動器以及至少一個閘極驅動器。顯示面板400可實施為薄膜電晶體液晶顯示器(thin-film-transistor liquid-crystal display,TFT-LCD)面板、有機發光二極體(organic light-emitting diode,OLED)顯示面板、主動矩陣OLED(active-matrix organic light-emitting diode,AMOLED)顯示面板、可撓性顯示面板、LCD面板等。 The driving circuit block 350 can drive the display material to the display panel 400 according to the display data output from the image processing circuit 344 and the synchronization signal. Moreover, it should be understood that the driver circuit block 350 can include at least one source driver and at least one gate driver. The display panel 400 can be implemented as a thin-film-transistor liquid-crystal display (TFT-LCD) panel, an organic light-emitting diode (OLED) display panel, and an active matrix OLED (active). -matrix organic light-emitting diode, AMOLED) display panel, flexible display panel, LCD panel, and the like.
圖2為根據例示性實施例的頻率計算電路250A的方塊圖。舉例而言,頻率計算電路250A可實施為圖1所說明的頻率計算電路250。圖4為根據例示性實施例的頻率計算電路250A的操作的時序圖。參看圖2,頻率計算電路250A包含邊緣偵測器251、頻率計數器255以及頻率計算器256。頻率計算電路250A亦可包含分頻器253。 2 is a block diagram of a frequency calculation circuit 250A, in accordance with an exemplary embodiment. For example, frequency calculation circuit 250A can be implemented as frequency calculation circuit 250 illustrated in FIG. FIG. 4 is a timing diagram of the operation of frequency calculation circuit 250A, in accordance with an exemplary embodiment. Referring to FIG. 2, the frequency calculation circuit 250A includes an edge detector 251, a frequency counter 255, and a frequency calculator 256. The frequency calculation circuit 250A may also include a frequency divider 253.
參看圖4中的狀況I,頻率計算電路250A可使用參考時鐘信號fref或frefd而對資料傳輸時序控制信號TE的特定週期(例如,上升邊緣間的間隔(下文中,稱為「第一週期」))RTR進行計數,且可使用對應於計數結果的計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt。 Referring to the condition I in FIG. 4, the frequency calculation circuit 250A can transmit a specific period of the data transmission timing control signal TE using the reference clock signal fref or frefd (for example, an interval between rising edges (hereinafter, referred to as "first period") )) The RTR counts, and the frequency fcnt of the data transmission timing control signal TE can be calculated using the count value CNT corresponding to the count result.
邊緣偵測器251回應於參考時鐘信號fref或frefd而偵測 資料傳輸時序控制信號TE的上升邊緣,產生具有脈衝波形的偵測信號DET,且將資料傳輸時序控制信號TE輸出至頻率計數器255。偵測信號DET的波形可與資料傳輸時序控制信號TE的波形相同、實質上相同或類似。 The edge detector 251 detects in response to the reference clock signal fref or frefd The rising edge of the data transmission timing control signal TE generates a detection signal DET having a pulse waveform, and outputs the data transmission timing control signal TE to the frequency counter 255. The waveform of the detection signal DET may be the same, substantially the same or similar to the waveform of the data transmission timing control signal TE.
頻率計數器255可使用參考時鐘信號fref或frefd來對第一週期RTR進行計數,且產生對應於計數結果的計數值CNT。舉例而言,頻率計數器255可對第一週期RTR中的參考時鐘信號fref或frefd的循環的數目進行計數。頻率計算器256可使用計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt,且可將頻率fcnt輸出至CPU 210。根據一或多個例示性實施例,頻率計數器255以及頻率計算器256可一起實施於單個電路中,但應理解,一或多個其他例示性實施例不限於此。 The frequency counter 255 can count the first period RTR using the reference clock signal fref or frefd, and generate a count value CNT corresponding to the count result. For example, the frequency counter 255 can count the number of cycles of the reference clock signal fref or frefd in the first period RTR. The frequency calculator 256 can calculate the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and can output the frequency fcnt to the CPU 210. In accordance with one or more exemplary embodiments, frequency counter 255 and frequency calculator 256 may be implemented together in a single circuit, although it should be understood that one or more other illustrative embodiments are not limited thereto.
頻率計數器255回應於已啟動的偵測信號DET而重設先前計數值,使用參考時鐘信號fref或frefd來對第一週期RTR進行計數,且產生計數值CNT。 The frequency counter 255 resets the previous count value in response to the activated detection signal DET, uses the reference clock signal fref or frefd to count the first period RTR, and generates the count value CNT.
CPU 210可判定自頻率計算器256輸出的頻率fcnt是否處於DDI 300的預定範圍(例如,中心操作頻率範圍)內,且基於判定結果而產生第一頻率控制信號。可基於中心操作頻率以及偏差而判定中心操作頻率範圍。中心操作頻率以及偏差可隨著DDI 300的設計規格而變化。舉例而言,當中心操作頻率為60赫茲且偏差為±0.2%時,中心操作頻率範圍可被判定為59.88赫茲至60.12赫茲。 The CPU 210 may determine whether the frequency fcnt output from the frequency calculator 256 is within a predetermined range (for example, a central operating frequency range) of the DDI 300, and generate a first frequency control signal based on the determination result. The central operating frequency range can be determined based on the center operating frequency and the deviation. The center operating frequency and deviation can vary with the design specifications of the DDI 300. For example, when the center operating frequency is 60 Hz and the deviation is ±0.2%, the center operating frequency range can be determined to be 59.88 Hz to 60.12 Hz.
DDI 300可基於與主機200所產生的第一頻率控制信號相關的第二頻率控制信號而調整(例如,增大或減小)資料傳輸時序控制信號TE的頻率。舉例而言,當頻率fcnt不處於中心操作頻率範圍內時,主機200將第一頻率控制信號輸出至DDI 300,以使得DDI 300可基於與第一頻率控制信號相關或基於第一頻率控制信號的第二頻率控制信號而即時地調整資料傳輸時序控制信號TE的頻率。舉例而言,當按照命令的形式來傳輸第一頻率控制信號時,第二頻率控制信號可為經解碼的命令。 The DDI 300 can adjust (eg, increase or decrease) the frequency of the data transmission timing control signal TE based on a second frequency control signal associated with the first frequency control signal generated by the host 200. For example, when the frequency fcnt is not within the central operating frequency range, the host 200 outputs the first frequency control signal to the DDI 300 such that the DDI 300 can be based on the first frequency control signal or based on the first frequency control signal. The second frequency control signal adjusts the frequency of the data transmission timing control signal TE in real time. For example, when the first frequency control signal is transmitted in the form of a command, the second frequency control signal may be a decoded command.
在圖4中,RTRa表示具有由DDI 300調整的頻率的資料傳輸時序控制信號TE的第一週期。因為基於主機200所產生的第一頻率控制信號而調整(例如,增大)資料傳輸時序控制信號TE的第一週期,所以第一週期RTR及RTRa彼此不同,如圖4所示。 In FIG. 4, RTRa represents the first period of the data transmission timing control signal TE having the frequency adjusted by the DDI 300. Since the first period of the data transmission timing control signal TE is adjusted (eg, increased) based on the first frequency control signal generated by the host 200, the first period RTR and RTRa are different from each other, as shown in FIG.
頻率計數器255使用參考時鐘信號fref或frefd來對第一週期RTRa進行計數,且產生對應於計數結果的計數值CNT。頻率計算器256使用計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt,且將頻率fcnt輸出至CPU 210。CPU 210比較頻率fcnt與中心操作頻率範圍且基於比較結果而判定是否產生第一頻率控制信號及/或判定第一頻率控制信號的類型(例如,指示增大、減小或維持資料傳輸時序控制信號TE的頻率)。 The frequency counter 255 counts the first period RTRa using the reference clock signal fref or frefd, and generates a count value CNT corresponding to the count result. The frequency calculator 256 calculates the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and outputs the frequency fcnt to the CPU 210. The CPU 210 compares the frequency fcnt with the central operating frequency range and determines whether to generate the first frequency control signal and/or determine the type of the first frequency control signal based on the comparison result (eg, indicating to increase, decrease, or maintain the data transmission timing control signal) TE frequency).
參看圖4中的狀況II,頻率計算電路250A可使用參考時鐘信號fref或frefd而對資料傳輸時序控制信號TE的特定週期(例如,下降邊緣間的間隔(下文中,稱為「第二週期」))FTF進行 計數,且可使用對應於計數結果的計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt。 Referring to the situation II in FIG. 4, the frequency calculation circuit 250A can transmit a specific period of the data transmission timing control signal TE using the reference clock signal fref or frefd (for example, the interval between the falling edges (hereinafter, referred to as "second period") )) FTF Counting, and the frequency fcnt of the data transmission timing control signal TE can be calculated using the count value CNT corresponding to the counting result.
邊緣偵測器251偵測資料傳輸時序控制信號TE的下降邊緣,產生具有脈衝波形的偵測信號DET,且將資料傳輸時序控制信號TE輸出至頻率計數器255。頻率計數器255使用參考時鐘信號fref或frefd來對第二週期FTF進行計數,且產生計數值CNT。頻率計算器256使用計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt,且將頻率fcnt輸出至CPU 210。 The edge detector 251 detects the falling edge of the data transmission timing control signal TE, generates the detection signal DET having the pulse waveform, and outputs the data transmission timing control signal TE to the frequency counter 255. The frequency counter 255 counts the second period FTF using the reference clock signal fref or frefd, and generates a count value CNT. The frequency calculator 256 calculates the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and outputs the frequency fcnt to the CPU 210.
CPU 210可判定自頻率計算器256輸出的頻率fcnt是否處於DDI 300的預定範圍(例如,中心操作頻率範圍)內,且基於判定結果而控制第一頻率控制信號的產生。 The CPU 210 may determine whether the frequency fcnt output from the frequency calculator 256 is within a predetermined range (for example, a center operating frequency range) of the DDI 300, and control the generation of the first frequency control signal based on the determination result.
DDI 300可基於與主機200所產生的第一頻率控制信號相關的第二頻率控制信號而調整資料傳輸時序控制信號TE的頻率。舉例而言,當頻率fcnt不處於中心操作頻率範圍內時,主機200將第一頻率控制信號輸出至DDI 300,以使得DDI 300可基於第一頻率控制信號而即時地調整資料傳輸時序控制信號TE的頻率。 The DDI 300 can adjust the frequency of the data transmission timing control signal TE based on a second frequency control signal associated with the first frequency control signal generated by the host 200. For example, when the frequency fcnt is not within the central operating frequency range, the host 200 outputs the first frequency control signal to the DDI 300, so that the DDI 300 can instantly adjust the data transmission timing control signal TE based on the first frequency control signal. Frequency of.
在圖4中,FTFa表示具有由DDI 300調整的頻率的資料傳輸時序控制信號TE的第二週期。因為基於主機200所產生的第一頻率控制信號而調整(例如,增大)資料傳輸時序控制信號TE的第二週期,所以第二週期FTF及FTFa彼此不同,如圖4所示。 In FIG. 4, FTFa represents the second period of the data transmission timing control signal TE having the frequency adjusted by the DDI 300. Since the second period of the data transmission timing control signal TE is adjusted (eg, increased) based on the first frequency control signal generated by the host 200, the second periods FTF and FTFa are different from each other, as shown in FIG.
頻率計數器255使用參考時鐘信號fref或frefd來對第二 週期FTFa進行計數,且產生計數值CNT。頻率計算器256使用計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt,且將頻率fcnt輸出至CPU 210。CPU 210比較頻率fcnt與中心操作頻率範圍,且基於比較結果而判定是否產生第一頻率控制信號。 The frequency counter 255 uses the reference clock signal fref or frefd to pair the second The period FTFa is counted and a count value CNT is generated. The frequency calculator 256 calculates the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and outputs the frequency fcnt to the CPU 210. The CPU 210 compares the frequency fcnt with the center operating frequency range, and determines whether or not the first frequency control signal is generated based on the comparison result.
分頻器253以按照預定分頻因數來對晶體振盪器X-OSC的輸出時鐘信號fref進行分頻,且將經分頻的時鐘信號frefd輸出至頻率計數器255。因此,參考時鐘信號可為晶體振盪器X-OSC的輸出時鐘信號fref或經分頻的時鐘信號frefd。可根據主機200的設計規格來決定分頻因數。應理解,在一或多個其他例示性實施例中,可省略分頻器253。 The frequency divider 253 divides the output clock signal fref of the crystal oscillator X-OSC by a predetermined division factor, and outputs the divided clock signal frefd to the frequency counter 255. Therefore, the reference clock signal can be the output clock signal fref of the crystal oscillator X-OSC or the divided clock signal frefd. The division factor can be determined according to the design specifications of the host 200. It should be understood that the frequency divider 253 may be omitted in one or more other exemplary embodiments.
在圖2所說明的本例示性實施例中,資料傳輸時序控制信號TE的頻率fcnt被傳輸至CPU 210。然而,應理解一或多個其他例示性實施例不限於此。舉例而言,根據另一例示性實施例,計數值CNT被直接傳輸至CPU 210。在此狀況下,CPU 210可使用計數值CNT來計算資料傳輸時序控制信號TE的頻率fcnt,判定頻率fcnt是否處於預定範圍(例如,中心操作頻率範圍)內,且基於判定結果而決定是否產生第一頻率控制信號。 In the present exemplary embodiment illustrated in FIG. 2, the frequency fcnt of the material transmission timing control signal TE is transmitted to the CPU 210. However, it should be understood that one or more other exemplary embodiments are not limited thereto. For example, according to another exemplary embodiment, the count value CNT is directly transmitted to the CPU 210. In this case, the CPU 210 can calculate the frequency fcnt of the data transmission timing control signal TE using the count value CNT, determine whether the frequency fcnt is within a predetermined range (for example, a central operating frequency range), and determine whether or not to generate the first based on the determination result. A frequency control signal.
圖3為根據另一例示性實施例的頻率計算電路250B的方塊圖。舉例而言,頻率計算電路250B可實施為圖1所說明的頻率計算電路250。除頻率比較電路257(例如,頻率比較器)之外,圖3所說明的頻率計算電路250B的結構及操作與圖2所說明的頻率計算電路250A的結構及操作相同、實質上相同或類似。圖5A 及圖5B為根據另一例示性實施例的頻率計算電路250B的操作的時序圖。 FIG. 3 is a block diagram of a frequency calculation circuit 250B in accordance with another exemplary embodiment. For example, frequency calculation circuit 250B can be implemented as frequency calculation circuit 250 illustrated in FIG. The configuration and operation of the frequency calculation circuit 250B illustrated in FIG. 3 is identical, substantially identical, or similar to the configuration and operation of the frequency calculation circuit 250A illustrated in FIG. 2, except for the frequency comparison circuit 257 (eg, frequency comparator). Figure 5A And FIG. 5B is a timing diagram of the operation of frequency calculation circuit 250B, in accordance with another exemplary embodiment.
參看圖3、圖5A及圖5B,頻率比較電路257可判定自頻率計算器256輸出的頻率fcnt是否處於預定範圍(例如,頻率窗FW)內,且可根據判定結果而將控制信號(例如,中斷INT)輸出至CPU 210。頻率比較電路257可充當產生中斷INT的中斷產生電路。 Referring to FIGS. 3, 5A and 5B, the frequency comparison circuit 257 can determine whether the frequency fcnt output from the frequency calculator 256 is within a predetermined range (for example, the frequency window FW), and can control the signal according to the determination result (for example, The interrupt INT) is output to the CPU 210. The frequency comparison circuit 257 can function as an interrupt generation circuit that generates an interrupt INT.
圖5A及圖5B所說明的頻率窗FW可與上文參看圖2及圖4的中心操作頻率範圍相同、實質上相同或類似。參看圖5A及圖5B中的狀況I,當由頻率計算器256計算的頻率fcnt(=fcnt1)低於頻率窗FW的下限時,頻率比較電路257可將第一中斷INT輸出至CPU 210。CPU 210可回應於第一中斷INT而產生指示增大DDI 300的操作時鐘信號的頻率的第一頻率控制信號。因此,DDI 300可基於第一頻率控制信號而增大資料傳輸時序控制信號TE的頻率。 The frequency window FW illustrated in Figures 5A and 5B may be substantially the same, substantially the same, or similar to the central operating frequency range of Figures 2 and 4 above. Referring to the condition I in FIGS. 5A and 5B, when the frequency fcnt (=fcnt1) calculated by the frequency calculator 256 is lower than the lower limit of the frequency window FW, the frequency comparison circuit 257 can output the first interrupt INT to the CPU 210. The CPU 210 may generate a first frequency control signal indicating a frequency of increasing the operational clock signal of the DDI 300 in response to the first interrupt INT. Therefore, the DDI 300 can increase the frequency of the data transmission timing control signal TE based on the first frequency control signal.
參看圖5A中的狀況II,當由頻率計算器256計算的頻率fcnt(=fcnt2)處於頻率窗FW的下限與上限之間或處於頻率窗FW內時,頻率比較電路257不將第一中斷INT輸出至CPU 210。同時,參看圖5B中的狀況II,當由頻率計算器256計算的頻率fcnt(=fcnt2)處於頻率窗FW的下限與上限之間或處於頻率窗FW內時,頻率比較電路257將第二中斷INT輸出至CPU 210。CPU 210可回應於第二中斷INT而產生指示維持DDI 300的操作時鐘信號 的頻率的第一頻率控制信號。在一或多個其他例示性實施例中,CPU 210可不產生第一頻率控制信號,以使得DDI 300維持資料傳輸時序控制信號TE的頻率。 Referring to the condition II in FIG. 5A, when the frequency fcnt (= fcnt2) calculated by the frequency calculator 256 is between the lower limit and the upper limit of the frequency window FW or within the frequency window FW, the frequency comparison circuit 257 does not set the first interrupt INT. Output to the CPU 210. Meanwhile, referring to the situation II in FIG. 5B, when the frequency fcnt (= fcnt2) calculated by the frequency calculator 256 is between the lower limit and the upper limit of the frequency window FW or within the frequency window FW, the frequency comparison circuit 257 will be the second interrupt. The INT is output to the CPU 210. The CPU 210 may generate an operation clock signal indicating that the DDI 300 is maintained in response to the second interrupt INT. The frequency of the first frequency control signal. In one or more other exemplary embodiments, CPU 210 may not generate a first frequency control signal to cause DDI 300 to maintain the frequency of the data transmission timing control signal TE.
參看圖5A及圖5B中的狀況III,當由頻率計算器256計算的頻率fcnt(=fcnt3)高於頻率窗FW的上限時,頻率比較電路257可將第三中斷INT輸出至CPU 210。CPU 210可回應於第三中斷INT而產生指示減小DDI 300的操作時鐘信號的頻率的第一頻率控制信號。因此,DDI 300可基於第一頻率控制信號而減小資料傳輸時序控制信號TE的頻率。 Referring to the situation III in FIGS. 5A and 5B, when the frequency fcnt (=fcnt3) calculated by the frequency calculator 256 is higher than the upper limit of the frequency window FW, the frequency comparison circuit 257 can output the third interrupt INT to the CPU 210. The CPU 210 may generate a first frequency control signal indicating a frequency of reducing the operation clock signal of the DDI 300 in response to the third interrupt INT. Therefore, the DDI 300 can reduce the frequency of the data transmission timing control signal TE based on the first frequency control signal.
圖6為根據又一例示性實施例的頻率計算電路250C的方塊圖。舉例而言,頻率計算電路250C可實施為圖1所說明的頻率計算電路250。圖7為圖6所說明的頻率計算電路250C的操作的時序圖。參看圖6,頻率計算電路250C包含邊緣偵測電路252、頻率計數器255以及頻率計算器256。頻率計算電路250C亦可包含分頻器253。 FIG. 6 is a block diagram of a frequency calculation circuit 250C in accordance with yet another exemplary embodiment. For example, frequency calculation circuit 250C can be implemented as frequency calculation circuit 250 illustrated in FIG. FIG. 7 is a timing diagram of the operation of the frequency calculation circuit 250C illustrated in FIG. 6. Referring to FIG. 6, the frequency calculation circuit 250C includes an edge detection circuit 252, a frequency counter 255, and a frequency calculator 256. The frequency calculation circuit 250C may also include a frequency divider 253.
參看圖6及圖7,頻率計算電路250C可使用參考時鐘信號fref或frefd而對資料傳輸時序控制信號TE的特定週期(例如,高週期寬度HIW)進行計數,且可使用對應於計數結果的計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt。 Referring to FIGS. 6 and 7, the frequency calculation circuit 250C may count a specific period (for example, a high period width HIW) of the data transmission timing control signal TE using the reference clock signal fref or frefd, and may use a meter corresponding to the count result. The frequency CNT is used to calculate the frequency fcnt of the data transmission timing control signal TE.
邊緣偵測電路252可包含及閘252-1以及邊緣偵測器252-3。及閘252-1對資料傳輸時序控制信號TE以及參考時鐘信號fref或frefd執行「及」運算,且將運算結果DTE輸出至頻率 計數器255。邊緣偵測器252-3可回應於資料傳輸時序控制信號TE而產生偵測信號DET。邊緣偵測電路252可產生回應於資料傳輸時序控制信號TE的上升邊緣而啟動的偵測信號DET。頻率計數器255可回應於已啟動的偵測信號DET而重設先前計數值CNT,使用參考時鐘信號fref或frefd而對自及閘252-1輸出的運算結果DTE進行計數,且輸出對應於計數結果的當前計數值CNT。 The edge detection circuit 252 can include a gate 252-1 and an edge detector 252-3. The gate 252-1 performs an AND operation on the data transmission timing control signal TE and the reference clock signal fref or frefd, and outputs the operation result DTE to the frequency. Counter 255. The edge detector 252-3 can generate the detection signal DET in response to the data transmission timing control signal TE. The edge detection circuit 252 can generate the detection signal DET that is activated in response to the rising edge of the data transmission timing control signal TE. The frequency counter 255 resets the previous count value CNT in response to the activated detection signal DET, and counts the operation result DTE output from the AND gate 252-1 using the reference clock signal fref or frefd, and the output corresponds to the count result. Current count value CNT.
頻率計算器256使用計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt,且將所計算的頻率fcnt輸出至CPU 210。CPU 210可判定自頻率計算器256輸出的頻率fcnt是否處於DDI 300的預定範圍(例如,中心操作頻率範圍)內,且基於判定結果而控制第一頻率控制信號的產生。 The frequency calculator 256 calculates the frequency fcnt of the data transmission timing control signal TE using the count value CNT, and outputs the calculated frequency fcnt to the CPU 210. The CPU 210 may determine whether the frequency fcnt output from the frequency calculator 256 is within a predetermined range (for example, a center operating frequency range) of the DDI 300, and control the generation of the first frequency control signal based on the determination result.
DDI 300可基於與主機200所產生的第一頻率控制信號相關或基於第一頻率控制信號的第二頻率控制信號而調整資料傳輸時序控制信號TE的頻率。舉例而言,當按照命令的形式來傳輸第一頻率控制信號時,第二頻率控制信號可為經解碼的命令。 The DDI 300 can adjust the frequency of the data transmission timing control signal TE based on a first frequency control signal generated by the host 200 or based on a second frequency control signal of the first frequency control signal. For example, when the first frequency control signal is transmitted in the form of a command, the second frequency control signal may be a decoded command.
當所計算的頻率fcnt處於中心操作頻率範圍外時,主機200將第一頻率控制信號輸出至DDI 300,以使得DDI 300基於第一頻率控制信號而即時地調整資料傳輸時序控制信號TE的頻率。 When the calculated frequency fcnt is outside the center operating frequency range, the host 200 outputs the first frequency control signal to the DDI 300 to cause the DDI 300 to instantaneously adjust the frequency of the data transmission timing control signal TE based on the first frequency control signal.
參看圖7,HIWa表示已由DDI 300調整的資料傳輸時序控制信號TE的高週期寬度。因為基於主機200所產生的第一頻率控制信號而調整(例如,增大)資料傳輸時序控制信號TE的高週期寬度HIW,所以高週期寬度HIW及HIWa彼此不同,如圖7所 示。可以線時間為單位來調整高週期寬度HIW及HIWa。 Referring to Figure 7, HIWa represents the high cycle width of the data transfer timing control signal TE that has been adjusted by the DDI 300. Since the high period width HIW of the data transmission timing control signal TE is adjusted (for example, increased) based on the first frequency control signal generated by the host 200, the high period widths HIW and HIWa are different from each other, as shown in FIG. Show. The high cycle widths HIW and HIWa can be adjusted in line time.
圖8為根據又一例示性實施例的頻率計算電路250D的方塊圖。舉例而言,頻率計算電路250D可實施為圖1所說明的頻率計算電路250。除頻率比較電路257之外,圖8所說明的頻率計算電路250D的結構及操作可與圖6所說明的頻率計算電路250C的結構及操作相同、實質上相同或類似。圖8所說明的頻率比較電路257的操作可與已在上文參看圖3、圖5A及圖5B所述的頻率比較電路257的操作相同、實質上相同或類似。 FIG. 8 is a block diagram of a frequency calculation circuit 250D in accordance with yet another exemplary embodiment. For example, frequency calculation circuit 250D can be implemented as frequency calculation circuit 250 illustrated in FIG. The configuration and operation of the frequency calculation circuit 250D illustrated in FIG. 8 may be identical, substantially identical, or similar to the configuration and operation of the frequency calculation circuit 250C illustrated in FIG. 6, except for the frequency comparison circuit 257. The operation of the frequency comparison circuit 257 illustrated in FIG. 8 may be substantially the same, substantially the same as or similar to the operation of the frequency comparison circuit 257 described above with reference to FIGS. 3, 5A, and 5B.
圖9為根據另一例示性實施例的頻率計算電路250E的方塊圖。舉例而言,頻率計算電路250E可實施為圖1所說明的頻率計算電路250。圖10為圖9所說明的頻率計算電路250E的操作的時序圖。頻率計算電路250E包含邊緣偵測電路252、頻率計數器255以及頻率計算器256。頻率計算電路250E亦可包含分頻器253。 FIG. 9 is a block diagram of a frequency calculation circuit 250E, in accordance with another exemplary embodiment. For example, frequency calculation circuit 250E can be implemented as frequency calculation circuit 250 illustrated in FIG. FIG. 10 is a timing chart showing the operation of the frequency calculation circuit 250E illustrated in FIG. The frequency calculation circuit 250E includes an edge detection circuit 252, a frequency counter 255, and a frequency calculator 256. The frequency calculation circuit 250E may also include a frequency divider 253.
參看圖9及圖10,頻率計算電路250E可使用參考時鐘信號fref或frefd而對資料傳輸時序控制信號TE的特定週期(例如,低週期寬度LIW)進行計數,且可使用計數值CNT而計算資料傳輸時序控制信號TE的頻率fcnt。 Referring to FIGS. 9 and 10, the frequency calculation circuit 250E can count a specific period (for example, a low period width LIW) of the data transmission timing control signal TE using the reference clock signal fref or frefd, and can calculate the data using the count value CNT. The frequency fcnt of the timing control signal TE is transmitted.
邊緣偵測電路252可包含及閘252-1、反相器252-2以及邊緣偵測器252-3。反相器252-2對資料傳輸時序控制信號TE進行反相,且將經反相的資料傳輸時序控制信號輸出至及閘252-1以及邊緣偵測器252-3。及閘252-1對反相器252-2的輸出信號以 及參考時鐘信號fref或frefd執行「及」運算,且將運算結果DTE輸出至頻率計數器255。 The edge detection circuit 252 can include a AND gate 252-1, an inverter 252-2, and an edge detector 252-3. The inverter 252-2 inverts the data transfer timing control signal TE, and outputs the inverted data transfer timing control signal to the AND gate 252-1 and the edge detector 252-3. And the output signal of the gate 252-1 to the inverter 252-2 is And the reference clock signal fref or frefd performs an AND operation, and outputs the operation result DTE to the frequency counter 255.
邊緣偵測電路252可產生回應於資料傳輸時序控制信號TE的下降邊緣而啟動的偵測信號DET。頻率計數器255可回應於已啟動的偵測信號DET而重設先前計數值CNT,使用參考時鐘信號fref或frefd而對自及閘252-1輸出的運算結果DTE進行計數,且輸出計數值CNT。圖9所說明的元件253、255及256的操作可與圖6所說明的元件253、255及256的操作相同、實質上相同或類似。 The edge detection circuit 252 can generate the detection signal DET that is activated in response to the falling edge of the data transmission timing control signal TE. The frequency counter 255 resets the previous count value CNT in response to the activated detection signal DET, counts the operation result DTE output from the AND gate 252-1 using the reference clock signal fref or frefd, and outputs the count value CNT. The operations of elements 253, 255, and 256 illustrated in FIG. 9 may be identical, substantially identical, or similar to the operations of elements 253, 255, and 256 illustrated in FIG.
參看圖10,LIWa表示已由DDI 300調整的資料傳輸時序控制信號TE的低週期寬度。因為基於主機200所產生的第一頻率控制信號而調整(例如,增大)資料傳輸時序控制信號TE的低週期寬度LIW,所以低週期寬度LIW及LIWa彼此不同,如圖10所示。 Referring to Figure 10, LIWa represents the low cycle width of the data transfer timing control signal TE that has been adjusted by the DDI 300. Since the low cycle width LIW of the material transfer timing control signal TE is adjusted (for example, increased) based on the first frequency control signal generated by the host 200, the low cycle widths LIW and LIWa are different from each other as shown in FIG.
圖11為根據又一例示性實施例的頻率計算電路250F的方塊圖。舉例而言,頻率計算電路250F可實施為圖1所說明的頻率計算電路250。除頻率比較電路257之外,圖11所說明的頻率計算電路250F的結構及操作可與圖9所說明的頻率計算電路250E的結構及操作相同、實質上相同或類似。圖11所說明的頻率比較電路257的操作可與已在上文參看圖3、圖5A及圖5B所述的頻率比較電路257的操作相同、實質上相同或類似。 FIG. 11 is a block diagram of a frequency calculation circuit 250F, in accordance with yet another exemplary embodiment. For example, frequency calculation circuit 250F can be implemented as frequency calculation circuit 250 illustrated in FIG. Except for the frequency comparison circuit 257, the configuration and operation of the frequency calculation circuit 250F illustrated in FIG. 11 may be substantially the same or substantially the same as the configuration and operation of the frequency calculation circuit 250E illustrated in FIG. The operation of the frequency comparison circuit 257 illustrated in FIG. 11 may be substantially the same, substantially the same as or similar to the operation of the frequency comparison circuit 257 described above with reference to FIGS. 3, 5A, and 5B.
圖12為根據例示性實施例的對系統100進行操作的方法 的流程圖。參看圖1至圖12,在操作S110中,主機200自DDI 300接收資料傳輸時序控制信號TE。 FIG. 12 is a method of operating system 100 in accordance with an exemplary embodiment. Flow chart. Referring to FIGS. 1 through 12, the host 200 receives the data transfer timing control signal TE from the DDI 300 in operation S110.
在操作S120中,主機200使用參考時鐘信號fref或frefd而計算資料傳輸時序控制信號TE的頻率fcnt。舉例而言,在操作S120中,主機200的頻率計算電路250使用參考時鐘信號fref或frefd而對資料傳輸時序控制信號TE的特定週期進行計數,產生計數值CNT,且使用計數值CNT來計算資料傳輸時序控制信號TE的頻率。雖然在本例示性實施例中,主機200計算資料傳輸時序控制信號TE的頻率fcnt(操作S120),但應理解一或多個其他例示性實施例不限於此。舉例而言,根據另一例示性實施例,外部頻率計算電路(即,主機200外部)可計算資料傳輸時序控制信號TE的頻率fcnt,且將所計算的頻率fcnt傳輸至主機200。 In operation S120, the host 200 calculates the frequency fcnt of the data transmission timing control signal TE using the reference clock signal fref or frefd. For example, in operation S120, the frequency calculation circuit 250 of the host 200 counts a specific period of the data transmission timing control signal TE using the reference clock signal fref or frefd, generates a count value CNT, and uses the count value CNT to calculate data. The frequency of the timing control signal TE is transmitted. Although in the present exemplary embodiment, the host 200 calculates the frequency fcnt of the material transmission timing control signal TE (operation S120), it should be understood that one or more other exemplary embodiments are not limited thereto. For example, according to another exemplary embodiment, the external frequency calculation circuit (ie, external to the host 200) may calculate the frequency fcnt of the data transmission timing control signal TE and transmit the calculated frequency fcnt to the host 200.
在操作S130中,CPU 210基於所計算的頻率fcnt而產生用於調整資料傳輸時序控制信號TE的頻率的第一頻率控制信號,且將第一頻率控制信號傳輸至DDI 300。 In operation S130, the CPU 210 generates a first frequency control signal for adjusting the frequency of the material transmission timing control signal TE based on the calculated frequency fcnt, and transmits the first frequency control signal to the DDI 300.
DDI 300基於對應於自主機200傳輸的第一頻率控制信號的第二頻率控制信號而調整振盪器330的內部時鐘信號ifc的頻率。舉例而言,當按照命令的形式來傳輸第一頻率控制信號時,第二頻率控制信號可為經解碼的命令。在操作S140中,DDI 300基於第二頻率控制信號而調整資料傳輸時序控制信號TE的頻率。DDI 300將頻率已被調整的資料傳輸時序控制信號TE傳輸至主機200。如上所述,DDI 300的操作時鐘信號(例如,內部時鐘 信號ifc)的頻率經調整以使得DDI 300使用具有經調整的頻率的操作時鐘信號來執行PSR。 The DDI 300 adjusts the frequency of the internal clock signal ifc of the oscillator 330 based on the second frequency control signal corresponding to the first frequency control signal transmitted from the host 200. For example, when the first frequency control signal is transmitted in the form of a command, the second frequency control signal may be a decoded command. In operation S140, the DDI 300 adjusts the frequency of the data transmission timing control signal TE based on the second frequency control signal. The DDI 300 transmits the data transmission timing control signal TE whose frequency has been adjusted to the host 200. As described above, the operation clock signal of the DDI 300 (for example, an internal clock) The frequency of the signal ifc) is adjusted such that the DDI 300 performs the PSR using an operational clock signal having an adjusted frequency.
圖13為根據另一例示性實施例的系統100A的方塊圖。參看圖13,系統100A包含主機200A、DDI 300A、顯示面板400、外部記憶體500以及相機600。除TX I/F 270A以及頻率計算電路250之外,圖13所說明的主機200A的結構及操作可與圖1所說明的主機200的結構及操作相同、實質上相同或類似。 FIG. 13 is a block diagram of a system 100A in accordance with another exemplary embodiment. Referring to FIG. 13, system 100A includes a host 200A, a DDI 300A, a display panel 400, an external memory 500, and a camera 600. Except for the TX I/F 270A and the frequency calculation circuit 250, the structure and operation of the host 200A illustrated in FIG. 13 may be substantially the same or substantially the same as the structure and operation of the host 200 illustrated in FIG.
除用於影像資料的傳輸的時鐘信號外,主機200A亦經由專屬傳輸線11a而將專屬時鐘信號CLK傳輸至DDI 300A。換言之,介面11包含用於時鐘信號的傳輸的傳輸線、用於影像資料的傳輸的傳輸線以及用於專屬時鐘信號CLK的傳輸的專屬傳輸線11a。當介面11支援MIPI或eDP時,介面11更包含用於專屬時鐘信號CLK的傳輸的專屬傳輸線11a。 In addition to the clock signal for transmission of the image data, the host 200A also transmits the dedicated clock signal CLK to the DDI 300A via the dedicated transmission line 11a. In other words, the interface 11 includes a transmission line for transmission of a clock signal, a transmission line for transmission of image data, and a dedicated transmission line 11a for transmission of the dedicated clock signal CLK. When the interface 11 supports MIPI or eDP, the interface 11 further includes a dedicated transmission line 11a for transmission of the dedicated clock signal CLK.
DDI 300A可將專屬時鐘信號CLK用作操作時鐘信號。在本例示性實施例中,DDI 300A不包含振盪器。專屬時鐘信號CLK對程序變化、電壓變化及/或溫度變化毫不在意。 The DDI 300A can use the dedicated clock signal CLK as an operation clock signal. In the present exemplary embodiment, DDI 300A does not include an oscillator. The dedicated clock signal CLK does not care about program changes, voltage changes, and/or temperature changes.
DDI 300A的RX I/F 310A使用時鐘信號而自影像資料恢復資料、資料啟用信號以及同步信號,且將時鐘信號傳輸至控制電路320A。RX I/F 310A亦將專屬時鐘信號CLK傳輸至控制電路320A。 The RX I/F 310A of the DDI 300A recovers the data, the data enable signal, and the sync signal from the image data using the clock signal, and transmits the clock signal to the control circuit 320A. The RX I/F 310A also transmits the dedicated clock signal CLK to the control circuit 320A.
在寫入操作期間,控制電路320A使用時鐘信號以及寫入控制信號而將所恢復的資料寫入至畫面緩衝器325。在讀取操作期 間,控制電路320A使用專屬時鐘信號CLK以及讀取控制信號而自畫面緩衝器325讀取資料(例如,所恢復的資料)且將所讀取的資料傳輸至影像處理電路344。可使用專屬時鐘信號CLK而產生讀取控制信號。 During the write operation, control circuit 320A writes the recovered data to picture buffer 325 using the clock signal and the write control signal. During the read operation period The control circuit 320A reads the data (e.g., recovered data) from the picture buffer 325 using the dedicated clock signal CLK and the read control signal and transmits the read data to the image processing circuit 344. The read control signal can be generated using the dedicated clock signal CLK.
時序控制器340A的時序控制信號產生器342使用專屬時鐘信號CLK而產生資料傳輸時序控制信號TE,且將資料傳輸時序控制信號TE傳輸至主機200A。TX I/F 270A基於資料傳輸時序控制信號TE而將影像資料傳輸至DDI 300A。 The timing control signal generator 342 of the timing controller 340A generates a material transmission timing control signal TE using the dedicated clock signal CLK, and transmits the material transmission timing control signal TE to the host 200A. The TX I/F 270A transmits the image data to the DDI 300A based on the data transmission timing control signal TE.
時序控制器340A的影像處理電路344使用專屬時鐘信號CLK而處理自控制電路320A輸出的資料,且將對應於處理結果的顯示資料傳輸至驅動電路區塊350。如上所述,DDI 300A將經由專屬傳輸線11a自主機200A傳輸的專屬時鐘信號CLK用作操作時鐘信號而處理自主機200A傳輸的影像資料。 The image processing circuit 344 of the timing controller 340A processes the material output from the control circuit 320A using the dedicated clock signal CLK, and transmits the display material corresponding to the processing result to the driving circuit block 350. As described above, the DDI 300A processes the image data transmitted from the host 200A by using the dedicated clock signal CLK transmitted from the host 200A via the dedicated transmission line 11a as an operation clock signal.
圖14為根據又一例示性實施例的系統100B的方塊圖。系統100B包含主機200A、DDI 300B、顯示面板400、外部記憶體500以及相機600。除頻率計算電路250之外,圖14所說明的主機200A的結構及操作可與圖1所說明的主機200的結構及操作相同、實質上相同或類似。 FIG. 14 is a block diagram of a system 100B in accordance with yet another exemplary embodiment. The system 100B includes a host 200A, a DDI 300B, a display panel 400, an external memory 500, and a camera 600. In addition to the frequency calculation circuit 250, the structure and operation of the host 200A illustrated in FIG. 14 may be substantially the same or similar to the structure and operation of the host 200 illustrated in FIG.
在系統100B的操作期間,主機200A不斷地(例如,一直)將時鐘信號HCLK傳輸至DDI 300B。DDI 300B將與時鐘信號HCLK相關的時鐘信號CLK用作操作時鐘信號,且DDI 300B不包含振盪器。此時,時鐘信號HCLK的頻率高於時鐘信號CLK 的頻率。時鐘信號HCLK可為MIPI時鐘信號。當系統100B按照MIPI命令模式操作時,主機200A不斷地對DDI 300B提供時鐘信號。 During operation of system 100B, host 200A continuously (eg, always) transmits clock signal HCLK to DDI 300B. The DDI 300B uses the clock signal CLK associated with the clock signal HCLK as the operational clock signal, and the DDI 300B does not include the oscillator. At this time, the frequency of the clock signal HCLK is higher than the clock signal CLK. Frequency of. The clock signal HCLK can be a MIPI clock signal. When system 100B operates in the MIPI command mode, host 200A continually provides a clock signal to DDI 300B.
時鐘信號HCLK對DDI 300B的程序變化、電壓變化及/或溫度變化毫不在意。DDI 300B的RX I/F 310B使用時鐘信號HCLK而自影像資料恢復資料、資料啟用信號以及同步信號,且將時鐘信號HCLK傳輸至控制電路320B。 The clock signal HCLK does not care about program changes, voltage variations, and/or temperature variations of the DDI 300B. The RX I/F 310B of the DDI 300B recovers the data, the data enable signal, and the sync signal from the image data using the clock signal HCLK, and transmits the clock signal HCLK to the control circuit 320B.
在寫入操作期間,控制電路320B使用時鐘信號HCLK以及寫入控制信號而將所恢復的資料寫入至畫面緩衝器325。在讀取操作期間,控制電路320B使用時鐘信號CLK以及讀取控制信號而自畫面緩衝器325讀取資料(例如,所恢復的資料)且將所讀取的資料傳輸至影像處理電路344。可使用時鐘信號CLK而產生讀取控制信號。 During the write operation, the control circuit 320B writes the recovered data to the picture buffer 325 using the clock signal HCLK and the write control signal. During a read operation, control circuit 320B reads data (eg, recovered data) from picture buffer 325 using clock signal CLK and read control signals and transmits the read data to image processing circuit 344. The read control signal can be generated using the clock signal CLK.
時序控制器340A的時序控制信號產生器342使用時鐘信號CLK而產生資料傳輸時序控制信號TE,且將資料傳輸時序控制信號TE傳輸至主機200A。TX I/F 270基於資料傳輸時序控制信號TE而將影像資料傳輸至DDI 300B。 The timing control signal generator 342 of the timing controller 340A generates the data transfer timing control signal TE using the clock signal CLK, and transmits the material transfer timing control signal TE to the host 200A. The TX I/F 270 transmits the image data to the DDI 300B based on the data transmission timing control signal TE.
時序控制器340A的影像處理電路344使用時鐘信號CLK而處理自控制電路320B輸出的資料,且將對應於處理結果的顯示資料傳輸至驅動電路區塊350。 The image processing circuit 344 of the timing controller 340A processes the material output from the control circuit 320B using the clock signal CLK, and transmits the display material corresponding to the processing result to the drive circuit block 350.
圖15為根據又一例示性實施例的系統100C的方塊圖。系統100C包含主機200B、DDI 300、顯示面板400、外部記憶體 500、相機600以及頻率計算積體電路(頻率計算IC)700。除介面290之外,圖15所說明的主機200B的結構及操作可與圖1所說明的主機200的結構及操作相同、實質上相同或類似。主機200B以及頻率計算IC 700可經由介面290而彼此通信。頻率計算IC 700可包含上述頻率計算電路250、250A、250B、250C、250D、250E、250F中的任一者。 FIG. 15 is a block diagram of a system 100C in accordance with yet another exemplary embodiment. The system 100C includes a host 200B, a DDI 300, a display panel 400, and an external memory. 500, camera 600 and frequency calculation integrated circuit (frequency calculation IC) 700. Except for the interface 290, the structure and operation of the host 200B illustrated in FIG. 15 may be substantially the same, substantially the same as or similar to the structure and operation of the host 200 illustrated in FIG. Host 200B and frequency calculation IC 700 can communicate with one another via interface 290. The frequency calculation IC 700 can include any of the frequency calculation circuits 250, 250A, 250B, 250C, 250D, 250E, 250F described above.
頻率計算IC 700計算資料傳輸時序控制信號TE的頻率fcnt且/或使用參考時鐘信號fref或frefd而對資料傳輸時序控制信號TE的週期進行計數,以產生對應於計數結果的計數值CNT。 The frequency calculation IC 700 calculates the frequency fcnt of the data transmission timing control signal TE and/or counts the period of the data transmission timing control signal TE using the reference clock signal fref or frefd to generate a count value CNT corresponding to the count result.
由頻率計算IC 700的頻率計算電路250計算的計數值CNT或頻率fcnt經由主機200B中的介面290以及匯流排201而傳輸至CPU 210。CPU 210使用計數值CNT(例如,藉由基於計數值CNT而判定頻率fcnt)或頻率fcnt來產生第一頻率控制信號,且經由TX I/F 270以及介面12而將第一頻率控制信號傳輸至DDI 300。DDI 300基於第一頻率控制信號而調整DDI 300的操作時鐘信號的頻率。 The count value CNT or frequency fcnt calculated by the frequency calculation circuit 250 of the frequency calculation IC 700 is transmitted to the CPU 210 via the interface 290 in the host 200B and the bus bar 201. The CPU 210 generates a first frequency control signal using the count value CNT (for example, by determining the frequency fcnt based on the count value CNT) or the frequency fcnt, and transmits the first frequency control signal to the TX I/F 270 and the interface 12 via the TX I/F 270 and the interface 12 DDI 300. The DDI 300 adjusts the frequency of the operational clock signal of the DDI 300 based on the first frequency control signal.
介面12包含用於控制信號的傳輸的傳輸線以及用於影像資料傳輸的傳輸線。介面12可實施為MIPI、eDP介面或高速串列介面。 The interface 12 includes a transmission line for controlling transmission of signals and a transmission line for transmission of image data. Interface 12 can be implemented as an MIPI, eDP interface, or high speed serial interface.
圖15所說明的DDI 300的結構及操作可與圖1所說明的DDI 300的結構及操作相同、實質上相同或類似。如圖15所示,系統100C使用頻率計算IC 700以及主機200B而調整DDI 300的 操作時鐘信號(例如,內部時鐘信號ifc)的頻率。 The structure and operation of the DDI 300 illustrated in FIG. 15 may be substantially the same or similar to the structure and operation of the DDI 300 illustrated in FIG. As shown in FIG. 15, the system 100C adjusts the DDI 300 using the frequency calculation IC 700 and the host 200B. The frequency at which the clock signal (eg, internal clock signal ifc) is operated.
如上所述,根據例示性實施例,主機(例如,IC、SoC、處理器、AP、行動AP等)自DDI接收資料傳輸時序控制信號,使用參考時鐘信號而計算資料傳輸時序控制信號的頻率,基於所計算的頻率而產生用於調整資料傳輸時序控制信號的頻率的頻率控制信號,且將頻率控制信號傳輸至DDI。主機校正DDI的操作時鐘信號中的頻率偏差,藉此防止包含主機以及DDI的系統中所使用的裝置(諸如,觸碰螢幕或觸控筆)的錯誤操作。換言之,DDI減少或消除由於頻率偏差而發生的EMI,從而防止系統中所使用的其他裝置(諸如,觸碰螢幕以及觸控筆)異常操作。 As described above, according to an exemplary embodiment, a host (eg, IC, SoC, processor, AP, mobile AP, etc.) receives a data transmission timing control signal from the DDI, and calculates a frequency of the data transmission timing control signal using the reference clock signal, A frequency control signal for adjusting a frequency of the data transmission timing control signal is generated based on the calculated frequency, and the frequency control signal is transmitted to the DDI. The host corrects for frequency deviations in the DDI's operational clock signal, thereby preventing erroneous operations of devices used in systems including the host and DDI, such as touching a screen or a stylus. In other words, DDI reduces or eliminates EMI due to frequency deviations, thereby preventing abnormal operation of other devices used in the system, such as touching the screen and the stylus.
此外,因為主機校正DDI的操作時鐘信號中的頻率偏差,所以主機不需要對DDI提供獨立的參考時鐘信號。因此,簡化了系統的電路結構。此外,因為主機校正DDI的操作時鐘信號中的頻率偏差,所以DDI不需要額外晶體振盪器。 In addition, because the host corrects the frequency offset in the DDI's operational clock signal, the host does not need to provide an independent reference clock signal to the DDI. Therefore, the circuit structure of the system is simplified. In addition, DDI does not require an additional crystal oscillator because the host corrects the frequency offset in the DDI's operating clock signal.
儘管已在上文特定地展示且描述了例示性實施例,但一般熟習此項技術者將理解,在不脫離如由所附申請專利範圍界定的本發明概念的精神以及範疇的情況下,可對例示性實施例進行形式以及細節上的各種改變。 While the exemplifying embodiments have been particularly shown and described in the foregoing, it will be understood by those skilled in the art that, without departing from the spirit and scope of the inventive concept as defined by the appended claims Various changes in form and detail are made to the illustrative embodiments.
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