TWI638434B - 電子組件封裝結構 - Google Patents

電子組件封裝結構 Download PDF

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Publication number
TWI638434B
TWI638434B TW107113089A TW107113089A TWI638434B TW I638434 B TWI638434 B TW I638434B TW 107113089 A TW107113089 A TW 107113089A TW 107113089 A TW107113089 A TW 107113089A TW I638434 B TWI638434 B TW I638434B
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TW
Taiwan
Prior art keywords
electronic component
conductive
holes
packaging structure
insulating substrate
Prior art date
Application number
TW107113089A
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English (en)
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TW201944552A (zh
Inventor
陳蓉萱
Original Assignee
國立臺灣師範大學
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Application filed by 國立臺灣師範大學 filed Critical 國立臺灣師範大學
Priority to TW107113089A priority Critical patent/TWI638434B/zh
Priority to US16/006,041 priority patent/US20190318985A1/en
Application granted granted Critical
Publication of TWI638434B publication Critical patent/TWI638434B/zh
Publication of TW201944552A publication Critical patent/TW201944552A/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Abstract

本發明係揭露一種電子組件封裝結構，包含一多孔性絕緣基板、一導電材、一第一電子組件、至少一第一導電凸塊、一第二電子組件與至少一第二導電凸塊。多孔性絕緣基板具有貫穿自身之複數通孔，每一通孔之孔徑大於0，且小於1微米，又導電材填滿所有通孔。第一電子組件位於多孔性絕緣基板之下方，以透過第一導電凸塊電性連接所有通孔中的導電材。第二電子組件位於多孔性絕緣基板之上方，以透過第二導電凸塊電性連接通孔中的導電材，進而電性連接第一電子組件。本發明能大幅降低焊錫橋接(bridge)發生的機率、焊錫假焊(non-wetting)或冷焊(cold joint)之機率與製造成本。

Description

電子組件封裝結構
本發明係關於一種封裝結構，且特別關於一種電子組件封裝結構。
半導體裝置使用於各種電子應用中，舉例而言，諸如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的製造通常是藉由在半導體基板上依序沉積絕緣層或介電層材料、導電層材料以及半導體層材料，接著使用微影製程圖案化所形成的各種材料層，藉以在此半導體基板之上形成電路零件及組件。通常在單一個半導體晶圓上製造許多積體電路，並且藉由沿著切割線在積體電路之間進行切割，以切割位在晶圓上的各個晶粒。舉例而言，接著將個別的晶粒分別封裝在多晶片模組中或其它類型的封裝結構中。
在一般封裝結構中，如第1圖所示，第一晶片(chip)10上設有複數個第一導電接墊12，第二晶片14上亦設有複數個第二導電接墊16，第一導電接墊12透過焊錫凸塊(solder bump)18電性連接第二導電接墊16，使第一晶片10電性連接第二晶片14。然而，在先進製程中，當焊錫凸塊18的間距愈小，愈容易發生鄰近的焊錫橋接(solder bridge)的現象，進而造成元件短路的問題。此外，由於一個第一導電接墊12只會透過一個焊錫凸塊18電性連接一個第二導電接墊16，若焊接技巧不好，則容易造成假焊或冷焊的現象，降低製程良率。
因此，本發明係在針對上述的困擾，提出一種電子組件封裝結構，以解決習知所產生的問題。
本發明的主要目的，在於提供一種電子組件封裝結構，其係利用多孔性絕緣基板限制焊錫流動與變形，以大幅降低焊錫橋接發生的機率。此外，一個導電凸塊連接數百個通孔中的焊錫，以減少焊錫假焊(non-wetting)或冷焊(cold joint)之機率與製造成本，並增加製程良率。
為達上述目的，本發明提供一種電子組件封裝結構，其係包含一多孔性絕緣基板、一導電材、一第一電子組件、至少一第一導電凸塊、一第二電子組件與至少一第二導電凸塊。多孔性絕緣基板具有貫穿自身之複數通孔。舉例來說，通孔之數量為數百個。每一通孔之孔徑大於0，且小於1微米，又導電材填滿所有通孔。第一電子組件位於多孔性絕緣基板之下方，以透過第一導電凸塊電性連接所有通孔中的導電材。第二電子組件位於多孔性絕緣基板之上方，以透過第二導電凸塊電性連接通孔中的導電材，進而電性連接第一電子組件。
在本發明之一實施例中，導電材為焊錫，例如為含錫之低熔點金屬、含錫之合金或含錫之金屬複合材料。
在本發明之一實施例中，所有通孔之數量為數百個。
在本發明之一實施例中，第一導電凸塊與第二導電凸塊為圓形或方形，且第一導電凸塊與第二導電凸塊之材質為銅、鋁、鎳或是含錫之低熔點金屬。
在本發明之一實施例中，第一導電凸塊之數量為複數個，每一第一導電凸塊電性連接所有通孔之數百個中的導電材。
在本發明之一實施例中，第二導電凸塊之數量為複數個，每一第二導電凸塊電性連接所有通孔之數百個中的導電材。
在本發明之一實施例中，多孔性絕緣基板之材質為氧化鋁(Al 2O 3)、二氧化矽(SiO 2)、聚甲基丙烯酸甲酯（PMMA）、聚碳酸酯（PC）或聚醯亞胺（PI）。
在本發明之一實施例中，第一電子組件與第二電子組件選自印刷電路板、中介層(interposer)或電子晶片。
茲為使　貴審查委員對本發明的結構特徵及所達成的功效更有進一步的瞭解與認識，謹佐以較佳的實施例圖及配合詳細的說明，說明如後：
本發明之實施例將藉由下文配合相關圖式進一步加以解說。盡可能的，於圖式與說明書中，相同標號係代表相同或相似構件。於圖式中，基於簡化與方便標示，形狀與厚度可能經過誇大表示。可以理解的是，未特別顯示於圖式中或描述於說明書中之元件，為所屬技術領域中具有通常技術者所知之形態。本領域之通常技術者可依據本發明之內容而進行多種之改變與修改。
以下請參閱第2圖與第3圖， 以介紹本發明之電子組件封裝結構之第一實施例。電子組件封裝結構包含一多孔性絕緣基板20、一導電材22、一第一電子組件24、至少一第一導電凸塊26、一第二電子組件28與至少一第二導電凸塊30，其中多孔性絕緣基板20之材質為氧化鋁(Al 2O 3)、二氧化矽(SiO 2)、聚甲基丙烯酸甲酯（PMMA）、聚碳酸酯（PC）或聚醯亞胺（PI），導電材22可為焊錫，例如為含錫之低熔點金屬、含錫之合金或含錫之金屬複合材料。金屬複合材料為金屬中添加非金屬材料，其中金屬的含量較非金屬材料多，用以增加該金屬之材料特性，例如增加導電性、散熱性或機械性質等特性。第一導電凸塊26與第二導電凸塊30可為圓形或方形，且第一導電凸塊26與第二導電凸塊30之材質可為銅、鋁、鎳或是含錫之低熔點金屬。多孔性絕緣基板20之厚度為0.5-200微米(um)。多孔性絕緣基板20具有貫穿自身之複數通孔32。每一通孔32之孔徑大於0，且小於1微米，又導電材22填滿所有通孔32。多孔性絕緣基板20限制焊錫流動與變形，以大幅降低焊錫橋接發生的機率。第一電子組件24位於多孔性絕緣基板20之下方，以透過第一導電凸塊26電性連接所有通孔32中的導電材22。第二電子組件28位於多孔性絕緣基板20之上方，以透過第二導電凸塊30電性連接通孔32中的導電材22，進而電性連接第一電子組件24。舉例來說，當第一導電凸塊26與第二導電凸塊30之數量分別為一時，通孔32之數量可為數百個。在第一實施例中，第一導電凸塊26之數量為複數個，每一第一導電凸塊26電性連接所有通孔32之數百個中的導電材22，第二導電凸塊30之數量亦為複數個，每一第二導電凸塊30電性連接所有通孔32之數百個中的導電材22。換言之，導電凸塊的尺寸係遠大於通孔32之尺寸，故一個導電凸塊可電性連接數百個通孔32中的焊錫，以減少焊錫假焊(non-wetting)或冷焊(cold joint)之機率與製造成本，並增加製程良率。銲錫是置於多孔性絕緣基板20當中，具有一定的厚度與機械強度，因此導電凸塊可以降低高度，節省材料的使用。
第一電子組件24與第二電子組件28選自印刷電路板、中介層(interposer)或電子晶片。在第一實施例中，第一電子組件24與第二電子組件28分別以印刷電路板34與中介層36為例。
以下請參閱第4圖與第5圖， 以介紹本發明之電子組件封裝結構之第二實施例。第二實施例與第一實施例之結構相同，於此不再贅述。第二實施例與第一實施例之差別僅在於第二電子組件28。在第二實施例中，第二電子組件28係以電子晶片38為例。
綜上所述，本發明利用多孔性絕緣基板限制焊錫流動與變形，以大幅降低焊錫橋接發生的機率。此外，一個導電凸塊連接數百個通孔中的焊錫，以減少焊錫假焊或冷焊之機率與製造成本，並增加製程良率。
以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
10‧‧‧第一晶片
12‧‧‧第一導電接墊
14‧‧‧第二晶片
16‧‧‧第二導電接墊
18‧‧‧焊錫凸塊
20‧‧‧多孔性絕緣基板
22‧‧‧導電材
24‧‧‧第一電子組件
26‧‧‧第一導電凸塊
28‧‧‧第二電子組件
30‧‧‧第二導電凸塊
32‧‧‧通孔
34‧‧‧印刷電路板
36‧‧‧中介層
38‧‧‧電子晶片
第1圖為先前技術之封裝結構之結構剖視圖。 第2圖為本發明之電子組件封裝結構之第一實施例之結構示意圖。 第3圖為本發明之電子組件封裝結構之第一實施例之結構分解圖。 第4圖為本發明之電子組件封裝結構之第二實施例之結構示意圖。 第5圖為本發明之電子組件封裝結構之第二實施例之結構分解圖。

Claims (8)

  1. 一種電子組件封裝結構，包含：一多孔性絕緣基板，具有貫穿自身之複數通孔，每一該通孔之孔徑大於0，且小於1微米，該些通孔之數量為數百個；一導電材，填滿該些通孔，該導電材為焊錫；一第一電子組件，位於該多孔性絕緣基板之下方，以透過至少一第一導電凸塊電性連接該些通孔中的該導電材；以及一第二電子組件，位於該多孔性絕緣基板之上方，以透過至少一第二導電凸塊電性連接該些通孔中的該導電材，進而電性連接該第一電子組件。
  2. 如請求項1所述之電子組件封裝結構，其中該焊錫為含錫之低熔點金屬、含錫之合金或含錫之金屬複合材料。
  3. 如請求項1所述之電子組件封裝結構，其中該至少一第一導電凸塊與該至少一第二導電凸塊為圓形或方形。
  4. 如請求項1所述之電子組件封裝結構，其中該至少一第一導電凸塊與該至少一第二導電凸塊之材質為銅、鋁、鎳或是含錫之低熔點金屬。
  5. 如請求項1所述之電子組件封裝結構，其中該至少一第一導電凸塊之數量為複數個，每一該第一導電凸塊電性連接該些通孔之數百個中的該導電材。
  6. 如請求項1所述之電子組件封裝結構，其中該至少一第二導電凸塊之數量為複數個，每一該第二導電凸塊電性連接該些通孔之數百個中的該導電材。
  7. 如請求項1所述之電子組件封裝結構，其中該多孔性絕緣基板之材質為氧化鋁(Al2O3)、二氧化矽(SiO2)、聚甲基丙烯酸甲酯(PMMA)、聚碳酸酯(PC)或聚醯亞胺(PI)。
  8. 如請求項1所述之電子組件封裝結構，其中該第一電子組件與該第二電子組件選自印刷電路板、中介層(interposer)或電子晶片。
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