TWI633533B - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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TWI633533B
TWI633533B TW106132498A TW106132498A TWI633533B TW I633533 B TWI633533 B TW I633533B TW 106132498 A TW106132498 A TW 106132498A TW 106132498 A TW106132498 A TW 106132498A TW I633533 B TWI633533 B TW I633533B
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sub
pixel
gate
data
electrically coupled
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TW106132498A
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TW201915995A (en
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紀佑旻
蘇松宇
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友達光電股份有限公司
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Priority to CN201711139339.XA priority patent/CN107909973B/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本發明提出一種液晶顯示裝置，液晶顯示裝置有複數條資料線、複數條閘極線、源極驅動電路、第一閘極驅動電路、第二閘極驅動電路、複數個解多工模組以及複數個畫素。每個畫素具有第一子畫素及第二子畫素；第一子畫素電性耦接第2N+1條的閘極線，第二子畫素電性耦接第2N條的閘極線，第一子畫素及第二子畫素的其中之一電性耦接第2M條的資料線，以及第一子畫素及第二子畫素的其中之另一電性耦接第2M+1條的資料線，第一子畫素和每一第二子畫素的極性彼此相反， M和N為正整數。The invention provides a liquid crystal display device. The liquid crystal display device has a plurality of data lines, a plurality of gate lines, a source driving circuit, a first gate driving circuit, a second gate driving circuit, a plurality of demultiplexing modules, and A plurality of pixels. Each pixel has a first sub-pixel and a second sub-pixel; the first sub-pixel is electrically coupled to the 2N + 1 gate line, and the second sub-pixel is electrically coupled to the 2N gate Epipolar line, one of the first subpixel and the second subpixel is electrically coupled to the 2M data line, and the other of the first subpixel and the second subpixel is electrically coupled In the 2M + 1 data line, the polarities of the first sub-pixel and each second sub-pixel are opposite to each other, and M and N are positive integers.

Description

液晶顯示裝置Liquid crystal display device

本發明係關於一種顯示技術，尤其是有關於一種液晶顯示裝置。The present invention relates to a display technology, and more particularly to a liquid crystal display device.

現今的高解析度液晶顯示器通常會增加解多工器在源極驅動電路以及資料線之間以解決源極驅動電路輸出埠(pin)數目不足的問題，同時也提高顯示器解析度，然而顯示器在兩個資料極性不同的資料訊號轉換期間，資料線會從正電壓瞬間轉換成負電壓，在大尺寸顯示器上容易產生資料線在充電時有阻容負載(RC Loading)過大造成阻容延遲(RC Delay)的問題，特別是在兩個畫面期間因此在顯示器會有顯示不均(Mura)的現象，此現象在大尺寸顯示器上猶為明顯。Today's high-resolution liquid crystal displays usually increase the demultiplexer between the source driving circuit and the data line to solve the problem of insufficient number of output pins of the source driving circuit, and also improve the display resolution. During the conversion of two data signals with different data polarities, the data line will instantly change from a positive voltage to a negative voltage. On a large-sized display, it is easy to generate a data line that has a large resistance load (RC loading) during charging and a resistance delay (RC) The problem of delay), especially during the two pictures, so there will be a phenomenon of display unevenness (Mura) on the display, this phenomenon is still obvious on large-sized displays.

本發明之一目的在提供一種液晶顯示裝置，其主要是提供一種畫素配置搭配驅動方法，藉由一個畫素區域包含第一子畫素與第二子畫素，在第一畫面期間，提供至第一子畫素的資料訊號為第一極性；在第二畫面期間，提供至第二子畫素的資料訊號為第二極性，使得資料線在兩個畫面期間轉換時，不需要進行資料訊號反轉，以解決液晶顯示裝置的資料線阻容負載過大造成阻容延遲的問題，特別是低溫多晶矽製程的液晶顯示裝置因負載大造成的阻容延遲。An object of the present invention is to provide a liquid crystal display device, which mainly provides a pixel configuration and driving method. A pixel area includes a first sub pixel and a second sub pixel. The data signal to the first sub-pixel is the first polarity; during the second frame, the data signal provided to the second sub-pixel is the second polarity, so that when the data line is switched between the two frames, no data is required. The signal is inverted to solve the problem of resistance-capacitance delay caused by too large resistance-capacitance load of the data line of the liquid crystal display device, especially the resistance-capacitance delay caused by the large load in the liquid crystal display device of the low-temperature polycrystalline silicon process.

本發明提出一種液晶顯示裝置，液晶顯示裝置包括有複數條資料線、複數條閘極線、源極驅動電路、第一閘極驅動電路、第二閘極驅動電路、複數個解多工模組以及畫素陣列。複數條資料線，包含複數條第2M條資料線及複數條第2M+1條資料線。複數條閘極線，包含複數條第2N條閘極線及複數條第2N+1條閘極線。源極驅動電路，電性耦接資料線，源極驅動電路包含複數個輸出埠以輸出資料訊號，並且相鄰兩條資料線傳輸的資料訊號彼此電壓極性不同。第一閘極驅動電路，電性耦接第2N+1條閘極線，用以輸出第一閘極驅動訊號。第二閘極驅動電路，電性耦接第2N條閘極線，用以輸出第二閘極驅動訊號。複數個解多工模組，電性耦接於源極驅動電路與資料線之間。畫素陣列，具有以陣列方式排列的複數個畫素，每一畫素具有第一子畫素及第二子畫素；其中，第一子畫素電性耦接第2N+1條的閘極線，第二子畫素電性耦接第2N條的閘極線，第一子畫素及第二子畫素的其中之一電性耦接第2M條的資料線，以及第一子畫素及第二子畫素的其中之另一電性耦接第2M+1條的資料線，其中每一第一子畫素和每一第二子畫素的極性彼此相反，且M和N為正整數。The invention provides a liquid crystal display device. The liquid crystal display device includes a plurality of data lines, a plurality of gate lines, a source driving circuit, a first gate driving circuit, a second gate driving circuit, and a plurality of demultiplexing modules. And pixel array. The plurality of data lines includes a plurality of 2M data lines and a plurality of 2M + 1 data lines. The plurality of gate lines includes a plurality of 2N gate lines and a plurality of 2N + 1 gate lines. The source driving circuit is electrically coupled to the data line. The source driving circuit includes a plurality of output ports to output data signals, and the data signals transmitted by two adjacent data lines have different voltage polarities from each other. The first gate driving circuit is electrically coupled to the 2N + 1 gate lines for outputting the first gate driving signal. The second gate driving circuit is electrically coupled to the 2N gate line for outputting a second gate driving signal. A plurality of demultiplexing modules are electrically coupled between the source driving circuit and the data line. The pixel array has a plurality of pixels arranged in an array, and each pixel has a first sub-pixel and a second sub-pixel; wherein the first sub-pixel is electrically coupled to the 2N + 1 gate The polar line, the second sub-pixel is electrically coupled to the 2N gate line, one of the first sub-pixel and the second sub-pixel is electrically coupled to the 2M data line, and the first sub-pixel The other of the pixel and the second sub-pixel is electrically coupled to the 2M + 1 data line, wherein the polarities of each first sub-pixel and each second sub-pixel are opposite to each other, and M and N is a positive integer.

在本發明之液晶顯示裝置中，其主要是提供一種畫素配置搭配驅動方法，藉由一個畫素區域包含第一子畫素與第二子畫素，在第一個畫面期間，提供至第一子畫素的資料訊號為第一極性；在第二畫面期間，提供至第二子畫素的資料訊號為第二極性，使得資料線在兩個畫面期間轉換時，不需要進行資料訊號反轉，以解決液晶顯示裝置的資料線阻容負載過大造成阻容延遲的問題，特別是低溫多晶矽製程的液晶顯示裝置因負載大造成的阻容延遲。In the liquid crystal display device of the present invention, it mainly provides a pixel configuration and driving method. A pixel area includes a first sub-pixel and a second sub-pixel, and is provided to a first sub-pixel during a first frame period. The data signal of a sub-pixel is the first polarity; during the second frame, the data signal provided to the second sub-pixel is the second polarity, so that when the data line is switched between the two frames, the data signal does not need to be inverted. In order to solve the problem of resistance-capacitance delay caused by too large resistance-capacitance load of the data line of the liquid crystal display device, especially the resistance-capacitance delay caused by the large-load in the liquid crystal display device of the low-temperature polycrystalline silicon process.

為了讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings, as follows.

圖1繪有依照本發明一實施例之液晶顯示裝置的電路示意圖。如圖1所示，本發明提出一種液晶顯示裝置100，此液晶顯示裝置100例如是低溫多晶矽顯示面板(Low Temperature Poly-silicon，LTPS)，但本發明不以此為限，液晶顯示裝置100包括有資料線D 1-D 4、閘極線G 0-G 5、源極驅動電路11、閘極驅動電路12、閘極驅動電路13、解多工模組14以及畫素陣列15。如圖1所示閘極驅動電路12及閘極驅動電路13分布於畫素陣列15的相對兩側，本發明並不以此為限。 FIG. 1 is a schematic circuit diagram of a liquid crystal display device according to an embodiment of the present invention. As shown in FIG. 1, the present invention provides a liquid crystal display device 100. The liquid crystal display device 100 is, for example, a low temperature poly-silicon (LTPS) display panel, but the present invention is not limited thereto. The liquid crystal display device 100 includes There are data lines D 1 -D 4 , gate lines G 0 -G 5 , source driving circuit 11, gate driving circuit 12, gate driving circuit 13, demultiplexing module 14 and pixel array 15. As shown in FIG. 1, the gate driving circuit 12 and the gate driving circuit 13 are distributed on opposite sides of the pixel array 15, and the present invention is not limited thereto.

源極驅動電路11可透過解多工模組14電性耦接資料線D 1-D 4，源極驅動電路11包含複數個輸出埠用以輸出資料訊號至解多工模組14，並且相鄰兩條資料線D 1與D 2傳輸的資料訊號彼此電壓極性不同，意即當第2M+1條資料線(奇數條資料線)傳輸的資料訊號為正電壓，第2M條資料線(偶數條資料線)傳輸的資料訊號則是負電壓，反之亦然。閘極驅動電路12電性耦接第2N+1條閘極線(奇數條閘極線)，用以輸出閘極驅動訊號G 1、G 3及G 5。閘極驅動電路13電性耦接第2N條閘極線(偶數條閘極線)，用以輸出閘極驅動訊號G 0、G 2及G 4。解多工模組14電性耦接於源極驅動電路11與資料線D 1-D 4之間。畫素陣列15以陣列方式排列，每一畫素P1具有子畫素151及152。子畫素151電性耦接第2N+1條的閘極線，子畫素152電性耦接第2N條的閘極線，子畫素151及152的其中之一電性耦接第2M條的資料線，以及子畫素151及152的其中之另一電性耦接第2M+1條的資料線，其中提供至子畫素151及152的資料訊號極性彼此相反，且M和N為正整數。當子畫素151依據第2M條的資料線提供的資料訊號被驅動，則子畫素152依據第2M+1條的資料線上傳輸的資料訊號而被驅動以顯示畫面。當子畫素151依據第2M+1條的資料線上傳輸的資料訊號而被驅動，則子畫素152也是依據第2M條的資料線上傳輸的資料訊號而被驅動以顯示畫面。 The source driving circuit 11 can be electrically coupled to the data lines D 1 -D 4 through the demultiplexing module 14. The source driving circuit 11 includes a plurality of output ports for outputting data signals to the demultiplexing module 14. The data signals transmitted by two adjacent data lines D 1 and D 2 have different voltage polarities, which means that when the data signal transmitted by the 2M + 1 data line (odd data line) is a positive voltage, the data signal transmitted by the 2M data line (even number) Data lines) are transmitted with a negative voltage and vice versa. The gate driving circuit 12 is electrically coupled to the 2N + 1 gate lines (odd number of gate lines) for outputting the gate driving signals G 1 , G 3 and G 5 . The gate driving circuit 13 is electrically coupled to the 2N gate lines (even gate lines) for outputting the gate driving signals G 0 , G 2 and G 4 . The demultiplexing module 14 is electrically coupled between the source driving circuit 11 and the data lines D 1 -D 4 . The pixel array 15 is arranged in an array. Each pixel P1 has sub-pixels 151 and 152. Subpixel 151 is electrically coupled to the 2N + 1 gate line, subpixel 152 is electrically coupled to the 2N gate line, and one of the subpixels 151 and 152 is electrically coupled to the 2M Data lines, and the other one of the sub-pixels 151 and 152 is electrically coupled to the 2M + 1 data line, in which the data signals provided to the sub-pixels 151 and 152 have opposite polarities, and M and N Is a positive integer. When the sub-pixel 151 is driven according to the data signal provided by the data line of the 2M line, the sub-pixel 152 is driven according to the data signal transmitted by the data line of the 2M + 1 line to be displayed. When the sub-pixel 151 is driven according to the data signal transmitted on the data line of the 2M + 1, the sub-pixel 152 is also driven to display the screen according to the data signal transmitted on the data line of the 2M.

接著說明解多工模組14，請繼續參考圖1，解多工模組14包括解多工器141及142，解多工器141電性耦接源極驅動電路11的輸出埠的其中之一以及資料線D 1及D 3，用以將從源極驅動電路11饋入之資料訊號分配至資料線D 1及D 3；以及解多工器142電性耦接源極驅動電路11的輸出埠的其中之另一以及資料線D 2及D 4，用以將從源極驅動電路11饋入之資料訊號分配至資料線D 2及D 4。在本發明的實施例中，是採用一對二的解多工器，一個源極驅動電路11的輸出埠對應兩條資料線，本發明的解多工器是指輸出固定極性的電壓並且與間隔一條的資料線耦接，舉例而言，解多工器141是與資料線D 1及D 3耦接並且輸出負極性電壓，解多工器142是與資料線D 2及D 4耦接並且輸出正極性電壓，因此此架構可以到畫素間正負極性的切換。 Next, the demultiplexing module 14 will be described. Please continue to refer to FIG. 1. The demultiplexing module 14 includes demultiplexers 141 and 142, and the demultiplexer 141 is electrically coupled to one of the output ports of the source driving circuit 11. First, the data lines D 1 and D 3 are used to distribute the data signals fed from the source driving circuit 11 to the data lines D 1 and D 3 ; and the demultiplexer 142 is electrically coupled to the source driving circuit 11 The other of the output ports and the data lines D 2 and D 4 are used to distribute the data signals fed from the source driving circuit 11 to the data lines D 2 and D 4 . In the embodiment of the present invention, a one-to-two demultiplexer is used. The output port of one source driving circuit 11 corresponds to two data lines. The demultiplexer of the present invention refers to a voltage with a fixed polarity and is connected to One data line is coupled. For example, the demultiplexer 141 is coupled to the data lines D 1 and D 3 and outputs a negative polarity voltage. The demultiplexer 142 is coupled to the data lines D 2 and D 4 And it outputs a positive polarity voltage, so this architecture can switch the positive and negative polarity between pixels.

請參考圖2，圖2為依照本發明一實施例之液晶顯示裝置的子畫素配置示意圖。圖2並未繪出源極驅動電路11、第一閘極驅動電路12、第二閘極驅動電路13、解多工模組14等元件，僅繪出資料線D 1、D 2及D 3、閘極線G 0、G 1、G 2及G 3、畫素P1、P1’與子畫素151及152，但並不影響本實施例的操作。在圖2的範例中，僅以畫素P1及 P1’內的子畫素151及152舉例說明，本領域具有通常知識者，應可以從以下敘述推之其他子畫素與閘極線和資料線的耦接關係，本說明書不再贅述。接著說明每一畫素P1包含的子畫素151及152，子畫素151包括電晶體T1及液晶電容C1。電晶體T1的源極端電性耦接資料線D 1，電晶體T1的閘極端電性耦接閘極線G 1，液晶電容C1電性耦接該電晶體T1的汲極端。子畫素152包括電晶體T2及液晶電容C2。電晶體T2的源極端電性耦接資料線D 2，電晶體T2的閘極端電性耦接閘極線G 2，液晶電容C2電性耦接電晶體T2的汲極端。其中資料線D 1與資料線D 2提供的資料訊號極性不同。然而畫素矩陣15內的其他畫素P1之子畫素配置亦可有所變化，例如是下一列畫素P1’的子畫素151可耦接資料線D2而子畫素152可耦接資料線D1，以此種方式配置畫素P1’所提供的資料訊號極性仍為不同。因此本發明不以圖2所繪示的子畫素配置為限，只要是在畫素P1內提供給子畫素151跟子畫素152的資料訊號極性不同即可完成本發明。 Please refer to FIG. 2, which is a schematic diagram of a sub-pixel configuration of a liquid crystal display device according to an embodiment of the present invention. FIG 2 depicts No source driving circuit 11, a first gate driving circuit 12, a second gate driving circuit 13, de-multiplexing module 14 and other components, only shows data line D 1, D 2 and D 3 , Gate lines G 0 , G 1 , G 2, and G 3 , pixels P1, P1 ′, and sub-pixels 151 and 152, but do not affect the operation of this embodiment. In the example in FIG. 2, only the sub-pixels 151 and 152 in the pixels P1 and P1 'are used as examples. Those with ordinary knowledge in the field should be able to infer other sub-pixels and gate lines and data from the following description. The coupling relationship of the wires is not described in this specification. Next, the sub-pixels 151 and 152 included in each pixel P1 are described. The sub-pixel 151 includes a transistor T1 and a liquid crystal capacitor C1. The source terminal of transistor T1 is electrically coupled to data lines D 1, the gate terminal of transistor T1 is electrically coupled to the gate line G 1, the liquid crystal capacitor C1 is electrically coupled to the drain terminal of the transistor T1. The sub-pixel 152 includes a transistor T2 and a liquid crystal capacitor C2. The source terminal of transistor T2 is electrically coupled to data lines D 2, the gate terminal of transistor T2 is electrically coupled to the gate line G 2, the liquid crystal capacitor C2 is electrically coupled to the drain terminal of transistor T2. The data lines D 1 and D 2 provide data signals with different polarities. However, the sub-pixel configuration of other pixels P1 in the pixel matrix 15 may also be changed. For example, the sub-pixel 151 of the next pixel P1 'may be coupled to the data line D2 and the sub-pixel 152 may be coupled to the data line. D1, the polarity of the data signal provided by the pixel P1 'configured in this way is still different. Therefore, the present invention is not limited to the sub-pixel configuration shown in FIG. 2, as long as the data signals provided to the sub-pixel 151 and the sub-pixel 152 in the pixel P1 have different polarities, the present invention can be completed.

請繼續參考圖2，接著說明畫素P1及子畫素151及152的耦接關係及操作，子畫素151是連接到資料線D 1以及閘極線G 1，子畫素152是連接到資料線D 2以及閘極線G 2，接著一個畫面期間導通一組閘極線(奇數組閘極線一組，偶數組閘極線一組)，因此如果閘極線G 1、G 3導通，資料線D 1將負極性資料訊號輸入至子畫素151，畫素P1此時為負極性。然而當下一個畫面期間時，導通另一組閘極線，因此閘極線G 0、G 2導通，資料線D 2將正極性資料訊號輸入至子畫素152，畫素P1此時即為正極性。因此由此實施例可以看出畫素P1的極性可以隨著幀的轉換，而有正負極性的切換，但資料線D 1、D 2及D 3只需要輸出固定極性的資料訊號(意即充正電荷或負電荷)即可，不需要做正負極性的切換。 Please continue to refer to FIG. 2, and then explain the coupling relationship and operation of the pixel P1 and the sub-pixels 151 and 152. The sub-pixel 151 is connected to the data line D 1 and the gate line G 1. The sub-pixel 152 is connected to Data line D 2 and gate line G 2 , and a set of gate lines are turned on during one screen (one set of odd gate lines and one set of even gate lines), so if the gate lines G 1 and G 3 are turned on The data line D 1 inputs the negative polarity data signal to the sub-pixel 151, and the pixel P1 is now the negative polarity. However, during the next screen period, another set of gate lines is turned on, so the gate lines G 0 and G 2 are turned on, and the data line D 2 inputs the positive data signal to the sub-pixel 152, and the pixel P1 is now the positive electrode. Sex. Therefore, it can be seen from this embodiment that the polarity of the pixel P1 can be switched with the polarity of the frame as the frame is switched, but the data lines D 1 , D 2 and D 3 only need to output data signals of a fixed polarity (meaning charging Positive charge or negative charge), there is no need to switch between positive and negative polarity.

請繼續參考圖2，本發明的閘極線配置是由奇數組閘極線與偶數組閘極線彼此平行交錯設置，第2N+1條的閘極線與第2N條的閘極線兩者之間具有距離d1，第2N+1條的閘極線與第2N+2條的閘極線兩者之間具有距離d2，而距離d1小於距離d2。由圖2所示的範例中可以看出，閘極線G 0與閘極線G 1之間的距離d1小於閘極線G 1與閘極線G 2之間的距離d2，然此並非用以限制本發明。本發明的閘極線配置特徵在於，多加了一組閘極線但在不影響畫素開口率的情況下，奇數組閘極線的其中之一會與偶數組閘極線的其中之一間隔一距離，並且與偶數組閘極線的其中之另一間隔另一距離，偶數組閘極線的配置情況與奇數組相同，在此不再贅述。 Please continue to refer to FIG. 2, the gate line configuration of the present invention is an odd array gate line and an even array gate line are staggered in parallel to each other, both the 2N + 1 gate line and the 2N gate line There is a distance d1 between them, there is a distance d2 between the gate line of the 2N + 1th and the gate line of the 2N + 2, and the distance d1 is less than the distance d2. It can be seen from the example shown in FIG. 2 that the distance d1 between the gate line G 0 and the gate line G 1 is smaller than the distance d2 between the gate line G 1 and the gate line G 2 , but this is not a use To limit the invention. The gate line configuration of the present invention is characterized in that an additional set of gate lines is added but without affecting the pixel aperture ratio, one of the odd-numbered gate lines is spaced from one of the even-numbered gate lines One distance, and another distance from the other of the even array gate lines, the arrangement of the even array gate lines is the same as the odd array, and is not repeated here.

接著請一併參考圖2及圖3，圖3為依照本發明一實施例之液晶顯示裝置的時序圖。由圖2及圖3的範例中可知，在第一個畫面期間時是由閘極線G 1(奇數組閘極線)上所傳送的閘極驅動訊號來導通每一個畫素P1的子畫素151，接著在最後一條閘極線G 2N+1驅動完畢後，繼續第二畫面期間，在第二個畫面期間由閘極線G 2(偶數組閘極線)上所傳送的閘極驅動訊號來導通每一個畫素P1的子畫素152。請再參考圖2及圖3，在第一個畫面期間時資料線D 1提供負極性資料訊號至子畫素151，資料線D 2提供正極性資料訊號至畫素P1’的子畫素151，畫素P1此時為負極性，而畫素 P1’此時為正極性，而在第二個畫面期間時資料線D 2提供正極性資料訊號至子畫素152，畫素P1此時為正極性，由此可看出資料線D 2係分時提供正極性資料訊號至畫素P1的子畫素151及畫素P1’的子畫素152，搭配在不同畫面期間時奇數組閘極線及偶數組閘極線會輪流導通子畫素151、152，使得資料線可以只輸出固定極性的資料訊號，但可讓畫素P1的子畫素151與子畫素152不同極性的切換。 Please refer to FIG. 2 and FIG. 3 together. FIG. 3 is a timing diagram of a liquid crystal display device according to an embodiment of the present invention. As can be seen from the examples in FIG. 2 and FIG. 3, during the first frame period, the gate driving signal transmitted on the gate line G 1 (odd array gate line) is used to turn on the sub-picture of each pixel P1. Prime 151, after the last gate line G 2N + 1 is driven, the second frame period is continued, and the second gate period is driven by the gate transmitted on the gate line G 2 (even gate line). The signal is used to turn on the sub-pixel 152 of each pixel P1. Please refer to FIG. 2 and FIG. 3 again. During the first picture period, the data line D 1 provides a negative polarity data signal to the sub-pixel 151, and the data line D 2 provides a positive polarity data signal to the sub-pixel 151 of the pixel P1 '. The pixel P1 is negative, and the pixel P1 ′ is positive, and the data line D 2 provides a positive data signal to the sub-pixel 152 during the second frame period. The pixel P1 is now The positive polarity, it can be seen that the data line D 2 provides the positive polarity data signal to the sub-pixel 151 of the pixel P1 and the sub-pixel 152 of the pixel P1 ′ in time sharing, with the odd array gates in different picture periods. The lines and even array gate lines will turn on the sub-pixels 151 and 152 in turn, so that the data line can only output data signals of a fixed polarity, but the sub-pixels 151 and 152 of the pixel P1 can be switched with different polarities.

綜上所述，由於本發明之液晶顯示裝置中，利用兩組閘極線以及兩個子畫素共用一個畫素區域，在一個畫面期間的時間內驅動奇數組閘極線，在下一個畫面期間的時間內驅動偶數組閘極線，使得頻率轉換間可以讓畫素內部極性反轉，但資料線不需要做不同極性的電壓轉換只需要充固定極性的電壓(例如：0V~5V或0V~-5V)，相較於原本的電壓範圍(例如：-5V~5V)，本發明除了可以降低電源的供應外，也解決資料線阻容負載過大造成阻容延遲而產生在顯示裝置會有顯示不均現象的問題。In summary, since the liquid crystal display device of the present invention uses two sets of gate lines and two sub-pixels to share a pixel area, the odd-numbered gate lines are driven in one frame period, and in the next frame period The gate line of the even array is driven within a period of time, so that the internal polarity of the pixel can be reversed between frequency conversions, but the data line does not need to perform voltage conversion of different polarities, but only needs to charge a fixed polarity voltage (for example: 0V ~ 5V or 0V ~ -5V), compared with the original voltage range (for example: -5V ~ 5V), in addition to reducing the power supply, the present invention also solves the resistance-capacitance delay caused by the data line resistance-capacity load being too large, which will cause a display on the display device. The problem of unevenness.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技術者，在不脫離本發明之精神和範圍內，當可做些許之更動與潤飾，因此本發明之保護範圍當視後付之申請專利範圍所界定者為準。Although the present invention has been disclosed as above by way of example, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the post-paid application patent scope.

100‧‧‧液晶顯示裝置
11‧‧‧源極驅動電路
12、13‧‧‧閘極驅動電路
14‧‧‧解多工模組
141、142‧‧‧解多工器
15‧‧‧畫素陣列
151、152‧‧‧子畫素
T1、T2‧‧‧電晶體
C1、C2‧‧‧液晶電容
P1、P1’‧‧‧畫素
D1、D2、D3、D4‧‧‧資料線
G0、G1、G2、G3、G4、G5、G2N、G2N+1‧‧‧閘極線
d1、d2‧‧‧距離100‧‧‧LCD display device
11‧‧‧Source driving circuit
12, 13‧‧‧Gate driving circuit
14‧‧‧Demultiplexing Module
141, 142‧‧‧ Demultiplexer
15‧‧‧ pixel array
151, 152‧‧‧ sub pixels
T1, T2‧‧‧Transistors
C1, C2‧‧‧ LCD Capacitor
P1, P1'‧‧‧ pixels
D 1 , D 2 , D 3 , D 4 ‧‧‧ data cable
G 0 , G 1 , G 2 , G 3 , G 4 , G 5 , G 2N , G 2N + 1 ‧‧‧ gate line
d1, d2‧‧‧ distance

圖1為依照本發明一實施例之液晶顯示裝置的電路示意圖； 圖2為依照本發明一實施例之液晶顯示裝置的示意圖；以及 圖3為依照本發明一實施例之液晶顯示裝置的時序圖。1 is a schematic circuit diagram of a liquid crystal display device according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a liquid crystal display device according to an embodiment of the present invention; and FIG. 3 is a timing diagram of the liquid crystal display device according to an embodiment of the present invention .

Claims (8)

一種液晶顯示裝置，包括： 複數條資料線，包含複數條第2M條資料線及複數條第2M+1條資料線； 複數條閘極線，包含複數條第2N條閘極線及複數條第2N+1條閘極線； 一源極驅動電路，電性耦接該些資料線，該源極驅動電路包含複數個輸出埠以輸出該些資料訊號，並且相鄰兩條該些資料線傳輸的該些資料訊號彼此電壓極性不同； 一第一閘極驅動電路，電性耦接該些第2N+1條閘極線，用以輸出複數個第一閘極驅動訊號； 一第二閘極驅動電路，電性耦接該些第2N條閘極線，用以輸出複數個第二閘極驅動訊號； 複數個解多工模組，電性耦接於該源極驅動電路與該些資料線之間；以及 一畫素陣列，具有以陣列方式排列的複數個畫素，每一該些畫素具有一第一子畫素及一第二子畫素； 其中，該第一子畫素電性耦接第2N+1條的閘極線，該第二子畫素電性耦接第2N條的閘極線，該第一子畫素及該第二子畫素的其中之一電性耦接第2M條的資料線，以及該第一子畫素及該第二子畫素的其中之另一電性耦接第2M+1條的資料線，其中提供至每一該些第一子畫素和每一該些第二子畫素的資料訊號極性彼此相反，且M和N為正整數。A liquid crystal display device includes: a plurality of data lines including a plurality of 2M data lines and a plurality of 2M + 1 data lines; a plurality of gate lines including a plurality of 2N gate lines and a plurality of data lines 2N + 1 gate lines; a source drive circuit electrically coupled to the data lines, the source drive circuit includes a plurality of output ports to output the data signals, and two adjacent data lines transmit The data signals have different voltage polarities from each other; a first gate driving circuit is electrically coupled to the 2N + 1 gate lines for outputting a plurality of first gate driving signals; a second gate A driving circuit electrically coupled to the 2N gate lines for outputting a plurality of second gate driving signals; a plurality of demultiplexing modules electrically coupled to the source driving circuit and the data Between lines; and a pixel array having a plurality of pixels arranged in an array, each of the pixels having a first sub-pixel and a second sub-pixel; wherein the first sub-pixel Electrically coupled to the 2N + 1 gate line, the The two sub-pixels are electrically coupled to the 2N gate line, one of the first sub-pixel and the second sub-pixel are electrically coupled to the 2M data line, and the first sub-pixel And another one of the second sub-pixels is electrically coupled to the 2M + 1 data line, wherein data signals are provided to each of the first sub-pixels and each of the second sub-pixels The polarities are opposite to each other, and M and N are positive integers. 如申請專利範圍第1項所述之液晶顯示裝置，其中該第一子畫素包括： 一第一電晶體，其源極端電性耦接第2M+1條的資料線或第2M條的資料線，其閘極端電性耦接第2N+1條的閘極線；以及 一第一液晶電容，電性耦接該第一電晶體的汲極端。The liquid crystal display device according to item 1 of the scope of patent application, wherein the first sub-pixel includes: a first transistor whose source terminal is electrically coupled to the 2M + 1 data line or the 2M data Line, its gate terminal is electrically coupled to the 2N + 1 gate line; and a first liquid crystal capacitor is electrically coupled to the drain terminal of the first transistor. 如申請專利範圍第1項所述之液晶顯示裝置，其中該第二子畫素包括： 一第二電晶體，其源極端電性耦接第2M+1條的資料線或第2M條的資料線，其閘極端電性耦接第2N條的閘極線；以及 一第二液晶電容，電性耦接該第二電晶體的汲極端。The liquid crystal display device according to item 1 of the scope of patent application, wherein the second sub-pixel includes: a second transistor whose source terminal is electrically coupled to the 2M + 1 data line or the 2M data Line, whose gate terminal is electrically coupled to the 2N gate line; and a second liquid crystal capacitor, which is electrically coupled to the drain terminal of the second transistor. 如申請專利範圍第1項所述之液晶顯示裝置，其中複數個解多工模組包括： 一第一解多工器，電性耦接該源極驅動電路該些輸出埠的其中之一以及第2M+1條的資料線，用以將從該源極驅動電路饋入之該些資料訊號分配至第2M+1條的資料線；以及 一第二解多工器，電性耦接該源極驅動電路該些輸出埠的其中之另一以及第2M條的資料線，用以將從該源極驅動電路饋入之該些資料訊號分配至第2M條的資料線。According to the liquid crystal display device described in item 1 of the scope of patent application, the plurality of demultiplexing modules include: a first demultiplexer, which is electrically coupled to one of the output ports of the source driving circuit and The 2M + 1 data line is used to distribute the data signals fed from the source driving circuit to the 2M + 1 data line; and a second demultiplexer is electrically coupled to the The other of the output ports of the source driving circuit and the 2M data line are used to distribute the data signals fed from the source driving circuit to the 2M data line. 如申請專利範圍第1項所述之液晶顯示裝置，其中第2N+1條的閘極線與第2N條的閘極線彼此平行交錯設置，並且兩者之間具有一第一距離，第2N+1條的閘極線與第2N+2條的閘極線彼此之間具有一第二距離，而該第一距離小於該第二距離。The liquid crystal display device according to item 1 of the scope of patent application, wherein the gate lines of the 2N + 1th and the gate lines of the 2Nth are staggered in parallel with each other, and there is a first distance between the two, the 2N The +1 gate lines and the 2N + 2 gate lines have a second distance from each other, and the first distance is smaller than the second distance. 如申請專利範圍第1項所述之液晶顯示裝置，其中該些第一閘極驅動訊號的致能時間先於該些第二閘極驅動訊號的致能時間，當該些第一閘極驅動訊號致能時，該第一子畫素根據在第2M+1條的資料線上所傳輸的資料而被驅動，當該些第二閘極驅動訊號致能時，該第二子畫素根據在第2M條的資料線上所傳輸的資料而被驅動。According to the liquid crystal display device described in item 1 of the scope of patent application, the enabling time of the first gate driving signals is earlier than the enabling time of the second gate driving signals. When the signal is enabled, the first sub-pixel is driven according to the data transmitted on the 2M + 1 data line. When the second gate driving signals are enabled, the second sub-pixel is driven based on the The data transmitted on the 2M data line is driven. 如申請專利範圍第1項所述之液晶顯示裝置，其中該些第一閘極驅動訊號的致能時間先於該些第二閘極驅動訊號的致能時間，當該些第一閘極驅動訊號致能時，該第一子畫素根據在第2M條的資料線上所傳輸的資料而被驅動，當該些第二閘極驅動訊號致能時，該第二子畫素根據在第2M+1條的資料線上所傳輸的資料而被驅動。According to the liquid crystal display device described in item 1 of the scope of patent application, the enabling time of the first gate driving signals is earlier than the enabling time of the second gate driving signals. When the signal is enabled, the first sub-pixel is driven according to the data transmitted on the data line of Article 2M. When the second gate driving signals are enabled, the second sub-pixel is driven according to the 2M The data transmitted on the +1 data line is driven. 如申請專利範圍第1項所述之液晶顯示裝置，其中在第一閘極驅動訊號致能時該些畫素的極性與在第二閘極驅動訊號致能時該些畫素的極性相反。 The liquid crystal display device according to item 1 of the scope of patent application, wherein the polarities of the pixels when the first gate driving signal is enabled are opposite to the polarities of the pixels when the second gate driving signal is enabled.
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