TWI626655B - Memory device, word line decoder and operating method of memory device - Google Patents
Memory device, word line decoder and operating method of memory device Download PDFInfo
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Abstract
一種記憶體裝置、字元線解碼器及記憶體裝置之操作方法。字元線解碼器包括數個字元線驅動器。各個字元線驅動器具有一輸入端及一輸出端。該輸出端電性連接於該些字元線之其中之一。各該字元線驅動器包括一拉升電晶體、一下拉電晶體及一中間電晶體。該拉升電晶體提供一第一字元線電壓至已選擇之該些字元線之其中之一。該下拉電晶體提供一第二字元線電壓至未選擇之其餘該些字元線。該未選擇電壓高於該選擇電壓。該中間電晶體電性連接於該輸入端及該下拉電晶體，以降低提供至該下拉電晶體之該未選擇電壓。 A memory device, a word line decoder, and a method of operating a memory device. The word line decoder includes a number of word line drivers. Each word line driver has an input and an output. The output is electrically connected to one of the word lines. Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor. The pull-up transistor provides a first word line voltage to one of the selected word lines. The pull-down transistor provides a second word line voltage to the remaining of the word lines that are not selected. The unselected voltage is higher than the selected voltage. The intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor.
Description
本發明是有關於一種記憶體裝置、字元線解碼器及記憶體裝置之操作方法。 The present invention relates to a memory device, a word line decoder, and a method of operating a memory device.
隨著儲存技術的發展，各式記憶體不斷推陳出新。在記憶體中，數條字元線電性連接於一記憶胞陣列。在編程或讀取記憶體時，字元線之其中之一被選擇，其餘字元線則未被選擇。自操作過程中，未選擇之字元線被施加0V。為了下拉施加於未選擇字元線的電壓至0V。電性連接於未選擇字元線之字元線驅動器必須被施加高電壓，以開啟字元線驅動器之NMOS電晶體。因此，NMOS電晶體必須承受閘極高電壓(gate stress)。 With the development of storage technology, all kinds of memory are constantly being updated. In the memory, a plurality of word lines are electrically connected to a memory cell array. When programming or reading a memory, one of the word lines is selected and the remaining word lines are not selected. During the self-operation, the unselected word line is applied with 0V. In order to pull down the voltage applied to the unselected word line to 0V. The word line driver electrically connected to the unselected word line must be applied with a high voltage to turn on the NMOS transistor of the word line driver. Therefore, the NMOS transistor must withstand the gate stress.
請參照第1圖，其繪示NMOS電晶體承受閘極高電壓後的示意圖。在初始狀態時，NMOS電晶體具有一原始電流-電壓曲線C1。在承受一段時間的閘極高電壓後，NMOS電晶體具有一已變化電流-電壓曲線C2。從已變化電流-電壓曲線C2與原始電流 -電壓曲線C1的比較來看，長時間的閘極高壓已經造成斷路電流(OFF-current,Ioff)明顯的增加且造成導通電流(ON-current,Ion)明顯的下降。因此，如何改善此情況，已成為一項重要議題。 Please refer to FIG. 1 , which is a schematic diagram of the NMOS transistor after receiving the gate high voltage. In the initial state, the NMOS transistor has an original current-voltage curve C1. After being subjected to a gate high voltage for a period of time, the NMOS transistor has a changed current-voltage curve C2. From the changed current-voltage curve C2 and the original current - Comparison of the voltage curve C1, the long-term gate high voltage has caused a significant increase in the off-current (Ioff) and caused a significant drop in the ON-current (Ion). Therefore, how to improve this situation has become an important issue.
本發明係有關於一種記憶體裝置、字元線解碼器及其操作方法，其利用一中間電晶體來降低提供之高電壓，以避免閘極高電壓(gate stress)的情況。 The present invention relates to a memory device, a word line decoder, and a method of operating the same that utilizes an intermediate transistor to reduce the high voltage supplied to avoid gate stress.
根據本發明之一方面，提出一種記憶體裝置。記憶體裝置包括一記憶胞陣列及一字元線解碼器。記憶胞陣列包括數條字元線(word line)。字元線解碼器包括數個字元線驅動器。各個字元線驅動器具有一輸入端及一輸出端。該輸出端電性連接於該些字元線之其中之一。各該字元線驅動器包括一拉升電晶體(pull-up transistor)、一下拉電晶體(pull-down transistor)及一中間電晶體。該拉升電晶體電性連接於該輸入端及該輸出端。若藉由施加一選擇電壓使該拉升電晶體被開啟，則該拉升電晶體透過該輸出端提供一第一字元線電壓至已選擇之該些字元線之其中之一。該下拉電晶體電性連接於該輸入端及該輸出端。若藉由施加一未選擇電壓使該下拉電晶體被開啟，則該下拉電晶體透過該輸出端提供一第二字元線電壓至未選擇之其餘該些字元線。該未選擇電壓高於該選擇電壓。該中間電晶體電性連接於該輸入端及該下拉電晶體，以降低提供至該下拉電晶體之該未選擇電壓。 According to an aspect of the invention, a memory device is proposed. The memory device includes a memory cell array and a word line decoder. The memory cell array includes a number of word lines. The word line decoder includes a number of word line drivers. Each word line driver has an input and an output. The output is electrically connected to one of the word lines. Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor. The pull-up transistor is electrically connected to the input end and the output end. If the pull-up transistor is turned on by applying a selection voltage, the pull-up transistor provides a first word line voltage through the output terminal to one of the selected word lines. The pull-down transistor is electrically connected to the input end and the output end. If the pull-down transistor is turned on by applying an unselected voltage, the pull-down transistor provides a second word line voltage through the output terminal to the remaining selected word lines. The unselected voltage is higher than the selected voltage. The intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor.
根據本發明之另一方面，提出一種字元線解碼器。字元線解碼器包括數個字元線驅動器。各該字元線驅動器具有一輸入端及一輸出端。該輸出端電性連接於數條字元線之其中之一。各該字元線驅動器包括一拉升電晶體(pull-up transistor)、一下拉電晶體(pull-down transistor)及一中間電晶體。該拉升電晶體電性連接於該輸入端及該輸出端。若藉由施加一選擇電壓使該拉升電晶體被開啟，則該拉升電晶體透過該輸出端提供一第一字元線電壓至已選擇之該些字元線之其中之一。該下拉電晶體電性連接於該輸入端及該輸出端。若藉由施加一未選擇電壓使該下拉電晶體被開啟，則該下拉電晶體透過該輸出端提供一第二字元線電壓至未選擇之其餘該些字元線，該未選擇電壓高於該選擇電壓。該中間電晶體電性連接於該輸入端及該下拉電晶體，以降低提供至該下拉電晶體之該未選擇電壓。 According to another aspect of the present invention, a word line decoder is proposed. The word line decoder includes a number of word line drivers. Each of the word line drivers has an input and an output. The output is electrically connected to one of the plurality of word lines. Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor. The pull-up transistor is electrically connected to the input end and the output end. If the pull-up transistor is turned on by applying a selection voltage, the pull-up transistor provides a first word line voltage through the output terminal to one of the selected word lines. The pull-down transistor is electrically connected to the input end and the output end. If the pull-down transistor is turned on by applying an unselected voltage, the pull-down transistor provides a second word line voltage through the output terminal to the remaining unselected word lines, and the unselected voltage is higher than The selection voltage. The intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor.
根據本發明之再一方面，提出一種記憶體裝置之操作方法。該記憶體裝置包括一記憶胞陣列及一字元線解碼器。該記憶胞陣列包括複數條字元線。該字元線解碼器包括複數個字元線驅動器。各該字元線驅動器包括一拉升電晶體(pull-up transistor)、一下拉電晶體(pull-down transistor)及一中間電晶體。該操作方法包括以下步驟：在該些字元線驅動器之其中之一中，藉由施加一選擇電壓於該輸入端，以開啟該拉升電晶體並關閉該下拉電晶體，使得一第一字元線電壓透過該輸出端提供至已選擇之該些字元線之其中之一。在其餘之該些字元線驅動器 之任一中，藉由施加一未選擇電壓於該輸入端，以關閉該拉升電晶體並開啟該下拉電晶體，使得一第二字元線電壓透過該輸出端提供至未選擇之該些字元線之其中之一。於各該字元線驅動器中，該中間電晶體電性連接於該輸入端及該下拉電晶體，以降低提供至該下拉電晶體之該未選擇電壓。 According to still another aspect of the present invention, a method of operating a memory device is presented. The memory device includes a memory cell array and a word line decoder. The memory cell array includes a plurality of word lines. The word line decoder includes a plurality of word line drivers. Each of the word line drivers includes a pull-up transistor, a pull-down transistor, and an intermediate transistor. The method includes the steps of: in one of the word line drivers, applying a selection voltage to the input terminal to turn on the pull-up transistor and turn off the pull-down transistor to make a first word A line voltage is supplied through the output to one of the selected word lines. The rest of the word line drivers In either one, by applying an unselected voltage to the input terminal, the pull-up transistor is turned off and the pull-down transistor is turned on, so that a second word line voltage is supplied through the output terminal to the unselected ones. One of the word lines. In each of the word line drivers, the intermediate transistor is electrically connected to the input terminal and the pull-down transistor to reduce the unselected voltage supplied to the pull-down transistor.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
100‧‧‧記憶體裝置 100‧‧‧ memory device
110‧‧‧記憶胞陣列 110‧‧‧ memory cell array
120‧‧‧位元線解碼器 120‧‧‧ bit line decoder
130‧‧‧字元線解碼器 130‧‧‧ character line decoder
131‧‧‧字元線驅動器 131‧‧‧word line driver
1311‧‧‧拉升電晶體 1311‧‧‧Lifting the crystal
1312‧‧‧下拉電晶體 1312‧‧‧ Pull-down transistor
1313‧‧‧中間電晶體 1313‧‧‧Intermediate transistor
BL‧‧‧位元線 BL‧‧‧ bit line
C1‧‧‧原始電流-電壓曲線 C1‧‧‧Original current-voltage curve
C2‧‧‧已變化電流-電壓曲線 C2‧‧‧Changed current-voltage curve
D1、D2、D3‧‧‧汲極 D1, D2, D3‧‧‧ bungee
G1、G2、G3‧‧‧閘極 G1, G2, G3‧‧‧ gate
IN‧‧‧輸入端 IN‧‧‧ input
OUT‧‧‧輸出端 OUT‧‧‧ output
P0‧‧‧中間點 P0‧‧‧ intermediate point
S1、S2、S3‧‧‧源極 S1, S2, S3‧‧‧ source
S410、S420‧‧‧流程步驟 S410, S420‧‧‧ process steps
Vdd‧‧‧驅動電壓 Vdd‧‧‧ drive voltage
VS1‧‧‧第一電壓源 VS1‧‧‧ first voltage source
VS2‧‧‧第二電壓源 VS2‧‧‧second voltage source
VS3‧‧‧第三電壓源 VS3‧‧‧ third voltage source
Vpp‧‧‧第一字元線電壓 Vpp‧‧‧first word line voltage
Vss‧‧‧第二字元線電壓 Vss‧‧‧second word line voltage
WL‧‧‧字元線 WL‧‧‧ character line
WL0‧‧‧未選擇字元線 WL0‧‧‧No word line selected
WL1‧‧‧已選擇字元線 WL1‧‧‧Selected word line
Vhigh‧‧‧未選擇電壓 Vhigh‧‧‧ not selected voltage
Vhigh’‧‧‧下降後電壓 Vhigh’‧‧‧voltage after falling
Vlow‧‧‧選擇電壓 Vlow‧‧‧Select voltage
Vtn0、Vtn1‧‧‧臨限電壓 Vtn0, Vtn1‧‧‧ threshold voltage
第1圖繪示NMOS電晶體承受閘極高電壓後的示意圖。 FIG. 1 is a schematic view showing the NMOS transistor after receiving a gate high voltage.
第2圖繪示根據本發明一實施例之記憶體裝置的示意圖。 2 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.
第3A圖繪示電性連接於一已選擇字元線之字元線驅動器的示意圖。 FIG. 3A is a schematic diagram showing a word line driver electrically connected to a selected word line.
第3B圖繪示電性連接於未選擇字元線之字元線驅動器的示意圖。 FIG. 3B is a schematic diagram of a word line driver electrically connected to an unselected word line.
第4圖繪示記憶體裝置之操作方法的流程圖。 Figure 4 is a flow chart showing the method of operation of the memory device.
請參照第2圖，其繪示根據本發明一實施例之記憶體裝置100的示意圖。記憶體裝置100包括一記憶胞陣列110、一位元線解碼器120及一字元線解碼器130。記憶胞陣列110包 括數條字元線WL及數條位元線BL。位元線解碼器120用以選擇其中一條位元線BL，字元線解碼器130用以選擇其中一條字元線WL。 Please refer to FIG. 2, which illustrates a schematic diagram of a memory device 100 in accordance with an embodiment of the present invention. The memory device 100 includes a memory cell array 110, a bit line decoder 120, and a word line decoder 130. Memory cell array 110 package A plurality of word lines WL and a plurality of bit lines BL are included. The bit line decoder 120 is configured to select one of the bit lines BL, and the word line decoder 130 is used to select one of the word lines WL.
字元線解碼器130包括複數個字元線驅動器131。各個字元線驅動器131具有一輸入端IN及一輸出端OUT。各個輸出端OUT電性連接於一條字元線WL。字元線驅動器131透過輸出端OUT提供第一字元線電壓Vpp至選擇之字元線WL，並透過輸出端OUT提供第二字元線電壓Vss至未被選擇之其餘字元線WL。第一字元線電壓Vpp高於第二字元線電壓Vss。舉例來說，第一字元線電壓Vpp可以是介於6V到9V之間，例如是8V；第二字元線電壓Vss可以是0V或1V。 The word line decoder 130 includes a plurality of word line drivers 131. Each word line driver 131 has an input terminal IN and an output terminal OUT. Each output terminal OUT is electrically connected to one word line WL. The word line driver 131 supplies the first word line voltage Vpp to the selected word line WL through the output terminal OUT, and provides the second word line voltage Vss through the output terminal OUT to the remaining word lines WL that are not selected. The first word line voltage Vpp is higher than the second word line voltage Vss. For example, the first word line voltage Vpp may be between 6V and 9V, such as 8V; the second word line voltage Vss may be 0V or 1V.
請參照第3A及3B圖。第3A圖繪示電性連接於一已選擇字元線WL1之字元線驅動器131的示意圖。第3B圖繪示電性連接於未選擇字元線WL0之字元線驅動器131的示意圖。字元線驅動器131包括一拉升電晶體(pull-up transistor)1311、一下拉電晶體(pull-down transistor)1312及一中間電晶體(intermediate transistor)1313。在一實施例中，拉升電晶體1311係為一P型金屬氧化物半導體電晶體(P type Metal-Oxide-Semiconductor transistor,PMOS transistor)，下拉電晶體1312係為一N型金屬氧化物半導體電晶體(N type Metal-Oxide-Semiconductor transistor,NMOS transistor)，中間電晶體1313係為一N型金屬氧化物半導體電晶體(NMOS)。 在另一實施例中，中間電晶體1313可以是一P型金屬氧化物半導體電晶體(PMOS)。拉升電晶體1311之閘極G1電性連接於輸入端IN，拉升電晶體1311之源極S1電性連接於第一電壓源VS1，拉升電晶體1311之汲極D1電性連接於輸出端OUT。下拉電晶體1312之汲極D2電性連接於輸出端OUT及拉升電晶體1311之汲極D1，下拉電晶體1312之源極S2電性連接於第二電壓源VS2，下拉電晶體1312之閘極G2電性連接於中間電晶體1313。中間電晶體1313之汲極D3電性連接於輸入端IN，中間電晶體1313之源極S3電性連接於下拉電晶體1312之閘極G2，中間電晶體1313之閘極G3電性連接於第三電壓源VS3。 Please refer to Figures 3A and 3B. FIG. 3A is a schematic diagram showing the word line driver 131 electrically connected to a selected word line WL1. FIG. 3B is a schematic diagram showing the word line driver 131 electrically connected to the unselected word line WL0. The word line driver 131 includes a pull-up transistor 1311, a pull-down transistor 1312, and an intermediate transistor 1313. In one embodiment, the pull-up transistor 1311 is a P-type metal-oxide-semiconductor transistor (PMOS transistor), and the pull-down transistor 1312 is an N-type metal oxide semiconductor device. The crystal (N type Metal-Oxide-Semiconductor transistor, NMOS transistor), the intermediate transistor 1313 is an N-type metal oxide semiconductor transistor (NMOS). In another embodiment, the intermediate transistor 1313 can be a P-type metal oxide semiconductor transistor (PMOS). The gate G1 of the pull-up transistor 1311 is electrically connected to the input terminal IN, the source S1 of the pull-up transistor 1311 is electrically connected to the first voltage source VS1, and the drain D1 of the pull-up transistor 1311 is electrically connected to the output. End OUT. The drain D2 of the pull-down transistor 1312 is electrically connected to the output terminal OUT and the drain D1 of the pull-up transistor 1311. The source S2 of the pull-down transistor 1312 is electrically connected to the second voltage source VS2, and the gate of the pull-down transistor 1312 is pulled down. The pole G2 is electrically connected to the intermediate transistor 1313. The drain D3 of the intermediate transistor 1313 is electrically connected to the input terminal IN, the source S3 of the intermediate transistor 1313 is electrically connected to the gate G2 of the pull-down transistor 1312, and the gate G3 of the intermediate transistor 1313 is electrically connected to the gate Three voltage source VS3.
請參照第3A、3B圖及下述表一。表一說明第3A及3B圖的運作。如第3A圖所示，當拉升電晶體1311開啟且下拉電晶體1312關閉，第一字元線電壓Vpp會透過輸出端OUT提供至已選擇字元線WL1。為了要開啟拉升電晶體1311並關閉下拉電晶體1312，需施加一選擇電壓Vlow於輸入端IN。 Please refer to Figures 3A and 3B and Table 1 below. Table 1 illustrates the operation of Figures 3A and 3B. As shown in FIG. 3A, when the pull-up transistor 1311 is turned on and the pull-down transistor 1312 is turned off, the first word line voltage Vpp is supplied to the selected word line WL1 through the output terminal OUT. In order to open the pull-up transistor 1311 and turn off the pull-down transistor 1312, a selection voltage Vlow is applied to the input terminal IN.
如第3B圖所示，當拉升電晶體1311關閉且下拉電晶體1312開啟，則第二字元線電壓Vss會透過輸出端OUT提供至未選擇字元線WL0。為了要關閉拉升電晶體1311並開啟下拉電晶體1312，需施加一未選擇電壓Vhigh於輸入端IN。 As shown in FIG. 3B, when the pull-up transistor 1311 is turned off and the pull-down transistor 1312 is turned on, the second word line voltage Vss is supplied to the unselected word line WL0 through the output terminal OUT. In order to turn off the pull-up transistor 1311 and turn on the pull-down transistor 1312, an unselected voltage Vhigh is applied to the input terminal IN.
未選擇電壓Vhigh遠高於選擇電壓Vlow。為了避免下拉電晶體1312發生閘極高電壓(gate stress)，將中間電晶體1313設置於輸入端IN與下拉電晶體1312之間，以降低未選擇電壓Vhigh。 The unselected voltage Vhigh is much higher than the selection voltage Vlow. In order to avoid gate voltage of the pull-down transistor 1312, an intermediate transistor 1313 is disposed between the input terminal IN and the pull-down transistor 1312 to lower the unselected voltage Vhigh.
如第3B圖所示，藉由施加一驅動電壓Vdd來開啟中間電晶體1313。驅動電壓Vdd高於中間電晶體1313之臨限電壓Vtn0。在中間點P0，未選擇電壓Vhigh已被降低至一下降後電壓Vhigh’。下降後電壓Vhigh’等於驅動電壓Vdd減去中間電晶體1313之臨限電壓Vtn0之值(Vhigh’=Vdd-Vtn0)。 As shown in FIG. 3B, the intermediate transistor 1313 is turned on by applying a driving voltage Vdd. The driving voltage Vdd is higher than the threshold voltage Vtn0 of the intermediate transistor 1313. At the intermediate point P0, the unselected voltage Vhigh has been lowered to a falling voltage Vhigh'. The voltage Vhigh' after the falling is equal to the value of the driving voltage Vdd minus the threshold voltage Vtn0 of the intermediate transistor 1313 (Vhigh' = Vdd - Vtn0).
由於未選擇電壓Vhigh已被降低為下降後電壓Vhigh’，下拉電晶體1312能夠有效避免遭受到閘極高電壓。因 此，下拉電晶體1312之電流-電壓曲線能夠被穩定地維持。如此一來，斷路電流(OFF-current,Ioff)與導通電流(ON-current,Ion)能夠被維持在正常水準。 Since the unselected voltage Vhigh has been lowered to the post-drop voltage Vhigh', the pull-down transistor 1312 can effectively avoid the gate high voltage. because Thus, the current-voltage curve of the pull-down transistor 1312 can be stably maintained. In this way, the OFF-current (Ioff) and the ON-current (Ion) can be maintained at normal levels.
為了要順利啟動下拉電晶體1312，下降後電壓Vhigh’被控制在高於下拉電晶體1312之臨限電壓Vtn1。在一實施例中，未選擇電壓Vhigh可以等於第一字元線電壓Vpp，選擇電壓Vlow可以等於第二字元線電壓Vss。第一字元線電壓Vpp例如是8V，第二字元線電壓例如是0V。中間電晶體1313之臨限電壓Vtn0例如是介於-1V至2V，下拉電晶體1312之臨限電壓Vtn1例如是1V。中間電晶體1313之驅動電壓Vdd例如是介於3V至7V之間。 In order to smoothly start the pull-down transistor 1312, the voltage Vhigh' after the falling is controlled to be higher than the threshold voltage Vtn1 of the pull-down transistor 1312. In an embodiment, the unselected voltage Vhigh may be equal to the first word line voltage Vpp, and the select voltage Vlow may be equal to the second word line voltage Vss. The first word line voltage Vpp is, for example, 8V, and the second word line voltage is, for example, 0V. The threshold voltage Vtn0 of the intermediate transistor 1313 is, for example, -1V to 2V, and the threshold voltage Vtn1 of the pull-down transistor 1312 is, for example, 1V. The driving voltage Vdd of the intermediate transistor 1313 is, for example, between 3V and 7V.
請參照第4圖，其繪示記憶體裝置100之操作方法的流程圖。流程圖包括步驟S410及S420。步驟S410及步驟S420可以同時執行。在步驟S410中，於此些字元線驅動器131之其中之一中，藉由施加選擇電壓Vlow於輸入端IN，以開啟拉升電晶體1311並關閉下拉電晶體1312，使得第一字元線電壓Vpp透過輸出端OUT提供至已選擇之字元線WL。 Please refer to FIG. 4 , which illustrates a flow chart of a method of operating the memory device 100 . The flowchart includes steps S410 and S420. Step S410 and step S420 can be performed simultaneously. In step S410, in one of the word line drivers 131, by applying a selection voltage Vlow to the input terminal IN, the pull-up transistor 1311 is turned on and the pull-down transistor 1312 is turned off, so that the first word line The voltage Vpp is supplied to the selected word line WL through the output terminal OUT.
在步驟S420中，於其他的任一字元線驅動器131中，藉由施加未選擇電壓Vhigh於輸入端，以關閉拉升電晶體1311並開啟下拉電晶體1312，使得第二字元線電壓Vss透過輸出端OUT提供至未選擇之字元線WL。中間電晶體1313用以降低提供至下拉電晶體1312之未選擇電壓Vhigh。 In step S420, in any of the other word line drivers 131, by applying the unselected voltage Vhigh to the input terminal, the pull-up transistor 1311 is turned off and the pull-down transistor 1312 is turned on, so that the second word line voltage Vss Provided to the unselected word line WL through the output terminal OUT. The intermediate transistor 1313 serves to reduce the unselected voltage Vhigh supplied to the pull-down transistor 1312.
上述實施例能夠有效避免下拉電晶體1312產生閘極高電壓。因此，下拉電晶體1312之電流-電壓曲線能夠維持不變且記憶體裝置100的可靠度能夠獲得改善。 The above embodiment can effectively prevent the pull-down transistor 1312 from generating a gate high voltage. Therefore, the current-voltage curve of the pull-down transistor 1312 can be maintained and the reliability of the memory device 100 can be improved.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In the above, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the invention. Change and retouch. Therefore, the scope of the invention is defined by the scope of the appended claims.
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