TW201349243A - Pure logic compatible nonvolatile memory - Google Patents

Pure logic compatible nonvolatile memory Download PDF

Info

Publication number
TW201349243A
TW201349243A TW102118447A TW102118447A TW201349243A TW 201349243 A TW201349243 A TW 201349243A TW 102118447 A TW102118447 A TW 102118447A TW 102118447 A TW102118447 A TW 102118447A TW 201349243 A TW201349243 A TW 201349243A
Authority
TW
Taiwan
Prior art keywords
level
high voltage
volatile memory
logic
vpp4
Prior art date
Application number
TW102118447A
Other languages
Chinese (zh)
Inventor
Seung-Hwan Song
Original Assignee
Seung-Hwan Song
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020120056429A external-priority patent/KR20130133111A/en
Application filed by Seung-Hwan Song filed Critical Seung-Hwan Song
Publication of TW201349243A publication Critical patent/TW201349243A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

A nonvolatile memory consisting of logic transistors in accordance with the present invention is composed of a memory cell array having multiple WL and multiple BL where the control signal of a coupling device and the control signal of an erase device of each unit cell are shared between adjacent cells in the WL direction, a high voltage switch block selectively switching from about logic ground level to about 3 to 4 times nominal supply voltage level of the logic transistors that constitute the high voltage switch block, wherein each of them operates within the nominal supply voltage range, and memory column peripheral circuit consisting of low voltage driver and data sense block; therefore, the said nonvolatile memory does not need additional process steps beyond general logic process, enabling it to be fabricated with general logic circuits such as microprocessor within a same wafer during a semiconductor fabrication process.

Description

純邏輯相容非揮發性記憶體 Pure logic compatible non-volatile memory

本發明涉及一種非揮發性記憶體，尤其是一種與通用邏輯電路製程相容的非揮發性記憶體系統之結構。 The present invention relates to a non-volatile memory, and more particularly to a non-volatile memory system that is compatible with general logic circuit processing.

習知技術已提出各種不同使用標準邏輯製造過程之包含邏輯電晶體之非揮發性記憶體，藉此，其可被整合在系統單晶片中無需額外半導體製造過程步驟。舉例而言，如在美國專利7,095,076號，名稱-電力可變式非揮發記憶胞("ELECTRICALLY-ALTERABLE NON-VOLATILE MEMORY CELL")、美國專利7,355,914號，名稱-用於感測放大器的方法與裝置("METHODS AND APPARATUSES FOR A SENSE AMPLIFIER")、美國專利7,796,450號，名稱-包括可配置的單一位元/雙位元記憶體的無線射頻標籤("RADIO FREQUENCY(RFID)TAG INCLUDING CONFIGURABLE SINGLE BIT/DUAL BITS MEMORY")、美國專利7,263,001號，名稱-緻密非揮發記憶胞及陣列系統("COMPACT NON-VOLATILE MEMORY CELL AND ARRAY SYSTEM")、美國專利7,755,941號，名稱-非揮發性半導體記憶元件("NONVOLATILE SEMICONDUCTOR MEMORY DEVICE")、美國專利6,678,190 號，名稱-單一多晶矽嵌入式可抹除可編程化唯讀記憶體("SINGLE POLY EMBEDDED EPROM")、及美國專利8,199,578號，名稱-單一多晶矽層非揮發記憶體及其運作方法("SINGLE POLYSILICON LAYER NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF")公開的邏輯相容嵌入式非揮發性記憶體可被含括於本發明之參考中。 Conventional techniques have proposed various non-volatile memories containing logic transistors that use standard logic fabrication processes whereby they can be integrated into a system single wafer without the need for additional semiconductor fabrication process steps. For example, U.S. Patent No. 7,095,076, entitled "ELECTRICALLY-ALTERABLE NON-VOLATILE MEMORY CELL", US Patent No. 7,355,914, the name - Method and Apparatus for Sense Amplifier ("METHODS AND APPARATUSES FOR A SENSE AMPLIFIER"), US Patent 7,796,450, name - including configurable single-bit/dual-bit memory radio frequency tags ("RADIO FREQUENCY(RFID)TAG INCLUDING CONFIGURABLE SINGLE BIT/DUAL BITS MEMORY"), US Patent No. 7,263,001, "COMPACT NON-VOLATILE MEMORY CELL AND ARRAY SYSTEM", US Patent 7,755,941, name-non-volatile semiconductor memory element ("NONVOLATILE" SEMICONDUCTOR MEMORY DEVICE"), US Patent 6,678,190 No., Name - Single Polycrystalline Embedded Readable Programmable Read Only Memory ("SINGLE POLY EMBEDDED EPROM"), and US Patent No. 8,199,578, Name - Single Polycrystalline Layer Nonvolatile Memory and Its Operation ("SINGLE POLYSILICON" The logically compatible embedded non-volatile memory disclosed by LAYER NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF") can be included in the reference of the present invention.

包含純邏輯電晶體的嵌入式非揮發性記憶體可被整合在如微處理器、靜態隨機存取記憶體、類比電路等的通用邏輯模塊之相同晶圓晶片中；因此，其可被用於微處理器之單晶片(on-chip)非揮發性記憶體、靜態隨機存取記憶體之冗餘控制邏輯、類比電路之微調控制方法及其他。如此的單晶片非揮發式記憶體即使在關閉電源條件下仍可安全地存儲資料，其高度有益於低功率行動系統，這是由於嵌入式非揮發記憶體不會消耗待機電力。進而，如此的嵌入式非揮發性記憶體可被利用以存儲安全資訊於晶片上而無需傳輸其至晶片外。一般而言，單晶片非揮發性記憶體之存取可快於晶片外非揮發性記憶體之存取。 Embedded non-volatile memory including pure logic transistors can be integrated into the same wafer of general-purpose logic modules such as microprocessors, static random access memories, analog circuits, etc.; therefore, it can be used Microprocessor on-chip non-volatile memory, redundant control logic for static random access memory, fine-tuning control method for analog circuits, and others. Such single-chip non-volatile memory can safely store data even when the power is turned off, which is highly beneficial for low-power mobile systems because embedded non-volatile memory does not consume standby power. Furthermore, such embedded non-volatile memory can be utilized to store secure information on the wafer without transferring it out of the wafer. In general, access to a single-chip non-volatile memory can be faster than access to non-volatile memory outside the wafer.

第一圖表示具有二堆疊閘極11、12之習知非揮發性記憶胞10及具有單獨閘極21之邏輯電晶體20之剖面。利用如特殊記憶胞10之習知非揮發性記憶體需要二個堆疊閘輯11、12之特殊製程，而如微處理器的通用邏輯電路係使用具有單獨閘極21層之一邏輯電晶體20來製造；因此，習知非揮發性記憶體係難以與如微處理器的通用邏輯電路整合，而包含邏輯電晶體之非揮發性記憶體可容易地與通用邏輯電路整合而無需額外製程步驟。 The first figure shows a cross section of a conventional non-volatile memory cell 10 having two stacked gates 11, 12 and a logic transistor 20 having a separate gate 21. A conventional non-volatile memory such as a special memory cell 10 requires a special process of two stacked gates 11, 12, and a general-purpose logic circuit such as a microprocessor uses a logic transistor 20 having a single gate 21 layer. To make; therefore, conventional non-volatile memory systems are difficult to integrate with general purpose logic circuits such as microprocessors, while non-volatile memory containing logic transistors can be easily integrated with general purpose logic circuits without the need for additional processing steps.

舉例而言，第二圖表示公告於美國專利8,199,578號與其他關 聯文獻的由邏輯電晶體20構成的習知嵌入式非揮發性記憶體系統之簡明方塊圖。在此習知非揮發性記憶體系統中的資料寫入運作之一偏壓條件及干擾問題係表示於第三圖的方塊圖中。在此非揮發性記體系統中，邏輯接地電壓VSS或寫入電壓VPGM係於選擇記憶胞310b之一寫入運作期間施加於選擇的BL(BL0)，其係根據進入一記憶體行周邊電路100之一高電壓開關110a的寫入資料，而VPGM或VSS係於選擇的記憶胞310b之一寫入運作期間施加於選擇的WL(WLn)。舉例而言，當選擇的非揮發性記憶胞310b係由“低”的WDTA0所寫入時，VPGM準位必需施加於WLn且一VSS準位需施加於BL0；反之，當選擇的非揮發性記憶胞310b係由“高”的WDTA0所寫入時，VSS準位需施加於WLn而VPGM準位需施加於BL0。在此例子中，於此寫入運作期間避免記憶感測模塊120之超量電壓應力及於未選擇的WL(WLm)及BL(BL1)中的記憶胞干擾，寫入保護電壓VPT需額外施加於此記憶體感測模塊及此未選擇的WL，其增加高電壓產生器900及記憶體行周邊電路100之複雜性及面積，並需要額外功率損耗。一般而言，VPGM準位係大於構成非揮發性記憶胞310的裝置之標稱供應電壓的二倍，且VPT準位係大於其標稱供應電壓；因此，由邏輯電晶體構成的此習知非揮發性記憶體系統於一單獨選擇的WL中記憶胞之複數個寫入運作期間係重複地施加高於標稱供應電壓的電壓準位至在複數個未選擇的WL中記憶胞，導致未選擇記憶胞之存儲資料之干擾。 For example, the second figure shows the announcement in US Patent 8,199,578 and other A concise block diagram of a conventional embedded non-volatile memory system consisting of a logic transistor 20 of the joint document. One of the bias conditions and interference problems in the data writing operation in the conventional non-volatile memory system is shown in the block diagram of the third figure. In this non-volatile recording system, the logic ground voltage VSS or the write voltage VPGM is applied to the selected BL (BL0) during a write operation of the selected memory cell 310b, which is based on entering a memory line peripheral circuit. 100 is written to the high voltage switch 110a, and VPGM or VSS is applied to the selected WL (WLn) during one of the selected memory cells 310b. For example, when the selected non-volatile memory cell 310b is written by "low" WDTA0, the VPGM level must be applied to WLn and a VSS level is applied to BL0; conversely, when selected non-volatile When the memory cell 310b is written by the "high" WDTA0, the VSS level needs to be applied to WLn and the VPGM level is applied to BL0. In this example, during the write operation, the excessive voltage stress of the memory sensing module 120 and the memory cell interference in the unselected WL (WLm) and BL (BL1) are avoided, and the write protection voltage VPT needs to be additionally applied. The memory sensing module and the unselected WL increase the complexity and area of the high voltage generator 900 and the memory line peripheral circuit 100 and require additional power loss. In general, the VPGM level is greater than twice the nominal supply voltage of the device constituting the non-volatile memory cell 310, and the VPT level is greater than its nominal supply voltage; therefore, this conventional configuration consists of logic transistors The non-volatile memory system repeatedly applies a voltage level higher than the nominal supply voltage to the memory cells in the plurality of unselected WLs during a plurality of write operations of the memory cells in a separately selected WL, resulting in no Select the interference of the memory data stored in the memory cell.

於另一方面，舉例而言，第四圖表示公告於美國專利7,796,450號與其他關聯文獻的根據由邏輯電晶體20構成的互補式記憶胞320的另一習知嵌入式非揮發性記憶體系統之簡明方塊圖。第五圖表示於此 習知非揮發性記憶體系統中的資料寫入運作之一偏壓條件及干擾問題之方塊圖。於此非揮發性記憶體系統中，舉例而言，當進入記憶體行周邊電路100之高電壓開關130a的寫入資料為“低”時，在選擇的記憶胞320b之寫入運作期間，邏輯接地電壓VSS及寫入電壓VPGM係施加於選擇的BL(BL0)及BLB(BLB0)；反之，當進入記憶體行周邊電路100之高電壓開關130b的寫入資料為“高”時，於選擇的記憶胞320b之寫入運作期間，寫入電壓VPGM及邏輯接地電壓VSS係施加於另外選擇的BL(BL1)及BLB(BLB1)，且VPGM於選擇的記憶胞320b之一寫入運作期間係施加至選擇的WL(WLn)。於此例子中，為了於此寫入運作期間避免記憶感測模塊140之超量電壓應力及於未選擇WL(WLm)中的記憶胞干擾，寫入保護電壓VPT需額外地施加至此記憶體感測模塊及未選擇的WL，其增加高電壓產生器900及記憶體行周邊電路100之複雜性與面積，且需要額外功率損耗。一般而言，VPGM準位係大於構成非揮性記憶胞320的裝置之標稱供應電壓的二倍，且VPT準位係大於其標稱供電壓；因此，根據由邏輯電晶體構成的互補式記憶胞320的習知嵌入式非揮發性記憶體系統於單獨選擇的WL中之記憶胞之複數個寫入運作期間，係重複地施加高於標稱供應電壓的電壓準位至在複數個未選擇的WL中之記憶胞，導致此未選擇的記憶胞之存儲資料之干擾。未避免干擾問題，舉例而言，在美國專利7,755,941號、美國專利7,355,914號及在2004年國際固態電路會議中公開的嵌入式非揮發性記憶體，即“用於一0.13μm互補式金氧半導體邏輯製程中的安全應用之嵌入式快閃記憶體”(Embedded Flash Memory for Security Application in a 0.13μm CMOS Logic Process)之文獻上，個別非揮發性記憶胞320包括簡明闡示在第六圖之一高電壓開關210以選擇性地提 供VPGM或VSS入此個別非揮發性記憶胞320內，然而，此機制大幅增加非揮發性記憶胞320及非揮發性記憶體陣列300之面積。在此習知高電壓開關210中，構成此高電壓開關210的邏輯電晶體之標稱供應電壓係近似於在VPT準位的VDDE，且此VPGM準位係將近VPT準位的二倍，且閘極氧化層電壓應限制在約VPGM-VPT或VPT準位內以藉由在輸出階段中連接VPT準位至N型金氧半導體電晶體211之閘極來防止氧化層(oxide)可靠性的問題。若VOUT需要被充電至大於VDDE準位二倍的電壓準位，大於標稱供應電壓VDDE的電壓會施加至此N型金氧半導體電晶體211之閘極氧化層，導致此N型金氧半導體電晶體211及其他之可靠性的問題。因此，一般而言，此高電壓開關210之VOUT準位係限制在約略VDDE準位二倍內，減緩自此高電壓開關210所供應的非揮發性記憶胞310、320之編程與抹除速度。一般而言，較高的編程或抹除電壓準位促使較快的非揮發性記憶胞之編程或抹除速度。 In another aspect, for example, the fourth figure shows another conventional embedded non-volatile memory system according to the complementary memory cell 320 formed by the logic transistor 20, which is disclosed in U.S. Patent No. 7,796,450 and other related documents. A concise block diagram. The fifth picture shows this A block diagram of one of the bias conditions and the interference problem of the data writing operation in the conventional non-volatile memory system. In this non-volatile memory system, for example, when the write data of the high voltage switch 130a entering the memory line peripheral circuit 100 is "low", during the write operation of the selected memory cell 320b, logic The ground voltage VSS and the write voltage VPGM are applied to the selected BL (BL0) and BLB (BLB0); conversely, when the write data of the high voltage switch 130b entering the memory line peripheral circuit 100 is "high", the selection is made. During the write operation of the memory cell 320b, the write voltage VPGM and the logic ground voltage VSS are applied to the additionally selected BLs (BL1) and BLBs (BLB1), and the VPGM is written to one of the selected memory cells 320b. Applied to the selected WL (WLn). In this example, in order to avoid the excessive voltage stress of the memory sensing module 140 during the writing operation and the memory cell interference in the unselected WL (WLm), the write protection voltage VPT needs to be additionally applied to the memory sense. The module and the unselected WL increase the complexity and area of the high voltage generator 900 and the memory line peripheral circuit 100 and require additional power loss. In general, the VPGM level is greater than twice the nominal supply voltage of the device constituting the non-volatile memory cell 320, and the VPT level is greater than its nominal supply voltage; therefore, according to the complementary form formed by the logic transistor The conventional embedded non-volatile memory system of the memory cell 320 repeatedly applies a voltage level higher than the nominal supply voltage during a plurality of write operations of the memory cells in the individually selected WL to a plurality of The memory cells in the selected WL cause interference with the stored data of the unselected memory cells. The problem of interference is not avoided, for example, the embedded non-volatile memory disclosed in U.S. Patent No. 7,755,941, U.S. Patent No. 7,355,914, and at the International Solid State Circuits Conference 2004, "for a 0.13 μm complementary MOS semiconductor. In the literature of the Embedded Flash Memory for Security Application in a 0.13μm CMOS Logic Process, the individual non-volatile memory cells 320 include a concise illustration in one of the sixth figures. High voltage switch 210 to selectively VPGM or VSS is incorporated into the individual non-volatile memory cells 320. However, this mechanism substantially increases the area of the non-volatile memory cells 320 and the non-volatile memory array 300. In the conventional high voltage switch 210, the nominal supply voltage of the logic transistor constituting the high voltage switch 210 is approximately VDDE at the VPT level, and the VPGM level is nearly twice the VPT level, and The gate oxide voltage should be limited to about VPGM-VPT or VPT level to prevent oxide reliability by connecting the VPT level to the gate of the N-type MOS transistor 211 in the output stage. problem. If VOUT needs to be charged to a voltage level greater than twice the VDDE level, a voltage greater than the nominal supply voltage VDDE is applied to the gate oxide layer of the N-type MOS transistor 211, resulting in the N-type MOS semiconductor The problem of crystal 211 and other reliability. Therefore, in general, the VOUT level of the high voltage switch 210 is limited to approximately twice the VDDE level, slowing down the programming and erasing speed of the non-volatile memory cells 310, 320 supplied from the high voltage switch 210. . In general, higher programming or erase voltage levels cause faster programming or erasing of non-volatile memory cells.

另一方面，由邏輯電晶體構成的此非揮發性記憶胞310、320之閘極氧化層一般不被優化成為具有較長的保留時間(retention time)，導致於編程運作完畢較長一段時間之後於此非揮發性記憶胞310、320的存儲資料之失真。 On the other hand, the gate oxide layer of the non-volatile memory cells 310, 320 composed of logic transistors is generally not optimized to have a longer retention time, resulting in a long period of time after the programming operation has been completed. The distortion of the stored data of the non-volatile memory cells 310, 320.

本發明係關於解決由邏輯電晶體所構成之習知非揮發性記憶體系統之技術問題。本發明係關於提供由邏輯電晶體所構成的一非揮發性記憶體系統之一種記憶體結構與製造方法，該非揮發性記憶體系統具有 複數個WL及複數個BL、一種由邏輯電晶體所構成的高電壓開關模塊之電路結構及製造方法、以及非揮發性記憶體之選擇性更新方法及其電路結構，以延長晶片壽命。本發明也係關於提供一種低電壓互補式非揮發性記憶體架構及低電力高電壓開關之結構與製造方法。 The present invention is directed to solving the technical problems of conventional non-volatile memory systems constructed of logic transistors. The present invention relates to a memory structure and a manufacturing method for providing a non-volatile memory system composed of a logic transistor having A circuit structure and manufacturing method of a plurality of WLs and a plurality of BLs, a high voltage switching module composed of a logic transistor, and a selective updating method of a nonvolatile memory and a circuit structure thereof to extend the life of the wafer. The present invention is also directed to providing a low voltage complementary non-volatile memory architecture and a low power high voltage switch structure and method of manufacture.

為達到前述目的，本發明提供一種由邏輯電晶體所構成的記憶體結構及製造方法，其中該非揮發性記憶體具有複數個WL及複數個BL，該等WL及BL包含複數個存儲一電荷在一浮動閘極中的非揮發性記憶胞，且該浮動閘極係由在以通用邏輯製造過程步驟的一耦合元件、一抹除元件、及一讀取元之每一閘極之連結所形成，且該耦合元件及抹除元件在WL方向中介於相鄰記憶胞之間共享控制信號。 In order to achieve the foregoing object, the present invention provides a memory structure and a manufacturing method comprising a logic transistor, wherein the non-volatile memory has a plurality of WLs and a plurality of BLs, and the WLs and BLs comprise a plurality of memories. a non-volatile memory cell in a floating gate, and the floating gate is formed by a coupling element, a erasing element, and a gate of a read cell in a general logic manufacturing process step, And the coupling element and the erasing element share a control signal between adjacent memory cells in the WL direction.

在本發明之一實施例中，位於不同WL中的非揮發性記憶胞不共享一控制訊號，致使單獨WL抹除、編程及讀取運作。 In one embodiment of the invention, non-volatile memory cells located in different WLs do not share a control signal, resulting in separate WL erase, program, and read operations.

在本發明之一實施例中，於編程運作期間關閉在一尚未選擇BL中連接到記憶胞之讀取元件的所選擇之電晶體，使得該讀取元件自BL及CSL隔絕，防止在未選擇BL中的記憶胞被編程化。 In one embodiment of the invention, the selected transistor connected to the read element of the memory cell in a selected BL is turned off during the programming operation such that the read element is isolated from BL and CSL, preventing unselected The memory cells in BL are programmed.

在本發明之一實施例中，該耦合元件具有相較於抹除及讀取元件5到10倍的通道寬度，致使依據發明的非揮發性記憶體之編程與抹除速度係被強化或用於編程及抹除運作之電壓準位被降低，而無需犧牲太多的面積。 In an embodiment of the invention, the coupling element has a channel width of 5 to 10 times that of the erase and read element, such that the programming and erasing speed of the non-volatile memory according to the invention is enhanced or used. The voltage level for programming and erase operations is reduced without sacrificing too much area.

在本發明之一實施例中，該抹除元件係N型金氧半導體場效電晶體致使依據本發明的非揮發性記憶胞之抹除速度被強化。 In one embodiment of the invention, the eraser element is an N-type MOS field effect transistor such that the erase speed of the non-volatile memory cell in accordance with the present invention is enhanced.

在本發明之一實施例中，該抹除元件係P型金氧半導體場效 電晶體致使依據本發明的非揮發性記憶胞之留存時間(retention time)被強化。 In an embodiment of the invention, the erase component is a P-type MOS field effect The crystal lens causes the retention time of the non-volatile memory cells according to the present invention to be enhanced.

在本發明之一實施例中，該耦合元件係N型金氧半導體場效電晶體且該抹除元件係N型金氧半導體場效電晶體，且該耦合元件之源極與汲極節點係經由一選擇電晶體連接至BL，因此於選擇之WL之位元對位元寫入運作期間，該浮動閘極電位係取決於BL電壓準位而調變。 In an embodiment of the invention, the coupling element is an N-type MOS field effect transistor and the erasing element is an N-type MOSFET, and the source and the drain node of the coupling element Connected to the BL via a select transistor, such that during the bit write operation of the selected WL, the floating gate potential is modulated depending on the BL voltage level.

為達成其他目的，本發明提供一種由邏輯電晶體所構成的一互補式非揮發性記憶體之電路結構及製造方法，其中該非揮發性記憶體具有複數個WL、複數個BL及BLB，且複數個WL共享大約為一邏輯供應電壓準位及大約一邏輯接地電壓準位的BL及BLB訊號，且一互補式低電壓驅動器提供BL及BLB訊號，且一互補式非揮發性記憶胞係由BL及BLB訊號所寫入，且互補式非揮發性記憶胞之一互補式資料感測模塊係由邏輯供應電壓所供應。 To achieve other purposes, the present invention provides a complementary non-volatile memory circuit structure and a manufacturing method comprising a logic transistor, wherein the non-volatile memory has a plurality of WLs, a plurality of BLs and BLBs, and a plurality of The WLs share BL and BLB signals that are approximately a logic supply voltage level and approximately a logic ground voltage level, and a complementary low voltage driver provides BL and BLB signals, and a complementary non-volatile memory cell is provided by BL. And the BLB signal is written, and one of the complementary non-volatile memory cells is supplied by the logic supply voltage.

在本發明之一實施例中，互補式非揮發性記憶胞係由一單元對所構成，且單元對之一半係由耦合元件、抹除元件、讀取元件及串聯到讀取元件的二選擇電晶體所組成，且單元對之一半係連接到BL且單元對之其他一半係連接到BLB。 In an embodiment of the invention, the complementary non-volatile memory cell system is composed of a pair of cells, and one of the pair of cells is selected by a coupling component, an erasing component, a reading component, and a serial to read component. The transistor is composed of one half of the pair of cells connected to the BL and the other half of the pair of cells is connected to the BLB.

為達成其他目的，本發明提供一種由邏輯電晶體構成的高電壓開關模塊之電路結構及製造方法，其中該高電壓開關模塊係由VPP4準位，及大約VPP4準位0、0.25、0.5、0.75倍之VSS、VPP1、VPP2、VPP3準位所供應，且該VPP4準位係在標稱供應電壓準位內運作的該邏輯電晶體之標稱供應電壓準位的約3到4倍，且該高電壓開關模塊包含準位移位級及驅 動級，且該準位移位級根據一選擇訊號產生在VSS、VPP1、VPP2、VPP3、VPP4準位之中的輸出訊號，且該驅動級具有系列連接的N型金氧半導體及P型金氧半導體電晶體，且源自該準位移位級的輸出訊號係連接至該驅動級之P型金氧半導體及N型金氧半導體之閘極，且該高電壓開關模塊根據其輸入訊號選擇開關輸出一VSS或VPP4準位。 To achieve other purposes, the present invention provides a circuit structure and a manufacturing method of a high voltage switch module composed of a logic transistor, wherein the high voltage switch module is based on VPP4 level, and approximately VPP4 levels are 0, 0.25, 0.5, 0.75. The VSS, VPP1, VPP2, and VPP3 levels are supplied, and the VPP4 level is about 3 to 4 times the nominal supply voltage level of the logic transistor operating in the nominal supply voltage level, and the High voltage switch module includes quasi-displacement level and drive a driving stage, wherein the quasi-displacement level generates an output signal among the VSS, VPP1, VPP2, VPP3, and VPP4 levels according to a selection signal, and the driving stage has a series connected N-type MOS and P-type gold An oxy-semiconductor transistor, and an output signal derived from the quasi-displacement level is connected to a gate of a P-type MOS and an N-type MOS semiconductor of the driver stage, and the high-voltage switch module selects according to an input signal thereof The switch outputs a VSS or VPP4 level.

為達成其他目的，本發明提供一種由邏輯電晶體構成的高電壓開關模塊之電路結構及製造方法，其中在寫入期間，該高電壓開關模塊係由VPP4準位，及大約為該VPP4準位0、0.25、0.5、0.75倍之VSS、VPP1、VPP2、VPP3準位所供應，且該VPP4準位約為在標稱供應電壓準位內運作的該邏輯電晶體之標稱供應電壓準位的3到4倍，且該高電壓開關模塊根據其輸入訊號輸出VSS或VPP4準位，而在讀取期間，該高電壓開關模塊係由該標稱供應電壓及低於該標稱供應電壓的VRD所供應，且VSS大約0V，且該高電壓開關模塊係根據其輸入訊號輸出VSS或VRD準位。 To achieve other purposes, the present invention provides a circuit structure and a manufacturing method of a high voltage switch module composed of a logic transistor, wherein during writing, the high voltage switch module is leveled by VPP4, and approximately is the VPP4 level. 0, 0.25, 0.5, 0.75 times the VSS, VPP1, VPP2, VPP3 levels are supplied, and the VPP4 level is approximately the nominal supply voltage level of the logic transistor operating within the nominal supply voltage level. 3 to 4 times, and the high voltage switch module outputs VSS or VPP4 level according to its input signal, and during reading, the high voltage switch module is based on the nominal supply voltage and VRD lower than the nominal supply voltage It is supplied, and VSS is about 0V, and the high voltage switch module outputs VSS or VRD level according to its input signal.

為達成其他目的，本發明提供一種由邏輯電晶體構成的高電壓準位控制模塊之電路結構與製造方法，其中該高電壓準位控制模塊具有一高電壓準位感應器及一高電壓開關，且該高電壓準位控制模塊係由一VPP4_E準位及大約為該VPP4準位0、0.25、0.5、0.75倍之VSS、VPP1_E、VPP2_E、VPP3_E準位、及該邏輯電晶體之一標稱供應電壓所供應，且該高電壓準位感測器偵測VPP1_E準位，且當該VPP1_E準位足夠高時高電壓準位控制模塊輸出VPP1_E、VPP2_E、VPP3_E、VPP4_E準位，且當該VPP1_E準位足夠低時，該高電壓準位控制模塊輸出該標稱供應電壓。 To achieve other purposes, the present invention provides a circuit structure and a manufacturing method of a high voltage level control module composed of a logic transistor, wherein the high voltage level control module has a high voltage level sensor and a high voltage switch. And the high voltage level control module is provided by a VPP4_E level and approximately VSS, VPP1_E, VPP2_E, VPP3_E level, and one of the logic transistors of the VPP4 level 0, 0.25, 0.5, 0.75 times. The voltage is supplied, and the high voltage level sensor detects the VPP1_E level, and when the VPP1_E level is sufficiently high, the high voltage level control module outputs the VPP1_E, VPP2_E, VPP3_E, and VPP4_E levels, and when the VPP1_E is When the bit is low enough, the high voltage level control module outputs the nominal supply voltage.

為達成其他目的，本發明提供一種非揮發性記憶體之選擇性 更新方法及其電路結構，其中一貧弱WL之一偵測階段構成該選擇性更新方法，在該貧弱WL之該偵測階段中，在一介於抹除階段及編程化階段之間的尾端帶中的記憶胞數量係大於貧弱WL之一資料更新階段及一特定數量。 For other purposes, the present invention provides a non-volatile memory selectivity An update method and a circuit structure thereof, wherein a detection phase of a weak WL constitutes the selective update method, and in the detection phase of the weak WL, a tail band between the erase phase and the programming phase The number of memory cells is greater than the data update phase and a specific number of the weak WL.

在本發明之一實施例中，在一尾端帶之記憶胞數量係自比較在二讀取參考電壓上的讀取結果計算而得。 In one embodiment of the invention, the number of memory cells in a trailing end band is calculated from comparing the reading results on the two read reference voltages.

根據本發明之上述說明，由邏輯電晶體所構成的非揮發性記憶胞之面積可藉由於WL方向上介於相鄰記憶胞之間共享一控制訊號而被大幅地降低。進而，在本發明中，BL及BLB電壓準位係控制在邏輯供應準位內，減少功率耗損及防止未選擇的WL被干擾。 In accordance with the above description of the present invention, the area of the non-volatile memory cells formed by the logic transistors can be substantially reduced by sharing a control signal between adjacent memory cells in the WL direction. Further, in the present invention, the BL and BLB voltage levels are controlled within the logic supply level to reduce power consumption and prevent unselected WL from being disturbed.

依據本發明，一高電壓開關模塊可自大約邏輯接地準位切換至構成該高電壓開關模塊的邏輯電晶體之標稱供應電壓準位的約3到4倍，而每一邏輯電晶體於運作期間在該標稱供應電壓範圍內運作。 According to the present invention, a high voltage switch module can be switched from approximately logic ground level to about 3 to 4 times the nominal supply voltage level of the logic transistors constituting the high voltage switch module, and each logic transistor operates It operates during this nominal supply voltage range.

依據本發明，於寫入運作期間另一高電壓開關模塊係為構成高電壓開關模塊的邏輯電晶體之大約3到4倍標稱供應電壓準所供應，而於讀取運作期間高電壓開關模塊係由構成高電壓開關模塊的邏輯電晶體之標稱供應電壓準位所供應，大幅地降低讀取遲延及電力耗損。構成高電壓開關的每一邏輯電晶體在標稱供應電壓範圍內運作。 According to the present invention, another high voltage switch module is supplied during the write operation by approximately 3 to 4 times the nominal supply voltage of the logic transistor constituting the high voltage switch module, and the high voltage switch module during the read operation It is supplied by the nominal supply voltage level of the logic transistor that constitutes the high voltage switch module, which greatly reduces read delay and power consumption. Each of the logic transistors that make up the high voltage switch operates within a nominal supply voltage range.

依據本發明，由一薄型通道氧化物構成的一非揮發性記憶胞之選擇性更新方法可有效延長資料持有時間。 According to the present invention, a selective updating method of a non-volatile memory cell composed of a thin channel oxide can effectively extend the data holding time.

10‧‧‧非揮發性記憶胞電晶體 10‧‧‧Non-volatile memory cell

11‧‧‧閘極 11‧‧‧ gate

12‧‧‧閘極 12‧‧‧ gate

20‧‧‧邏輯電晶體 20‧‧‧Logical Crystals

21‧‧‧邏輯電晶體閘極 21‧‧‧Logical transistor gate

30‧‧‧非揮發性記憶胞 30‧‧‧Non-volatile memory cells

40‧‧‧非揮發性記憶胞 40‧‧‧Non-volatile memory cells

100‧‧‧記憶體行周邊電路 100‧‧‧ memory line peripheral circuit

110‧‧‧高電壓開關 110‧‧‧High voltage switch

120‧‧‧感測模塊 120‧‧‧Sensor module

130‧‧‧互補式高電壓開關 130‧‧‧Complementary high voltage switch

140‧‧‧感測模塊 140‧‧‧Sensing module

200‧‧‧高電壓開關陣列 200‧‧‧High voltage switch array

210‧‧‧高電壓開關 210‧‧‧High voltage switch

211‧‧‧N型金氧半導體 211‧‧‧N type MOS

300‧‧‧非揮發性記憶胞陣列 300‧‧‧Non-volatile memory cell array

310‧‧‧記憶胞 310‧‧‧ memory cells

320‧‧‧記憶胞 320‧‧‧ memory cells

900‧‧‧高電壓產生器 900‧‧‧High voltage generator

1000‧‧‧VPP準位控制模塊 1000‧‧‧VPP level control module

1010‧‧‧VPP準位感測器 1010‧‧‧VPP level sensor

1020‧‧‧VPP_E放電模塊 1020‧‧‧VPP_E discharge module

1030‧‧‧VPP開關 1030‧‧‧VPP switch

1100‧‧‧記憶體行週邊電路 1100‧‧‧ memory line peripheral circuit

1110‧‧‧低電壓驅動器 1110‧‧‧Low voltage driver

1120‧‧‧資料感測模塊 1120‧‧‧ Data Sensing Module

1130‧‧‧互補低電壓驅動器 1130‧‧‧Complementary low voltage driver

1140‧‧‧感測模塊 1140‧‧‧Sensor module

1200‧‧‧高電壓開關陣列 1200‧‧‧High voltage switch array

1210‧‧‧高電壓開關 1210‧‧‧High voltage switch

1211‧‧‧準位移位級 1211‧‧‧quasi-displacement level

1212‧‧‧驅動級 1212‧‧‧Driver

1213‧‧‧脈波產生器 1213‧‧‧ Pulse Generator

1214‧‧‧電晶體 1214‧‧‧Optoelectronics

1300‧‧‧非揮發性記憶胞陣列 1300‧‧‧Non-volatile memory cell array

1301‧‧‧貧弱WL 1301‧‧‧ Weak and weak WL

1310‧‧‧非揮發性記胞 1310‧‧‧Non-volatile cells

1311‧‧‧電晶體M1、M2、M3結合 1311‧‧•Transistor M1, M2, M3 combination

1320‧‧‧記憶胞 1320‧‧‧ memory cells

1400‧‧‧記憶體位址解碼器 1400‧‧‧Memory Address Decoder

1500‧‧‧ECC模塊 1500‧‧‧ECC module

A‧‧‧節點 A‧‧‧ node

B‧‧‧節點 B‧‧‧ node

C‧‧‧節點 C‧‧‧ node

D‧‧‧節點 D‧‧‧ node

E‧‧‧節點 E‧‧‧ node

F‧‧‧節點 F‧‧‧ node

H‧‧‧節點 H‧‧‧ node

M‧‧‧節點 M‧‧‧ node

BL0‧‧‧記憶胞陣列之第0個位元線 The 0th bit line of the BL0‧‧‧ memory cell array

BLB0‧‧‧記憶胞陣列之第0個位元線棒 The 0th bit line of the BLB0‧‧‧ memory cell array

BL1‧‧‧記憶胞陣列之第1個位元線 The first bit line of the BL1‧‧‧ memory cell array

BLB1‧‧‧記憶胞陣列之第1個位元線棒 The first bit line bar of BLB1‧‧‧ memory cell array

M1‧‧‧耦合元件 M1‧‧‧ coupling element

M2‧‧‧抹除元件 M2‧‧‧wiping components

M3‧‧‧讀取元件 M3‧‧‧ reading component

S1、S2、S3‧‧‧選擇電晶體 S1, S2, S3‧‧‧ select transistor

FG‧‧‧浮動閘極節點 FG‧‧‧ Floating Gate Node

DD‧‧‧共用節點 DD‧‧‧ shared node

SS‧‧‧共用節點 SS‧‧‧ shared node

GOX‧‧‧氧化層厚度 GOX‧‧‧ oxide thickness

WM1‧‧‧通道寬度 WM1‧‧‧ channel width

WM2‧‧‧通道寬度 WM2‧‧‧ channel width

WM3‧‧‧通道寬度 WM3‧‧‧ channel width

RDATA0‧‧‧讀取資料 RDATA0‧‧‧Reading data

RDATA 1‧‧‧讀取資料 RDATA 1‧‧‧Reading data

RWLm、PWLm、WWLm、EWLm、CSLm‧‧‧第m行訊號 RWLm, PWLm, WWLm, EWLm, CSLm‧‧‧ m line signal

RWLn、PWLn、WWLn、EWLn、CSLm‧‧‧第n行訊號 RWLn, PWLn, WWLn, EWLn, CSLm‧‧‧ nth line signal

VDD‧‧‧標稱核心供應電壓 VDD‧‧‧ nominal core supply voltage

VDDE‧‧‧標稱供應電壓 VDDE‧‧‧ nominal supply voltage

VE‧‧‧讀取參考電壓 VE‧‧‧Read reference voltage

VP‧‧‧讀取參考電壓 VP‧‧‧Read reference voltage

VRD‧‧‧讀取參考電壓以感測記憶胞資料 VRD‧‧‧Read reference voltage to sense memory cell data

VPGM‧‧‧編程電壓 VPGM‧‧‧ programming voltage

VERS‧‧‧抹除電壓 VERS‧‧‧ erase voltage

VPT‧‧‧保護電壓 VPT‧‧‧protection voltage

VPP、VPP1、VPP2、VPP3、VPP4‧‧‧供應電壓 VPP, VPP1, VPP2, VPP3, VPP4‧‧‧ supply voltage

VPP_E、VPP1_E、VPP2_E、VPP3_E、VPP4_E‧‧‧供應電壓 VPP_E, VPP1_E, VPP2_E, VPP3_E, VPP4_E‧‧‧ supply voltage

VIN‧‧‧輸入訊號 VIN‧‧‧ input signal

VOUT‧‧‧輸出訊號 VOUT‧‧‧ output signal

VSS‧‧‧標稱接地電壓 VSS‧‧‧ nominal ground voltage

WDATA 0‧‧‧寫入資料 WDATA 0‧‧‧Writing information

WDATA1‧‧‧寫入資料 WDATA1‧‧‧Writing information

WLm‧‧‧第m個字元線 WLm‧‧‧m word line

WLn‧‧‧第n個字元線 WLn‧‧‧nth character line

SEL1、EN1、SEL2、EN2、SGD、SRD‧‧‧輸入訊號 SEL1, EN1, SEL2, EN2, SGD, SRD‧‧‧ input signal

BOOSTED、BOOSTEDB‧‧‧輸入訊號 BOOSTED, BOOSTEDB‧‧‧ input signal

DIS‧‧‧輸入訊號 DIS‧‧‧Input signal

Nt‧‧‧決策準則 Nt‧‧‧ decision criteria

E‧‧‧電子 E‧‧‧Electronics

P‧‧‧編程狀態 P‧‧‧Programming status

E‧‧‧抹除狀態 E‧‧‧Erasing status

第一圖係一具有二堆疊閘極的習知非揮發性記憶胞電晶體及一具有一單一閘極的一邏輯電晶體的剖面圖。 The first figure is a cross-sectional view of a conventional non-volatile memory cell having two stacked gates and a logic transistor having a single gate.

第二圖係一由邏輯電晶體所構成的一習知嵌入式非揮發性記憶體系統之簡明方塊圖。 The second figure is a concise block diagram of a conventional embedded non-volatile memory system constructed of logic transistors.

第三圖係為闡示在由邏輯電晶體構成的一習知非揮發性記憶體系統中的資料寫入運作之一偏壓條件及干擾問題的方塊圖。 The third figure is a block diagram illustrating one of the bias conditions and interference problems of data writing operations in a conventional non-volatile memory system composed of logic transistors.

第四圖係為根據由邏輯電晶體構成的一互補式記憶胞之一習知非揮發性記憶體系統的簡明方塊圖。 The fourth figure is a simplified block diagram of a conventional non-volatile memory system based on a complementary memory cell composed of logic transistors.

第五圖係為闡示在一習知非揮發性記憶體系統中根據由邏輯電晶體所構成的一互補式記憶胞的資料寫入運作之一偏壓條件及干擾問題的方塊圖。 The fifth figure is a block diagram illustrating a biasing condition and an interference problem in accordance with a data writing operation of a complementary memory cell composed of a logic transistor in a conventional non-volatile memory system.

第六圖係為一高電壓開關之電路圖，其限制VOUT範圍在一邏輯電晶體之標稱供應電壓的二倍內。 The sixth diagram is a circuit diagram of a high voltage switch that limits the VOUT range to twice the nominal supply voltage of a logic transistor.

第七圖係依據本發明的由邏輯電晶體所構成的一非揮發性記憶體系統之簡明方塊圖。 Figure 7 is a simplified block diagram of a non-volatile memory system constructed of logic transistors in accordance with the present invention.

第八圖係依據本發明之一實施例的由邏輯電晶體所構成的一非揮發性記憶體系統之電路圖。 Figure 8 is a circuit diagram of a non-volatile memory system constructed of logic transistors in accordance with one embodiment of the present invention.

第九圖係依據本發明之一實施例的電路圖，解釋由邏輯電晶體所構成的一非揮發性記憶體系統之一抹除運作。 The ninth drawing is a circuit diagram illustrating an erase operation of a non-volatile memory system constructed of logic transistors in accordance with an embodiment of the present invention.

第十圖係依據本發明之一實施例的電路圖，解釋由邏輯電晶體所構成的一非揮發性記憶體系統之一編程運作。 The tenth diagram is a circuit diagram illustrating the programming operation of one of the non-volatile memory systems formed by the logic transistors in accordance with an embodiment of the present invention.

第十一圖係依據本發明之一實施例的由邏輯電晶體所構成的一非揮發性記憶胞之簡明部局圖。 The eleventh diagram is a simplified diagram of a non-volatile memory cell composed of a logic transistor in accordance with an embodiment of the present invention.

第十二圖係據本發明之一實施例的為由邏輯電晶體所構成的一嵌入 式非揮發性記憶胞之一部份的三電晶體組合之鳥瞰圖。 A twelfth embodiment is an embedding of a logic transistor according to an embodiment of the present invention A bird's eye view of a tri-crystal combination of a portion of a non-volatile memory cell.

第十三圖係依據本發明之另一實施例的由邏輯電晶體所構成的一非揮發性記憶胞之電路圖及抹除/編程偏壓條件。 Figure 13 is a circuit diagram and erase/program bias conditions of a non-volatile memory cell formed of a logic transistor in accordance with another embodiment of the present invention.

第十四圖係依據本發明之另一實施例的由邏輯電晶體所構成的一非揮發性記憶胞之電路圖及抹除//編程偏壓條件。 Figure 14 is a circuit diagram and erase/program bias conditions of a non-volatile memory cell constructed of logic transistors in accordance with another embodiment of the present invention.

第十五圖係依據本發明之另一實施例的由邏輯電晶體所構成的一非揮發性記憶胞之電路圖及寫入偏壓條件。 The fifteenth diagram is a circuit diagram and write bias conditions of a non-volatile memory cell composed of a logic transistor in accordance with another embodiment of the present invention.

第十六圖係本發明的由邏輯電晶體所構成的一低電壓互補式非揮發性記憶體系統之簡明方塊圖。 Figure 16 is a simplified block diagram of a low voltage complementary non-volatile memory system constructed of logic transistors of the present invention.

第十七圖係依據本發明之另一實施例的由邏輯電晶體所構成的一低電壓互補式非揮發性記憶體系統之電路圖。 Figure 17 is a circuit diagram of a low voltage complementary non-volatile memory system constructed of logic transistors in accordance with another embodiment of the present invention.

第十八圖係依據本發明的由邏輯電晶體所構成的一高電壓開關之簡明方塊圖。 Figure 18 is a simplified block diagram of a high voltage switch constructed of logic transistors in accordance with the present invention.

第十九圖係依據本發明之一實施例的由邏輯電晶體所構成的一高電壓開關之電路圖。 Figure 19 is a circuit diagram of a high voltage switch constructed of a logic transistor in accordance with an embodiment of the present invention.

第二十圖係依據本發明的由邏輯電晶體所構成的另一高電壓開關之簡明方塊圖。 Figure 20 is a simplified block diagram of another high voltage switch constructed of logic transistors in accordance with the present invention.

第二十一圖係依據本發明之一實施例的由邏輯電晶體所構成的另一高電壓開關之電路圖。 A twenty-first drawing is a circuit diagram of another high voltage switch constructed of a logic transistor in accordance with an embodiment of the present invention.

第二十二圖係依據本發明之一實施例的由邏輯電晶體所構成的另一高電壓開關之電路圖，展示當VOUT改變至寫入電壓準位時節點電壓的轉移。 A twenty-second diagram is a circuit diagram of another high voltage switch constructed of a logic transistor in accordance with an embodiment of the present invention, showing the transition of the node voltage when VOUT changes to the write voltage level.

第二十三圖係依據本發明之一實施例的由邏輯電晶體所構成的另一高電壓開關之電路圖，展示當VOUT改變至VRD準位時節點電壓的轉移。 A twenty-third figure is a circuit diagram of another high voltage switch constructed of a logic transistor in accordance with an embodiment of the present invention, showing the transition of the node voltage when VOUT changes to the VRD level.

第二十四圖係依據本發明的由邏輯電晶體所構成的一VPP準位控制模塊之簡明方塊圖。 The twenty-fourth embodiment is a simplified block diagram of a VPP level control module constructed of logic transistors in accordance with the present invention.

第二十五圖係依據本發明之一實施例的由邏輯電晶體所構成的一VPP準位控制模塊之簡明電路圖。 A twenty-fifth diagram is a simplified circuit diagram of a VPP level control module constructed of a logic transistor in accordance with an embodiment of the present invention.

第二十六圖係依據本發明之一實施例的由邏輯電晶體所構成的一VPP準位控制模塊之簡明電路圖，展示當VPP1_E準位夠高時節點電壓的準位。 Figure 26 is a simplified circuit diagram of a VPP level control module constructed of logic transistors in accordance with an embodiment of the present invention, showing the level of the node voltage when the VPP1_E level is sufficiently high.

第二十七圖係依據本發明之一實施例的由邏輯電晶體所構成的一VPP準位控制模塊之簡明電路圖，展示當VPP1_E準位夠低時節點電壓的準位。 Figure 27 is a simplified circuit diagram of a VPP level control module constructed of logic transistors in accordance with an embodiment of the present invention, showing the level of the node voltage when the VPP1_E level is low enough.

第二十八圖為一FG型非揮發性記憶胞之編程運作後記憶胞臨界電壓分佈之變化之展示圖。 The twenty-eighthth figure is a display of the change of the memory cell critical voltage distribution after the programming operation of an FG type non-volatile memory cell.

第二十九圖為一FG型非揮發性記憶胞之更新運作後記憶胞臨界電壓分佈之變化之展示圖。 The twenty-ninth figure is a display of the change of the memory cell threshold voltage distribution after the FG-type non-volatile memory cell is updated and operated.

第三十圖係依據本發明的一非揮發性記憶胞之選擇性更新運作之流程圖。 Figure 30 is a flow chart showing the operation of selective updating of a non-volatile memory cell in accordance with the present invention.

第三十一圖係為闡示依據本發明於一非揮發性記憶胞之選擇性更新運作期間的資料流動路徑的方塊圖。 The thirty-first figure is a block diagram illustrating a data flow path during a selective update operation of a non-volatile memory cell in accordance with the present invention.

為使貴審查委員能清楚了解本發明之內容，謹以下列說明搭配圖式。 In order for your review board to have a clear understanding of the contents of the present invention, the following description will be used in conjunction with the drawings.

第七圖為根據本發明之由邏輯電晶體20所構成一非揮發性記憶體系統之簡明方塊圖，於該非揮性記憶體系統中，一記憶體行周邊電 路1100包含一低電壓驅動器1110及一資料感測模塊1120，該低電壓驅動器1110及該資料感測模塊1120由通用邏輯技術中提供之高效能核心電晶體所構成且在一核心供應電壓(VDD)範圍內作業；因此，依照本發明，不需額外施加由邏輯電晶體所構成之非揮發性記憶體系統中所需要的寫入保護電壓(VPT)到該記憶體行週邊電路1100及一非揮發性記憶胞陣列1300。 Figure 7 is a simplified block diagram of a non-volatile memory system constructed by a logic transistor 20 in accordance with the present invention. In the non-volatile memory system, a memory bank peripheral power The circuit 1100 includes a low voltage driver 1110 and a data sensing module 1120. The low voltage driver 1110 and the data sensing module 1120 are formed by a high performance core transistor provided in a general logic technology and supply voltage at a core (VDD). In the range of operation; therefore, according to the present invention, it is not necessary to additionally apply a write protection voltage (VPT) required in a non-volatile memory system composed of a logic transistor to the memory line peripheral circuit 1100 and a non- Volatile memory cell array 1300.

請參照第八圖，依照本發明所示之由邏輯電晶體20所構成之一非揮發性記憶體系統具有複數個WL(word line/字元線)及BL(bit line/位元線)且包含具有複數個存儲一電荷於一浮動閘(FG)中之非揮發性記憶胞之一非揮性性記憶體陣列1300；一高電壓開關陣列1200；一VPP準位控制模塊1000，接收來自一高電壓產生器900之一高電壓準位(VPP_E)並提供該高電壓準位(VPP)至該高電壓開關陣列1200；一記憶體位址解碼器1400，提供如RWL、EWL、CSL的WL訊號；以及一行周邊電路1100，包含一低電壓驅動器1110及一資料感測模塊1120。該浮動閘極係由習知通用邏輯製程方法中的一耦合元件M1、一抹除元件M2、及一讀取元件M3之每一閘極聯結所形成，且該耦合元件及該抹除元件在WL方向上介於所相鄰記憶胞之間的共享控制訊號(例如於記憶胞1310a及1310c之PWLm及WWLm，以及於記憶胞1310b及1310d之PWLn及WWLn)，降低了該非揮發性記憶體陣列1300之BL節距(pitch)以及增進記憶密度，而控制信號PWL及WWL並沒有在位在不同WLS內的記憶胞間所共享，允許單一WL抹除、編程及讀取運作。該高電壓開關陣列1200及該非揮性性記憶體陣列1300係於晶片製程步驟過程中，使用在一通用互補金氧半導體(CMOS)邏輯製程中設置之標準輸入/輸出電晶體所形成。 Referring to the eighth figure, a non-volatile memory system composed of a logic transistor 20 according to the present invention has a plurality of WLs (word line/word lines) and BLs (bit lines/bit lines). a non-volatile memory array 1300 having a plurality of non-volatile memory cells storing a charge in a floating gate (FG); a high voltage switch array 1200; a VPP level control module 1000, receiving from a One of the high voltage generators 900 has a high voltage level (VPP_E) and provides the high voltage level (VPP) to the high voltage switch array 1200; a memory address decoder 1400 that provides WL signals such as RWL, EWL, CSL And a row of peripheral circuits 1100, including a low voltage driver 1110 and a data sensing module 1120. The floating gate is formed by a gate coupling of a coupling component M1, an erasing component M2, and a reading component M3 in a conventional general logic processing method, and the coupling component and the erasing component are in WL The non-volatile memory array 1300 is reduced in the direction of shared control signals between adjacent memory cells (eg, PWLm and WWLm of memory cells 1310a and 1310c, and PWLn and WWLn of memory cells 1310b and 1310d). The BL pitch and improved memory density, while the control signals PWL and WWL are not shared between memory cells located in different WLSs, allowing for a single WL erase, programming, and read operation. The high voltage switch array 1200 and the non-volatile memory array 1300 are formed during a wafer fabrication process using standard input/output transistors disposed in a common complementary metal oxide semiconductor (CMOS) logic process.

第九圖闡釋依據本發明之一實施例的由邏輯電晶體20所構成之一非揮發性記憶體系統之一抹除運作。於該抹除運作中，抹除電壓(VERS)係施加在所選擇之WL(WWLn)，而接地電壓(VSS)係經由一高電壓開關1210施加在未選擇之WL(WWLm)，致使一單獨WL抹除運作，也就是說，當於選擇之WL(WLn)中的非揮發性記憶胞1310b、1310d被抹除時，於一未選擇之WL中的非揮發性記憶胞1310a、1310c不會被施加在選擇之WL的高抹除電壓(VERS)所影響。在本發明之一實施例中，該耦合元件M1具有相較於抹除及讀取元件之5到10倍的通道寬度，因此，當一適當的高抹除電壓(VERS)施加於所選擇之該非揮發性記憶胞1310b、1010d之WWL時，一充足的電場係產生在抹除元件M2之閘氧化物(GOX)中。因此，存儲在FG中之電子可經由穿隧射入該抹除元件M2中。 The ninth diagram illustrates an erase operation of one of the non-volatile memory systems formed by the logic transistor 20 in accordance with an embodiment of the present invention. In the erase operation, the erase voltage (VERS) is applied to the selected WL (WWLn), and the ground voltage (VSS) is applied to the unselected WL (WWLm) via a high voltage switch 1210, resulting in a separate WL erase operation, that is, when the non-volatile memory cells 1310b, 1310d in the selected WL (WLn) are erased, the non-volatile memory cells 1310a, 1310c in an unselected WL will not It is affected by the high erase voltage (VERS) applied to the selected WL. In one embodiment of the invention, the coupling element M1 has a channel width of 5 to 10 times that of the erase and read elements, and therefore, when a suitable high erase voltage (VERS) is applied to the selected At the WWL of the non-volatile memory cells 1310b, 1010d, a sufficient electric field is generated in the gate oxide (GOX) of the eraser element M2. Therefore, electrons stored in the FG can be incident into the erasing element M2 via tunneling.

第十圖闡釋依據本發明之一實施例的由邏輯電晶體20所構成之一非揮發性記憶體系統之一編程運作。在該編程運作中，編程電壓(VPGM)係施加在所選擇之WL(PWLn及WWLn)，而該接地電壓(VSS)係經由該高電壓開關1210施加在未選擇之WL(PWLn及WWLm)，致使一單獨WL編程運作，也就是說，在一未選擇之WL中的非揮發性記憶胞1310a、1310c不會被施加在所選擇之WL的高編程電壓(VPGM)所影響。VSS係施加在所選擇之BL(BL0)，而VDD係施加在未選擇之BL(BL1)以用於所選擇WL之編程運作，因而允許單一位元編程運作。於所選擇之非揮發性記憶胞1310b中，一選擇電晶體S1被開啟，使讀取元件M3之通道電壓接近VSS，在該所選擇非揮發性記憶胞1310b之編程運作期間，讓電子經由穿隧射入FG中，而在未選擇之非揮發性記憶胞1310d中，一選擇電晶體S1被關閉，使該讀取元件 M3之通道電壓根據FG電壓而上耦合(couple up)，防止所選擇之WL的編程運作過程中電子射入FG之中。另一選擇電晶體S2被關閉，該讀取元件M3於所選擇之WL的編程運作期間自共同源極線(CSL/common source line)隔絕。 The tenth diagram illustrates the programming operation of one of the non-volatile memory systems formed by the logic transistor 20 in accordance with an embodiment of the present invention. In the programming operation, a program voltage (VPGM) is applied to the selected WL (PWLn and WWLn), and the ground voltage (VSS) is applied to the unselected WL (PWLn and WWLm) via the high voltage switch 1210. This results in a single WL programming operation, that is, non-volatile memory cells 1310a, 1310c in an unselected WL are not affected by the high programming voltage (VPGM) applied to the selected WL. VSS is applied to the selected BL (BL0) and VDD is applied to the unselected BL (BL1) for programming operation of the selected WL, thus allowing single bit programming operation. In the selected non-volatile memory cell 1310b, a select transistor S1 is turned on, causing the channel voltage of the read element M3 to approach VSS, allowing electrons to pass through during the programming operation of the selected non-volatile memory cell 1310b. Tunneling into the FG, and in the unselected non-volatile memory cell 1310d, a selection transistor S1 is turned off, causing the reading element The channel voltage of M3 is coupled up according to the FG voltage to prevent electrons from entering the FG during the programming operation of the selected WL. Another selection transistor S2 is turned off and the read element M3 is isolated from the common source line (CSL/common source line) during the programming operation of the selected WL.

當一讀取參考電壓VRD(第二十八、二十九圖)施加在一選擇之WL的PWL及WWL時，依據本發明之一實施例所述由邏輯電晶體20所構成之一非揮發性記憶體系統之一讀取運作係根據一介於處於一抹除狀態下之一記憶胞以及處於一編程化狀態下之一記憶胞之間的電流感測，這是因為記憶胞臨界電壓(記憶胞VTH)係取決於一非揮發性記憶胞狀態而調變。 When a read reference voltage VRD (the twenty-eighth, twenty-ninth figure) is applied to PWL and WWL of a selected WL, one of the logic transistors 20 is non-volatile according to an embodiment of the present invention. The reading operation of one of the memory systems is based on a current sense between a memory cell in an erased state and a memory cell in a programmed state, because the memory cell threshold voltage (memory cell) VTH) is modulated depending on a non-volatile memory cell state.

第十一圖闡述依據本發明之一實施例的由邏輯電晶體20所構成之一非揮發性記憶胞1310之簡明佈局。第十二圖闡述依據本發明之一實施例的三電晶體M1、M2、M3結合體1311之鳥瞰，其組成由邏輯電晶體20所構成之一嵌入式非揮發性記憶胞1310。在本發明之一實施例中，該耦合元件M1具有該相較抹除與該讀取元件大約5到10倍通道寬度，強化了該非揮性記憶胞之抹除與編程速度，或減少抹除與編程電壓準位VERS、VPGM而不會占用過多的面積。 The eleventh diagram illustrates a concise layout of one of the non-volatile memory cells 1310 formed by the logic transistor 20 in accordance with an embodiment of the present invention. The twelfth diagram illustrates a bird's-eye view of a combination of three transistors M1, M2, and M3 in accordance with an embodiment of the present invention, which is composed of an embedded non-volatile memory cell 1310 composed of a logic transistor 20. In an embodiment of the invention, the coupling element M1 has a channel width of about 5 to 10 times that of the eraser and the read element, which enhances erasing and programming speed of the non-volatile memory cell, or reduces erasure. And programming voltage levels VERS, VPGM without occupying too much area.

第十三圖闡述依據本發明之另一實施例的由邏輯電晶體20所構成之一非揮發性記憶胞1310之一電路示意圖及抹除/編程偏壓條件。在此實施例中，N型金氧半場效電晶體(NMOSFET)係被用於一抹除元件M2，而在先前實施例(例如第八至第十圖)中，P型金氧半場效電晶體(PMOSFET)係被用於一抹除元件M2。在二者實施例中，P型金氧半場效電晶體係用於一耦合元件M1。N型金氧半場效電晶體及P型金氧半場效電晶體係為一標準CMOS技術下之非耗乏模式金氧半場效電晶體。P型金氧半場效電晶體可有 利於一較長之資料留存時間(retention time)，這是因為P型金氧半場效電晶體具有少於N型金氧半場效電晶體之導帶電子，而N型金氧半場效電晶體可有利於較快之抹除運作，因N型金氧半場效電晶體具有多於P型金氧半場效電晶體之導帶電子。因此抹除元件M2型式將會依嵌入式非揮發性記憶體之應用所決定。另一方面，P型金氧半場效電晶體之一耦合元件M1強化資料留存時間及編程性能，這是因為P型金氧半場效電晶體具有少於N型金氧半導體之導帶電子及提供高於耗乏模式之金氧半場效電晶體之耦合能力。 A thirteenth diagram illustrates a circuit diagram and erase/program bias conditions for a non-volatile memory cell 1310 formed by logic transistor 20 in accordance with another embodiment of the present invention. In this embodiment, an N-type metal oxide half field effect transistor (NMOSFET) is used for a eraser element M2, and in the previous embodiment (for example, the eighth to tenth figures), a P-type gold oxide half field effect transistor (PMOSFET) is used for a erase component M2. In both embodiments, a P-type gold oxide half field effect transistor system is used for a coupling element M1. The N-type gold-oxygen half-field effect transistor and the P-type gold-oxygen half-field effect electro-crystal system are non-depleted mode gold-oxygen half-field effect transistors under a standard CMOS technology. P-type gold oxide half field effect transistor can have Conducive to a longer retention time, because the P-type gold oxide half-field effect transistor has less conduction band electrons than the N-type gold-oxygen half-field effect transistor, and the N-type gold-oxygen half-field effect transistor can It is beneficial to the faster erasing operation, because the N-type gold-oxygen half-field effect transistor has more conduction band electrons than the P-type gold-oxygen half-field effect transistor. Therefore, the eraser component M2 type will be determined by the application of the embedded non-volatile memory. On the other hand, one of the P-type MOS half-phase effect transistor coupling elements M1 enhances the data retention time and programming performance, because the P-type MOS field-effect transistor has less conduction band electrons than the N-type MOS and provides The coupling ability of the gold-oxygen half-field effect transistor is higher than the consumption mode.

第十四圖闡述依據本發明之另一實施例的由邏輯電晶體20所構成之一非揮發性記憶胞1310之一電路示意圖及抹除/編程偏壓條件。在此實施例中，N型金氧半場效電晶體係用於一抹除元件M2及一耦合元件M1。在抹除運作期間，遠低於VSS準位的VPGM準位係施加於WWL，而VDD準位施加於該非揮發性記憶胞之PWL。在編程運作期間，遠低於VSS準位的VPGM準位係施加於WWL及PWL，而VDD準位施加於欲被編程至“1”的一非揮發性記憶胞之BL，而VSS準位係施加於欲被編程至“0”的一非揮發性記憶胞之BL。 The fourteenth diagram illustrates a circuit diagram and erase/program bias conditions for a non-volatile memory cell 1310 formed by logic transistor 20 in accordance with another embodiment of the present invention. In this embodiment, the N-type gold oxide half field effect transistor system is used for a eraser component M2 and a coupling component M1. During the erase operation, the VPGM level, which is much lower than the VSS level, is applied to the WWL, and the VDD level is applied to the PWL of the non-volatile memory cell. During the programming operation, the VPGM level far below the VSS level is applied to WWL and PWL, and the VDD level is applied to the BL of a non-volatile memory cell to be programmed to "1", while the VSS level system A BL applied to a non-volatile memory cell to be programmed to "0".

第十五圖闡述依據本發明之另一實施例的由邏輯電晶體20所構成之一非揮發性記憶胞1310之一電路示意圖及寫入偏壓條件。僅僅當BL電壓為高電壓時，一選擇電晶體(S3、S3A或S3B)係連接耦合裝置M1之源極與汲極至BL。當在寫入運作其SWL為0V期間BL電壓為低電壓時，所選擇電晶體為關閉。因此，當一高負電壓施加至WWL時，一浮動閘極電壓係基於BL電壓而不同地下耦合(coupled down)。在連結至“0”BL之一記憶胞中，選擇的電晶體S3A係關閉，自WWL產生到FG0的更高耦合，而在連接至“1” BL之一記憶胞中，選擇的電晶體S3B係開啟，自WWL產生到FG1的較低耦合。因此，在寫入“0”與“1”操作期間，至FG0及FG1的耦合效應感應出足夠低之FG0電壓(例如-5.2V到-4.2V)及足夠高之FG1電壓(例如-1.9V到0.6V)；因此，在寫入“0”運作期間，連接到“0”BL之記憶胞經由電子穿隧而在一抹除元件M2A內損失FG之電子，而在寫入“1”期間，連結至“1”BL的記憶胞經由電子穿隧增益在一抹除元件M2B內FG中之電子，致使由邏輯電晶體構成之非揮發性記憶體的位元對位元資料更新運作。 The fifteenth diagram illustrates a circuit diagram and write bias conditions for one of the non-volatile memory cells 1310 formed by the logic transistor 20 in accordance with another embodiment of the present invention. Only when the BL voltage is at a high voltage, a selection transistor (S3, S3A or S3B) is connected to the source and drain of the coupling device M1 to BL. When the BL voltage is low during the write operation when its SWL is 0V, the selected transistor is turned off. Therefore, when a high negative voltage is applied to WWL, a floating gate voltage is coupled down differently based on the BL voltage. In one of the memory cells connected to the "0" BL, the selected transistor S3A is turned off, from WWL to a higher coupling of FG0, and connected to "1" In one of the BL memory cells, the selected transistor S3B is turned on, resulting in a lower coupling from WWL to FG1. Therefore, during the operation of writing "0" and "1", the coupling effect to FG0 and FG1 induces a sufficiently low FG0 voltage (for example, -5.2V to -4.2V) and a sufficiently high FG1 voltage (for example, -1.9V). Up to 0.6V); therefore, during the write "0" operation, the memory cell connected to the "0" BL loses the electron of the FG in the erase element M2A via the electron tunneling, and during the writing of "1", The memory cells connected to the "1" BL are electronically tunneled to erase the electrons in the FG in the element M2B, causing the bits of the non-volatile memory composed of the logic transistors to update the bit data.

第十六圖闡述依據本發明由邏輯電晶體20所構成之一低電壓互補性非揮發性記憶體系統之簡明方塊圖。在此非揮發性記憶體系統中，記憶體行周邊電路1100包括一互補低電壓驅動器1130及一互補資料感測模塊1140，該互補低電壓驅動器1130及該互補資料感測模塊1140由於一通用邏輯技術中提供之高效能核心電晶體所構成並在一核心供應電壓VDD範圍內作業。該互補低電壓驅動器1130以一互補方式下，根據寫入資料(WDTAT0或WDATA1)分別提供大約一核心供應電壓及接地準位至BL及BLB(位元線條)；因此，依據本發明，在由邏輯電晶體所構成之一習知互補非揮發性記憶體系統(第四至第五圖)中所需的寫入保護電壓VPT不需被施加至該記憶體行周邊電路1100及一非揮發性記憶胞陣列1300，其大幅度地降低電力耗損及面積需耗，並強化在其構成該行周邊電路1100的高效能核心電晶體之讀出存取時間。 Figure 16 illustrates a simplified block diagram of a low voltage complementary non-volatile memory system constructed from logic transistor 20 in accordance with the present invention. In the non-volatile memory system, the memory line peripheral circuit 1100 includes a complementary low voltage driver 1130 and a complementary data sensing module 1140. The complementary low voltage driver 1130 and the complementary data sensing module 1140 are due to a general logic. The high-performance core transistor provided in the technology is constructed and operates within a core supply voltage VDD range. The complementary low voltage driver 1130 provides approximately one core supply voltage and ground level to BL and BLB (bit line) according to the write data (WDTAT0 or WDATA1) in a complementary manner; therefore, according to the present invention, The write protection voltage VPT required in one of the conventional complementary non-volatile memory systems (fourth to fifth figures) of the logic transistor need not be applied to the memory line peripheral circuit 1100 and a non-volatile The memory cell array 1300 greatly reduces power consumption and area consumption, and enhances the read access time of the high-performance core transistor constituting the peripheral circuit 1100 of the line.

請參照第十七圖，依據本發明之一實施例的由邏輯電晶體20所構成之一低電壓互補性非揮發性記憶體系統可使用由一單元對所構成之一低電壓互補性記憶胞1320所施行，且該單元對之一半係由耦合元件、抹 除元件、讀取元件、及串接至該讀取元件的二選擇電晶體所構成，且該單元對之一半係連接至BL，而該單元對之其他一半係連接至BLB。 Referring to FIG. 17, a low voltage complementary non-volatile memory system composed of a logic transistor 20 according to an embodiment of the present invention may use a low voltage complementary memory cell composed of a cell pair. 1320 is implemented, and one of the pair of units is coupled by a coupling element In addition to the component, the read component, and the two select transistors connected in series to the read component, one half of the pair is connected to the BL, and the other half of the pair is connected to the BLB.

根據本發明之一實施例的一互補資料感測模塊1140之讀取運作係根據介於連接至BL的一記憶胞及連接至BLB的一記憶胞之間的一電流感測，這是因為記憶胞臨界電壓(記憶胞VTH)係取決一非揮發性記憶胞狀態而進行調變。為能快速讀取運作，BL及BLB可在讀取期間被維持在大約VDD的準位。 The read operation of a complementary data sensing module 1140 according to an embodiment of the present invention is based on a current sensing between a memory cell connected to the BL and a memory cell connected to the BLB, because the memory The cell threshold voltage (memory cell VTH) is modulated by a non-volatile memory cell state. For fast read operation, BL and BLB can be maintained at approximately VDD during read.

第十八圖闡述依據本發明由邏輯電晶體所構成之一高電壓開關1210之簡明方塊圖。一準位移位級1211及驅動級1212構成由一VPP4準位，及該VPP4準位0、0.25、0.5、0.75倍之VSS、VPP1、VPP2、VPP3準位所供應之高電壓開關1210，且該VPP4準位係該邏輯電晶體之標稱供應電壓準位約3到4倍，且準位移位級根據一選擇訊號VIN產生在該VSS、VPP1、VPP2、VPP3、VPP4準位之中的輸出訊號A、B、C、D、E、F，且該驅動級具有串連之P型金氧半導體及N型金氧半導體電晶體，且源自該準位移位級的該輸出訊號係連接至該驅動級之該P型金氧半導體與該N型金氧半導體之閘極，且該高電壓開關係根據其輸入訊號以輸出VSS或VPP4準位。依據本發明的高電壓開關之上升VPP4準位，根據本發明的由邏輯電晶體所構成之該非揮發性記憶胞改善了介於編程化及抹除化階段之間的記憶胞臨界電壓餘裕。 Figure 18 illustrates a simplified block diagram of a high voltage switch 1210 constructed of logic transistors in accordance with the present invention. A quasi-displacement level 1211 and a driver stage 1212 constitute a high voltage switch 1210 supplied by a VPP4 level and VSS, VPP1, VPP2, VPP3 levels of the VPP4 level 0, 0.25, 0.5, 0.75 times, and The VPP4 level is about 3 to 4 times the nominal supply voltage level of the logic transistor, and the quasi-displacement level is generated according to a selection signal VIN among the VSS, VPP1, VPP2, VPP3, and VPP4 levels. Output signals A, B, C, D, E, F, and the driver stage has a series of P-type MOS and N-type MOS transistors, and the output signal derived from the quasi-displacement stage The P-type MOS semiconductor connected to the driver stage is connected to the gate of the N-type MOS, and the high voltage-on relationship is based on the input signal to output VSS or VPP4. According to the rising VPP4 level of the high voltage switch of the present invention, the non-volatile memory cell composed of the logic transistor according to the present invention improves the memory cell threshold voltage margin between the programming and erasing stages.

請參照第十九圖，依據本發明由邏輯電晶體20所構成之一高電壓開關係由具有複數個堆疊鎖存(stacked latches)1211之準位移位級，及一驅動級1212所構成。當VIN訊號自低至高切換，節點A、B、D、F被放電至 VPP3、VPP2、VPP1、VSS，且節點C、E係拉升至VPP3、VPP2，這使VOUT經由在驅動級中堆疊P型金氧半導體電晶體拉升至VPP4準位而無需構成高電壓開關1210的邏輯電晶體之一過載電壓，這是因為每一邏輯電晶體係在標稱供應電壓準位內運作。在一相似方式中，當VIN訊號自高切換至低時，節點A、B、D、F被拉升至VPP4、VPP3、VPP2、VPP1，且節點C、E被放電至VPP2、VPP1，這使VOUT經由驅動級中堆疊N型金氧半導體電晶體放電至VSS準位而無需構成高電壓開關1210的邏輯電晶體之一過載電壓。當VIN訊號準位改變時，一脈波產生器1213僅短時間開啟一選擇的電晶體1214，以最小化該準位移位級1211之電力耗損。 Referring to FIG. 19, a high voltage open relationship formed by logic transistor 20 in accordance with the present invention is comprised of a quasi-displacement level having a plurality of stacked latches 1211 and a driver stage 1212. When the VIN signal switches from low to high, nodes A, B, D, and F are discharged to VPP3, VPP2, VPP1, VSS, and nodes C, E are pulled up to VPP3, VPP2, which causes VOUT to be pulled up to the VPP4 level via stacking P-type MOS transistors in the driver stage without forming a high voltage switch 1210 One of the logic transistors overloads the voltage because each logic cell system operates at a nominal supply voltage level. In a similar manner, when the VIN signal switches from high to low, nodes A, B, D, and F are pulled up to VPP4, VPP3, VPP2, and VPP1, and nodes C and E are discharged to VPP2 and VPP1, which makes VOUT is discharged to the VSS level via the stacked N-type MOS transistor in the driver stage without an overload voltage of one of the logic transistors constituting the high voltage switch 1210. When the VIN signal level changes, a pulse generator 1213 turns on a selected transistor 1214 for only a short time to minimize the power consumption of the quasi-displacement level 1211.

第二十圖闡述依據本發明的由邏輯電晶體構成之另一高電壓開關1210之一簡明方塊圖。一準位移位級1211及驅動級1212構成該高電壓開關1210。該準位移位級1211係由VSS、VPP1_E、VPP2_E、VPP3_E、VPP1、VPP2、VPP3、VPP4、VRD所供應，並由SEL1、EN1、SEL2、EN2訊號所控制，並根據一選擇訊號SEL1、EN1、SEL2、EN2產生在VSS、VPP1、VPP2、VPP3、VPP4準位中之輸出訊號A、C、D、E、F、H。該驅動級具有串連之P型金氧半導體及N型金氧半導體電晶體，且來自該準位移位級之輸出訊號及另外的控制訊號(SGD及SRD)係連接至該驅動級之P型金氧半導體及N型金氧半導體之閘極。在寫入運作期間，VPP1、VPP2、VPP3準位變成約VPP4的0.25、0.5、0.75倍，且VPP1_E、VPP2_E、VPP3_E準位成為約VPP1、VPP2、VPP3的準位，且VPP4準位變成該邏輯電晶體之標稱供應電壓準位之大約3到4倍，且該高電壓開關根據輸入訊號輸出VSS或VPP4準位。在讀取運作期間，VPP1、VPP2、VPP3、VPP4準位成為構成高電壓開 關1210的邏輯電晶體之標稱供應電壓。VRD係低於該標稱供應電壓，且VSS係約0V，且該高電壓開關模塊根據其輸入訊號輸出VSS或VRD準位。 Figure 20 illustrates a simplified block diagram of another high voltage switch 1210 constructed of logic transistors in accordance with the present invention. A quasi-displacement stage 1211 and a driver stage 1212 form the high voltage switch 1210. The quasi-displacement level 1211 is supplied by VSS, VPP1_E, VPP2_E, VPP3_E, VPP1, VPP2, VPP3, VPP4, VRD, and is controlled by SEL1, EN1, SEL2, EN2 signals, and according to a selection signal SEL1, EN1 , SEL2, and EN2 generate output signals A, C, D, E, F, and H in the VSS, VPP1, VPP2, VPP3, and VPP4 levels. The driver stage has a series of P-type MOS and N-type MOS transistors, and an output signal from the quasi-displacement level and another control signal (SGD and SRD) are connected to the driver stage. Gates of type MOS and N-type MOS. During the write operation, the VPP1, VPP2, and VPP3 levels become approximately 0.25, 0.5, and 0.75 times of VPP4, and the VPP1_E, VPP2_E, and VPP3_E levels become the levels of approximately VPP1, VPP2, and VPP3, and the VPP4 level becomes the logic. The nominal supply voltage level of the transistor is approximately 3 to 4 times, and the high voltage switch outputs VSS or VPP4 level according to the input signal. During the read operation, the VPP1, VPP2, VPP3, and VPP4 levels become high voltage on. Turn off the nominal supply voltage of the logic transistor of 1210. The VRD is lower than the nominal supply voltage, and the VSS is about 0V, and the high voltage switch module outputs VSS or VRD level according to its input signal.

請參閱第二十一圖，依據本發明之實施例的由邏輯電晶體所構成之一高電壓開關1210係由準位移位級1211，及一驅動級1212所構成。該準位移位級1211具有由VPP4、VPP3、VPP2、VPP1及VPP3_E、VPP2_E、VPP1_E所供應之複數個堆疊鎖存。 Referring to the twenty-first embodiment, a high voltage switch 1210 composed of a logic transistor according to an embodiment of the present invention is composed of a quasi-displacement stage 1211 and a driver stage 1212. The quasi-displacement level 1211 has a plurality of stacked latches supplied by VPP4, VPP3, VPP2, VPP1, and VPP3_E, VPP2_E, and VPP1_E.

請參閱第二十二圖，依據本發明之實施例，舉例而言，由邏輯電晶體所構成之一高電壓開關1210之供應電壓VPP4、VPP3、VPP2、VPP1可為10V、7.5V、5V、2.5V，且在寫入運作期間VPP3_E、VPP2_E、VPP1_E準位可為7.5 V、5 V、2.5 V。當SEL1及SEL2訊號自低切換至高時，節點A、C、E、SGD係被放電至VPP3_E、VPP2_E、VPP1_E、VSS，且節點D及F被拉升至VPP3、VPP2，使VOUT經由於驅動級中的堆疊之P型金氧半導體電晶體拉升至VPP4準位。在一近似方式中，當SEL1及SEL2訊號自高切換至低時，節點A、C、E、SGD係拉升至VPP4、VPP3、VPP2、VPP1，且節點D、F被放電至VPP2_E、VPP1_E，使VOUT經由該驅動級中的堆疊之N型金氧半導體電晶體放電至VSS。每個構成該高電壓開關1210之邏輯電晶體係在標稱供應電壓準位內運作。當SEL1/SEL2訊號改變時，脈波訊號EN1及EN2僅開啟選擇電晶體於一短時間，以為了最小化準位移位級1211之電力耗損。 Referring to FIG. 22, according to an embodiment of the present invention, for example, a supply voltage VPP4, VPP3, VPP2, and VPP1 of a high voltage switch 1210 formed by a logic transistor may be 10V, 7.5V, 5V, 2.5V, and the VPP3_E, VPP2_E, and VPP1_E levels can be 7.5 V, 5 V, and 2.5 V during write operation. When the SEL1 and SEL2 signals are switched from low to high, nodes A, C, E, and SGD are discharged to VPP3_E, VPP2_E, VPP1_E, and VSS, and nodes D and F are pulled up to VPP3 and VPP2, so that VOUT passes through the driver stage. The stacked P-type MOS transistors are pulled up to the VPP4 level. In an approximate manner, when the SEL1 and SEL2 signals are switched from high to low, nodes A, C, E, and SGD are pulled up to VPP4, VPP3, VPP2, and VPP1, and nodes D and F are discharged to VPP2_E and VPP1_E. VOUT is discharged to VSS via the stacked N-type MOS transistors in the driver stage. Each of the logic cell systems that make up the high voltage switch 1210 operates at a nominal supply voltage level. When the SEL1/SEL2 signal changes, the pulse signals EN1 and EN2 only turn on the selection transistor for a short period of time in order to minimize the power loss of the quasi-displacement level 1211.

請參閱第二十三圖，依據本發明之實施例，舉例而言，由邏輯電晶體構成一高電壓開關1210之供應電壓數可為2.5V，即在一標準互補式金氧半導體製程技術中的大約2.5V輸入/輸出裝置之標稱供應電壓，且VPP3_E、VPP2_E及VPP1_E準位在讀取運作期間可為VSS1準位。該準位移 位級，舉例而言，具有0V之SEL1訊號及2.5V之SEL2訊號，使B、C、E節點為0V且A、D、F節點為2.5V。因此，當SGD/SRD訊號自高/低切換為低/高時，VRD準位可被快速地轉移至VOUT無需改變該準位移位級之狀態，促使在一選擇之WL中的一讀取參考電壓VRD之快速啟動以及使由邏輯電晶體構成之該非揮發性記憶胞之讀取延遲最小化。 Referring to the twenty-third figure, according to an embodiment of the present invention, for example, the supply voltage of a high voltage switch 1210 formed by a logic transistor can be 2.5V, that is, in a standard complementary MOS process technology. The nominal supply voltage of the approximately 2.5V input/output device, and the VPP3_E, VPP2_E, and VPP1_E levels can be VSS1 level during the read operation. Quasi displacement The bit level, for example, has a SEL1 signal of 0V and a SEL2 signal of 2.5V, so that the B, C, and E nodes are 0V and the A, D, and F nodes are 2.5V. Therefore, when the SGD/SRD signal is switched from high/low to low/high, the VRD level can be quickly transferred to VOUT without changing the state of the quasi-displaced bit level, causing a read in a selected WL. The fast start of the reference voltage VRD and the read delay of the non-volatile memory cell composed of the logic transistor are minimized.

請參照第二十四圖，依據本發明，由邏輯電晶體構成之VPP準位控制模塊1000包含VPP準位感測器1010、選擇性地放電VPP1_E、VPP2_E、VPP3_E及VPP4_E準位的VPP_E放電模塊1020、以及控制VPP1、VPP2、VPP3及VPP4準位的VPP開關1030。該VPP開關1030由VPP4_E準位及約VPP4_E準位0.25、0.5、0.75倍之VPP1_E、VPP2_E、VPP3_E準位、以及邏輯電晶體之標稱供應電壓VDDE所供應。 Referring to FIG. 24, in accordance with the present invention, a VPP level control module 1000 composed of a logic transistor includes a VPP level sensor 1010, and a VPP_E discharge module that selectively discharges VPP1_E, VPP2_E, VPP3_E, and VPP4_E levels. 1020, and a VPP switch 1030 that controls the VPP1, VPP2, VPP3, and VPP4 levels. The VPP switch 1030 is supplied by the VPP4_E level and the VPP1_E, VPP2_E, VPP3_E level of about 0.25, 0.5, 0.75 times of the VPP4_E level, and the nominal supply voltage VDDE of the logic transistor.

請參照第二十五圖，依據本發明之一實施例，VPP_E放電模塊1020係由為VPP1、VPP2、VPP3準位所控制之複數個N型金氧半導體構成，且該VPP開關1030係由串接之P型金氧半導體開關級所構成。 Referring to FIG. 25, in accordance with an embodiment of the present invention, a VPP_E discharge module 1020 is composed of a plurality of N-type MOS semiconductors controlled by VPP1, VPP2, and VPP3 levels, and the VPP switch 1030 is composed of a string. Connected to the P-type MOS transistor switching stage.

請參閱第二十六圖，依據本發明之一實施例，當VPP1_E準位足夠高時，該VPP準位感測器1010產生到BOOSTEDB/BOOSTED的VSS/VDDE準位；因此VPP1、VPP2、VPP3、VPP4節點係依序連接到在VPP開關1030中的VPP1_E、VPP2_E、VPP3_E、VPP4_E。另一方面，VSS係施加至VPP_E放電模塊中的DIS，防止VPP1_E、VPP2_E、VPP3_E、VPP4_E連接到VSS準位。在VPP_E放電模塊1020中的此系列N型金氧半導體電晶體劃分VPP2_E、VPP3_E、VPP4_E準位，致使每個個別邏輯電晶體可在一標稱供應電壓範圍內運作。 Referring to FIG. 26, in accordance with an embodiment of the present invention, when the VPP1_E level is sufficiently high, the VPP level sensor 1010 generates a VSS/VDDE level to BOOSTEDB/BOOSTED; thus, VPP1, VPP2, and VPP3 The VPP4 node is sequentially connected to VPP1_E, VPP2_E, VPP3_E, and VPP4_E in the VPP switch 1030. On the other hand, VSS is applied to the DIS in the VPP_E discharge module to prevent VPP1_E, VPP2_E, VPP3_E, and VPP4_E from being connected to the VSS level. The series of N-type MOS transistors in the VPP_E discharge module 1020 divides the VPP2_E, VPP3_E, VPP4_E levels such that each individual logic transistor can operate within a nominal supply voltage range.

請參閱第二十七圖，依據本發明之一實施例，當VPP1_E準位足夠低時，VPP準位感測器1010產生至BOOSTEDB/BOOSTED的VDDE/VSS準位；因此VPP1、VPP2、VPP3、VPP4節點係全部依序地連接至在VPP開關1030中的VDDE。另一方面，VDDE係施加至在VPP_E放電模塊中的DIS，使VPP1_E、VPP2_E、VPP3_E、VPP4_E經由堆疊N型金氧半導體電晶體放電至VSS準位。 Referring to FIG. 27, in accordance with an embodiment of the present invention, when the VPP1_E level is sufficiently low, the VPP level sensor 1010 generates a VDDE/VSS level to BOOSTEDB/BOOSTED; thus, VPP1, VPP2, VPP3, The VPP4 nodes are all sequentially connected to VDDE in the VPP switch 1030. On the other hand, VDDE is applied to the DIS in the VPP_E discharge module, causing VPP1_E, VPP2_E, VPP3_E, VPP4_E to be discharged to the VSS level via the stacked N-type MOS transistor.

第二十八圖闡示一非揮發性記憶胞1310之記憶胞相較於緊接著編程運作後，臨界電壓分佈可在編程運作很長一段時間後產生改變。這是因為當閘極氧化層因重覆性編程與抹除循環而退化時，在非揮發性記憶胞之FG中的存儲電荷可在編程運作很長一段時間後改變。閘極氧化層組成存儲在由邏輯電晶體構成的非揮發性記憶胞之FG中的電子穿隧屏障，其在一標準邏輯製程技術中並不需要被最佳化成具有長留存時間(retention time)，舉例而言，記憶胞電晶體之閘極氧化層厚度GOX可為薄型，因此難以維持由邏輯電晶體構成一非揮發性記憶胞之長留存時間。因此，由二讀取參考電壓(VE及VP)所定義之尾部記憶胞數量可在編程運作後之一留存模式期間而增加。 The twenty-eighth figure illustrates that the memory voltage of a non-volatile memory cell 1310 can be changed after a long period of programming operation after the programming operation. This is because when the gate oxide layer is degraded by repetitive programming and erase cycles, the stored charge in the FG of the non-volatile memory cell can change after a long period of programming operation. The gate oxide layer constitutes an electron tunneling barrier stored in the FG of a non-volatile memory cell composed of a logic transistor, which does not need to be optimized to have a long retention time in a standard logic process technique For example, the gate oxide thickness GOX of the memory cell can be thin, so it is difficult to maintain a long retention time of a non-volatile memory cell composed of a logic transistor. Therefore, the number of tail memory cells defined by the two read reference voltages (VE and VP) can be increased during one of the retention modes after the programming operation.

另一方面，請參照第二十九圖，非揮發性記憶胞之記憶胞臨界電壓位移可在一FG型非揮發性記憶胞之更新作業進行後減少係為已知現象。因此，即便編成作業很長一段時間後，由該二讀取參考電壓(VE及VP)所定義之尾部記憶胞數量仍可是極少數的。 On the other hand, please refer to the twenty-ninth figure, the memory cell threshold voltage displacement of the non-volatile memory cell can be reduced after a FG-type non-volatile memory cell update operation is a known phenomenon. Therefore, even after a long period of programming, the number of tail memory cells defined by the two read reference voltages (VE and VP) can be very small.

請參閱第三十圖，本發明提供一非揮發性記憶體之一選擇性更新方法以達到較長之晶片壽命。該選擇性更新方法由以下步驟所構成： 步驟2000-位在VE及VP之讀取參考電壓的一非揮發性記憶胞之二讀取運作算出在一尾端區域中的記憶胞數量，及下一步-執行檢查操作以決定在尾端區域中的記憶胞數量是否大於貧弱WL(Nt)之決策準則2010，及下一步-如果決定條件為真，則在VRD之讀取參考電壓執行另一讀取運作2020接著進行抹除與編程運作2030。如果尾端記憶胞數量並未超過貧弱WL(Nt)之決定準則，則不進行更新運作以避免非揮發性記憶胞之額外不必要的抹除與編程運作。 Referring to the thirtieth aspect, the present invention provides a method of selectively updating a non-volatile memory to achieve a longer wafer lifetime. The selective update method consists of the following steps: Step 2000 - The reading operation of a non-volatile memory cell of the read reference voltage of VE and VP calculates the number of memory cells in a tail end region, and the next step - performs an inspection operation to determine the end region Whether the number of memory cells is greater than the weak WL (Nt) decision criterion 2010, and the next step - if the decision condition is true, then the read reference voltage of the VRD is performed for another read operation 2020 followed by the erase and program operation 2030 . If the number of memory cells at the end does not exceed the WL (Nt) decision criterion, no update operation is performed to avoid additional unnecessary erasure and programming operations of the non-volatile memory cells.

請參閱第三十一圖，依據本發明，於該貧弱WL(WL N在第三十一圖中)中的存儲資料係備份至行周邊模塊以及接著由一ECC(誤差修正碼)模塊1500的存儲或修復資料在較貧弱WL之抹除運作後再編程化至原本WL。 Referring to the thirty-first figure, according to the present invention, the storage data in the lean WL (WL N in the thirty-first figure) is backed up to the line peripheral module and then by an ECC (Error Correction Code) module 1500. The stored or repaired data is programmed to the original WL after the weaker WL erase operation.

綜上所述，本發明之技術內容及技術特點巳揭示如上實施例以協助進一步理解，然而熟悉本項技術之人士仍可能基於本發明之揭示而作各種不背離本案發明精神之替換及修飾。因此，本發明之保護範圍應不限於實施例所揭示者，而應包括各種不背離本發明之替換及修飾，並為以下之申請專利範圍所涵蓋。 In view of the above, the technical content and technical features of the present invention are disclosed in the above embodiments to facilitate further understanding. However, those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

900‧‧‧高電壓產生器 900‧‧‧High voltage generator

1000‧‧‧VPP準位控制模塊 1000‧‧‧VPP level control module

1110‧‧‧低電壓驅動器 1110‧‧‧Low voltage driver

1120‧‧‧資料感測模塊 1120‧‧‧ Data Sensing Module

1200‧‧‧高電壓開關陣列 1200‧‧‧High voltage switch array

1210‧‧‧高電壓開關 1210‧‧‧High voltage switch

1300‧‧‧非揮發性記憶胞陣列 1300‧‧‧Non-volatile memory cell array

1310‧‧‧非揮發性記胞 1310‧‧‧Non-volatile cells

Claims (10)

一種由邏輯電晶體構成之非揮發性記憶體之記憶體結構，其特徵在於，具有複數個字元線及複數個位元線的該非揮發性記憶體包含複數個非揮發性記憶胞，該等非揮發性記憶胞存儲一電荷在一浮動閘極中，且該浮動閘極係以已經在通用邏輯製程步驟中具備的一耦合元件、一抹除元件、及一讀取元件之每一閘極的聯結所形成，且該耦合元件及該抹除元件在字元線方向上介於相鄰記憶胞之間共享控制信號。 A memory structure of a non-volatile memory composed of a logic transistor, wherein the non-volatile memory having a plurality of word lines and a plurality of bit lines includes a plurality of non-volatile memory cells, and the like The non-volatile memory cell stores a charge in a floating gate, and the floating gate is a coupling element, a eraser component, and a gate of a read component that are already provided in a general logic process step A junction is formed, and the coupling element and the erasing element share a control signal between adjacent memory cells in the direction of the word line. 如申請專利範圍第1項所述之記憶體結構，其中，位於不同字元線中的該等非揮發性記憶胞不共享一控制訊號，而允許單獨字元線運作。 The memory structure of claim 1, wherein the non-volatile memory cells located in different word lines do not share a control signal, but allow individual word lines to operate. 如申請專利範圍第1項所述之記憶體結構，其中，於未選擇的位元線中連接至該讀取元件的選擇的電晶體係於編程運作期間關閉，使得該讀取元件自位元線及共同源極線隔絕。 The memory structure of claim 1, wherein the selected electro-optic system connected to the read element in the unselected bit line is turned off during a programming operation, such that the read element is self-biting The line and the common source line are isolated. 如申請專利範圍第1項所述之記憶體結構，其中，該耦合元件係為非耗乏模式金氧半導體場效電晶體且該抹除元件係非耗乏模式金氧半導體場效電晶體。 The memory structure of claim 1, wherein the coupling element is a non-depleted mode MOS field effect transistor and the erase element is a non-depleted mode MOS field effect transistor. 如申請專利範圍第4項所述之記憶體結構，其中，該耦合元件之源極及汲極節點係經由一選擇電晶體而選擇性連接至位元線，而因此於選擇的該字元線之位元接著位元的寫入運作期間該浮動閘極電位係基於位元線電壓準位而調變。 The memory structure of claim 4, wherein the source and the drain node of the coupling element are selectively connected to the bit line via a selection transistor, and thus the selected word line The floating gate potential is modulated based on the bit line voltage level during the write operation of the bit and then the bit. 一種由邏輯電晶體所構成的一非揮發性記憶體之電路結構，其特徵在於，該非揮發性記憶體具有複數個字元線、複數個位元線及位元線條，且該等字元線共享位元線及位元線條訊號，該訊號為大約一邏輯供應電壓準位及大約一邏輯接地電壓準位，且該位元線及位元線條訊號係由一互補式低電壓驅動器所提供，且一互補式非揮發性記憶胞係由該位元線及位元線條訊號所寫入，且該互補式非揮發性記憶胞之一互補式資料感測模塊係由該邏輯供應電壓所供應。 A non-volatile memory circuit structure composed of a logic transistor, wherein the non-volatile memory has a plurality of word lines, a plurality of bit lines, and bit lines, and the word lines Sharing a bit line and a bit line signal, the signal is about a logic supply voltage level and about a logic ground voltage level, and the bit line and bit line signals are provided by a complementary low voltage driver. And a complementary non-volatile memory cell is written by the bit line and the bit line signal, and one of the complementary non-volatile memory cells is supplied by the logic supply voltage. 一種由邏輯電晶體所構成的高電壓開關模塊之電路結構，其特徵在於，該高電壓開關模塊包含準位移位級及驅動級，且該高電壓開關模塊係由一VPP4準位、及約該VPP4準位的0、0.25、0.5、0.75倍之VSS、VPP1、VPP2、VPP3準位所供應，且該VPP4準位係在標稱供應電壓準位內運作的該邏輯電晶體之該標稱供應電壓準位之約3到4倍，且該準位移位級係基於一選擇訊號產生在該VSS、VPP1、VPP2、VPP3、VPP4準位之間的輸出訊號，且該驅動級具有串聯的P型金氧半導體及N型金氧半導體電晶體，且來自該準位移位級的該輸出訊號係連接至該驅動級之該P型金氧半導體及N型金氧半導體電晶體之閘極，且該高電壓開關模塊係根據該高電壓開關模塊之輸入訊號輸出VSS或VPP4準位。 A circuit structure of a high voltage switch module composed of a logic transistor, wherein the high voltage switch module comprises a quasi-displacement level and a drive stage, and the high voltage switch module is controlled by a VPP4 level The VPP4 level is supplied by the VSS, VPP1, VPP2, and VPP3 levels of 0, 0.25, 0.5, and 0.75 times, and the VPP4 level is the nominal of the logic transistor operating in the nominal supply voltage level. The supply voltage level is about 3 to 4 times, and the quasi-displacement level generates an output signal between the VSS, VPP1, VPP2, VPP3, and VPP4 levels based on a selection signal, and the driving stage has a series connection. a P-type MOS and an N-type MOS transistor, and the output signal from the quasi-displacement stage is connected to the gate of the P-type MOS and the N-type MOS transistor of the driver stage And the high voltage switch module outputs the VSS or VPP4 level according to the input signal of the high voltage switch module. 一種由邏輯電晶體所構成的高電壓開關模塊之電路結構，其特徵在於，在一寫入運作期間，該高電壓開關模塊係由一VPP4準位、及約該VPP4準位的0、0.25、0.5、0.75倍之VSS、VPP1、VPP2、VPP3準位所供應，且該VPP4準位係在標稱供應電壓準位內運作的該邏輯電晶體之該標稱供應電壓準位之約3到4倍，且該高電壓開關模塊係基於該高電壓開關模塊之輸入訊號輸 出VSS或VPP4準位，而在一讀取運作期間，該高電壓開關模塊係由該標稱供應電壓及低於該標稱供應電壓的VRD，及約0V的VSS所供應，且該高電壓開關模塊係根據該高電壓開關模塊之輸入訊號輸出VSS或VRD準位。 A circuit structure of a high voltage switch module composed of a logic transistor, wherein during a write operation, the high voltage switch module is controlled by a VPP4 level and about 0, 0.25 of the VPP4 level. 0.5, 0.75 times the VSS, VPP1, VPP2, VPP3 levels are supplied, and the VPP4 level is about 3 to 4 of the nominal supply voltage level of the logic transistor operating in the nominal supply voltage level. Times, and the high voltage switch module is based on the input signal input of the high voltage switch module Out of VSS or VPP4 level, and during a read operation, the high voltage switch module is supplied by the nominal supply voltage and VRD lower than the nominal supply voltage, and VSS of about 0V, and the high voltage The switch module outputs VSS or VRD level according to the input signal of the high voltage switch module. 一種由邏輯電晶體所構成的高電壓準位控制模塊之電路結構，其特徵在於，該高電壓準位控制模塊包括一高電壓準位感測器及一高電壓開關，且該高電壓準位控制模塊係由一VPP4_E準位、及約該VPP4_E準位的0、0.25、0.5、0.75倍之VSS、VPP1_E、VPP2_E、VPP3_E準位、及該邏輯電晶體之一標稱供應電壓所供應，且該高電壓準位感測器偵測該VPP1_E準位，且當該VPP1_E準位夠高時該高電壓開關輸出該VPP1_E、VPP2_E、VPP3_E、VPP4_E準位，且當該VPP1_E準位夠低時該高電壓開關輸出該標稱供應電壓。 A circuit structure of a high voltage level control module formed by a logic transistor, wherein the high voltage level control module comprises a high voltage level sensor and a high voltage switch, and the high voltage level The control module is supplied by a VPP4_E level, and a VSS, VPP1_E, VPP2_E, VPP3_E level of about 0, 0.25, 0.5, 0.75 times of the VPP4_E level, and a nominal supply voltage of the logic transistor, and The high voltage level sensor detects the VPP1_E level, and when the VPP1_E level is high enough, the high voltage switch outputs the VPP1_E, VPP2_E, VPP3_E, and VPP4_E levels, and when the VPP1_E level is low enough, the The high voltage switch outputs the nominal supply voltage. 一種非揮發性記憶體之選擇性更新方法，其特徵在於，該選擇性更新方法由一貧弱字元線之一偵測階段所構成，其中被發現在一介於抹除階段及編程化階段之間的尾端帶中的記憶胞數量係大於該貧弱字元線之一特定數量及一資料更新階段。 A method for selectively updating non-volatile memory, characterized in that the selective updating method consists of a detection phase of a weak word line, which is found between an erase phase and a programming phase The number of memory cells in the end band is greater than a specific number of the weak word lines and a data update phase.
TW102118447A 2012-05-28 2013-05-24 Pure logic compatible nonvolatile memory TW201349243A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020120056429A KR20130133111A (en) 2012-05-28 2012-05-28 Pure logic compatible flash memory
KR20130031195 2013-03-22

Publications (1)

Publication Number Publication Date
TW201349243A true TW201349243A (en) 2013-12-01

Family

ID=49674000

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102118447A TW201349243A (en) 2012-05-28 2013-05-24 Pure logic compatible nonvolatile memory

Country Status (2)

Country Link
TW (1) TW201349243A (en)
WO (1) WO2013180401A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI665552B (en) * 2018-08-01 2019-07-11 華邦電子股份有限公司 Circuit for recovering from power loss and electronic device using the same circuit and method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11694751B2 (en) 2019-11-30 2023-07-04 Semibrain Inc. Logic compatible flash memory programming with a pulse width control scheme
CN115599194B (en) * 2022-12-14 2023-03-10 上海泰矽微电子有限公司 Design system and method for enabling Embedded Flash to quickly enter low power consumption

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI665552B (en) * 2018-08-01 2019-07-11 華邦電子股份有限公司 Circuit for recovering from power loss and electronic device using the same circuit and method thereof

Also Published As

Publication number Publication date
WO2013180401A2 (en) 2013-12-05

Similar Documents

Publication Publication Date Title
US6717861B2 (en) Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof
US7616487B2 (en) Decoders and decoding methods for nonvolatile semiconductor memory devices
KR101721005B1 (en) Method of programming a non-volatile semiconductor memory device
TWI715871B (en) Improved flash memory cell and associated decoders
US6111785A (en) Nonvolatile semiconductor memory device capable of decreasing layout area for writing defective address
US9633735B2 (en) System and method to inhibit erasing of portion of sector of split gate flash memory cells
US9025382B2 (en) Lithography-friendly local read circuit for NAND flash memory devices and manufacturing method thereof
JP4338656B2 (en) Method for writing semiconductor memory device
TWI691971B (en) Method and apparatus for configuring array columns and rows for accessing flash memory cells
US7724582B2 (en) Decoders and decoding methods for nonvolatile memory devices using level shifting
JP2006114121A (en) Nonvolatile semiconductor memory device and its writing method
US9837161B2 (en) Split-gate memory having sector retirement with reduced current and method therefor
US9564238B1 (en) Flash memory system using memory cell as source line pull down circuit
JP5329815B2 (en) Flash memory device
CN107430882B (en) Memory cell and memory device
TWI576856B (en) High voltage tolerant row driver
TW201349243A (en) Pure logic compatible nonvolatile memory
KR100673408B1 (en) Momory cell and memory device employing single electron transistor
US5973967A (en) Page buffer having negative voltage level shifter
US6868004B2 (en) Thin film magnetic memory device suppressing resistance of transistors present in current path
KR20130133111A (en) Pure logic compatible flash memory
JP3181478B2 (en) Nonvolatile semiconductor memory device
TWI588830B (en) Current detection circuit and semiconductor memory apparatus
JPH02133960A (en) Writable nonvolatile semiconductor memory device
JP5045696B2 (en) Semiconductor memory device and writing method thereof