TWI621180B - 使用選擇性沉積之金屬與介層洞的自行對準 - Google Patents
使用選擇性沉積之金屬與介層洞的自行對準 Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 title claims description 68
- 239000002184 metal Substances 0.000 title claims description 68
- 230000008021 deposition Effects 0.000 title abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims abstract description 53
- 238000000059 patterning Methods 0.000 claims abstract description 36
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 239000003989 dielectric material Substances 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 92
- 238000005530 etching Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 20
- 238000012546 transfer Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 230000015271 coagulation Effects 0.000 claims description 3
- 238000005345 coagulation Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 238000012545 processing Methods 0.000 abstract description 19
- 238000001465 metallisation Methods 0.000 abstract description 8
- 230000001681 protective effect Effects 0.000 abstract description 4
- 239000007769 metal material Substances 0.000 abstract 2
- 239000010408 film Substances 0.000 description 28
- 239000012634 fragment Substances 0.000 description 13
- 230000005855 radiation Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000001459 lithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000002094 self assembled monolayer Substances 0.000 description 2
- 239000013545 self-assembled monolayer Substances 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005661 hydrophobic surface Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
本文之技術包括基板圖案化的方法,例如用於後段(BEOL,back end of line)金屬化處理。本文之技術實現完全自行對準的介層洞及線。本文之處理包括使用選擇性沉積、保護膜、及組合蝕刻遮罩,以精準地使基板圖案化。在具有金屬材料及介電材料的被揭開部份的基板中,使介電材料向上生長,但不覆蓋金屬材料。此凸起的介電材料係受到保形地保護,並且用於後續圖案化步驟以使介層洞及線的設置對準。這樣的組合減輕了覆蓋誤差。
Description
[相互申請案之交互參照]本申請案主張申請於2016年2月2日、名稱為「Self-Alignment of Metal and Via Using Selective Deposition」的美國臨時專利申請案第62/290282號,其係於此全部併入作為參考。
此揭露內容涉及基板處理,尤其有關用於基板圖案化(包括半導體晶圓圖案化)的技術。
微影製程中之縮小線寬的方法歷來包含使用較大NA(numerical aperture,數值孔徑)的光學元件、較短曝光波長、或除了空氣以外的界面介質(例如水浸入)。隨著習知微影製程的解析度接近理論極限,製造者開始轉向雙重圖案化(DP,double-patterning)方法,以克服光學限制。
在材料處理方法中(如光微影),產生圖案化之層包含:將幅射敏感性材料(如光阻)的薄層塗佈在基板的上表面。此幅射敏感性材料轉變為一起伏圖案,其可作為將圖案轉移至基板上的下方層內之蝕刻遮罩。使幅射敏感性材料圖案化通常涉及利用例如光微影系統並經由遮罩(及相關光學元件)而使光化性輻射線曝射在幅射敏感性材料上。在曝射後,接著可使用顯影劑將幅射敏感性材料的被照射區域移除(例如正光阻的情況)、或將未被照射區域移除(例如負光阻的情況)。此遮罩層可包含多數子層。
使輻射線或光線的圖案曝射在基板上的習知微影技術具有各種挑戰,這些挑戰限制曝光特徵部的尺寸、及限制曝光特徵部之間的節距或間距。用以減輕曝光限制的一種習知技術係使用雙重圖案化方法,其允許以比目前可能的習知微影技術的更小節距來圖案化更小特徵部。
隨著製作更小的裝置,圖案化特徵部的臨界尺寸(CD,critical dimension)或解析度對生產而言變得越具挑戰性。此外,另一挑戰為覆蓋的問題,例如光微影未對準。若遮罩及圖案未適當對準,則可能發生裝置缺陷及失效,例如線在期望的位置被部份切割或未被切割,或例如開口錯位或在其他情況下產生短路。由於金屬線及介層洞的多數層將使電晶體互相連接,故上述未對準問題是基板金屬化的一項挑戰。不僅覆蓋問題是一項挑戰,而且金屬化的另一挑戰為在不損壞周圍介電材料的情況下,產生溝渠及介層洞。
本文之技術包括基板圖案化的方法,例如用於後段(BEOL,back end of line)金屬化處理。本文之技術實現完全自行對準的介層洞及線。本文之處理包括使用選擇性沉積、保護膜、及組合蝕刻遮罩,以精準地使基板圖案化。
在一實施方式中,接收具有複數第一金屬線的基板,該些第一金屬線與複數第一介電線在基板的工作表面上相間隔。該些第一金屬線及該些第一介電線係被揭開,並且一起定義一平面表面。藉由選擇性地在該些第一介電線上沉積介電材料,但不在該些第一金屬線上沉積介電材料,而在該些第一介電線上形成複數第二介電線。該些第二介電線定義複數溝渠,並且使該些第一金屬線處於揭開的狀態。替代性地,相對於該些第一介電線而使該些第一金屬線凹入。
在基板的工作表面上沉積保形膜。保形膜覆蓋該些第二介電線的側壁及頂面,並且覆蓋該些第一金屬線的頂面。保形膜提供一預定蝕刻抗性。沉積介電層,該介電層填充所定義之該些溝渠、覆蓋該些第二介電線、並為基板的工作表面提供一平面表面。在介電層上方形成第一起伏圖案,第一起伏圖案定義欲轉移至介電層內之複數第二金屬線的位置。在介電層上方形成第二起伏圖案。第二起伏圖案定義欲轉移至介電層內之複數介層洞的位置。
藉由利用第二起伏圖案作為第一蝕刻遮罩,並蝕穿介電層而停止在該些第一金屬線上方的保形膜上,以將第二起伏圖案轉移至介電層內。保形膜防止被第二起伏圖案所揭開的該些第二介電線及該些第一金屬線受到蝕刻。藉由利用第一起伏圖案作為第二蝕刻遮罩以蝕刻至介電層內,並利用保形膜作為蝕刻停止層而停止在該些第二介電線的頂面上,以將第一起伏圖案轉移至介電層內。隨後,可移除該些起伏圖案,並且金屬化基板具有完全自行對準的介層洞。
當然,為了清楚說明起見而提出如於此所述之各個步驟的討論順序。一般而言,這些步驟可以任何適當的順序執行。此外,雖然本文之各個不同的特徵、技術、配置等等會在此揭露內容的不同地方予以討論,但意欲使各個概念可彼此獨立執行或彼此結合執行。因此,本發明可用許多不同方式來實現及看待。
應注意到此發明內容章節並非要指出本揭露內容或所請發明的每一個實施方式及/或增加新穎性實施態樣。反而此發明內容章節僅提供不同實施方式及相對於習知技術具有新穎特點的初步討論。關於本發明及實施方式的額外細節及/或可能觀點,讀者可詳見如以下進一步討論之本揭露內容的實施方式章節及對應圖式。
本文之技術包括基板圖案化的方法,例如用於後段(BEOL)金屬化處理。本文之技術實現完全自行對準的介層洞及線。本文之處理包括使用選擇性沉積、保護膜、及組合蝕刻遮罩,以精準地使基板圖案化。這樣的組合藉由使用下方結構而使圖案自行對準來減輕覆蓋誤差,並且保護介電材料以避免退化。
實施方式包括基板(例如半導體晶圓)圖案化的方法。現在參考圖1A及1B,接收具有第一金屬線111的基板,第一金屬線111與第一介電線121在基板105的工作表面上相間隔。第一金屬線111及第一介電線121係被揭開,並且一起定義一平面表面。這樣的表面可為化學機械研磨(CMP,chemical-mechanical polishing)步驟的結果。注意到基板的整個工作表面可不包括上述間隔線,但至少一些部份或區域具有這些間隔線。亦應注意這些線可為直線或曲線。基板的其他部份可具有各種不同的結構。此外,基板在該間隔線之層的下方可具有接觸孔,接觸孔將金屬線連接至裝置(如電晶體)。下方層107係描述為單一材料,但多數層及結構可組成下方層107。圖1A、1B及後續圖式範例基板片段的立體圖,其中帶有字母「A」的圖式顯示一立體圖,且帶有字母「B」的圖式顯示一接近側視之不同角度的立體圖,藉此更能顯示本文的示範性處理。
現在參考圖2A及2B,藉由選擇性沉積介電材料在第一介電線121上,但不沉積介電材料在第一金屬線111上,而在第一介電線121上形成第二介電線122。因此,第二介電線122定義溝渠,而使第一金屬線111處於揭開狀態。換言之,在使用選擇性沉積技術的情況下,介電線係實質上向上生長。這些第二介電線122的高度可等於所欲製作之對應的介層洞的預定設計高度(舉例而言)。可選擇使用各種材料。例如,第一介電線可為氧化物材料,並接著將更多氧化物材料(或其他介電材料)沉積在其上,但不沉積在第一金屬線上(或在第一金屬線正上方)。因此,沉積不應有輪廓退化。
沉積在第一介電線121上的特定介電材料可獲益於選擇具有類似第一介電線的特性(其可包括極低K值材料)。可使用各種技術來完成選擇性沉積。其中一種技術係氣相自組裝單分子層(SAM,self-assembled monolayer)。可使用原子層沉積(ALD,atomic layer deposition),但ALD製程會被疏水性表面抑制。因此,可執行表面處理,以藉由將濕潤角度改變成與特定沉積材料相容,從而增進選擇性沉積處理。
現在參考圖3A及3B,保形膜130係沉積在基板105的工作表面上。保形膜130覆蓋第二介電線122的側壁及頂面,並且覆蓋第一金屬線111的頂面。保形膜130提供一預定蝕刻抗性。較佳地,保形膜130的蝕刻抗性係不同於介電材料及金屬的蝕刻抗性。因此,能使用特定化學品來蝕刻介電材料,但不蝕刻保形膜材料。換言之,將相對的薄膜沉積在基板的工作表面上,以作為後續步驟中的蝕刻停止層(至少作為介層洞蝕刻的蝕刻停止層)。沉積在金屬線上方的特定保形膜可獲益於與所使用之介電材料具有相同的介電特性,但具有不同的蝕刻選擇性。
現在參考圖4A及4B,介電層135係沉積在基板上,以使介電層135填充所定義之溝渠、覆蓋第二介電線122、並為基板的工作表面提供一平面表面。例如,可藉由旋塗沉積來沉積介電層,以使基板的工作表面實質上平面化,並填充所定義之全部開口及提供過量的材料。可使用其他能產生提供一平面表面之介電層的沉積技術。具有一平面表面係有利於形成在其上的後續蝕刻遮罩。
現在參考圖5A及5B,第一起伏圖案141係形成在介電層135上方。第一起伏圖案141定義欲轉移至介電層135內之第二金屬線的位置。如此之第一起伏圖案可為習知光微影圖案化及/或雙重圖案化技術(如自行對準四重圖案化處理)的結果。第一起伏圖案141可為一光阻圖案,或可形成在硬遮罩材料(如鈦氮化物)內。具有含金屬硬遮罩可提供蝕刻選擇性的好處。
現在參考圖6A及6B,第二起伏圖案142係形成在介電層135上方。第二起伏圖案可定義欲轉移至介電層內之介層洞的位置。換言之,可產生介層洞「保留」(keep)圖案。應注意到,可使用額外的中間層,例如:平坦化層、抗反射塗層等等。第二起伏圖案可形成在第一起伏圖案上方,或與第一起伏圖案在相同平面,例如藉由執行防止第一起伏圖案的後續溶解度變化之凝結操作。
藉由利用第二起伏圖案142作為第一蝕刻遮罩,並蝕穿介電層135而停止在第一金屬線上方的保形膜上,以使第二起伏圖案142(或是由此起伏圖案所定義的圖案)轉移至介電層135內。保形膜130防止被第二起伏圖案所揭開的第二介電線及第一金屬線受到蝕刻。換言之,將基板向下蝕刻至介電層135內,直到溝渠的底部(其中第一蝕刻遮罩允許方向性蝕刻),但停止在位於第一金屬線之正上方之保形膜上。應注意到,覆蓋在保形膜中的凸起介電線作為對準導引,以確保將介層洞蝕刻在期望的位置。圖7A及7B顯示了在上述蝕刻後的示範結果。這些圖式顯示基板上沒有第二起伏圖案142(及其伴隨的平坦化層)的情況,以更適當地顯示出在介層洞不與金屬線重疊的情況下,如何將介層洞向下蝕刻至金屬線。任何由於對準誤差的重疊將位於凸起介電線(第二介電線122)的頂部上。此蝕刻步驟實質上產生用於形成介層洞的空間,其停止在位於第一金屬線上方、但位於第二介電線頂面下方的下格層或蝕刻停止層上。
藉由利用第一起伏圖案141作為第二蝕刻遮罩以蝕刻至介電層135內,並利用保形膜130作為蝕刻停止層而停止在第二介電線122的頂面上,以將第一起伏圖案141係轉移至介電層135內。換言之,溝渠(待填入金屬)係產生在介電層內,但介電層僅部份且非完全蝕刻。執行蝕刻步驟,直到揭開或部份揭開第二介電線122的頂面為止,亦即直到揭開這些頂面上的保形膜(保護膜)為止。圖8A及8B顯示一示範結果。應注意到,第二介電線122的頂面已被揭開,但介電材料仍填充在第二介電線之間的溝渠內(除了已被蝕刻的介層洞處)。因此,在至少介層洞係自行對準且該圖案化步驟不受覆蓋誤差影響的情況下,於介電層135內產生溝渠及介層洞。
在產生用於線及介層洞的空間之情況下,可將基板金屬化。移除第一起伏圖案141,並接著藉由用預定金屬112(例如:銅、鋁等等)填充溝渠及介層洞,以使基板金屬化。金屬沉積可產生過量的金屬,然後能藉由CMP或其他平坦化處理將其移除。圖9A及9B顯示一示範結果。在金屬化之前,且移除第一起伏圖案及第二起伏圖案之後,可將保形膜的被揭開部份移除。換言之,可執行穿透蝕刻以揭開第一金屬線,以使介層洞電性連接。如此之穿透蝕刻可揭開第二介電線的頂部,而且由於保形膜及介電層皆可作為絕緣體,故這是可接受的。在一些實施方式中,所有的介電線及介電層可選自相同材料。
一些替代性方法可用以產生金屬化的自行對準。例如,圖10A及10B顯示類似圖1A及1B的開始點。然而,可使用凹入蝕刻來產生自行對準特徵部,以代替選擇性沉積。參考圖11A及11B,蝕刻處理使第一金屬線111凹入至第一介電線121的頂面以下。此金屬凹入實質上提供凸起的介電線,以作為介層洞的自行對準。圖12A及12B顯示保形膜130沉積在具有凹入金屬線的基板上。然後,可接續如以上所述之處理流程。
本文之技術比習知技術具有更多優點。這些優點包括:介層洞形狀係由上方及下方金屬層所定義,臨界尺寸(CD,critical dimension)及臨界尺寸均勻性係由自行對準所定義。邊緣設置誤差(EPE,edge placement error)係經由自行對準來控制。此技術允許「跨越」( fly-overs)或鄰近的介層洞圖案化。這樣的介層洞圖案化可減化以「保留」(keep)遮罩。因此,本文之技術能實現對上方及下方金屬層兩者的完全自行對準。
在先前敘述中,已提出一些具體細節,例如:一處理系統的特定幾何結構、以及其中所使用的各種元件和製程之敘述。然而,應注意到本文之技術可在偏離這些具體細節的其他實施方式中加以實施,並且這些細節係作為說明之目的而非限制性。於此所揭露之實施方式已參照附圖而加以敘述。同樣地,為了說明之目的而提出具體數量、材料、及配置,故提供徹底之瞭解。儘管如此,仍可在不具有如此具體細節的情況下實現這些實施方式。實質上具有相同功能結構之元件係以同樣的參考符號表示,且因此省略任何冗贅的敘述。
各個技術內容已描述為多個分離操作,以幫助瞭解各種實施方式。描述的順序不應被理解為暗示著這些操作必須依照這些順序。事實上,這些操作並不需依照描述之順序執行。所描述之操作可按不同於所敘述之實施方式的順序來執行。在額外的實施方式中,可執行各種額外操作且/或可省略所敘述之操作。
如於此所使用之「基板」或「目標基板」一般是指依據本發明所處理之物件。基板可包括裝置(尤其是半導體或其他電子裝置)的任何材料部份或結構,並且可例如為一基底基板結構(如半導體晶圓)、或是在基底基板結構上或覆蓋基底基板結構之一層(如一薄膜)。因此,基板並不限於任何特定基底結構、下方層、或上覆層(圖案化或不圖案化),而是預期包括任何這類的層或基底結構、以及這些層及/或基底結構的任何組合。本說明書可能涉及特定類型的基板,但這只是為了說明之目的。
本領域中具有通常技術者亦將瞭解可對以上說明之技術操作做出許多變化,而同時仍可達到本發明之相同目標。欲使如此之變化涵蓋在本揭露內容的範圍內。因此,上述之本發明實施方式敘述並非意欲為限制性。反而任何對本發明之實施方式的限制係敘述在以下申請專利範圍中。
105 基板 107 下方層 111 第一金屬線 112 金屬 121 第一介電線 122 第二介電線 130 保形膜 135 介電層 141 第一起伏圖案 142 第二起伏圖案
在參照以下配合附圖之詳細描述後,本發明之各種實施方式及許多其伴隨優點的更完整理解將立刻變得顯而易知。這些圖式並不一定按照比例繪製,而是強調說明其特徵、原理、及概念。
圖1A及1B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的處理流程。
圖2A及2B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的選擇性沉積及處理流程。
圖3A及3B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的保形膜沉積及處理流程。
圖4A及4B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的平坦化及處理流程。
圖5A及5B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的遮罩產生及處理流程。
圖6A及6B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的遮罩產生及處理流程。
圖7A及7B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的圖案轉移及處理流程。
圖8A及8B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的圖案轉移及處理流程。
圖9A及9B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的金屬化及處理流程。
圖10A及10B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的處理流程。
圖11A及11B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的金屬凹部及處理流程。
圖12A及12B係範例基板片段的橫剖面示意圖,其顯示根據於此所揭露之實施方式的保形膜沉積及處理流程。
Claims (20)
- 一種用於基板圖案化的方法,該方法包含: 接收具有複數第一金屬線的基板,該些第一金屬線與複數第一介電線在該基板的工作表面上相間隔,該些第一金屬線及該些第一介電線係被揭開,並且一起定義一平面表面; 藉由選擇性地在該些第一介電線上沉積介電材料,但不在該些第一金屬線上沉積介電材料,而在該些第一介電線上形成複數第二介電線,該些第二介電線定義複數溝渠,該些溝渠使該些第一金屬線處於揭開的狀態; 在該基板的工作表面上沉積保形膜,該保形膜覆蓋該些第二介電線的側壁及頂面,並且覆蓋該些第一金屬線的頂面,該保形膜提供一預定蝕刻抗性; 沉積介電層,該介電層填充所定義之該些溝渠、覆蓋該些第二介電線、並為該基板的工作表面提供一平面表面; 在該介電層上方形成第一起伏圖案,該第一起伏圖案定義欲轉移至該介電層內之複數第二金屬線的位置; 在該介電層上方形成第二起伏圖案,該第二起伏圖案定義欲轉移至該介電層內之複數介層洞的位置; 藉由利用該第二起伏圖案作為第一蝕刻遮罩,並蝕穿該介電層而停止在該些第一金屬線上方的該保形膜上,以將該第二起伏圖案轉移至該介電層內,該保形膜防止被該第二起伏圖案所揭開的該些第二介電線及該些第一金屬線受到蝕刻;及 藉由利用該第一起伏圖案作為第二蝕刻遮罩以蝕刻至該介電層內,並利用該保形膜作為蝕刻停止層而停止在該些第二介電線的頂面上,以將該第一起伏圖案轉移至該介電層內。
- 如申請專利範圍第1項之用於基板圖案化的方法,更包含: 移除該第二起伏圖案及該第一起伏圖案;及 用預定金屬填充由該介電層所定義之複數溝渠及複數介層洞,以使該介電層金屬化。
- 如申請專利範圍第1項之用於基板圖案化的方法,更包含:在移除該第二起伏圖案及該第一起伏圖案之後,移除該保形膜的被揭開部份,以揭開該些第一金屬線的頂面。
- 如申請專利範圍第1項之用於基板圖案化的方法,其中該些第一介電線、該些第二介電線、及該介電層係由相同材料所組成。
- 如申請專利範圍第1項之用於基板圖案化的方法,其中形成第一起伏圖案的步驟包括:在沉積於該介電層上方之硬遮罩層中形成該第一起伏圖案。
- 如申請專利範圍第1項之用於基板圖案化的方法,其中在介電層上方形成第二起伏圖案的步驟包括:在該第一起伏圖案上方形成該第二起伏圖案。
- 如申請專利範圍第1項之用於基板圖案化的方法,其中在介電層上方形成第二起伏圖案的步驟包括:在該第一起伏圖案的相同平面形成該第二起伏圖案。
- 如申請專利範圍第7項之用於基板圖案化的方法,其中在第一起伏圖案的相同平面形成第二起伏圖案的步驟包括:執行凝結操作,以防止該第一起伏圖案的後續溶解度變化。
- 如申請專利範圍第2項之用於基板圖案化的方法,其中該預定金屬係銅。
- 如申請專利範圍第2項之用於基板圖案化的方法,其中使介電層金屬化的步驟包括:移除該介電層的頂面上方之過量的該預定金屬。
- 一種用於基板圖案化的方法,該方法包含: 接收具有複數第一金屬線的基板,該些第一金屬線與複數第一介電線在該基板的工作表面上相間隔,該些第一金屬線及該些第一介電線係皆被揭開,並且定義一平面表面; 使該些第一金屬線凹入至該些第一介電線的頂面以下的一預定距離; 在該基板的工作表面上沉積保形膜,該保形膜覆蓋該些第一介電線的側壁及頂面,並且覆蓋該些第一金屬線的頂面,該保形膜提供一預定蝕刻抗性; 沉積介電層,該介電層填充由該些第一介電線所定義之複數溝渠、覆蓋該些第一介電線、並為該基板的工作表面提供一平面表面; 在該介電層上方形成第一起伏圖案,該第一起伏圖案定義欲轉移至該介電層內之複數第二金屬線的位置; 在該介電層上方形成第二起伏圖案,該第二起伏圖案定義欲轉移至該介電層內之複數介層洞的位置; 藉由利用該第二起伏圖案作為第一蝕刻遮罩,並蝕穿該介電層而停止在該些第一金屬線上方的該保形膜上,以將該第二起伏圖案轉移至該介電層內,該保形膜防止被該第二起伏圖案所揭開的該些第一介電線及該些第一金屬線受到蝕刻;及 藉由利用該第一起伏圖案作為第二蝕刻遮罩以蝕刻至該介電層內,並利用該保形膜作為蝕刻停止層而停止在該些第一介電線的頂面上,以將該第一起伏圖案轉移至該介電層內。
- 如申請專利範圍第11項之用於基板圖案化的方法,更包含: 移除該第二起伏圖案及該第一起伏圖案;及 用預定金屬填充由該介電層所定義之複數溝渠及複數介層洞,以使該介電層金屬化。
- 如申請專利範圍第11項之用於基板圖案化的方法,更包含:在移除該第二起伏圖案及該第一起伏圖案之後,移除該保形膜的被揭開部份,以揭開該些第一金屬線的頂面。
- 如申請專利範圍第11項之用於基板圖案化的方法,其中該些第一介電線及該介電層係由相同材料所組成。
- 如申請專利範圍第11項之用於基板圖案化的方法,其中形成第一起伏圖案的步驟包括:在沉積於該介電層上方之硬遮罩層中形成該第一起伏圖案。
- 如申請專利範圍第11項之用於基板圖案化的方法,其中在介電層上方形成第二起伏圖案的步驟包括:在該第一起伏圖案上方形成該第二起伏圖案。
- 如申請專利範圍第11項之用於基板圖案化的方法,其中在介電層上方形成第二起伏圖案的步驟包括:在該第一起伏圖案的相同平面形成該第二起伏圖案。
- 如申請專利範圍第17項之用於基板圖案化的方法,其中在第一起伏圖案的相同平面形成第二起伏圖案的步驟包括:執行凝結操作,以防止該第一起伏圖案的後續溶解度變化。
- 如申請專利範圍第12項之用於基板圖案化的方法,其中該預定金屬係銅。
- 如申請專利範圍第11項之用於基板圖案化的方法,其中該預定距離等於所設計之欲產生之介層洞的指定高度。
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