SG11201806578XA - Self-alignment of metal and via using selective deposition - Google Patents
Self-alignment of metal and via using selective depositionInfo
- Publication number
- SG11201806578XA SG11201806578XA SG11201806578XA SG11201806578XA SG11201806578XA SG 11201806578X A SG11201806578X A SG 11201806578XA SG 11201806578X A SG11201806578X A SG 11201806578XA SG 11201806578X A SG11201806578X A SG 11201806578XA SG 11201806578X A SG11201806578X A SG 11201806578XA
- Authority
- SG
- Singapore
- Prior art keywords
- international
- pct
- dielectric material
- selective deposition
- self
- Prior art date
Links
- 230000008021 deposition Effects 0.000 title abstract 3
- 239000002184 metal Substances 0.000 title abstract 2
- 238000000034 method Methods 0.000 abstract 5
- 239000003989 dielectric material Substances 0.000 abstract 3
- 238000000059 patterning Methods 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- 239000003795 chemical substances by application Substances 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 2
- 239000007769 metal material Substances 0.000 abstract 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 244000000188 Vaccinium ovalifolium Species 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 230000008520 organization Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Acyclic And Carbocyclic Compounds In Medicinal Compositions (AREA)
Abstract
INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization 111111110111101110101011111010111110111011100110111111011111111101111011111 International Bureau ... ..... ..Yi j (10) International Publication Number (43) International Publication Date ..... ...r .....1 WO 2017/136577 Al 10 August 2017(10.08.2017) WIPO I PCT (51) International Patent Classification: (74) Agent: MATHER, Joshua D.; Tokyo Electron U.S. Hold- HO1L 21/768 (2006.01) H01L 21/3205 (2006.01) ings, Inc., 2400 Grove Boulevard, Austin, Texas 78741 (US). (21) International Application Number: PCT/US2017/016253 (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, (22) International Filing Date: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, 2 February 2017 (02.02.2017) BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, (25) Filing Language: English DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, (26) Publication Language: English KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, (30) Priority Data: MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, 62/290,282 2 February 2016 (02.02.2016) US NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, (71) Applicant: TOKYO ELECTRON LIMITED [JP/JP]; TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, Akasaka Biz Tower, 3-1 Akasaka 5-chome, Minato-ku, ZA, ZM, ZW. Tokyo 107-6325 (JP). (84) Designated States (unless otherwise indicated, for every (71) Applicant (for JP only): TOKYO ELECTRON U.S. kind of regional protection available): ARIPO (BW, GH, HOLDINGS, INC. [US/US]; 2400 Grove Boulevard, Aus- GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, tin, Texas 78741 (US). TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, (72) Inventors: SMITH, 12 Wild Flower Way, Clifton TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, Jeffrey; Park New York 12065 (US). DEVILLIERS, Anton J.; DK, , EE, ES, FL FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, 734 Tanner Rd., Clifton Park, New York 12065 (US). LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CL CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). [Continued on next page] Title: SELF-ALIGNMENT OF METAL AND VIA USING SELECTIVE DEPOSITION = (54) 105 (57) : Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. i , .. , }141 135 In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent pattern- ing step to align via and line placement. Such combinations mitigate overlay errors. 130 1-1 111 N IN ir) cr) 1-1 FIG. 7A IN 1-1 0 ei 0 WO 2017/136577 Al MIDEDIM011111 11111111ME3011110111110011111111111111011110111111 Published: — before the expiration of the time limit for amending the — with international search report (Art. 21(3)) claims and to be republished in amendments (Rule 48.2(h)) the event of receipt of
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662290282P | 2016-02-02 | 2016-02-02 | |
PCT/US2017/016253 WO2017136577A1 (en) | 2016-02-02 | 2017-02-02 | Self-alignment of metal and via using selective deposition |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201806578XA true SG11201806578XA (en) | 2018-09-27 |
Family
ID=59387688
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201806578XA SG11201806578XA (en) | 2016-02-02 | 2017-02-02 | Self-alignment of metal and via using selective deposition |
Country Status (6)
Country | Link |
---|---|
US (1) | US9837314B2 (en) |
KR (1) | KR102142795B1 (en) |
CN (1) | CN108780777B (en) |
SG (1) | SG11201806578XA (en) |
TW (1) | TWI621180B (en) |
WO (1) | WO2017136577A1 (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI729457B (en) | 2016-06-14 | 2021-06-01 | 美商應用材料股份有限公司 | Oxidative volumetric expansion of metals and metal containing compounds |
TWI719262B (en) | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | Deposition and treatment of films for patterning |
EP3539154A4 (en) | 2016-11-08 | 2020-06-03 | Applied Materials, Inc. | Geometric control of bottom-up pillars for patterning applications |
WO2018156710A1 (en) | 2017-02-22 | 2018-08-30 | Applied Materials, Inc. | Critical dimension control for self-aligned contact patterning |
US10424507B2 (en) | 2017-04-04 | 2019-09-24 | Mirocmaterials LLC | Fully self-aligned via |
WO2018200212A1 (en) | 2017-04-25 | 2018-11-01 | Applied Materials, Inc. | Selective deposition of tungsten for simplified process flow of tungsten oxide pillar formation |
US10840186B2 (en) | 2017-06-10 | 2020-11-17 | Applied Materials, Inc. | Methods of forming self-aligned vias and air gaps |
TW201906035A (en) | 2017-06-24 | 2019-02-01 | 美商微材料有限責任公司 | Method of producing fully self-aligned vias and contacts |
JP6942555B2 (en) * | 2017-08-03 | 2021-09-29 | 東京エレクトロン株式会社 | Board processing method, computer storage medium and board processing system |
US10573555B2 (en) | 2017-08-31 | 2020-02-25 | Micromaterials Llc | Methods of producing self-aligned grown via |
WO2019046399A1 (en) | 2017-08-31 | 2019-03-07 | Micromaterials Llc | Methods of producing self-aligned vias |
WO2019050735A1 (en) | 2017-09-06 | 2019-03-14 | Micromaterials Llc | Methods of producing self-aligned vias |
CN107968047A (en) | 2017-11-23 | 2018-04-27 | 长江存储科技有限责任公司 | A kind of SADP page buffers cutting-off method and structure |
US10727056B2 (en) | 2017-11-23 | 2020-07-28 | Yangtze Memory Technologies Co., Ltd. | Method and structure for cutting dense line patterns using self-aligned double patterning |
CN110034017A (en) | 2017-12-07 | 2019-07-19 | 微材料有限责任公司 | Method for making metal and barrier layer-liner controllably be recessed |
EP3499557A1 (en) | 2017-12-15 | 2019-06-19 | Micromaterials LLC | Selectively etched self-aligned via processes |
KR20190104902A (en) | 2018-03-02 | 2019-09-11 | 마이크로머티어리얼즈 엘엘씨 | Methods for removing metal oxides |
US10790191B2 (en) | 2018-05-08 | 2020-09-29 | Micromaterials Llc | Selective removal process to create high aspect ratio fully self-aligned via |
TW202011547A (en) | 2018-05-16 | 2020-03-16 | 美商微材料有限責任公司 | A method for creating a fully self-aligned via |
US10699953B2 (en) | 2018-06-08 | 2020-06-30 | Micromaterials Llc | Method for creating a fully self-aligned via |
US10957579B2 (en) | 2018-11-06 | 2021-03-23 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a via and methods of forming the same |
US11164938B2 (en) | 2019-03-26 | 2021-11-02 | Micromaterials Llc | DRAM capacitor module |
US11437274B2 (en) | 2019-09-25 | 2022-09-06 | Micromaterials Llc | Fully self-aligned via |
EP3836198B1 (en) | 2019-12-12 | 2022-08-24 | Imec VZW | A method for forming a via hole self-aligned with a metal block on a substrate |
US20220238323A1 (en) * | 2021-01-28 | 2022-07-28 | Tokyo Electron Limited | Method for selective deposition of dielectric on dielectric |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62261156A (en) * | 1986-04-30 | 1987-11-13 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Method of forming conductive via route |
CN1358329A (en) * | 2000-01-20 | 2002-07-10 | 皇家菲利浦电子有限公司 | Damascene structure and method for forming damascene structure |
US6713395B2 (en) * | 2001-05-15 | 2004-03-30 | Infineon Technologies Ag | Single RIE process for MIMcap top and bottom plates |
KR100434505B1 (en) | 2002-06-19 | 2004-06-05 | 삼성전자주식회사 | Method for fabricating semiconductor devices by forming damascene interconnections |
US7041748B2 (en) * | 2003-01-08 | 2006-05-09 | International Business Machines Corporation | Patternable low dielectric constant materials and their use in ULSI interconnection |
US6958540B2 (en) * | 2003-06-23 | 2005-10-25 | International Business Machines Corporation | Dual damascene interconnect structures having different materials for line and via conductors |
KR100833201B1 (en) | 2007-06-15 | 2008-05-28 | 삼성전자주식회사 | Semiconductor device having fine patterns of wiring line integrated with contact plug and method of manufacturing the same |
US7829262B2 (en) | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7488685B2 (en) * | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7651947B2 (en) * | 2006-05-25 | 2010-01-26 | International Business Machines Corporation | Mask forming and implanting methods using implant stopping layer and mask so formed |
US7723237B2 (en) * | 2006-12-15 | 2010-05-25 | Tokyo Electron Limited | Method for selective removal of damaged multi-stack bilayer films |
US7700427B2 (en) * | 2007-06-13 | 2010-04-20 | Qimonda Ag | Integrated circuit having a Fin structure |
US20090093100A1 (en) * | 2007-10-09 | 2009-04-09 | Li-Qun Xia | Method for forming an air gap in multilevel interconnect structure |
US8026179B2 (en) | 2009-04-09 | 2011-09-27 | Macronix International Co., Ltd. | Patterning method and integrated circuit structure |
US8216939B2 (en) * | 2010-08-20 | 2012-07-10 | Micron Technology, Inc. | Methods of forming openings |
US8298943B1 (en) * | 2011-05-27 | 2012-10-30 | International Business Machines Corporation | Self aligning via patterning |
US8916337B2 (en) * | 2012-02-22 | 2014-12-23 | International Business Machines Corporation | Dual hard mask lithography process |
KR101883294B1 (en) * | 2012-03-28 | 2018-07-30 | 삼성전자주식회사 | Method for forming fine patterns of semiconductor device |
US8668835B1 (en) * | 2013-01-23 | 2014-03-11 | Lam Research Corporation | Method of etching self-aligned vias and trenches in a multi-layer film stack |
US9129906B2 (en) * | 2013-12-05 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned double spacer patterning process |
US9041217B1 (en) * | 2013-12-18 | 2015-05-26 | Intel Corporation | Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects |
US9236342B2 (en) * | 2013-12-18 | 2016-01-12 | Intel Corporation | Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects |
US9209077B2 (en) * | 2013-12-20 | 2015-12-08 | Intel Corporation | Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects |
KR102377372B1 (en) * | 2014-04-02 | 2022-03-21 | 어플라이드 머티어리얼스, 인코포레이티드 | Method for forming interconnects |
US9698200B2 (en) * | 2015-10-08 | 2017-07-04 | Globalfoundries Singapore Pte. Ltd. | Magnetism-controllable dummy structures in memory device |
-
2017
- 2017-02-02 SG SG11201806578XA patent/SG11201806578XA/en unknown
- 2017-02-02 CN CN201780017126.1A patent/CN108780777B/en active Active
- 2017-02-02 WO PCT/US2017/016253 patent/WO2017136577A1/en active Application Filing
- 2017-02-02 TW TW106103431A patent/TWI621180B/en active
- 2017-02-02 KR KR1020187025362A patent/KR102142795B1/en active IP Right Grant
- 2017-02-02 US US15/423,320 patent/US9837314B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20170221760A1 (en) | 2017-08-03 |
WO2017136577A1 (en) | 2017-08-10 |
CN108780777A (en) | 2018-11-09 |
US9837314B2 (en) | 2017-12-05 |
TWI621180B (en) | 2018-04-11 |
KR20180113200A (en) | 2018-10-15 |
KR102142795B1 (en) | 2020-09-14 |
CN108780777B (en) | 2023-02-17 |
TW201740464A (en) | 2017-11-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG11201806578XA (en) | Self-alignment of metal and via using selective deposition | |
SG11201810373YA (en) | Method for patterning a substrate using a layer with multiple materials | |
SG11201811396XA (en) | Extreme ultraviolet mask blank with multilayer absorber and method of manufacture | |
SG11201900218TA (en) | Layer 2 relay to support coverage and resource-constrained devices in wireless networks | |
SG11201811602QA (en) | Extreme ultraviolet mask blank with alloy absorber and method of manufacture | |
SG11201901207TA (en) | Strip process for high aspect ratio structure | |
SG11201805070TA (en) | Vapor disposition of silicon-containing films using penta-substituted disilanes | |
SG11201807803SA (en) | Semiconductor package and method of forming the same | |
SG11201809395XA (en) | Executable logic for processing keyed data in networks | |
SG11201806451VA (en) | Method and system for forming memory fin patterns | |
SG11201810919UA (en) | Engineered substrate structure for power and rf applications | |
SG11201807705RA (en) | Directional lock for interface headgear arrangement | |
SG11201808715RA (en) | Electro-polarizable compound and capacitor | |
SG11201905918RA (en) | Feedback techniques for wireless communications | |
SG11201803993XA (en) | Narrow band prach with multiple tone hopping distances | |
SG11201907057VA (en) | Improvements relating to insulation | |
SG11201810280YA (en) | Spiro-lactam nmda receptor modulators and uses thereof | |
SG11201809883QA (en) | Fan-out wafer-level packaging method and the package produced thereof | |
SG11201808781TA (en) | Coated glass surfaces and method for coating a glass substrate | |
SG11201805001UA (en) | Method of treating influenza a | |
SG11201810411VA (en) | Metamaterial split ring resonator, metamaterial split ring resonator array and energy harvesting apparatus | |
SG11201903241SA (en) | Catheter devices with valves and related methods | |
SG11201808856TA (en) | Production of steviol glycosides in recombinant hosts | |
SG11201803640SA (en) | Method for maintaining signal-to-noise ratio at a user terminal in a satellite system | |
SG11201901469TA (en) | Method and apparatus for sensor and/or actuator data processing on a server |