TWI620253B - Method for building conductive substrate - Google Patents
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Abstract
本發明的導電基板的製法包含有下述步驟：提供一穿孔基板，該穿孔基板包含有二穿孔及二分別環繞該等穿孔的內壁面，且該等穿孔具有相異的內徑；設置一絕緣層於該穿孔基板之該等內壁面上；以及令一充填於該穿孔基板之該等穿孔中的導電膠固化形成一與該絕緣層相接的導電層，並得一導電基板。本發明的導電基板的製法係能令所有的穿孔均充填有適量的導電膠，從而形成缺陷少且具有良好導電性的導電層，進而達到提升電子產品之可靠度之優點。The method for manufacturing a conductive substrate of the present invention comprises the steps of: providing a perforated substrate comprising two perforations and two inner wall surfaces respectively surrounding the perforations, and the perforations have different inner diameters; and providing an insulation Laminating on the inner wall surfaces of the perforated substrate; and curing a conductive paste filled in the perforations of the perforated substrate to form a conductive layer in contact with the insulating layer, and obtaining a conductive substrate. The method for manufacturing the conductive substrate of the present invention enables all the perforations to be filled with an appropriate amount of conductive paste, thereby forming a conductive layer having few defects and having good conductivity, thereby achieving the advantage of improving the reliability of the electronic product.
Description
本發明關於一種承載半導體元件的基板的製法，尤指一種導電基板的製法。The present invention relates to a method of fabricating a substrate carrying a semiconductor component, and more particularly to a method of fabricating a conductive substrate.
現有技術的承載半導體元件的基板，為了使兩分別設置於該基板之本體的相反兩側面上的半導體元件電性相接，係令該基板之本體上形成有貫穿該相反兩側面的導通孔，並以電化學方法沉積導電材料於該導通孔中以形成導電層，使得該等半導體元件能透過該導電層達到電性連接之目的。In the prior art substrate for carrying a semiconductor component, in order to electrically connect two semiconductor elements respectively disposed on opposite sides of the body of the substrate, a via hole penetrating the opposite side surfaces is formed on the body of the substrate. And electrically conducting a conductive material in the via hole to form a conductive layer, so that the semiconductor elements can achieve electrical connection through the conductive layer.
然而，當基板上具有不同孔徑或深度的導通孔時，電化學方法並無法使不同孔徑或深度的導通孔同時達到恰好填滿導電材料的效果。由於電化學方法沉積導電材料於一基板的本體之導通孔中時，僅能施加一組特定的電壓、電流密度等參數條件，而具有不同孔徑或深度的導通孔係需配合不同的電壓、電流密度等參數條件才能剛好填滿有適量的導電材料以形成導電層，導致僅有具有特定孔徑及深度的導通孔可以剛好填滿適量的導電材料，其他的導通孔卻無法剛好填滿適量的導電材料，甚而使獲得的導電層產生許多缺陷，從而影響到包含有基板的電子產品的可靠度。However, when there are via holes of different apertures or depths on the substrate, the electrochemical method does not allow the via holes of different apertures or depths to simultaneously fill the conductive material. Since the electrochemical method deposits the conductive material in the via hole of the body of a substrate, only a specific set of parameter conditions such as voltage and current density can be applied, and the via holes having different apertures or depths need to be matched with different voltages and currents. The parameter conditions such as density can just fill up the proper amount of conductive material to form the conductive layer, so that only the via hole with the specific aperture and depth can just fill the proper amount of conductive material, and the other via holes can not just fill the proper amount of conductive material. The material, even the resulting conductive layer, produces a number of defects that affect the reliability of the electronic product containing the substrate.
鑒於上述現有技術的缺點，本發明的目的在於提供一種導電基板的製法，其係能令所有導通孔都填滿有適量的導電材料，從而減少導電層的缺陷並提升電子產品的可靠度。In view of the above disadvantages of the prior art, it is an object of the present invention to provide a method for fabricating a conductive substrate which is capable of filling all of the via holes with an appropriate amount of conductive material, thereby reducing defects of the conductive layer and improving the reliability of the electronic product.
為達到前述的發明目的，本發明所採取的技術手段係令該導電基板的製法，其步驟包含： 提供一穿孔基板，該穿孔基板包含有二穿孔及二分別環繞該等穿孔的內壁面，且該等穿孔具有相異的內徑； 設置一絕緣層於該穿孔基板之該等內壁面上；以及 令一充填於該穿孔基板之該等穿孔中的導電膠固化形成一與該絕緣層相接的導電層，並得一導電基板。In order to achieve the foregoing object, the technical means adopted by the present invention is a method for manufacturing the conductive substrate, the method comprising: providing a perforated substrate, wherein the perforated substrate comprises two perforations and two inner wall surfaces respectively surrounding the perforations, and The perforations have different inner diameters; an insulating layer is disposed on the inner wall surfaces of the perforated substrate; and a conductive paste filled in the perforations of the perforated substrate is cured to form a contact with the insulating layer The conductive layer and a conductive substrate.
較佳的是，該導電膠包含有一導電填料，該導電填料包含有金(gold)、銀(silver)、銅(copper)或石墨(graphite)。Preferably, the conductive paste comprises a conductive filler comprising gold, silver, copper or graphite.
較佳的是，該導電膠包含有一樹脂，該樹脂包含環氧樹脂(epoxy resin)、有機矽樹脂(organosilicon resin)、酚醛樹脂(phenolic resin)或丙烯酸樹脂(acylic resin)。Preferably, the conductive paste comprises a resin comprising an epoxy resin, an organosilicon resin, a phenolic resin or an acylic resin.
較佳的是，該穿孔基板的材質包含矽(silicon)或鍺(germanium)。Preferably, the material of the perforated substrate comprises silicon or germanium.
較佳的是，該絕緣層的材質包含氧化矽(silicon oxide)或氧化鍺(germanium oxide)。Preferably, the material of the insulating layer comprises silicon oxide or germanium oxide.
較佳的是，各穿孔的內徑為1微米(μm)以上。更佳的是，各穿孔的內徑介於1 μm與200 μm之間。Preferably, each of the perforations has an inner diameter of 1 micrometer (μm) or more. More preferably, the inner diameter of each of the perforations is between 1 μm and 200 μm.
較佳的是，該等穿孔的內徑差為50 μm以上。更佳的是，該等穿孔的內徑差介於50 μm與200 μm之間。Preferably, the perforations have an inner diameter difference of 50 μm or more. More preferably, the inner diameter difference of the perforations is between 50 μm and 200 μm.
較佳的是，該穿孔基板包含有一第一表面及一相反於該第一表面的第二表面，該第一表面包含有一第一部份及一第二部份，該第一表面的第二部份連接於該第一表面的第一部份與該等內壁面之間，該第二表面包含有一第一部份及一第二部份，該第二表面的第二部份連接於該第二表面的第一部份與該等內壁面之間： 設置一第一阻隔層於該第一表面及該第二表面上，該第一阻隔層包含一第一保留區、一第二保留區及一移除區，該第一保留區覆蓋於該等內側壁上，該第二保留區覆蓋於該第一表面之第一部份及該第二表面之第一部份上，該移除區覆蓋於該第一表面之第二部份及該第二表面之第二部份上； 覆蓋一光阻於該第二保留區上； 移除該移除區； 移除該光阻； 蝕刻該第一表面之第二部份及該第二表面之第二部份，以形成一連接於該第一表面之第一部份與該等內壁面之間的第一凹部及一連接於該第二表面之第一部份與該等內壁面之間的第二凹部；以及 設置一與該第一阻隔層之第一保留區及第二保留區相接的第二阻隔層於該第一凹部及該第二凹部上，以獲得一形成於該第一保留區與該第二阻隔層之間的電路溝槽及該絕緣層，該絕緣層包含有該第一保留區、該第二保留區及該第二阻隔層； 且令該充填於該穿孔基板之該等穿孔中的導電膠固化形成該與該絕緣層相接的導電層，並得該導電基板之步驟包含： 充填該導電膠於該穿孔基板之該等穿孔及該電路溝槽中；以及 固化該導電膠以形成該與該絕緣層相接的導電層及一電路層，並獲得該導電基板。Preferably, the perforated substrate includes a first surface and a second surface opposite to the first surface, the first surface includes a first portion and a second portion, and the second surface is second a second portion of the second surface includes a first portion and a second portion, and the second portion of the second surface is coupled to the first portion Between the first portion of the second surface and the inner wall surface: a first barrier layer is disposed on the first surface and the second surface, the first barrier layer comprises a first reserved area and a second reserved And a removal area, the first retention area covers the inner sidewalls, the second retention area covers the first portion of the first surface and the first portion of the second surface, the shift The removing region covers the second portion of the first surface and the second portion of the second surface; covering a photoresist on the second reserved region; removing the removed region; removing the photoresist; Etching the second portion of the first surface and the second portion of the second surface to form a first connection to the first surface a first recess between the inner wall surface and a second recess connected between the first portion of the second surface and the inner wall surface; and a first retention of the first barrier layer And a second barrier layer contacting the second retention region on the first recess and the second recess to obtain a circuit trench formed between the first retention region and the second barrier layer and the insulation a layer, the insulating layer includes the first retention region, the second retention region, and the second barrier layer; and curing the conductive paste filled in the through holes of the perforated substrate to form the insulating layer The conductive layer, and the step of obtaining the conductive substrate comprises: filling the conductive paste in the through holes of the via substrate and the circuit trench; and curing the conductive paste to form the conductive layer contacting the insulating layer and a circuit layer and the conductive substrate is obtained.
藉由將導電膠充填於該穿孔基板的穿孔中之方式，本發明的導電基板的製法係能令所有的穿孔均充填有適量的導電膠，從而避免所形成的導電層產生缺陷並使該導電層具有良好導電性，進而達到提高包含有所述製法所製得的導電基板的電子產品之可靠度之優點。The conductive substrate of the present invention can be filled with a proper amount of conductive paste by filling the conductive paste into the perforations of the perforated substrate, thereby preventing the formed conductive layer from generating defects and making the conductive The layer has good electrical conductivity, which in turn achieves the advantage of increasing the reliability of the electronic product comprising the electrically conductive substrate produced by the process.
另外，本發明的導電基板的製法，係能於形成絕緣層時同時形成電路溝槽，而於充填導電膠時，將導電膠同時充填入各穿孔及該電路溝槽中，從而同時完成導電層及電路層之設置，達到縮短該導電基板的製程時間之優點。In addition, the conductive substrate of the present invention can be formed by simultaneously forming a circuit trench when forming an insulating layer, and filling the conductive paste into each of the via holes and the trench of the circuit while filling the conductive paste, thereby simultaneously completing the conductive layer. And the setting of the circuit layer achieves the advantage of shortening the processing time of the conductive substrate.
請參閱圖1所示，本發明的導電基板的製法包含有：提供一穿孔基板S1之步驟、設置一絕緣層於該穿孔基板上之步驟S2以及令一導電膠充填並固化於該穿孔基板之穿孔中以形成一與該絕緣層相接的導電層，從而獲得該導電基板之步驟S3。於一實施例中，所述導電基板的製法詳述如下。Referring to FIG. 1 , the method for manufacturing a conductive substrate of the present invention comprises the steps of: providing a through-substrate S1, providing an insulating layer on the through-substrate S2, and filling and curing a conductive paste on the perforated substrate. Step S3 is performed to form a conductive layer that is in contact with the insulating layer to obtain the conductive substrate. In an embodiment, the method for manufacturing the conductive substrate is as follows.
請參閱圖2所示，先齊備一原型基板10，該原型基板10包含有一第一表面11、一相反於該第一表面11的側面12及二相反的端壁13，該等端壁13連接於該第一表面11及該側面12之間；於本實施例中，該原型基板10之材質為矽，該原型基板10的厚度為400 μm。於其他實施例中，該原型基板之材質包含有鍺，且該原型基板之厚度介於300 μm至500 μm之間。Referring to FIG. 2, a prototype substrate 10 is prepared. The prototype substrate 10 includes a first surface 11 , a side surface 12 opposite to the first surface 11 , and two opposite end walls 13 . The end walls 13 are connected. Between the first surface 11 and the side surface 12; in the embodiment, the material of the prototype substrate 10 is 矽, and the thickness of the prototype substrate 10 is 400 μm. In other embodiments, the material of the prototype substrate comprises germanium, and the thickness of the prototype substrate is between 300 μm and 500 μm.
接著，以乾蝕刻製程對該第一表面11進行蝕刻以形成二內壁面14及二分別由該等內壁面14環繞的蝕刻凹槽15、16；進一步而言，該第一表面11包含有一第一部份111及一與該第一部份111相接的第二部份112，該第一表面11之第二部份112連接於該第一部份111與該等內壁面14之間，該等蝕刻凹槽15、16具有不同的內徑；於本實施例中，係使用深反應性離子蝕刻技術(deep reactive ion etching，縮寫DRIE)對該第一表面11進行蝕刻，以形成蝕刻凹槽15、16，其中一蝕刻凹槽15的內徑為30 μm，另一蝕刻凹槽16的內徑為100 μm，該等蝕刻凹槽15、16之間的內徑差為70 μm。本實施例於深反應性離子蝕刻技術所使用的蝕刻氣體為六氟化碳(hexafluoroethane)，鈍化氣體為八氟環丁烷(octafluorocyclobutane)。於其他實施例中，亦得以濕蝕刻製程或噴砂製程對該第一表面進行蝕刻。Then, the first surface 11 is etched by a dry etching process to form two inner wall faces 14 and two etched grooves 15, 16 respectively surrounded by the inner wall faces 14; further, the first surface 11 includes a first a portion 111 and a second portion 112 that is in contact with the first portion 111. The second portion 112 of the first surface 11 is connected between the first portion 111 and the inner wall surface 14. The etched grooves 15, 16 have different inner diameters; in the present embodiment, the first surface 11 is etched using deep reactive ion etching (DRIE) to form an etch recess. The grooves 15, 16 have an inner diameter of 30 μm for one etching groove 15 and 100 μm for the other etching groove 16, and the inner diameter difference between the etching grooves 15, 16 is 70 μm. The etching gas used in the deep reactive ion etching technique in this embodiment is hexafluoroethane, and the passivation gas is octafluorocyclobutane. In other embodiments, the first surface is also etched by a wet etch process or a sand blast process.
再來，研磨並拋光該側面12以形成一第二表面21，並得到所述穿孔基板20。該穿孔基板具有該第一表面11、該第二表面21、該等內壁面14、二穿孔22、23及該等端壁13，該等穿孔22、23分別為該等內壁面14所環繞而成型，且該第二表面21包含有一第一部份211、一第二部份212及一第三部份213，該第二表面21的第二部份212連接於該第一部份211與該等內壁面14之間，且該第三部份213與該第一部份211相接；於本實施例中，該等穿孔22、23呈圓形，且該等穿孔22、23之內徑分別為30 μm與100 μm。於其他實施例中，該等穿孔之形狀為矩形。Further, the side surface 12 is ground and polished to form a second surface 21, and the perforated substrate 20 is obtained. The perforated substrate has the first surface 11, the second surface 21, the inner wall surface 14, the two perforations 22, 23 and the end walls 13, and the perforations 22, 23 are surrounded by the inner wall surfaces 14, respectively. The second surface 21 includes a first portion 211, a second portion 212, and a third portion 213. The second portion 212 of the second surface 21 is coupled to the first portion 211. Between the inner wall faces 14 and the third portion 213 is in contact with the first portion 211; in the embodiment, the holes 22, 23 are circular, and the holes 22, 23 are The diameters are 30 μm and 100 μm, respectively. In other embodiments, the perforations are rectangular in shape.
請參閱圖3所示，將一第一阻隔層30設置於該穿孔基板20之第一表面11、第二表面21、該等內壁面14及該等端壁13上，該第一阻隔層30具有一第一保留區31、一第二保留區32、一移除區33，該第一保留區31覆蓋於該等內側壁14上，該第二保留區32覆蓋於該第一表面11之第一部份111、該第二表面21之第一部份211及該等端壁13上，該移除區33覆蓋於該第一表面11之第二部份112、該第二表面21之第二部份212上及該第二表面21之第三部份213上，該移除區33與該第二保留區32相接，且一部分之移除區33同時與該第一保留區31及該第二保留區32相接。於本實施例中，係以化學氣相沉積技術(chemical vapor deposition，縮寫：CVD)形成該第一阻隔層30，該第一阻隔層30之材質為二氧化矽，該第一阻隔層30之厚度為1 μm，其他實施例中，亦得以物理氣相沉積技術(physical vapor deposition，縮寫：PVD)形成該第一阻隔層。Referring to FIG. 3 , a first barrier layer 30 is disposed on the first surface 11 , the second surface 21 , the inner wall surfaces 14 , and the end walls 13 of the perforated substrate 20 , and the first barrier layer 30 . There is a first reserved area 31, a second reserved area 32, and a removed area 33. The first reserved area 31 covers the inner side walls 14. The second reserved area 32 covers the first surface 11. The first portion 111, the first portion 211 of the second surface 21, and the end walls 13 cover the second portion 112 of the first surface 11 and the second surface 21 The second portion 212 and the third portion 213 of the second surface 21, the removal region 33 is in contact with the second retention region 32, and a portion of the removal region 33 is simultaneously with the first retention region 31. And the second reserved area 32 is connected. In the present embodiment, the first barrier layer 30 is formed by chemical vapor deposition (CVD). The material of the first barrier layer 30 is ceria, and the first barrier layer 30 is The thickness is 1 μm. In other embodiments, the first barrier layer is also formed by physical vapor deposition (PVD).
接著，覆蓋一光阻40於該第二保留區32上；於本實施例中，該光阻40為乾膜光阻於另些實施例中，該光阻為濕膜光阻(wet film photoresist)，如AZ系列、TOK系列濕式光阻皆適用本發明。Then, a photoresist 40 is covered on the second retention region 32. In this embodiment, the photoresist 40 is a dry film photoresist. In other embodiments, the photoresist is a wet film photoresist (wet film photoresist). The invention is applicable to both AZ series and TOK series wet photoresists.
然後，以乾蝕刻製程移除該移除區33；於本實施例中，係以反應性離子蝕刻技術(reactive ion etching，縮寫RIE)移除該移除區33。於其他實施例中，亦得以濕蝕刻製程移除該移除區。Then, the removal region 33 is removed by a dry etching process; in the present embodiment, the removal region 33 is removed by reactive ion etching (abbreviation RIE). In other embodiments, the removal zone is also removed by a wet etch process.
再來，以光阻剝離劑移除該光阻40；於本實施例中，該光阻剝離劑為N-甲基吡咯酮(N-Methyl-pyrrolidinone)。Then, the photoresist 40 is removed by a photoresist stripper; in the embodiment, the photoresist stripper is N-Methyl-pyrrolidinone.
之後，以一蝕刻液蝕刻該第一表面11之第二部份112、該第二表面21之第二部份212及該第二表面21的第三部份213，以形成一連接於該第一表面11之第一部份111與該等內壁面14之間的第一凹部50、一連接於該第二表面21之第一部份211與該等內壁面14之間的第二凹部51及一與該第二表面21之第一部份211相接的第三凹部52；於本實施例中，該蝕刻液為氫氧化鉀溶液。Thereafter, the second portion 112 of the first surface 11, the second portion 212 of the second surface 21, and the third portion 213 of the second surface 21 are etched with an etching solution to form a connection to the first portion a first recess 50 between the first portion 111 of the surface 11 and the inner wall surface 14, a second recess 51 connected between the first portion 211 of the second surface 21 and the inner wall surface 14 And a third recess 52 that is in contact with the first portion 211 of the second surface 21; in the embodiment, the etching solution is a potassium hydroxide solution.
接下來，設置一與該第一保留區31及第二保留區32相接的第二阻隔層60於該第一凹部50、該第二凹部51及該第三凹部52上，以獲得一包含有該第一保留區31、該第二保留區32及該第二阻隔層60的絕緣層70於該穿孔基板20上以及一形成於該第一保留區31與該第二阻隔層60之間的電路溝槽75，該電路溝槽75與該等穿孔22、23相接，且該第一保留區31與該第二阻隔層60之間具有一高度差，該高度差即為該電路溝槽80的深度；於本實施例中，係以化學氣相沉積技術形成該第二阻隔層60，該第二阻隔層60之材質為二氧化矽，該第二阻隔層60的厚度為1 μm，該電路溝槽75的深度為15 μm。於其他實施例中，該第二阻隔層之材質為二氧化鍺。Next, a second barrier layer 60 that is in contact with the first and second retention regions 31 and 32 is disposed on the first recess 50, the second recess 51, and the third recess 52 to obtain an inclusion. An insulating layer 70 having the first retention region 31, the second retention region 32, and the second barrier layer 60 is disposed on the perforated substrate 20 and between the first retention region 31 and the second barrier layer 60. a circuit trench 75, the circuit trench 75 is in contact with the vias 22, 23, and a height difference between the first retention region 31 and the second barrier layer 60 is the circuit trench The depth of the trench 80; in the embodiment, the second barrier layer 60 is formed by a chemical vapor deposition technique, and the second barrier layer 60 is made of cerium oxide, and the second barrier layer 60 has a thickness of 1 μm. The circuit trench 75 has a depth of 15 μm. In other embodiments, the second barrier layer is made of cerium oxide.
請參閱圖4所示，將所述導電膠80充填該穿孔基板20的該等穿孔22、23及該電路溝槽75中且與該絕緣層70相接後，以一刮刀85令填入該等穿孔22、23及該電路溝槽75中的導電膠80之表面與該第二保留區32相互齊平，再令該導電膠80固化為一導電層91及一電路層92，以獲得所述導電基板90，該導電層91位於該等穿孔22、23中且與該絕緣層70之第一保留區31相接，該電路層92位於該電路溝槽75中且與該導電層91相接，所述導電膠80包含有一導電填料、一樹脂、溶劑及分散劑；於本實施例中，該導電填料為銀，該樹脂為光硬化型環氧樹脂，該溶劑包含水及油酸(oleic acid)，該分散劑為油酸鈉(sodium oleate)。該導電膠80係以10°C/分鐘之升溫速度、10分鐘之烘烤時間與1小時之爐冷時間固化為該導電層91及電路層92。於其他實施例中，該導電填料包含金、銅或石墨等，該樹脂包含環氧樹脂、有機矽樹脂、酚醛樹脂、丙烯酸樹脂等，該溶劑包含正己醇或環己烯等，且所述導電膠係可經由網版印刷技術或真空輔助充填技術充填於該等穿孔及該電路溝槽中。Referring to FIG. 4, the conductive paste 80 is filled in the through holes 22, 23 of the perforated substrate 20 and the circuit trench 75 and is in contact with the insulating layer 70, and then filled with a doctor blade 85. The surface of the conductive paste 80 in the through-holes 22, 23 and the circuit trench 75 is flush with the second retention region 32, and the conductive paste 80 is cured into a conductive layer 91 and a circuit layer 92. The conductive substrate 90 is located in the through holes 22, 23 and is in contact with the first reserved region 31 of the insulating layer 70. The circuit layer 92 is located in the circuit trench 75 and is opposite to the conductive layer 91. The conductive paste 80 comprises a conductive filler, a resin, a solvent and a dispersing agent. In the embodiment, the conductive filler is silver, and the resin is a photocurable epoxy resin, and the solvent comprises water and oleic acid ( Oleic acid), the dispersing agent is sodium oleate. The conductive paste 80 is cured into the conductive layer 91 and the circuit layer 92 at a temperature increase rate of 10 ° C /min, a baking time of 10 minutes, and a furnace cooling time of 1 hour. In other embodiments, the conductive filler comprises gold, copper or graphite, and the resin comprises an epoxy resin, an organic oxime resin, a phenol resin, an acrylic resin, etc., the solvent comprises n-hexanol or cyclohexene, and the conductive The glue system can be filled in the perforations and the trenches of the circuit via screen printing techniques or vacuum assisted filling techniques.
由於本實施例係以將導電膠80充填於該穿孔基板20的穿孔22、23中之方式製得所述導電基板90，故能令所有的穿孔22、23均充填有適量的導電膠80，從而避免導電膠所製成的導電層91之產生缺陷並使導電層91具有良好導電性，進而提高包含有所述製法所製得的導電基板90的電子產品之可靠度。In this embodiment, the conductive substrate 90 is formed by filling the conductive paste 80 into the through holes 22 and 23 of the through-substrate 20, so that all the through holes 22 and 23 can be filled with an appropriate amount of the conductive adhesive 80. Thereby, defects such as the conductive layer 91 made of the conductive paste are avoided and the conductive layer 91 has good conductivity, thereby improving the reliability of the electronic product including the conductive substrate 90 produced by the manufacturing method.
此外，本實施例於形成該絕緣層70時能同時形成所述與該等穿孔22、23相接的電路溝槽75，且於充填導電膠80於該等穿孔22、23中時，亦能同時將導電膠80充填於該電路溝槽75中，從而於形成該導電層91時能同時完成該電路層92之設置。因此，本實施例之導電基板的製法係能同時完成導電層91及電路層92之設置，從而縮短製程時間。In addition, in the embodiment, when the insulating layer 70 is formed, the circuit trenches 75 that are in contact with the through holes 22 and 23 can be simultaneously formed, and when the conductive paste 80 is filled in the through holes 22 and 23, At the same time, the conductive paste 80 is filled in the circuit trench 75, so that the circuit layer 92 can be simultaneously disposed when the conductive layer 91 is formed. Therefore, the manufacturing method of the conductive substrate of the embodiment can simultaneously complete the arrangement of the conductive layer 91 and the circuit layer 92, thereby shortening the process time.
10‧‧‧原型基板
11‧‧‧第一表面
111‧‧‧第一部份
112‧‧‧第二部份
12‧‧‧側面
13‧‧‧端壁
14‧‧‧內壁面
15、16‧‧‧蝕刻凹槽
20‧‧‧穿孔基板
21‧‧‧第二表面
211‧‧‧第一部份
212‧‧‧第二部份
213‧‧‧第三部份
22、23‧‧‧穿孔
30‧‧‧第一阻隔層
31‧‧‧第一保留區
32‧‧‧第二保留區
33‧‧‧移除區
40‧‧‧光阻
50‧‧‧第一凹部
51‧‧‧第二凹部
52‧‧‧第三凹部
60‧‧‧第二阻隔層
70‧‧‧絕緣層
75‧‧‧電路溝槽
80‧‧‧導電膠
85‧‧‧刮刀
90‧‧‧導電基板
91‧‧‧導電層
92‧‧‧電路層
S1、S2、S3‧‧‧步驟10‧‧‧Prototype substrate
11‧‧‧ first surface
111‧‧‧ first part
112‧‧‧ second part
12‧‧‧ side
13‧‧‧End wall
14‧‧‧ inner wall
15, 16‧‧‧ etching grooves
20‧‧‧Perforated substrate
21‧‧‧ second surface
211‧‧‧ first part
212‧‧‧Part 2
213‧‧‧Part III
22, 23‧‧‧ perforation
30‧‧‧First barrier
31‧‧‧First reserved area
32‧‧‧Second reserved area
33‧‧‧Removed area
40‧‧‧Light resistance
50‧‧‧First recess
51‧‧‧Second recess
52‧‧‧ Third recess
60‧‧‧Second barrier
70‧‧‧Insulation
75‧‧‧Circuit trench
80‧‧‧ conductive adhesive
85‧‧‧ scraper
90‧‧‧Electrical substrate
91‧‧‧ Conductive layer
92‧‧‧ circuit layer
S1, S2, S3‧‧‧ steps
圖1為本發明的導電基板的製法的流程圖； 圖2為本發明的導電基板的製法的提供一穿孔基板之步驟示意圖； 圖3為本發明的導電基板的製法的設置一絕緣層於該穿孔基板上之步驟示意圖； 圖4為本發明的導電基板的製法的令一導電膠充填並固化於該穿孔基板之穿孔中以形成一與該絕緣層相接的導電層，從而獲得該導電基板之步驟示意圖。1 is a flow chart of a method for manufacturing a conductive substrate of the present invention; FIG. 2 is a schematic view showing a step of providing a perforated substrate for a method for manufacturing a conductive substrate of the present invention; FIG. 3 is a view showing a method for manufacturing a conductive substrate of the present invention; FIG. 4 is a schematic diagram of a step of forming a conductive substrate according to the present invention; FIG. 4 is a method for manufacturing a conductive substrate according to the present invention, wherein a conductive paste is filled and cured in a through hole of the through-substrate to form a conductive layer that is in contact with the insulating layer, thereby obtaining the conductive substrate. A schematic diagram of the steps.
Claims (7)
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|---|---|---|---|
| TW105113005A TWI620253B (en) | 2016-04-26 | 2016-04-26 | Method for building conductive substrate |
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| Application Number | Priority Date | Filing Date | Title |
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| TW105113005A TWI620253B (en) | 2016-04-26 | 2016-04-26 | Method for building conductive substrate |
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| TWI620253B true TWI620253B (en) | 2018-04-01 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200501385A (en) * | 2003-06-16 | 2005-01-01 | Siliconware Precision Industries Co Ltd | Substrate for semiconductor package and method for fabricating the same |
| TW200734477A (en) * | 2006-03-01 | 2007-09-16 | Advanced Semiconductor Eng | Circuit substrate and method for fabricating plating through hole |
| TW200908847A (en) * | 2007-04-23 | 2009-02-16 | Matsushita Electric Ind Co Ltd | Conductive paste composition for via hole filling, printed board using the same, and method for manufacturing the printed board |
| TW201005904A (en) * | 2008-07-31 | 2010-02-01 | Powertech Technology Inc | Chip package having penetrative TSVs |
| TW201401393A (en) * | 2012-06-21 | 2014-01-01 | 位速科技股份有限公司 | Manufacturing method of conductive pillar for ceramic-packaged substrate |
| TW201405734A (en) * | 2012-07-26 | 2014-02-01 | Unimicron Technology Corp | Through-hole medium board, package substrate, and method of forming the same |
-
2016
- 2016-04-26 TW TW105113005A patent/TWI620253B/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200501385A (en) * | 2003-06-16 | 2005-01-01 | Siliconware Precision Industries Co Ltd | Substrate for semiconductor package and method for fabricating the same |
| TW200734477A (en) * | 2006-03-01 | 2007-09-16 | Advanced Semiconductor Eng | Circuit substrate and method for fabricating plating through hole |
| TW200908847A (en) * | 2007-04-23 | 2009-02-16 | Matsushita Electric Ind Co Ltd | Conductive paste composition for via hole filling, printed board using the same, and method for manufacturing the printed board |
| TW201005904A (en) * | 2008-07-31 | 2010-02-01 | Powertech Technology Inc | Chip package having penetrative TSVs |
| TW201401393A (en) * | 2012-06-21 | 2014-01-01 | 位速科技股份有限公司 | Manufacturing method of conductive pillar for ceramic-packaged substrate |
| TW201405734A (en) * | 2012-07-26 | 2014-02-01 | Unimicron Technology Corp | Through-hole medium board, package substrate, and method of forming the same |
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