US20180233479A1 - Semiconductor apparatus and method for preparing the same - Google Patents
Semiconductor apparatus and method for preparing the same Download PDFInfo
- Publication number
- US20180233479A1 US20180233479A1 US15/434,606 US201715434606A US2018233479A1 US 20180233479 A1 US20180233479 A1 US 20180233479A1 US 201715434606 A US201715434606 A US 201715434606A US 2018233479 A1 US2018233479 A1 US 2018233479A1
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- Prior art keywords
- conductive portion
- dielectric
- conductive
- semiconductor device
- semiconductor apparatus
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 171
- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000005530 etching Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 230000004927 fusion Effects 0.000 abstract description 21
- 238000004519 manufacturing process Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 7
- 230000001131 transforming effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
Definitions
- the present disclosure relates to a semiconductor apparatus and a method for preparing the same, and particularly relates to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same.
- Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while having greater functionality and greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, chip-on-chip technique is now widely used for manufacturing semiconductor devices. Numerous manufacturing processes such as epitaxial growing process or post via formation are undertaken in the production of such semiconductor packages.
- One embodiment of the present disclosure provides a semiconductor apparatus including a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression above an upper surface of the first conductive portion, wherein a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion, and a volume of the depression is substantially the same as a volume expansion of the first conductive portion from a first temperature to a second temperature higher than the first temperature.
- an upper end of the first conductive portion is lower than that of the first dielectric portion.
- a thickness of the first conductive portion is less than that of the first dielectric portion.
- the semiconductor apparatus further comprises a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion, wherein the first conductive portion faces the second conductive portion, the depression separates the first conductive portion from the second conductive portion, and the first dielectric portion contacts the second dielectric portion.
- a center of the first conductive portion is aligned with a center of the second conductive portion.
- Another embodiment of the present disclosure provides a semiconductor apparatus, comprising: a first semiconductor device having a first conductive portion and a first dielectric portion adjacent to the first conductive portion; and a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion.
- the first conductive portion is directly bonded to the second conductive portion substantially in the absence of a solder material between the first conductive portion and the second conductive portion, and the first dielectric portion is directly bonded to the second dielectric portion.
- a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion.
- the first semiconductor device and the second semiconductor device are vertically bonded, and the first conductive portion contacts the second conductive portion substantially in the absence of a lateral protrusion into an interface between the first dielectric portion and the second dielectric portion.
- a center of the first conductive portion is aligned with a center of the second conductive portion.
- Another embodiment of the present disclosure provides a method for preparing a semiconductor apparatus, including: forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.
- the forming of the first semiconductor device comprises: forming a first dielectric layer over a semiconductor substrate; forming an opening in the first dielectric layer; and forming the first conductive portion in the opening.
- the forming of the first conductive portion in the opening comprises: forming a conductive layer over the first dielectric layer and filling the opening; performing a planarization process to remove a portion of the conductive layer from an upper surface of the first dielectric layer; and performing a selective etching process to remove an upper portion of the conductive layer in the opening to form the depression.
- the forming of the first conductive portion in the opening comprises: forming a conductive layer over the first dielectric layer and filling the opening; performing a first planarization process to remove a portion of the conductive layer from an upper surface of the first dielectric layer; forming a mask covering the conductive layer in the opening; forming a second dielectric layer over first dielectric layer and covering the mask; performing a second planarization process to remove a portion of the second dielectric layer and expose the mask; and removing the mask to form a depression.
- a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion, and expanding at least one of the first conductive portion and the second conductive portion comprises performing a thermal treating process that expands a thickness of the first conductive portion more than a thickness of the first dielectric portion.
- the first conductive portion, having the depression is formed at a first temperature, and the thermal treating process heats at least one of the first conductive portion and the second conductive portion to a second temperature higher than the first temperature.
- the depression separates the first conductive portion from the second conductive portion, and the first dielectric portion contacts the second dielectric portion.
- the present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same.
- the semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions.
- the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to lateral protrusion is effectively eliminated.
- FIG. 1 is a cross-sectional view showing the transforming of a semiconductor device via application of heat in accordance with a comparative embodiment of the present disclosure.
- FIG. 2 is a cross-sectional view of a semiconductor apparatus in accordance with a comparative embodiment of the present disclosure.
- FIG. 3 is a cross-sectional view showing the transforming of a semiconductor device via application of heat in accordance with some embodiments of the present disclosure.
- FIG. 4 is a cross-sectional view showing the transforming of a semiconductor device via application of heat in accordance with some embodiments of the present disclosure.
- FIG. 5 is a cross-sectional view of a semiconductor apparatus in accordance with a comparative embodiment of the present disclosure.
- FIG. 6 is a cross-sectional view of a semiconductor apparatus in accordance with a comparative embodiment of the present disclosure.
- FIG. 7 is a flow chart of a method for preparing a semiconductor apparatus in accordance with some embodiments of the present disclosure.
- FIGS. 8 to 20 are schematic views of a process for preparing the semiconductor apparatus by the method of FIG. 7 in accordance with some embodiments of the present disclosure.
- references to “one embodiment,” “an embodiment,” “exemplary embodiment,” “other embodiments,” “another embodiment,” etc. indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may.
- the present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same.
- a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same.
- FIG. 1 is a cross-sectional view showing the transforming of a semiconductor device 10 A into a semiconductor device 10 A′ in accordance with a comparative embodiment of the present disclosure.
- the semiconductor device 10 A includes a substrate 11 , a conductive portion 13 and a dielectric portion 15 adjacent to the conductive portion 13 , wherein the upper end of the conductive portion 13 is substantially at the same level as that of the dielectric portion 15 after a planarization process such as a chemical mechanical polishing process, which is widely used in fabricating semiconductor devices.
- the substrate 11 is a silicon substrate
- the conductive portion 13 is made of copper
- the dielectric portion 15 is made of silicon oxide.
- the coefficient of thermal expansion of silicon is about 2.6 ppm/° C.
- the coefficient of thermal expansion of copper is about 17.0 ppm/° C.
- the coefficient of thermal expansion of silicon oxide is smaller than 1.5 ppm/° C.
- the conductive portion 13 of copper will expand more than the dielectric portion 15 of silicon oxide. Consequently, as the semiconductor device 10 A is heated, the volume (thickness) expansion of the conductive portion 13 is greater than that of the dielectric portion 15 , and the upper end of the conductive portion 13 ′ becomes higher than the upper end of the dielectric portion 15 ′ in the semiconductor device 10 A′.
- FIG. 2 is a cross-sectional view of a semiconductor apparatus 100 in accordance with a comparative embodiment of the present disclosure.
- the semiconductor apparatus 100 is formed by applying a fusion bonding to two vertically stacked semiconductor devices 10 A and 10 B.
- the semiconductor devices 10 A and 10 B may have the same configuration.
- the fusion bonding includes a thermal treating process that expands the volume (thickness) of the conductive portion 13 more than that of the dielectric portion 15 ; therefore, the conductive portion 13 ′ of the semiconductor apparatus 100 generates a lateral protrusion 17 into an interface between the two dielectric portions 15 ′ of the semiconductor apparatus 100 .
- the lateral protrusion 17 may cause the semiconductor apparatus 100 to fail to perform its electrical function.
- FIG. 3 is a cross-sectional view showing the transforming of a semiconductor device 20 A into a semiconductor device 20 A′ in accordance with some embodiments of the present disclosure.
- the semiconductor device 20 A includes a substrate 21 , a conductive portion 23 and a dielectric portion 25 adjacent to the conductive portion 23 , and a depression 27 above the non-planar (curvilinear) upper surface of the conductive portion 23 , wherein the coefficient of thermal expansion of the conductive portion 23 is higher than that of the dielectric portion 25 .
- the substrate 21 is a silicon substrate
- the conductive portion 23 is made of copper
- the dielectric portion 25 is made of silicon oxide.
- the bottom end of the depression 27 is defined by the upper surface of the conductive portion 23
- the upper end of the depression 27 is defined by the dashed line extending from the upper end of the dielectric portion 25 .
- the upper end of the conductive portion 23 is lower than that of the dielectric portion 25 , and the thickness of the conductive portion 23 is less than that of the dielectric portion 25 .
- the conductive portion 23 of copper expands more than the dielectric portion 25 of silicon oxide. Consequently, as the semiconductor device 20 A is heated, the volume (thickness) expansion of the conductive portion 23 is greater than that of the dielectric portion 25 , the conductive portion 23 fills the depression 27 , the upper end of the conductive portion 23 ′ becomes substantially at the same level as that of the dielectric portion 25 ′ of the semiconductor device 20 A′, and the thickness of the conductive portion 23 becomes substantially the same as that of the dielectric portion 25 .
- FIG. 4 is a cross-sectional view showing the transforming of a semiconductor device 30 A into a semiconductor device 30 A′ in accordance with some embodiments of the present disclosure.
- the semiconductor device 30 includes a substrate 31 , a conductive portion 33 and a dielectric portion 35 adjacent to the conductive portion 33 , and a depression 37 above the planar upper surface of the conductive portion 33 , wherein the coefficient of thermal expansion of the conductive portion 33 is higher than that of the dielectric portion 35 .
- the substrate 31 is a silicon substrate
- the conductive portion 33 is made of copper
- the dielectric portion 35 is made of silicon oxide.
- the bottom end of the depression 37 is defined by the upper surface of the conductive portion 33
- the upper end of the depression 37 is defined by the dashed line extending from the upper end of the dielectric portion 35 .
- the copper conductive portion 33 expands more than the silicon-oxide dielectric portion 35 . Consequently, as the semiconductor device 30 A is heated, the volume (thickness) expansion of the conductive portion 33 is greater than that of the dielectric portion 35 , the conductive portion 33 fills the depression 37 , and the upper end of the conductive portion 33 ′ is substantially at the same level as the upper end of the dielectric portion 35 ′ of the semiconductor device 30 A′.
- FIG. 5 is a cross-sectional view of a semiconductor apparatus 200 in accordance with a comparative embodiment of the present disclosure.
- the semiconductor apparatus 200 is formed by applying a fusion bonding to two vertically stacked semiconductor devices 20 A and 20 B.
- the semiconductor devices 20 A and 20 B may have the same configuration.
- the fusion bonding includes a thermal treating process that expands the volume (thickness) of the conductive portion 23 more than that of the dielectric portion 25 ; therefore, the conductive portion 23 ′ of the semiconductor apparatus 200 fills the depression 27 .
- the two semiconductor devices 20 A and 20 B are disposed in a manner such that the conductive portion 23 of the upper semiconductor device 20 A faces the conductive portion 23 of the lower semiconductor device 20 B, and the center of the conductive portion 23 of the upper semiconductor device 20 A is aligned with the center of the conductive portion 23 of the lower semiconductor device 20 B. Because the fusion bonding is applied, it is substantially not necessary to dispose a solder material or the like between the vertically stacked semiconductor devices 20 A and 20 B.
- a semiconductor apparatus 300 can be formed by applying a fusion bonding to two vertically stacked semiconductor devices 30 A and 30 B, as shown in FIG. 6 . Details of the fusion bonding are available in the article, An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization, J. Electrochem. Soc. 1011 volume 158, issue 6, P81-P86, the entirety of which is incorporated herein by reference and will not be repeated.
- FIG. 7 is a flow chart of a method for preparing a semiconductor apparatus in accordance with some embodiments of the present disclosure.
- the semiconductor apparatus can be formed by a method 300 of FIG. 7 .
- the method 300 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
- the method 300 includes a number of steps ( 301 , 303 , 305 , and 307 ).
- FIGS. 8 to 14 are schematic views of a process for preparing the semiconductor apparatus by the method of FIG. 7 in accordance with some embodiments of the present disclosure.
- a semiconductor device 30 A is fabricated as shown in FIGS. 8 to 13 .
- the semiconductor device 30 A has a conductive portion 33 , a dielectric portion 35 adjacent to the conductive portion 33 , and a depression 37 above a planar upper surface of the conductive portion 33 .
- the bottom end of the depression 37 is defined by the upper surface of the conductive portion 33
- the upper end of the depression 37 is defined by the dashed line extending from the upper end of the dielectric portion 35 .
- a dielectric layer 41 is formed on a substrate 31 such as a silicon substrate by performing a deposition process on the substrate 31 .
- the dielectric layer 41 is a silicon oxide layer.
- a patterned mask 43 is formed by performing deposition, lithographic and etching processes on the dielectric layer 41 .
- the patterned mask 43 is a photoresist layer having an aperture 45 .
- an etching process is performed by using the patterned mask 43 as an etching mask to remove a portion of the dielectric layer 31 under the aperture 45 so as to form an opening 47 in the dielectric layer 41 .
- the patterned mask 43 is removed, and a conductive layer 49 is formed by performing a deposition process on the substrate 31 and the dielectric layer 41 , wherein the conductive layer 49 fills the opening 47 and covers the upper surface of the dielectric layer 41 .
- a planarization process is performed to remove a portion of the conductive layer 49 from the upper surface of the dielectric layer 41 , while retaining the conductive layer 49 in the opening 47 .
- the planarization process is a chemical mechanical polishing process, and the upper end of the conductive layer 49 in the opening 47 is substantially at the same level as the dielectric layer 41 after the planarization process.
- a selective etching process is performed to remove an upper portion of the conductive layer 49 in the opening 47 to form the depression 37 .
- the remaining conductive layer 49 in the opening 47 forms a conductive portion 33
- the remaining dielectric layer 41 forms a dielectric portion 35 adjacent to the conductive portion 33
- the depression 37 is formed above the upper surface of the conductive portion 33 .
- the selective etching process is an anisotropic etching process such as the dry etching process, and the upper surface of the conductive portion 33 of the semiconductor device 30 A is substantially planar after the anisotropic etching process.
- the semiconductor device 20 A can be fabricated substantially by the same fabrication processes disclosed in FIGS. 8 to 13 , except for the selective etching process in FIG. 13 .
- the selective etching process for fabricating the semiconductor device 20 A is an isotropic etching process such as the wet etching process, and the upper surface of the conductive portion 23 of the semiconductor device 20 A is substantially non-planar (curvilinear) after the isotropic etching process.
- a semiconductor device 30 B is fabricated as shown in FIG. 15 .
- the semiconductor device 30 B similar to the semiconductor device 30 A, has a conductive portion 33 and a dielectric portion 35 adjacent to the conductive portion 33 .
- the semiconductor device 30 B has a depression 37 above the upper surface of the conductive portion 33 , and the fabrication of the semiconductor device 30 B may be the same as that of the semiconductor die 30 A shown in FIGS. 8 to 13 .
- step 305 the semiconductor device 30 A and the semiconductor device 30 B are assembled in a manner such that the conductive portion 33 of the semiconductor device 30 A faces the conductive portion 33 of the semiconductor device 30 B, as shown in FIG. 16 .
- the depression 37 separates the conductive portion 33 of the semiconductor device 30 A from the conductive portion 33 of the semiconductor device 30 B, and the dielectric portion 35 of the semiconductor device 30 A contacts the dielectric portion 35 of the semiconductor device 30 B.
- step 307 referring to FIG. 16 , at least one of the conductive portion 33 of the semiconductor device 30 A and the conductive portion 33 of the semiconductor device 30 B is expanded to fill the depression 37 ; consequently, the conductive portion 33 of the semiconductor device 30 A contacts the conductive portion 33 of the semiconductor device 30 B to form an electrical connection.
- the center of the conductive portion 33 of the semiconductor device 30 A is aligned with the center of the conductive portion 33 of the semiconductor device 20 B.
- the coefficient of thermal expansion of the conductive portion 33 is higher than that of the dielectric portion 35
- the expanding of the conductive portion 33 is implemented by applying the fusion bonding with a thermal treating process, which increases the volume (thickness) of the conductive portion 33 more than that of the dielectric portion 35 such that the depression 37 is filled by the conductor of the conductive portion 33 .
- the conductive portion 33 defining the bottom of the depression 37 is formed at a first temperature, and the thermal treating process heats at least one of the conductive portion 33 of the semiconductor device 30 A and the conductive portion 33 of the semiconductor device 30 B to a second temperature higher than the first temperature.
- the conductive portion 33 comprises copper, and the second temperature is substantially between 300° C. and 450° C.; and the first temperature is the processing temperature of the selective etching process in FIG. 13 .
- the volume of the depression 37 is substantially the same as the volume expansion of the conductive portion 33 from the first temperature to the second temperature.
- the depression 37 is designed to provide a space for the volume expansion of the conductive portion 33 ′ with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding; consequently, the semiconductor apparatus 300 does not exhibit a lateral protrusion into the interface between the two dielectric portions 35 ′. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.
- FIGS. 17 to 20 are schematic views of a process for preparing a semiconductor device 30 A corresponding the step 301 in FIG. 7 in accordance with some embodiments of the present disclosure.
- the fabrication processes disclosed in FIGS. 8 to 12 are performed, and a mask 51 is then formed by performing deposition, lithographic and etching processes on the conductive layer 49 , as shown in FIG. 17 .
- the mask 51 is a patterned photoresist layer selectively covering the conductive layer 49 in the opening 47 , and the upper end of the mask 51 is substantially higher than the upper end of the dielectric layer 41 .
- a dielectric layer 53 is formed over the dielectric layer 41 and covering the mask 51 .
- the dielectric layer 53 is made of silicon oxide, which is the same material as the dielectric layer 41 .
- a planarization process is performed to remove an upper portion of the dielectric layer 53 and expose the mask 51 .
- the planarization process is a chemical mechanical polishing process, and the upper end of the mask 51 is substantially at the same level as that of the dielectric layer 53 after the planarization process.
- the mask 51 is removed from the conductive layer 49 in the opening 47 so as to form a depression 37 above the upper surface of the conductive layer 49 in the opening 47 . Consequently, the conductive layer 49 in the opening 47 serves as the conductive portion 33 of the semiconductor device 30 A, and the remaining dielectric layer 53 and the dielectric layer 41 serve as the dielectric portion 35 of the semiconductor device 30 A.
- the present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same.
- the semiconductor devices have conductive portions with higher coefficient of thermal expansion than the dielectric portion.
- the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.
- One embodiment of the present disclosure provides a semiconductor apparatus including a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression above an upper surface of the first conductive portion, wherein a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion, and a volume of the depression is substantially the same as a volume expansion of the first conductive portion from a first temperature to a second temperature higher than the first temperature.
- Another embodiment of the present disclosure provides a semiconductor apparatus, including: a first semiconductor device having a first conductive portion and a first dielectric portion adjacent to the first conductive portion; and a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion.
- the first conductive portion is directly bonded to the second conductive portion substantially in the absence of a solder material between the first conductive portion and the second conductive portion, and the first dielectric portion is directly bonded to the second dielectric portion.
- Another embodiment of the present disclosure provides a method for preparing a semiconductor apparatus, including: forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one is of the first conductive portion and the second conductive portion to fill the depression.
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Abstract
The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.
Description
- The present disclosure relates to a semiconductor apparatus and a method for preparing the same, and particularly relates to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same.
- Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while having greater functionality and greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, chip-on-chip technique is now widely used for manufacturing semiconductor devices. Numerous manufacturing processes such as epitaxial growing process or post via formation are undertaken in the production of such semiconductor packages.
- However, the manufacturing of semiconductor devices in a miniaturized scale is becoming more complicated. An increase in the complexity of manufacturing semiconductor devices may cause deficiencies such as poor electrical interconnection, development of cracks, or delamination of components. As such, there are many challenges for modifying the structure and manufacture of semiconductor devices.
- This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
- One embodiment of the present disclosure provides a semiconductor apparatus including a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression above an upper surface of the first conductive portion, wherein a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion, and a volume of the depression is substantially the same as a volume expansion of the first conductive portion from a first temperature to a second temperature higher than the first temperature.
- In some embodiments, an upper end of the first conductive portion is lower than that of the first dielectric portion.
- In some embodiments, a thickness of the first conductive portion is less than that of the first dielectric portion.
- In some embodiments, the semiconductor apparatus further comprises a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion, wherein the first conductive portion faces the second conductive portion, the depression separates the first conductive portion from the second conductive portion, and the first dielectric portion contacts the second dielectric portion.
- In some embodiments, a center of the first conductive portion is aligned with a center of the second conductive portion.
- Another embodiment of the present disclosure provides a semiconductor apparatus, comprising: a first semiconductor device having a first conductive portion and a first dielectric portion adjacent to the first conductive portion; and a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion. The first conductive portion is directly bonded to the second conductive portion substantially in the absence of a solder material between the first conductive portion and the second conductive portion, and the first dielectric portion is directly bonded to the second dielectric portion.
- In some embodiments, a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion.
- In some embodiments, the first semiconductor device and the second semiconductor device are vertically bonded, and the first conductive portion contacts the second conductive portion substantially in the absence of a lateral protrusion into an interface between the first dielectric portion and the second dielectric portion.
- In some embodiments, a center of the first conductive portion is aligned with a center of the second conductive portion.
- Another embodiment of the present disclosure provides a method for preparing a semiconductor apparatus, including: forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.
- In some embodiments, the forming of the first semiconductor device comprises: forming a first dielectric layer over a semiconductor substrate; forming an opening in the first dielectric layer; and forming the first conductive portion in the opening.
- In some embodiments, the forming of the first conductive portion in the opening comprises: forming a conductive layer over the first dielectric layer and filling the opening; performing a planarization process to remove a portion of the conductive layer from an upper surface of the first dielectric layer; and performing a selective etching process to remove an upper portion of the conductive layer in the opening to form the depression.
- In some embodiments, the forming of the first conductive portion in the opening comprises: forming a conductive layer over the first dielectric layer and filling the opening; performing a first planarization process to remove a portion of the conductive layer from an upper surface of the first dielectric layer; forming a mask covering the conductive layer in the opening; forming a second dielectric layer over first dielectric layer and covering the mask; performing a second planarization process to remove a portion of the second dielectric layer and expose the mask; and removing the mask to form a depression.
- In some embodiments, a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion, and expanding at least one of the first conductive portion and the second conductive portion comprises performing a thermal treating process that expands a thickness of the first conductive portion more than a thickness of the first dielectric portion.
- In some embodiments, the first conductive portion, having the depression, is formed at a first temperature, and the thermal treating process heats at least one of the first conductive portion and the second conductive portion to a second temperature higher than the first temperature.
- In some embodiments, the depression separates the first conductive portion from the second conductive portion, and the first dielectric portion contacts the second dielectric portion.
- The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to lateral protrusion is effectively eliminated.
- The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
- A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures.
-
FIG. 1 is a cross-sectional view showing the transforming of a semiconductor device via application of heat in accordance with a comparative embodiment of the present disclosure. -
FIG. 2 is a cross-sectional view of a semiconductor apparatus in accordance with a comparative embodiment of the present disclosure. -
FIG. 3 is a cross-sectional view showing the transforming of a semiconductor device via application of heat in accordance with some embodiments of the present disclosure. -
FIG. 4 is a cross-sectional view showing the transforming of a semiconductor device via application of heat in accordance with some embodiments of the present disclosure. -
FIG. 5 is a cross-sectional view of a semiconductor apparatus in accordance with a comparative embodiment of the present disclosure. -
FIG. 6 is a cross-sectional view of a semiconductor apparatus in accordance with a comparative embodiment of the present disclosure. -
FIG. 7 is a flow chart of a method for preparing a semiconductor apparatus in accordance with some embodiments of the present disclosure. -
FIGS. 8 to 20 are schematic views of a process for preparing the semiconductor apparatus by the method ofFIG. 7 in accordance with some embodiments of the present disclosure. - The following description of the disclosure accompanies drawings, which are incorporated in and constitute a part of this specification, and which illustrate embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.
- References to “one embodiment,” “an embodiment,” “exemplary embodiment,” “other embodiments,” “another embodiment,” etc. indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may.
- The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. In order to make the present disclosure completely comprehensible, detailed steps and structures are provided in the following description. Obviously, implementation of the present disclosure does not limit special details known by persons skilled in the art. In addition, known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. Preferred embodiments of the present disclosure will be described below in detail. However, in addition to the detailed description, the present disclosure may also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the detailed description, and is defined by the claims.
-
FIG. 1 is a cross-sectional view showing the transforming of asemiconductor device 10A into asemiconductor device 10A′ in accordance with a comparative embodiment of the present disclosure. Thesemiconductor device 10A includes asubstrate 11, aconductive portion 13 and adielectric portion 15 adjacent to theconductive portion 13, wherein the upper end of theconductive portion 13 is substantially at the same level as that of thedielectric portion 15 after a planarization process such as a chemical mechanical polishing process, which is widely used in fabricating semiconductor devices. In some embodiments, thesubstrate 11 is a silicon substrate, theconductive portion 13 is made of copper, and thedielectric portion 15 is made of silicon oxide. - The coefficient of thermal expansion of silicon is about 2.6 ppm/° C., the coefficient of thermal expansion of copper is about 17.0 ppm/° C., and the coefficient of thermal expansion of silicon oxide is smaller than 1.5 ppm/° C. In other words, as the temperature increases, the
conductive portion 13 of copper will expand more than thedielectric portion 15 of silicon oxide. Consequently, as thesemiconductor device 10A is heated, the volume (thickness) expansion of theconductive portion 13 is greater than that of thedielectric portion 15, and the upper end of theconductive portion 13′ becomes higher than the upper end of thedielectric portion 15′ in thesemiconductor device 10A′. -
FIG. 2 is a cross-sectional view of asemiconductor apparatus 100 in accordance with a comparative embodiment of the present disclosure. Thesemiconductor apparatus 100 is formed by applying a fusion bonding to two vertically stackedsemiconductor devices semiconductor devices conductive portion 13 more than that of thedielectric portion 15; therefore, theconductive portion 13′ of thesemiconductor apparatus 100 generates alateral protrusion 17 into an interface between the twodielectric portions 15′ of thesemiconductor apparatus 100. However, thelateral protrusion 17 may cause thesemiconductor apparatus 100 to fail to perform its electrical function. -
FIG. 3 is a cross-sectional view showing the transforming of asemiconductor device 20A into asemiconductor device 20A′ in accordance with some embodiments of the present disclosure. Thesemiconductor device 20A includes asubstrate 21, aconductive portion 23 and adielectric portion 25 adjacent to theconductive portion 23, and adepression 27 above the non-planar (curvilinear) upper surface of theconductive portion 23, wherein the coefficient of thermal expansion of theconductive portion 23 is higher than that of thedielectric portion 25. In some embodiments, thesubstrate 21 is a silicon substrate, theconductive portion 23 is made of copper, and thedielectric portion 25 is made of silicon oxide. In some embodiments, the bottom end of thedepression 27 is defined by the upper surface of theconductive portion 23, and the upper end of thedepression 27 is defined by the dashed line extending from the upper end of thedielectric portion 25. - Before the thermal treating process, the upper end of the
conductive portion 23 is lower than that of thedielectric portion 25, and the thickness of theconductive portion 23 is less than that of thedielectric portion 25. As the temperature increases during a thermal treating process, theconductive portion 23 of copper expands more than thedielectric portion 25 of silicon oxide. Consequently, as thesemiconductor device 20A is heated, the volume (thickness) expansion of theconductive portion 23 is greater than that of thedielectric portion 25, theconductive portion 23 fills thedepression 27, the upper end of theconductive portion 23′ becomes substantially at the same level as that of thedielectric portion 25′ of thesemiconductor device 20A′, and the thickness of theconductive portion 23 becomes substantially the same as that of thedielectric portion 25. -
FIG. 4 is a cross-sectional view showing the transforming of asemiconductor device 30A into asemiconductor device 30A′ in accordance with some embodiments of the present disclosure. The semiconductor device 30 includes asubstrate 31, aconductive portion 33 and adielectric portion 35 adjacent to theconductive portion 33, and adepression 37 above the planar upper surface of theconductive portion 33, wherein the coefficient of thermal expansion of theconductive portion 33 is higher than that of thedielectric portion 35. In some embodiments, thesubstrate 31 is a silicon substrate, theconductive portion 33 is made of copper, and thedielectric portion 35 is made of silicon oxide. In some embodiments, the bottom end of thedepression 37 is defined by the upper surface of theconductive portion 33, and the upper end of thedepression 37 is defined by the dashed line extending from the upper end of thedielectric portion 35. - As the temperature increases during a thermal treating process, the copper
conductive portion 33 expands more than the silicon-oxide dielectric portion 35. Consequently, as thesemiconductor device 30A is heated, the volume (thickness) expansion of theconductive portion 33 is greater than that of thedielectric portion 35, theconductive portion 33 fills thedepression 37, and the upper end of theconductive portion 33′ is substantially at the same level as the upper end of thedielectric portion 35′ of thesemiconductor device 30A′. -
FIG. 5 is a cross-sectional view of asemiconductor apparatus 200 in accordance with a comparative embodiment of the present disclosure. Thesemiconductor apparatus 200 is formed by applying a fusion bonding to two vertically stackedsemiconductor devices semiconductor devices conductive portion 23 more than that of thedielectric portion 25; therefore, theconductive portion 23′ of thesemiconductor apparatus 200 fills thedepression 27. - In some embodiments, the two
semiconductor devices conductive portion 23 of theupper semiconductor device 20A faces theconductive portion 23 of thelower semiconductor device 20B, and the center of theconductive portion 23 of theupper semiconductor device 20A is aligned with the center of theconductive portion 23 of thelower semiconductor device 20B. Because the fusion bonding is applied, it is substantially not necessary to dispose a solder material or the like between the vertically stackedsemiconductor devices - Similarly, a
semiconductor apparatus 300 can be formed by applying a fusion bonding to two vertically stackedsemiconductor devices FIG. 6 . Details of the fusion bonding are available in the article, An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization, J. Electrochem. Soc. 1011 volume 158, issue 6, P81-P86, the entirety of which is incorporated herein by reference and will not be repeated. -
FIG. 7 is a flow chart of a method for preparing a semiconductor apparatus in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor apparatus can be formed by amethod 300 ofFIG. 7 . Themethod 300 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations. Themethod 300 includes a number of steps (301, 303, 305, and 307). -
FIGS. 8 to 14 are schematic views of a process for preparing the semiconductor apparatus by the method ofFIG. 7 in accordance with some embodiments of the present disclosure. Instep 301, asemiconductor device 30A is fabricated as shown inFIGS. 8 to 13 . In some embodiments, as shown inFIG. 13 , thesemiconductor device 30A has aconductive portion 33, adielectric portion 35 adjacent to theconductive portion 33, and adepression 37 above a planar upper surface of theconductive portion 33. In some embodiments, the bottom end of thedepression 37 is defined by the upper surface of theconductive portion 33, and the upper end of thedepression 37 is defined by the dashed line extending from the upper end of thedielectric portion 35. - In
FIG. 8 , adielectric layer 41 is formed on asubstrate 31 such as a silicon substrate by performing a deposition process on thesubstrate 31. In some embodiments, thedielectric layer 41 is a silicon oxide layer. - In
FIG. 9 , a patternedmask 43 is formed by performing deposition, lithographic and etching processes on thedielectric layer 41. In some embodiments, the patternedmask 43 is a photoresist layer having anaperture 45. - In
FIG. 10 , an etching process is performed by using the patternedmask 43 as an etching mask to remove a portion of thedielectric layer 31 under theaperture 45 so as to form anopening 47 in thedielectric layer 41. - In
FIG. 11 , the patternedmask 43 is removed, and aconductive layer 49 is formed by performing a deposition process on thesubstrate 31 and thedielectric layer 41, wherein theconductive layer 49 fills theopening 47 and covers the upper surface of thedielectric layer 41. - In
FIG. 12 , a planarization process is performed to remove a portion of theconductive layer 49 from the upper surface of thedielectric layer 41, while retaining theconductive layer 49 in theopening 47. In some embodiments, the planarization process is a chemical mechanical polishing process, and the upper end of theconductive layer 49 in theopening 47 is substantially at the same level as thedielectric layer 41 after the planarization process. - In
FIG. 13 , a selective etching process is performed to remove an upper portion of theconductive layer 49 in theopening 47 to form thedepression 37. In some embodiments, the remainingconductive layer 49 in theopening 47 forms aconductive portion 33, the remainingdielectric layer 41 forms adielectric portion 35 adjacent to theconductive portion 33, and thedepression 37 is formed above the upper surface of theconductive portion 33. In some embodiments, the selective etching process is an anisotropic etching process such as the dry etching process, and the upper surface of theconductive portion 33 of thesemiconductor device 30A is substantially planar after the anisotropic etching process. - In some embodiments, referring to
FIG. 14 , thesemiconductor device 20A can be fabricated substantially by the same fabrication processes disclosed inFIGS. 8 to 13 , except for the selective etching process inFIG. 13 . In some embodiments, the selective etching process for fabricating thesemiconductor device 20A is an isotropic etching process such as the wet etching process, and the upper surface of theconductive portion 23 of thesemiconductor device 20A is substantially non-planar (curvilinear) after the isotropic etching process. - In
step 303, asemiconductor device 30B is fabricated as shown inFIG. 15 . In some embodiments, similar to thesemiconductor device 30A, thesemiconductor device 30B has aconductive portion 33 and adielectric portion 35 adjacent to theconductive portion 33. In some embodiments, thesemiconductor device 30B has adepression 37 above the upper surface of theconductive portion 33, and the fabrication of thesemiconductor device 30B may be the same as that of the semiconductor die 30A shown inFIGS. 8 to 13 . - In
step 305, thesemiconductor device 30A and thesemiconductor device 30B are assembled in a manner such that theconductive portion 33 of thesemiconductor device 30A faces theconductive portion 33 of thesemiconductor device 30B, as shown inFIG. 16 . In some embodiments, thedepression 37 separates theconductive portion 33 of thesemiconductor device 30A from theconductive portion 33 of thesemiconductor device 30B, and thedielectric portion 35 of thesemiconductor device 30A contacts thedielectric portion 35 of thesemiconductor device 30B. - In
step 307, referring toFIG. 16 , at least one of theconductive portion 33 of thesemiconductor device 30A and theconductive portion 33 of thesemiconductor device 30B is expanded to fill thedepression 37; consequently, theconductive portion 33 of thesemiconductor device 30A contacts theconductive portion 33 of thesemiconductor device 30B to form an electrical connection. In some embodiments, the center of theconductive portion 33 of thesemiconductor device 30A is aligned with the center of theconductive portion 33 of thesemiconductor device 20B. - In some embodiments, the coefficient of thermal expansion of the
conductive portion 33 is higher than that of thedielectric portion 35, and the expanding of theconductive portion 33 is implemented by applying the fusion bonding with a thermal treating process, which increases the volume (thickness) of theconductive portion 33 more than that of thedielectric portion 35 such that thedepression 37 is filled by the conductor of theconductive portion 33. By applying the fusion bonding, it is substantially not necessary to dispose a solder material or the like between the vertically stackedsemiconductor devices - In some embodiments, the
conductive portion 33 defining the bottom of thedepression 37 is formed at a first temperature, and the thermal treating process heats at least one of theconductive portion 33 of thesemiconductor device 30A and theconductive portion 33 of thesemiconductor device 30B to a second temperature higher than the first temperature. In some embodiments, theconductive portion 33 comprises copper, and the second temperature is substantially between 300° C. and 450° C.; and the first temperature is the processing temperature of the selective etching process inFIG. 13 . In some embodiments, the volume of thedepression 37 is substantially the same as the volume expansion of theconductive portion 33 from the first temperature to the second temperature. - The
depression 37 is designed to provide a space for the volume expansion of theconductive portion 33′ with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding; consequently, thesemiconductor apparatus 300 does not exhibit a lateral protrusion into the interface between the twodielectric portions 35′. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated. -
FIGS. 17 to 20 are schematic views of a process for preparing asemiconductor device 30A corresponding thestep 301 inFIG. 7 in accordance with some embodiments of the present disclosure. In some embodiments, the fabrication processes disclosed inFIGS. 8 to 12 are performed, and amask 51 is then formed by performing deposition, lithographic and etching processes on theconductive layer 49, as shown inFIG. 17 . In some embodiments, themask 51 is a patterned photoresist layer selectively covering theconductive layer 49 in theopening 47, and the upper end of themask 51 is substantially higher than the upper end of thedielectric layer 41. - In
FIG. 18 , adielectric layer 53 is formed over thedielectric layer 41 and covering themask 51. In some embodiments, thedielectric layer 53 is made of silicon oxide, which is the same material as thedielectric layer 41. - In
FIG. 19 , a planarization process is performed to remove an upper portion of thedielectric layer 53 and expose themask 51. In some embodiments, the planarization process is a chemical mechanical polishing process, and the upper end of themask 51 is substantially at the same level as that of thedielectric layer 53 after the planarization process. - In
FIG. 20 , themask 51 is removed from theconductive layer 49 in theopening 47 so as to form adepression 37 above the upper surface of theconductive layer 49 in theopening 47. Consequently, theconductive layer 49 in theopening 47 serves as theconductive portion 33 of thesemiconductor device 30A, and the remainingdielectric layer 53 and thedielectric layer 41 serve as thedielectric portion 35 of thesemiconductor device 30A. - The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than the dielectric portion. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.
- One embodiment of the present disclosure provides a semiconductor apparatus including a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression above an upper surface of the first conductive portion, wherein a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion, and a volume of the depression is substantially the same as a volume expansion of the first conductive portion from a first temperature to a second temperature higher than the first temperature.
- Another embodiment of the present disclosure provides a semiconductor apparatus, including: a first semiconductor device having a first conductive portion and a first dielectric portion adjacent to the first conductive portion; and a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion. The first conductive portion is directly bonded to the second conductive portion substantially in the absence of a solder material between the first conductive portion and the second conductive portion, and the first dielectric portion is directly bonded to the second dielectric portion.
- Another embodiment of the present disclosure provides a method for preparing a semiconductor apparatus, including: forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one is of the first conductive portion and the second conductive portion to fill the depression.
- Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented through different methods, replaced by other processes, or a combination thereof.
- Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (20)
1. A semiconductor apparatus, comprising a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a first depression above an upper surface of the first conductive portion, wherein a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion, wherein a thickness of the first dielectric portion is increased from a first temperature to a second temperature higher than the first temperature, and a volume of the first depression is substantially the same as a volume expansion of the first conductive portion from the first temperature to the second temperature.
2. The semiconductor apparatus of claim 1 , wherein an upper end of the first conductive portion is lower than an upper end of the first dielectric portion.
3. The semiconductor apparatus of claim 1 , wherein a thickness of the first conductive portion is less than a thickness of the first dielectric portion.
4. The semiconductor apparatus of claim 1 , further comprising:
a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion, and a second depression above an upper surface of the second conductive portion;
wherein the first conductive portion faces the second conductive portion, the first depression and the second depress separate the first conductive portion from the second conductive portion, and the first dielectric portion contacts the second dielectric portion,
wherein a thickness of the second dielectric portion is increased from the first temperature to the second temperature, and a volume of the second depression is substantially the same as a volume expansion of the second conductive portion from the first temperature to the second temperature.
5. The semiconductor apparatus of claim 4 , wherein a center of the first conductive portion is aligned with a center of the second conductive portion.
6. The semiconductor apparatus of claim 4 , wherein the first conductive portion is directly bonded to the second conductive portion substantially in the absence of a solder material between the first conductive portion and the second conductive portion.
7. The semiconductor apparatus of claim 1 , wherein the first conductive portion comprises copper, and the second temperature is substantially between 300° C. and 450° C.
8. A semiconductor apparatus, comprising:
a first semiconductor device having a first conductive portion and a first dielectric portion adjacent to the first conductive portion; and
a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion;
wherein the first conductive portion is directly bonded to the second conductive portion substantially in the absence of a solder material between the first conductive portion and the second conductive portion, and the first dielectric portion is directly bonded to the second dielectric portion.
9. The semiconductor apparatus of claim 8 , wherein a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion.
10. The semiconductor apparatus of claim 8 , wherein the first semiconductor device and the second semiconductor device are vertically bonded, and the first conductive portion contacts the second conductive portion substantially in the absence of a lateral protrusion into an interface between the first dielectric portion and the second dielectric portion.
11. The semiconductor apparatus of claim 8 , wherein the first semiconductor device and the second semiconductor device are directly bonded substantially in the absence of a solder material between the first semiconductor device and the second semiconductor device.
12. The semiconductor apparatus of claim 8 , wherein a center of the first conductive portion is aligned with a center of the second conductive portion.
13. The semiconductor apparatus of claim 8 , wherein the first conductive portion comprises copper, and the second temperature is substantially between 300° C. and 450° C.
14. A method for preparing a semiconductor apparatus, comprising:
forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion;
forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion;
disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and
expanding at least one of the first conductive portion and the second conductive portion to fill the depression.
15. The method for preparing a semiconductor apparatus of claim 14 , wherein the forming of the first semiconductor device comprises:
forming a first dielectric layer over a semiconductor substrate;
forming an opening in the first dielectric layer; and
forming the first conductive portion in the opening.
16. The method for preparing a semiconductor apparatus of claim 15 , wherein the forming of the first conductive portion in the opening comprises:
forming a conductive layer over the first dielectric layer and filling the opening;
performing a planarization process to remove a portion of the conductive layer from an upper surface of the first dielectric layer; and
performing a selective etching process to remove an upper portion of the conductive layer in the opening to form the depression.
17. The method for preparing a semiconductor apparatus of claim 15 , wherein the forming of the first conductive portion in the opening comprises:
forming a conductive layer over the first dielectric layer and filling the opening;
performing a first planarization process to remove a portion of the conductive layer from an upper surface of the first dielectric layer;
forming a mask covering the conductive layer in the opening;
forming a second dielectric layer over the first dielectric layer and covering the mask;
performing a second planarization process to remove a portion of the second dielectric layer and expose the mask; and
removing the mask to form a depression.
18. The method for preparing a semiconductor apparatus of claim 14 , wherein a coefficient of thermal expansion of the first conductive portion is higher than that of the first dielectric portion, and expanding at least one of the first conductive portion and the second conductive portion comprises performing a thermal treating process that expands a thickness of the first conductive portion more than a thickness of the first dielectric portion.
19. The method for preparing a semiconductor apparatus of claim 18 , wherein the first conductive portion having the depression is formed at a first temperature, and the thermal treating process heats at least one of the first conductive portion and the second conductive portion to a second temperature higher than the first temperature.
20. The method for preparing a semiconductor apparatus of claim 14 , wherein the depression separates the first conductive portion from the second conductive portion, and the first dielectric portion contacts the second dielectric portion.
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Cited By (3)
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WO2020092200A1 (en) * | 2018-10-29 | 2020-05-07 | Applied Materials, Inc. | Methods for bonding substrates |
WO2021096552A1 (en) * | 2019-11-13 | 2021-05-20 | Sandisk Technologies Llc | Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same |
US11189563B2 (en) * | 2019-08-01 | 2021-11-30 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
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US20180233479A1 (en) | 2017-02-16 | 2018-08-16 | Nanya Technology Corporation | Semiconductor apparatus and method for preparing the same |
EP3900028A4 (en) | 2020-01-07 | 2022-08-03 | Yangtze Memory Technologies Co., Ltd. | Metal-dielectric bonding method and structure |
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US8716105B2 (en) * | 2011-03-31 | 2014-05-06 | Soitec | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods |
US8697493B2 (en) * | 2011-07-18 | 2014-04-15 | Soitec | Bonding surfaces for direct bonding of semiconductor structures |
TWI493690B (en) * | 2011-07-18 | 2015-07-21 | Soitec Silicon On Insulator | Improved bonding surfaces for direct bonding of semiconductor structures |
FR2993400A1 (en) * | 2012-07-12 | 2014-01-17 | St Microelectronics Crolles 2 | THREE-DIMENSIONAL INTEGRATED STRUCTURE FOR DETECTING TEMPERATURE ELEVATION |
US9123785B1 (en) * | 2014-03-10 | 2015-09-01 | Intermolecular, Inc. | Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/HCI solution |
KR102360381B1 (en) * | 2014-12-01 | 2022-02-11 | 삼성전자주식회사 | Semiconductor devices having stacking structures and methods for fabricating the same |
US9953941B2 (en) * | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
US20180233479A1 (en) | 2017-02-16 | 2018-08-16 | Nanya Technology Corporation | Semiconductor apparatus and method for preparing the same |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020092200A1 (en) * | 2018-10-29 | 2020-05-07 | Applied Materials, Inc. | Methods for bonding substrates |
US11309278B2 (en) | 2018-10-29 | 2022-04-19 | Applied Materials, Inc. | Methods for bonding substrates |
US11189563B2 (en) * | 2019-08-01 | 2021-11-30 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
WO2021096552A1 (en) * | 2019-11-13 | 2021-05-20 | Sandisk Technologies Llc | Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same |
US11094653B2 (en) | 2019-11-13 | 2021-08-17 | Sandisk Technologies Llc | Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same |
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TWI635594B (en) | 2018-09-11 |
TW201832338A (en) | 2018-09-01 |
US20180374818A1 (en) | 2018-12-27 |
US10825794B2 (en) | 2020-11-03 |
US10923455B2 (en) | 2021-02-16 |
US20180233480A1 (en) | 2018-08-16 |
CN108447839A (en) | 2018-08-24 |
CN108447839B (en) | 2020-01-10 |
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