TWI615922B - Method of manufacturing semiconductor memory device - Google Patents
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Abstract
一種半導體記憶元件的製造方法，其步驟如下。提供具有第一區、第二區以及第三區的基底。於第一區上形成第一堆疊結構。於第二區上形成第二堆疊結構。於第三區上形成第三堆疊結構。於基底上形成第一罩幕層，以覆蓋第三堆疊結構。進行第一離子佈植製程，使得第二堆疊結構的第二浮置閘極與第二控制閘極的導電型態轉變為第一導電型。於基底上形成第二罩幕層，以覆蓋第一堆疊結構與第二堆疊結構。進行第二離子佈植製程，使得第三堆疊結構的第三浮置閘極與第三控制閘極的導電型態轉變為第二導電型。A method of manufacturing a semiconductor memory device, the steps of which are as follows. A substrate having a first zone, a second zone, and a third zone is provided. A first stacked structure is formed on the first region. A second stack structure is formed on the second region. A third stacked structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. The first ion implantation process is performed such that the conductive patterns of the second floating gate and the second control gate of the second stacked structure are converted into the first conductivity type. A second mask layer is formed on the substrate to cover the first stacked structure and the second stacked structure. The second ion implantation process is performed such that the conductive patterns of the third floating gate and the third control gate of the third stacked structure are converted into the second conductivity type.
Description
本發明是有關於一種半導體元件的製造方法，且特別是有關於一種半導體記憶元件的製造方法。The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor memory device.
隨著科技日新月異，記憶元件為了達到降低成本及簡化製程步驟的需求，將晶胞區（Cell Region）與周邊電路區（Periphery Region）的元件整合在同一晶片上已逐漸成為一種趨勢。而且根據記憶元件中所需之功能不同，會在晶胞區與周邊電路區中分別形成具有不同功能的電晶體。With the rapid development of technology, memory components have become a trend in integrating the cells of the Cell Region and the Periphery Region on the same wafer in order to reduce the cost and simplify the process steps. Moreover, depending on the functions required in the memory element, transistors having different functions are formed in the cell region and the peripheral circuit region, respectively.
一般而言，周邊電路區的電晶體為互補式金氧半（CMOS）電晶體，其包括N型金氧半（NMOS）電晶體以及P型金氧半（PMOS）電晶體。然而，利用微影與離子佈植製程，以於周邊電路區上分別形成N型閘電極與P型閘電極時，後續的熱製程容易導致N型閘電極的N型摻質與P型閘電極的P型摻質中和（neutralize），而無法達到雙重功函數閘極（dual work function gate）的結構與功效。In general, the transistors in the peripheral circuit region are complementary metal oxide half (CMOS) transistors including N-type gold oxide half (NMOS) transistors and P-type gold oxide half (PMOS) transistors. However, when the lithography and ion implantation processes are used to form the N-type gate electrode and the P-type gate electrode respectively on the peripheral circuit region, the subsequent thermal process easily leads to the N-type dopant and the P-type gate electrode of the N-type gate electrode. The P-type dopant is neutralized and cannot achieve the structure and efficacy of the dual work function gate.
本發明提供一種半導體記憶元件的製造方法，其可結合三重閘介電層製程與雙重功函數閘極製程，以提升半導體記憶元件的效能。The invention provides a method for fabricating a semiconductor memory device, which can combine a triple gate dielectric layer process and a dual work function gate process to improve the performance of the semiconductor memory device.
本發明提供一種半導體記憶元件的製造方法，其步驟如下。提供具有第一區、第二區以及第三區的基底。於第一區上形成第一堆疊結構。第一堆疊結構依序包括第一閘介電層、第一浮置閘極、第一閘間介電層以及第一控制閘極。於第二區上形成第二堆疊結構。第二堆疊結構依序包括第二閘介電層、第二浮置閘極、第二閘間介電層以及第二控制閘極。於第三區上形成第三堆疊結構。第三堆疊結構依序包括第三閘介電層、第三浮置閘極、第三閘間介電層以及第三控制閘極。於基底上形成第一罩幕層，以覆蓋第三堆疊結構。進行第一離子佈植製程，使得第二浮置閘極以及第二控制閘極的導電型態轉變為第一導電型。移除第一罩幕層並於基底上形成第二罩幕層，以覆蓋第一堆疊結構與第二堆疊結構。進行第二離子佈植製程，使得第三浮置閘極以及第三控制閘極的導電型態轉變為第二導電型。The present invention provides a method of fabricating a semiconductor memory device, the steps of which are as follows. A substrate having a first zone, a second zone, and a third zone is provided. A first stacked structure is formed on the first region. The first stack structure sequentially includes a first gate dielectric layer, a first floating gate, a first inter-gate dielectric layer, and a first control gate. A second stack structure is formed on the second region. The second stack structure sequentially includes a second gate dielectric layer, a second floating gate, a second inter-gate dielectric layer, and a second control gate. A third stacked structure is formed on the third region. The third stack structure sequentially includes a third gate dielectric layer, a third floating gate, a third inter-gate dielectric layer, and a third control gate. A first mask layer is formed on the substrate to cover the third stack structure. The first ion implantation process is performed such that the conductive patterns of the second floating gate and the second control gate are converted into the first conductivity type. The first mask layer is removed and a second mask layer is formed on the substrate to cover the first stack structure and the second stack structure. The second ion implantation process is performed such that the conductive patterns of the third floating gate and the third control gate are converted into the second conductivity type.
在本發明的一實施例中，在進行第一離子佈植製程與第二離子佈植製程之前，所述方法更包括於第一區的基底中形成第一源極/汲極、於第二區的基底中形成第二源極/汲極以及於第三區的基底中形成第三源極/汲極。In an embodiment of the invention, before performing the first ion implantation process and the second ion implantation process, the method further comprises forming a first source/drain in the substrate of the first region, and second A second source/drain is formed in the substrate of the region and a third source/drain is formed in the substrate of the third region.
在本發明的一實施例中，在進行第二離子佈植製程之後，所述方法更包括以下步驟。移除第二罩幕層。於基底上形成金屬層，以覆蓋該第一控制閘極、第二控制閘極以及第三控制閘極的表面。進行金屬矽化製程，以於第一控制閘極上形成第一矽化金屬層、於第二控制閘極上形成第二矽化金屬層以及於第三控制閘極上形成第三矽化金屬層。In an embodiment of the invention, after performing the second ion implantation process, the method further comprises the following steps. Remove the second mask layer. A metal layer is formed on the substrate to cover surfaces of the first control gate, the second control gate, and the third control gate. A metal deuteration process is performed to form a first deuterated metal layer on the first control gate, a second deuterated metal layer on the second control gate, and a third deuterated metal layer on the third control gate.
在本發明的一實施例中，所述第一閘介電層、所述第二閘介電層以及所述第三閘介電層的厚度彼此不同。In an embodiment of the invention, the thicknesses of the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are different from each other.
在本發明的一實施例中，所述第二閘介電層的厚度大於所述第一閘介電層的厚度，且所述第一閘介電層的厚度大於所述第三閘介電層的厚度。In an embodiment of the invention, the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer, and the thickness of the first gate dielectric layer is greater than the third gate dielectric The thickness of the layer.
在本發明的一實施例中，所述第一區為晶胞區，所述第二區為高壓元件區，而所述第三區為低壓元件區。In an embodiment of the invention, the first region is a cell region, the second region is a high voltage device region, and the third region is a low voltage device region.
在本發明的一實施例中，在進行第一離子佈植製程時，其使得第一控制閘極的導電型態轉變為第一導電型。In an embodiment of the invention, when the first ion implantation process is performed, it causes the conductivity type of the first control gate to be converted into the first conductivity type.
在本發明的一實施例中，所述第一導電型與所述第二導電型不同。In an embodiment of the invention, the first conductivity type is different from the second conductivity type.
在本發明的一實施例中，所述第一堆疊結構、所述第二堆疊結構以及所述第三堆疊結構彼此分離而不互相連接。In an embodiment of the invention, the first stack structure, the second stack structure, and the third stack structure are separated from each other without being connected to each other.
在本發明的一實施例中，所述半導體記憶元件為快閃記憶體。In an embodiment of the invention, the semiconductor memory element is a flash memory.
基於上述，本發明提供一種半導體記憶元件的製造方法，其利用三重閘介電層製程與雙重功函數閘極製程將晶胞區與周邊電路區的元件整合在同一晶片上。在進行離子佈植製程的期間，由於晶胞區的閘極結構與周邊電路區的高壓元件區與低壓元件區的閘極結構彼此分離，因此，可避免後續的熱製程所導致的N/P型摻質的中和現象。如此一來，本發明之半導體記憶元件結合三重閘介電層與雙重功函數閘極，不僅可提升半導體記憶元件的效能，還可使得半導體記憶元件的配置更具有彈性，以符合設計者或使用者的需求。Based on the above, the present invention provides a method of fabricating a semiconductor memory device that integrates elements of a cell region and a peripheral circuit region on the same wafer using a triple gate dielectric layer process and a dual work function gate process. During the ion implantation process, since the gate structure of the cell region and the gate structure of the high voltage device region and the low voltage device region of the peripheral circuit region are separated from each other, the N/P caused by the subsequent thermal process can be avoided. Neutralization of type dopants. In this way, the semiconductor memory device of the present invention combines the triple gate dielectric layer and the dual work function gate to not only improve the performance of the semiconductor memory device, but also make the configuration of the semiconductor memory device more flexible to conform to the designer or use. The needs of the people.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not be repeated.
在以下的實施例中，第一導電型與第二導電型為不同導電型態。也就是說，當第一導電型為N型，第二導電型為P型；當第一導電型為P型，第二導電型為N型。在本實施例中，是以第一導電型為N型，第二導電型為P型為例來實施，但本發明並不以此為限。P型摻質例如是硼；N型摻質例如是磷或是砷。In the following embodiments, the first conductivity type and the second conductivity type are different conductivity types. That is, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, and the second conductivity type is N type. In the present embodiment, the first conductivity type is N-type and the second conductivity type is P-type as an example, but the invention is not limited thereto. The P-type dopant is, for example, boron; the N-type dopant is, for example, phosphorus or arsenic.
圖1A至圖1F為本發明一實施例的半導體記憶元件之製造流程剖面示意圖。1A to 1F are schematic cross-sectional views showing a manufacturing process of a semiconductor memory device according to an embodiment of the present invention.
請參照圖1A，提供基底100，基底100的材料例如是選自於由矽（Si）、鍺（Ge）、矽化鍺（SiGe）、磷化鎵（GaP）、砷化鎵（GaAs）、碳化矽（SiC）、碳化矽鍺（SiGeC）、砷化銦（InAs）與磷化銦（InP）所組成的群組中的至少一種材料。在一實施例中，基底100也可以是覆矽絕緣（SOI）基底。上述基底100具有晶胞區200（可視為第一區）與周邊電路區300。更詳細地說，周邊電路區300包括高壓元件區400（可視為第二區）與低壓元件區500（可視為第三區）。在替代實施例中，周邊電路區300也可包括低壓元件區400（可視為第二區）與超低壓元件區500（可視為第三區）。Referring to FIG. 1A, a substrate 100 is provided. The material of the substrate 100 is, for example, selected from the group consisting of germanium (Si), germanium (Ge), germanium telluride (SiGe), gallium phosphide (GaP), gallium arsenide (GaAs), carbonization. At least one material selected from the group consisting of bismuth (SiC), tantalum carbide (SiGeC), indium arsenide (InAs), and indium phosphide (InP). In an embodiment, the substrate 100 can also be a blanket insulating (SOI) substrate. The substrate 100 has a cell region 200 (which may be regarded as a first region) and a peripheral circuit region 300. In more detail, the peripheral circuit region 300 includes a high voltage element region 400 (which may be regarded as a second region) and a low voltage device region 500 (which may be regarded as a third region). In an alternate embodiment, peripheral circuit region 300 may also include low voltage component region 400 (which may be considered a second region) and ultra low voltage component region 500 (which may be considered a third region).
接著，於晶胞區200上形成第一堆疊結構110；於高壓元件區400上形成第二堆疊結構410；且於低壓元件區500上形成第三堆疊結構510。在本實施例中，第一堆疊結構110、第二堆疊結構410以及第三堆疊結構510彼此分離而不互相連接。另外，第一堆疊結構110、第二堆疊結構410以及第三堆疊結構510的形成順序並不受限，只要是可在基底100上形成彼此分離的第一堆疊結構110、第二堆疊結構410以及第三堆疊結構510即為本發明所保護的範疇。Next, a first stacked structure 110 is formed on the cell region 200; a second stacked structure 410 is formed on the high voltage element region 400; and a third stacked structure 510 is formed on the low voltage device region 500. In the present embodiment, the first stack structure 110, the second stack structure 410, and the third stack structure 510 are separated from each other without being connected to each other. In addition, the order of forming the first stacked structure 110, the second stacked structure 410, and the third stacked structure 510 is not limited as long as the first stacked structure 110, the second stacked structure 410, and the second stacked structure 410, which are separated from each other, can be formed on the substrate 100, and The third stack structure 510 is the scope of protection of the present invention.
詳細地說，第一堆疊結構110由下至上依序包括第一閘介電層102、第一浮置閘極104、第一閘間介電層106、第一控制閘極108、112以及第一頂蓋層114。在一實施例中，第一堆疊結構110可例如是選擇閘極（select gate）。In detail, the first stacked structure 110 includes a first gate dielectric layer 102, a first floating gate 104, a first gate dielectric layer 106, first control gates 108, 112, and a portion from bottom to top. A cap layer 114. In an embodiment, the first stack structure 110 can be, for example, a select gate.
第一閘介電層102可例如是穿隧介電層。在一實施例中，第一閘介電層102的材料包括氧化矽、氮氧化矽、氮化矽或其他合適的介電材料，其形成方法包括化學氣相沉積法或爐管氧化法等，且其厚度可為1 nm至20 nm，較佳為6 nm至9 nm。The first gate dielectric layer 102 can be, for example, a tunneling dielectric layer. In one embodiment, the material of the first gate dielectric layer 102 includes hafnium oxide, hafnium oxynitride, tantalum nitride or other suitable dielectric materials, and the formation method thereof includes chemical vapor deposition or furnace tube oxidation. The thickness may be from 1 nm to 20 nm, preferably from 6 nm to 9 nm.
在一實施例中，第一浮置閘極104的材料可例如是N型摻雜多晶矽，其形成方法包括化學氣相沈積法，其厚度為50 nm至100 nm。但本發明不以此為限，在其他實施例中，可藉由後續第一離子佈植製程210而使第一浮置閘極104具有N型導電型（如圖1D所示）。In one embodiment, the material of the first floating gate 104 may be, for example, an N-type doped polysilicon, and the formation method thereof includes a chemical vapor deposition method having a thickness of 50 nm to 100 nm. However, the present invention is not limited thereto. In other embodiments, the first floating gate 104 may have an N-type conductivity type (as shown in FIG. 1D) by the subsequent first ion implantation process 210.
第一閘間介電層106可以是由單層材料層或是多層材料層所構成之堆疊結構。舉例來說，第一閘間介電層106可例如是氧化矽/氮化矽/氧化矽（ONO）堆疊層或氮化矽/氧化矽/氮化矽/氧化矽/氮化矽（NONON）堆疊層，其形成方法包括化學氣相沈積法，其厚度可為5 nm至30 nm，較佳為10 nm至15 nm。於一較佳的實施例中，第一閘間介電層106的厚度大於第一閘介電層102的厚度。The first inter-gate dielectric layer 106 may be a stacked structure composed of a single layer of material or a plurality of layers of material. For example, the first inter-gate dielectric layer 106 can be, for example, a tantalum oxide/tantalum nitride/yttria (ONO) stacked layer or tantalum nitride/yttria/tantalum nitride/yttria/nitride (NONON). The stacked layer is formed by a chemical vapor deposition method and has a thickness of 5 nm to 30 nm, preferably 10 nm to 15 nm. In a preferred embodiment, the thickness of the first inter-gate dielectric layer 106 is greater than the thickness of the first gate dielectric layer 102.
第一控制閘極108、112的材料包括未摻雜多晶矽或本徵多晶矽（intrinsic polysilicon），其形成方法包括化學氣相沈積法。具體來說，第一控制閘極112位於第一控制閘極108上，且第一控制閘極112具有一突出結構。所述突出結構自第一控制閘極112的底面向下延伸並貫穿第一控制閘極108與第一閘間介電層106，以與第一浮置閘極104接觸。The material of the first control gates 108, 112 includes undoped polysilicon or intrinsic polysilicon, and the formation method thereof includes chemical vapor deposition. Specifically, the first control gate 112 is located on the first control gate 108, and the first control gate 112 has a protruding structure. The protruding structure extends downward from the bottom surface of the first control gate 112 and penetrates the first control gate 108 and the first inter-gate dielectric layer 106 to be in contact with the first floating gate 104.
第一頂蓋層114的材料包括氧化矽、氮化矽或其他合適的介電材料，其形成方法包括化學氣相沈積法，其厚度可為10 nm至100 nm，較佳為40 nm至100 nm。於一較佳的實施例中，第一頂蓋層114的厚度大於第一閘間介電層106的厚度。The material of the first cap layer 114 includes hafnium oxide, tantalum nitride or other suitable dielectric materials, and the formation method thereof includes chemical vapor deposition, and the thickness thereof may be 10 nm to 100 nm, preferably 40 nm to 100 nm. Nm. In a preferred embodiment, the thickness of the first cap layer 114 is greater than the thickness of the first inter-gate dielectric layer 106.
另外，除了第一堆疊結構110之外，晶胞區200上更包括多個字元線120。每一個字元線120由下至上依序包括第一閘介電層102、第四浮置閘極124、第四閘間介電層126、第四控制閘極128、132以及第四頂蓋層134。由於字元線120與第一堆疊結構110相似，且第一堆疊結構110的構件與形成方法已於上述段落說明過，於此便不再贅述。在一實施例中，第一堆疊結構110（例如是選擇閘極）的寬度W1可為100 nm至300 nm，較佳為140 nm至220 nm；而字元線120的寬度W2可為5 nm至80 nm，較佳為10 nm至58 nm。In addition, in addition to the first stacked structure 110, the cell region 200 further includes a plurality of word lines 120. Each word line 120 includes a first gate dielectric layer 102, a fourth floating gate 124, a fourth gate dielectric layer 126, fourth control gates 128, 132, and a fourth top cover sequentially from bottom to top. Layer 134. Since the word line 120 is similar to the first stacked structure 110, and the components and forming methods of the first stacked structure 110 have been described in the above paragraphs, they will not be described again. In an embodiment, the width W1 of the first stacked structure 110 (eg, a select gate) may be 100 nm to 300 nm, preferably 140 nm to 220 nm; and the width W2 of the word line 120 may be 5 nm. Up to 80 nm, preferably 10 nm to 58 nm.
另外，第二堆疊結構410由下至上依序包括第二閘介電層402、第二浮置閘極404、第二閘間介電層406、第二控制閘極408、412以及第二頂蓋層414。在一實施例中，第二堆疊結構410可例如是高壓金氧半電晶體。In addition, the second stack structure 410 sequentially includes a second gate dielectric layer 402, a second floating gate 404, a second inter-gate dielectric layer 406, second control gates 408, 412, and a second top from bottom to top. Cover layer 414. In an embodiment, the second stack structure 410 can be, for example, a high voltage MOS transistor.
由於第二堆疊結構410與第一堆疊結構110相似，且第一堆疊結構110的構件與形成方法已於上述段落說明過，於此便不再贅述。第二堆疊結構410與第一堆疊結構110的不同之處在於：第二堆疊結構410的第二閘介電層402的厚度大於第一閘介電層102的厚度，第二閘介電層402的厚度可為30 nm至50 nm。而且第二堆疊結構410的第二浮置閘極404以及第二控制閘極408、412可藉由後續第一離子佈植製程210成為具有N型導電型的多晶矽（如圖1D所示）。Since the second stack structure 410 is similar to the first stack structure 110, and the components and forming methods of the first stack structure 110 have been described in the above paragraphs, they will not be described again. The second stacked structure 410 is different from the first stacked structure 110 in that the thickness of the second gate dielectric layer 402 of the second stacked structure 410 is greater than the thickness of the first gate dielectric layer 102, and the second gate dielectric layer 402 is The thickness can range from 30 nm to 50 nm. Moreover, the second floating gate 404 and the second control gate 408, 412 of the second stacked structure 410 can be made into a polysilicon having an N-type conductivity by the subsequent first ion implantation process 210 (as shown in FIG. 1D).
此外，第三堆疊結構510由下至上依序包括第三閘介電層502、第三浮置閘極504、第三閘間介電層506、第三控制閘極508、512以及第三頂蓋層514。在一實施例中，第三堆疊結構510可例如是低壓金氧半電晶體。In addition, the third stack structure 510 sequentially includes a third gate dielectric layer 502, a third floating gate 504, a third gate dielectric layer 506, third control gates 508, 512, and a third top from bottom to top. Cover layer 514. In an embodiment, the third stack structure 510 can be, for example, a low voltage MOS transistor.
由於第三堆疊結構510與第一堆疊結構110相似，且第一堆疊結構110的構件與形成方法已於上述段落說明過，於此便不再贅述。第三堆疊結構510與第一堆疊結構110的不同之處在於：第三堆疊結構510的第三閘介電層502的厚度小於第一閘介電層102的厚度，其可為2 nm至4 nm。而且第三堆疊結構510的第三浮置閘極504以及第三控制閘極508、512可藉由後續第二離子佈植製程214成為具有P型導電型的多晶矽（如圖1E所示）。Since the third stacked structure 510 is similar to the first stacked structure 110, and the components and forming methods of the first stacked structure 110 have been described in the above paragraphs, they will not be described again. The third stacked structure 510 is different from the first stacked structure 110 in that the thickness of the third gate dielectric layer 502 of the third stacked structure 510 is smaller than the thickness of the first gate dielectric layer 102, which may be 2 nm to 4 Nm. Moreover, the third floating gate 504 and the third control gate 508, 512 of the third stacked structure 510 can be made into a polysilicon having a P-type conductivity by a subsequent second ion implantation process 214 (as shown in FIG. 1E).
本實施例之半導體記憶元件的製造方法可利用三重閘介電層製程，以於基底100上形成不同厚度的閘介電層，進而提升半導體記憶元件的效能。The method for fabricating the semiconductor memory device of the present embodiment can utilize a triple gate dielectric layer process to form gate dielectric layers of different thicknesses on the substrate 100, thereby improving the performance of the semiconductor memory device.
請參照圖1A與圖1B，在形成介電層202、204、206之前（或進行圖1D的第一離子佈植製程210之前），於第一堆疊結構110的兩側的基底100中形成第一源極/汲極12；於第二堆疊結構410的兩側的基底100中形成第二源極/汲極42；且於第三堆疊結構510的兩側的基底100中形成第三源極/汲極52。第一源極/汲極12、第二源極/汲極42以及第三源極/汲極52可以藉由形成罩幕圖案以及進行源極/汲極離子佈植製程來形成。舉例來說，可在高壓元件區400與低壓元件區500的基底100上形成罩幕圖案（未繪示），並以第一頂蓋層114與所述罩幕圖案為罩幕，進行源極/汲極離子佈植製程，以於第一堆疊結構110的兩側的基底100中形成第一源極/汲極12。以此類推，亦可用類似方法形成第二源極/汲極42以及第三源極/汲極52。在一實施例中，第一源極/汲極12所植入的摻質可例如是磷或是砷，其摻雜濃度可例如是1´10 12/cm 3至1´10 15/cm 3。第二源極/汲極42所植入的摻質可例如是磷或是砷，其摻雜濃度可例如是1´10 14/cm 3至3´10 16/cm 3。第三源極/汲極52所植入的摻質可例如是硼，其摻雜濃度可例如是1´10 14/cm 3至2.5´10 16/cm 3。 Referring to FIG. 1A and FIG. 1B, before forming the dielectric layers 202, 204, 206 (or before performing the first ion implantation process 210 of FIG. 1D), the first substrate 100 is formed on both sides of the first stacked structure 110. a source/drain 12; a second source/drain 42 is formed in the substrate 100 on both sides of the second stacked structure 410; and a third source is formed in the substrate 100 on both sides of the third stacked structure 510 / bungee 52. The first source/drain 12, the second source/drain 42 and the third source/drain 52 may be formed by forming a mask pattern and performing a source/drain ion implantation process. For example, a mask pattern (not shown) may be formed on the substrate 100 of the high voltage device region 400 and the low voltage device region 500, and the source is performed by using the first cap layer 114 and the mask pattern as a mask. / Bipolar ion implantation process to form a first source/drain 12 in the substrate 100 on both sides of the first stacked structure 110. By analogy, the second source/drain 42 and the third source/drain 52 can also be formed in a similar manner. In an embodiment, the dopant implanted in the first source/drain 12 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1 ́10 12 /cm 3 to 1 ́10 15 /cm 3 . . The dopant implanted in the second source/drain 42 may be, for example, phosphorus or arsenic, and its doping concentration may be, for example, 1 ́10 14 /cm 3 to 3 ́10 16 /cm 3 . The dopant implanted in the third source/drain 52 may be, for example, boron, and its doping concentration may be, for example, 1 ́10 14 /cm 3 to 2.5 ́10 16 /cm 3 .
接著，於基底100上形成介電層202。具體來說，介電層202覆蓋第一堆疊結構110、字元線120、第二堆疊結構410以及第三堆疊結構510的表面。介電層202亦填入第一堆疊結構110與字元線120之間的空隙以及兩相鄰字元線120之間的空隙。介電層202的材料包括填溝能力較佳的介電材料。Next, a dielectric layer 202 is formed on the substrate 100. Specifically, the dielectric layer 202 covers the surfaces of the first stacked structure 110, the word line 120, the second stacked structure 410, and the third stacked structure 510. Dielectric layer 202 also fills the gap between first stacked structure 110 and word line 120 and the gap between two adjacent word lines 120. The material of the dielectric layer 202 includes a dielectric material having a better trench filling ability.
之後，於介電層202上依序形成介電層204、206。介電層204的材料包括氮化矽；介電層206的材料包括氧化矽，其可為可流動性材料，例如為旋塗式玻璃（Spin-On Glass，SOG）、可流動氧化矽（flowable oxide）。如圖1B所示，在平坦化製程（例如是CMP製程）之後，晶胞區200、高壓元件區400以及低壓元件區500上的介電層204、206的頂面為共平面。Thereafter, dielectric layers 204, 206 are sequentially formed on dielectric layer 202. The material of the dielectric layer 204 includes tantalum nitride; the material of the dielectric layer 206 includes tantalum oxide, which may be a flowable material, such as spin-on glass (SOG), flowable tantalum oxide (flowable) Oxide). As shown in FIG. 1B, after the planarization process (eg, a CMP process), the top surfaces of the dielectric regions 204, 206 on the cell region 200, the high voltage device region 400, and the low voltage device region 500 are coplanar.
請參照圖1B與圖1C，進行回蝕刻製程，移除部分介電層202、204、206、第一頂蓋層114、第四頂蓋層134、第二頂蓋層414、第三頂蓋層514、部分第一控制閘極112、部分第四控制閘極132、部分第二控制閘極412以及部分第三控制閘極512，以暴露出第一控制閘極112a的上表面112U、第四控制閘極132a的上表面132U、第二控制閘極412a的上表面412U以及第三控制閘極512a的上表面512U。在替代實施例中，第一控制閘極112a、第四控制閘極132a、第二控制閘極412a以及第三控制閘極512a的部分側壁也外露於介電層202a、204a、206a。Referring to FIG. 1B and FIG. 1C, an etch back process is performed to remove portions of the dielectric layers 202, 204, 206, the first cap layer 114, the fourth cap layer 134, the second cap layer 414, and the third cap. a layer 514, a portion of the first control gate 112, a portion of the fourth control gate 132, a portion of the second control gate 412, and a portion of the third control gate 512 to expose the upper surface 112U of the first control gate 112a, The upper surface 132U of the control gate 132a, the upper surface 412U of the second control gate 412a, and the upper surface 512U of the third control gate 512a. In an alternate embodiment, portions of the sidewalls of the first control gate 112a, the fourth control gate 132a, the second control gate 412a, and the third control gate 512a are also exposed to the dielectric layers 202a, 204a, 206a.
請參照圖1C與圖1D，於基底100上形成第一罩幕層208。第一罩幕層208覆蓋低壓元件區500的第三堆疊結構510a。在一實施例中，第一罩幕層208的材料可例如是碳或光阻類材料等。接著，進行第一離子佈植製程210，使得原本為未摻雜多晶矽或本徵多晶矽的第一控制閘極108、112a、第四控制閘極128、132a、第二浮置閘極404以及第二控制閘極408、412a成為具有N型導電型的第一控制閘極108a、112b、第四控制閘極128a、132b、第二浮置閘極404a以及第二控制閘極408a、412b。在一實施例中，第一離子佈植製程210所植入的摻質可例如是磷或是砷，其摻雜濃度可例如是1´10 14/cm 3至5´10 16/cm 3。 Referring to FIG. 1C and FIG. 1D, a first mask layer 208 is formed on the substrate 100. The first mask layer 208 covers the third stack structure 510a of the low voltage element region 500. In an embodiment, the material of the first mask layer 208 may be, for example, a carbon or photoresist type material or the like. Next, the first ion implantation process 210 is performed such that the first control gates 108, 112a, the fourth control gates 128, 132a, the second floating gates 404, and the first, which are originally undoped polysilicon or intrinsic polysilicon, are The second control gates 408, 412a are first control gates 108a, 112b having an N-type conductivity, fourth control gates 128a, 132b, second floating gate 404a, and second control gates 408a, 412b. In an embodiment, the dopant implanted in the first ion implantation process 210 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 1 ́10 14 /cm 3 to 5 ́10 16 /cm 3 .
請參照圖1D與圖1E，移除第一罩幕層208並於基底100上形成第二罩幕層212。在一實施例中，第二罩幕層212的材料可例如是碳或光阻類材料等。第二罩幕層212覆蓋晶胞區200的第一堆疊結構110b、字元線120b以及高壓元件區400的第二堆疊結構410b。之後，進行第二離子佈植製程214，使得原本為未摻雜多晶矽或本徵多晶矽的第三浮置閘極504以及第三控制閘極508、512a成為具有P型導電型的第三浮置閘極504a以及第三控制閘極508a、512b。在一實施例中，第二離子佈植製程214所植入的摻質可例如是硼，其摻雜濃度可例如是1´10 14/cm 3至6´10 16/cm 3。 Referring to FIG. 1D and FIG. 1E, the first mask layer 208 is removed and a second mask layer 212 is formed on the substrate 100. In an embodiment, the material of the second mask layer 212 may be, for example, a carbon or photoresist type material or the like. The second mask layer 212 covers the first stacked structure 110b of the cell region 200, the word line 120b, and the second stacked structure 410b of the high voltage element region 400. Thereafter, the second ion implantation process 214 is performed such that the third floating gate 504 and the third control gates 508, 512a, which are originally undoped polysilicon or intrinsic polysilicon, become a third floating type having a P-type conductivity. Gate 504a and third control gates 508a, 512b. In one embodiment, the dopant implanted in the second ion implantation process 214 can be, for example, boron, and the doping concentration can be, for example, 1 ́10 14 /cm 3 to 6 ́10 16 /cm 3 .
值得一提的是，本實施例的半導體記憶元件藉由分別進行源極/汲極離子佈植製程、第一離子佈植製程210以及第二離子佈植製程214，使得第一源極/汲極12、第二源極/汲極42、第三源極/汲極52、N型的第一堆疊結構110b、N型的字元線120b與N型的第二堆疊結構410b以及P型的第三堆疊結構510b的摻雜濃度與配置更有彈性，以符合設計者或使用者的需求。此外，由於晶胞區200的第一堆疊結構110b與高壓元件區400的第二堆疊結構410b以及低壓元件區500的第三堆疊結構510b彼此分離，因此，可避免後續的熱製程所導致的N/P型摻質的中和現象。It is to be noted that the semiconductor memory device of the present embodiment has a first source/drain by performing a source/drain ion implantation process, a first ion implantation process 210, and a second ion implantation process 214, respectively. The pole 12, the second source/drain 42, the third source/drain 52, the N-type first stack 110b, the N-type word line 120b, the N-type second stack 410b, and the P-type The doping concentration and configuration of the third stacked structure 510b is more flexible to meet the needs of the designer or user. In addition, since the first stacked structure 110b of the cell region 200 and the second stacked structure 410b of the high voltage element region 400 and the third stacked structure 510b of the low voltage element region 500 are separated from each other, the N caused by the subsequent thermal process can be avoided. Neutralization of /P type dopants.
請參照圖1E與圖1F，在進行第二離子佈植製程214之後，移除第二罩幕層212。接著，在基底100上形成金屬層（未繪示），以與未被介電層202a、204a、206a所覆蓋的第一控制閘極112b、第四控制閘極132b、第二控制閘極412b以及第三控制閘極512b接觸。金屬層的材料可例如是鎳（Ni）、鈷（Co）、鈦（Ti）、鎢（W）、鉬（Mo）、鉑（Pt）或鈀（Pd）等金屬材料。Referring to FIG. 1E and FIG. 1F, after the second ion implantation process 214 is performed, the second mask layer 212 is removed. Next, a metal layer (not shown) is formed on the substrate 100 to be adjacent to the first control gate 112b, the fourth control gate 132b, and the second control gate 412b that are not covered by the dielectric layers 202a, 204a, 206a. And the third control gate 512b is in contact. The material of the metal layer may be, for example, a metal material such as nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), molybdenum (Mo), platinum (Pt) or palladium (Pd).
然後，進行金屬矽化製程，使得所述金屬層與所接觸的第一控制閘極112b、第四控制閘極132b、第二控制閘極412b以及第三控制閘極512b反應形成第一矽化金屬層116、第四矽化金屬層136、第二矽化金屬層416以及第三矽化金屬層516。在一實施例中，金屬矽化製程例如是熱回火（Anneal）製程。第一矽化金屬層116、第四矽化金屬層136、第二矽化金屬層416以及第三矽化金屬層516可包括矽化鎳（NiSi）、矽化鈷（CoSi）、矽化鈦（TiSi）、矽化鎢（WSi）、矽化鉬（MoSi）、矽化鉑（PtSi）或矽化鈀（PdSi）或其他矽化金屬材料。Then, a metal deuteration process is performed to cause the metal layer to react with the contacted first control gate 112b, the fourth control gate 132b, the second control gate 412b, and the third control gate 512b to form a first deuterated metal layer. 116. A fourth deuterated metal layer 136, a second deuterated metal layer 416, and a third deuterated metal layer 516. In one embodiment, the metal deuteration process is, for example, a thermal tempering process. The first deuterated metal layer 116, the fourth deuterated metal layer 136, the second deuterated metal layer 416, and the third deuterated metal layer 516 may include nickel telluride (NiSi), cobalt telluride (CoSi), titanium telluride (TiSi), and tungsten telluride (Titanium telluride). WSi), molybdenum molybdenum (MoSi), platinum (PtSi) or palladium (PdSi) or other deuterated metal materials.
順帶一提的是，圖1F所繪示的第一堆疊結構110的第一矽化金屬層116的厚度與字元線120c的第四矽化金屬層136的厚度可大於第二堆疊結構410c的第二矽化金屬層416的厚度以及第三堆疊結構510c的第三矽化金屬層516的厚度。第一矽化金屬層116與第四矽化金屬層136的形成方法可例如是在形成所述金屬層之前，移除晶胞區200的部分介電層202a、204a、206a，使得外露於介電層202b、204b、206b的第一控制閘極112b、第四控制閘極132b的面積增加。在一實施例中，上述移除部分介電層202a、204a、206a的步驟中不需要罩幕層。憑藉晶胞區200與周邊電路區300之間的負載效應（loading effect），直接進行蝕刻製程便可達到晶胞區200與周邊電路區300的介電層的高度差。因此，在形成所述金屬層之後，第一控制閘極112b、第四控制閘極132b與所述金屬層之間接觸面積也隨之增加。在進行所述金屬矽化製程之後，由於第一矽化金屬層116的厚度與第四矽化金屬層136的厚度增加，因此，其可降低第一矽化金屬層116的電阻值與第四矽化金屬層136，藉此增加元件的可靠度。Incidentally, the thickness of the first deuterated metal layer 116 of the first stacked structure 110 illustrated in FIG. 1F and the thickness of the fourth deuterated metal layer 136 of the word line 120c may be greater than the second thickness of the second stacked structure 410c. The thickness of the deuterated metal layer 416 and the thickness of the third deuterated metal layer 516 of the third stacked structure 510c. The first deuterated metal layer 116 and the fourth deuterated metal layer 136 may be formed by, for example, removing a portion of the dielectric layer 202a, 204a, 206a of the cell region 200 prior to forming the metal layer, such that the dielectric layer is exposed to the dielectric layer. The areas of the first control gate 112b and the fourth control gate 132b of 202b, 204b, 206b increase. In an embodiment, the mask layer is not required in the step of removing portions of the dielectric layers 202a, 204a, 206a. Due to the loading effect between the cell region 200 and the peripheral circuit region 300, the height difference of the dielectric layers of the cell region 200 and the peripheral circuit region 300 can be achieved by directly performing an etching process. Therefore, after the metal layer is formed, the contact area between the first control gate 112b and the fourth control gate 132b and the metal layer also increases. After the metal deuteration process is performed, since the thickness of the first deuterated metal layer 116 and the thickness of the fourth deuterated metal layer 136 are increased, the resistance value of the first deuterated metal layer 116 and the fourth deuterated metal layer 136 may be lowered. Thereby increasing the reliability of the component.
另外，雖然本實施例中是將高壓元件區400的第二堆疊結構410c視為N型金氧半電晶體；將低壓元件區500的第三堆疊結構510c視為P型金氧半電晶體，但本發明不以此為限。在其他實施例中，高壓元件區400的第二堆疊結構410c也可以是P型金氧半電晶體；而低壓元件區500的第三堆疊結構510c也可以是N型金氧半電晶體。In addition, although in the present embodiment, the second stacked structure 410c of the high voltage element region 400 is regarded as an N-type MOS transistor; the third stacked structure 510c of the low-voltage element region 500 is regarded as a P-type MOS transistor, However, the invention is not limited thereto. In other embodiments, the second stack structure 410c of the high voltage device region 400 may also be a P-type MOS transistor; and the third stack structure 510c of the low voltage device region 500 may also be an N-type MOS transistor.
在一實施例中，以上述方法所形成的半導體記憶元件可以是快閃記憶體，例如是反或快閃記憶體（NOR Flash）、反及快閃記憶體（NAND Flash）等快閃記憶體。本實施例的半導體記憶元件可結合三重閘介電層製程與雙重功函數閘極製程的優點，以提升半導體記憶元件的效能。舉例來說，本實施例可調整低壓元件區500的第三堆疊結構510c（亦即P型低壓半導體元件）的第三閘介電層502的厚度，以降低P型低壓半導體元件的臨界電壓（threshold voltage）。另一方面，在一定的臨界電壓下，則可提高P型低壓半導體元件的操作速度。因此，設計者可依據需求來調整不同元件的臨界電壓與操作速度，以提升半導體記憶元件的整體效能。In one embodiment, the semiconductor memory device formed by the above method may be a flash memory, such as a flash memory such as a reverse flash memory (NOR Flash), a reverse flash memory (NAND Flash), or the like. . The semiconductor memory device of the present embodiment can combine the advantages of the triple gate dielectric layer process and the dual work function gate process to improve the performance of the semiconductor memory device. For example, the present embodiment can adjust the thickness of the third gate dielectric layer 502 of the third stacked structure 510c (ie, the P-type low voltage semiconductor device) of the low voltage device region 500 to reduce the threshold voltage of the P-type low voltage semiconductor device ( Threshold voltage). On the other hand, at a certain threshold voltage, the operating speed of the P-type low voltage semiconductor device can be increased. Therefore, the designer can adjust the threshold voltage and operating speed of different components according to requirements to improve the overall performance of the semiconductor memory component.
綜上所述，本發明提供一種半導體記憶元件的製造方法，其利用三重閘介電層製程與雙重功函數閘極製程將晶胞區與周邊電路區的元件整合在同一晶片上。在進行離子佈植製程的期間，由於晶胞區的閘極結構與周邊電路區的高壓元件區與低壓元件區的閘極結構彼此分離，因此，可避免後續的熱製程所導致的N/P型摻質的中和現象。如此一來，本發明之半導體記憶元件結合三重閘介電層與雙重功函數閘極，不僅可提升半導體記憶元件的效能，還可使得半導體記憶元件的配置更具有彈性，以符合設計者或使用者的需求。In summary, the present invention provides a method of fabricating a semiconductor memory device that integrates components of a cell region and a peripheral circuit region on a same wafer using a triple gate dielectric layer process and a dual work function gate process. During the ion implantation process, since the gate structure of the cell region and the gate structure of the high voltage device region and the low voltage device region of the peripheral circuit region are separated from each other, the N/P caused by the subsequent thermal process can be avoided. Neutralization of type dopants. In this way, the semiconductor memory device of the present invention combines the triple gate dielectric layer and the dual work function gate to not only improve the performance of the semiconductor memory device, but also make the configuration of the semiconductor memory device more flexible to conform to the designer or use. The needs of the people.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
12‧‧‧第一源極/汲極
42‧‧‧第二源極/汲極
52‧‧‧第三源極/汲極
100‧‧‧基底
102‧‧‧第一閘介電層
104‧‧‧第一浮置閘極
106‧‧‧第一閘間介電層
108、108a、112、112a、112b、112c‧‧‧第一控制閘極
110、110a、110b、110c‧‧‧第一堆疊結構
112U、412U、512U‧‧‧上表面
114‧‧‧第一頂蓋層
116‧‧‧第一矽化金屬層
120、120a、120b、120c‧‧‧字元線
124‧‧‧第四浮置閘極
126‧‧‧第四閘間介電層
128、128a、132、132a、132b、132c‧‧‧第四控制閘極
134‧‧‧第四頂蓋層
136‧‧‧第四矽化金屬層
200‧‧‧晶胞區（第一區）
202、202a、202b、204、204a、204b、206、206a、206b‧‧‧介電層
208‧‧‧第一罩幕層
210‧‧‧第一離子佈植製程
212‧‧‧第二罩幕層
214‧‧‧第二離子佈植製程
300‧‧‧周邊電路區
400‧‧‧高壓元件區（第二區）
402‧‧‧第二閘介電層
404、404a‧‧‧第二浮置閘極
406‧‧‧第二閘間介電層
408、408a、412、412a、412b、412c‧‧‧第二控制閘極
410、410a、410b、410c‧‧‧第二堆疊結構
414‧‧‧第二頂蓋層
416‧‧‧第二矽化金屬層
500‧‧‧低壓元件區（第三區）
502‧‧‧第三閘介電層
504、504a‧‧‧第三浮置閘極
506‧‧‧第三閘間介電層
508、508a、512、512a、512b、512c‧‧‧第三控制閘極
510、510a、510b、510c‧‧‧第三堆疊結構
514‧‧‧第三頂蓋層
516‧‧‧第三矽化金屬層
W1、W2‧‧‧寬度12‧‧‧First source/bungee
42‧‧‧Second source/bungee
52‧‧‧ Third source/bungee
100‧‧‧Base
102‧‧‧First gate dielectric layer
104‧‧‧First floating gate
106‧‧‧The first gate dielectric layer
108, 108a, 112, 112a, 112b, 112c‧‧‧ first control gate
110, 110a, 110b, 110c‧‧‧ first stack structure
112U, 412U, 512U‧‧‧ upper surface
114‧‧‧First cover
116‧‧‧First metallized metal layer
120, 120a, 120b, 120c‧‧‧ character lines
124‧‧‧Fourth floating gate
126‧‧‧The fourth gate dielectric layer
128, 128a, 132, 132a, 132b, 132c‧‧‧ fourth control gate
134‧‧‧Four top cover
136‧‧‧fourth metallization layer
200‧‧‧cell area (1st district)
202, 202a, 202b, 204, 204a, 204b, 206, 206a, 206b‧‧‧ dielectric layer
208‧‧‧First mask layer
210‧‧‧First ion implantation process
212‧‧‧Second cover layer
214‧‧‧Second ion implantation process
300‧‧‧ peripheral circuit area
400‧‧‧High-voltage component area (Second area)
402‧‧‧Second gate dielectric layer
404, 404a‧‧‧second floating gate
406‧‧‧Second gate dielectric layer
408, 408a, 412, 412a, 412b, 412c‧‧‧ second control gate
410, 410a, 410b, 410c‧‧‧ second stack structure
414‧‧‧Second top cover
416‧‧‧Second metallized metal layer
500‧‧‧Low-voltage component area (third zone)
502‧‧‧ Third Gate Dielectric Layer
504, 504a‧‧‧ third floating gate
506‧‧‧ third gate dielectric layer
508, 508a, 512, 512a, 512b, 512c‧‧‧ third control gate
510, 510a, 510b, 510c‧‧‧ third stack structure
514‧‧‧ third cover
516‧‧‧ Third metallization layer
W1, W2‧‧‧ width
圖1A至圖1F為本發明一實施例的半導體記憶元件之製造流程剖面示意圖。1A to 1F are schematic cross-sectional views showing a manufacturing process of a semiconductor memory device according to an embodiment of the present invention.
12‧‧‧第一源極/汲極 12‧‧‧First source/bungee
42‧‧‧第二源極/汲極 42‧‧‧Second source/bungee
52‧‧‧第三源極/汲極 52‧‧‧ Third source/bungee
100‧‧‧基底 100‧‧‧Base
102‧‧‧第一閘介電層 102‧‧‧First gate dielectric layer
104‧‧‧第一浮置閘極 104‧‧‧First floating gate
106‧‧‧第一閘間介電層 106‧‧‧The first gate dielectric layer
108a、112c‧‧‧第一控制閘極 108a, 112c‧‧‧ first control gate
110c‧‧‧第一堆疊結構 110c‧‧‧First stack structure
116‧‧‧第一矽化金屬層 116‧‧‧First metallized metal layer
120c‧‧‧字元線 120c‧‧‧ character line
124‧‧‧第四浮置閘極 124‧‧‧Fourth floating gate
126‧‧‧第四閘間介電層 126‧‧‧The fourth gate dielectric layer
128a‧‧‧第四控制閘極 128a‧‧‧fourth control gate
136‧‧‧第四矽化金屬層 136‧‧‧fourth metallization layer
200‧‧‧晶胞區(第一區) 200‧‧‧cell area (1st district)
202b、204b、206b‧‧‧介電層 202b, 204b, 206b‧‧‧ dielectric layer
300‧‧‧周邊電路區 300‧‧‧ peripheral circuit area
400‧‧‧高壓元件區(第二區) 400‧‧‧High-voltage component area (Second area)
402‧‧‧第二閘介電層 402‧‧‧Second gate dielectric layer
404a‧‧‧第二浮置閘極 404a‧‧‧second floating gate
406‧‧‧第二閘間介電層 406‧‧‧Second gate dielectric layer
408a、412c‧‧‧第二控制閘極 408a, 412c‧‧‧second control gate
410c‧‧‧第二堆疊結構 410c‧‧‧Second stacking structure
416‧‧‧第二矽化金屬層 416‧‧‧Second metallized metal layer
500‧‧‧低壓元件區(第三區) 500‧‧‧Low-voltage component area (third zone)
502‧‧‧第三閘介電層 502‧‧‧ Third Gate Dielectric Layer
504a‧‧‧第三浮置閘極 504a‧‧‧third floating gate
506‧‧‧第三閘間介電層 506‧‧‧ third gate dielectric layer
508a、512c‧‧‧第三控制閘極 508a, 512c‧‧‧ third control gate
510c‧‧‧第三堆疊結構 510c‧‧‧ third stack structure
516‧‧‧第三矽化金屬層 516‧‧‧ Third metallization layer
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