TWI614852B - 晶片封裝體及其製造方法 - Google Patents
晶片封裝體及其製造方法 Download PDFInfo
- Publication number
- TWI614852B TWI614852B TW105129059A TW105129059A TWI614852B TW I614852 B TWI614852 B TW I614852B TW 105129059 A TW105129059 A TW 105129059A TW 105129059 A TW105129059 A TW 105129059A TW I614852 B TWI614852 B TW I614852B
- Authority
- TW
- Taiwan
- Prior art keywords
- shielding layer
- cover plate
- chip package
- substrate
- layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 110
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 239
- 239000011241 protective layer Substances 0.000 claims description 49
- 125000006850 spacer group Chemical group 0.000 claims description 42
- 238000005520 cutting process Methods 0.000 claims description 14
- 230000000873 masking effect Effects 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 5
- 239000013598 vector Substances 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 26
- 239000000463 material Substances 0.000 description 17
- 230000003287 optical effect Effects 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 229910010272 inorganic material Inorganic materials 0.000 description 8
- 239000011147 inorganic material Substances 0.000 description 8
- 229910044991 metal oxide Inorganic materials 0.000 description 8
- 150000004706 metal oxides Chemical class 0.000 description 8
- 239000002861 polymer material Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 7
- 238000012858 packaging process Methods 0.000 description 7
- 229920000642 polymer Polymers 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 229920000620 organic polymer Polymers 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- KMWHNPPKABDZMJ-UHFFFAOYSA-N cyclobuten-1-ylbenzene Chemical compound C1CC(C=2C=CC=CC=2)=C1 KMWHNPPKABDZMJ-UHFFFAOYSA-N 0.000 description 5
- 229920000052 poly(p-xylylene) Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 239000011135 tin Substances 0.000 description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 3
- 150000001252 acrylic acid derivatives Chemical class 0.000 description 3
- 150000001412 amines Chemical class 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229920002098 polyfluorene Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 229920001940 conductive polymer Polymers 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000011133 lead Substances 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- OGZARXHEFNMNFQ-UHFFFAOYSA-N 1-butylcyclobutene Chemical compound CCCCC1=CCC1 OGZARXHEFNMNFQ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000417 polynaphthalene Polymers 0.000 description 1
- -1 polyparaphenylene Toluene Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/05611—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05669—Platinum [Pt] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Micromachines (AREA)
Abstract
本發明揭露一種晶片封裝體,包括一基底。基底具有一第一表面及與其相對的一第二表面,且基底內包括一感測區。一蓋板位於第一表面上且覆蓋感測區。一遮蔽層覆蓋蓋板的一側壁且朝第二表面延伸。遮蔽層具有鄰近蓋板的一內側表面及遠離蓋板的一外側表面,且外側表面朝第二表面延伸的長度小於內側表面朝第二表面延伸的長度而不小於蓋板的側壁的長度。本發明亦揭露一種晶片封裝體的製造方法。
Description
本發明係有關於一種晶片封裝技術,特別為有關於一種具有遮蔽層的晶片封裝體及其製造方法。
光電元件(例如,光感測元件)在擷取影像等應用中扮演著重要的角色,其已廣泛地應用於例如數位相機(digital camera)、數位錄影機(digital video recorder)、手機(mobile phone)等電子產品中,而晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將感測晶片保護於其中,使其免受外界環境污染外,還提供感測晶片內部電子元件與外界之電性連接通路。
隨著科技之演進,對於光感測元件之感測精準度的需求隨之提高。因此,有必要尋求一種新穎的晶片封裝體及其製造方法,其能夠提供具有高感測精準度之感光晶片封裝體。
本發明實施例係提供一種晶片封裝體,包括一基底。基底具有一第一表面及與其相對的一第二表面,且基底內包括一感測區。一蓋板位於第一表面上且覆蓋感測區。一遮蔽層覆蓋蓋板的一側壁且朝第二表面延伸。遮蔽層具有鄰近蓋板
的一內側表面及遠離蓋板的一外側表面,且外側表面朝第二表面延伸的長度小於內側表面朝第二表面延伸的長度而不小於蓋板的側壁的長度。
本發明實施例係提供一種晶片封裝體的製造方法,包括提供一基底。基底具有一第一表面及與其相對的一第二表面,且基底內包括一感測區。在第一表面上提供一蓋板,以覆蓋感測區。形成一遮蔽層,以覆蓋蓋板的一側壁,並朝第二表面延伸。遮蔽層具有鄰近蓋板的一內側表面及遠離蓋板的一外側表面,且外側表面朝第二表面延伸的長度小於內側表面朝第二表面延伸的長度而不小於側壁的長度。
100‧‧‧基底
100a‧‧‧第一表面
100b‧‧‧第二表面
110‧‧‧晶片區
120‧‧‧感測區
130、210‧‧‧絕緣層
140‧‧‧導電墊
150‧‧‧光學部件
160‧‧‧間隔層
170‧‧‧蓋板
180‧‧‧空腔
190‧‧‧開口
200‧‧‧開口
220‧‧‧重佈線層
230‧‧‧保護層
240‧‧‧孔洞
250‧‧‧開口
260‧‧‧黏著層
270‧‧‧承載基底
280‧‧‧導電結構
290‧‧‧溝槽
300‧‧‧遮蔽層
300’‧‧‧凸出部
300a‧‧‧內側表面
300a’‧‧‧延伸線
300b‧‧‧外側表面
300c‧‧‧下表面
300d‧‧‧上表面
310‧‧‧溝槽
400、500、600‧‧‧晶片封裝體
L1、L2、L3、L4‧‧‧長度
P‧‧‧局部
SC‧‧‧切割道
第1A至1I圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第2圖係繪示出根據本發明一實施例之晶片封裝體的局部剖面示意圖。
第3A及3B圖係繪示出根據本發明各種實施例之晶片封裝體的平面示意圖。
第4圖係繪示出根據本發明另一實施例之晶片封裝體的剖面示意圖。
第5A及5B圖係分別繪示出根據本發明又另一實施例之晶片封裝體的剖面示意圖及平面示意圖。
以下將詳細說明本發明實施例之製作與使用方
式。然應注意的是,本發明提供許多可供應用的發明概念,其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式,非用以限制本發明之範圍。此外,在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明,不代表所討論之不同實施例及/或結構之間具有任何關連性。再者,當述及一第一材料層位於一第二材料層上或之上時,包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此,例如在本發明之晶片封裝體的實施例中,其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components),例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System,MEMS)、生物辨識元件(biometric device)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package,WSP)製程對影像感測元件、發光二極體(light-emitting diodes,LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器(fingerprint recognition device)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導
體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後,再予以切割成獨立的封裝體,然而,在一特定實施例中,例如將已分離之半導體晶片重新分布在一承載晶圓上,再進行封裝製程,亦可稱之為晶圓級封裝製程。另外,上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓,以形成多層積體電路(multi-layer integrated circuit devices)或系統級封裝(System in Package,SIP)之晶片封裝體。
請參照第1I圖、第3A圖及第3B圖,第1I圖繪示出根據本發明一實施例之晶片封裝體400的剖面示意圖,第3A圖及第3B圖係繪示出根據本發明各種實施例之晶片封裝體的平面示意圖。晶片封裝體400包括一基底100、一蓋板170及一遮蔽層300。基底100具有一第一表面100a及與其相對的一第二表面100b。在一實施例中,基底100可為一矽基底或其他半導體基底。
在本實施例中,基底100內具有一感測區120。感測區120可鄰近於第一表面100a,且感測區120內包括一感測元件。在一實施例中,感測區120內包括感光元件或其他適合的光電元件。在其他實施例中,感測區120內可包括感測生物特徵的元件(例如,一指紋辨識元件)、感測環境特徵的元件(例如,一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的感測元件。
基底100的第一表面100a上具有一絕緣層130。一
般而言,絕緣層130可由層間介電層(interlayer dielectric,ILD)、金屬間介電層(inter-metal dielectric,IMD)及覆蓋之鈍化層(passivation)組成。為簡化圖式,此處僅繪示出單層絕緣層130。換句話說,晶片封裝體400包括一晶片/晶粒,而晶片/晶粒包括基底100及絕緣層130。在本實施例中,絕緣層130可包括無機材料,例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
在本實施例中,基底100的第一表面100a上的絕緣層130內具有一個或一個以上的導電墊140。在一實施例中,導電墊140可為單層導電層或具有多層之導電層結構。為簡化圖式,此處僅以單層導電層作為範例說明,並以絕緣層130內的兩個導電墊140作為範例說明。在本實施例中,絕緣層130內包括一個或一個以上的開口,露出對應的導電墊140。在一實施例中,感測區120內的感測元件可透過基底100內的內連線結構(未繪示)而與導電墊140電性連接。
在本實施例中,一光學部件150設置於絕緣層130上,且對應於感測區120。在本實施例中,光學部件150可為微透鏡陣列、濾光層、其組合或其他適合的光學部件。
蓋板170設置於基底100的第一表面100a上,以保護光學部件150。在本實施例中,蓋板170可包括玻璃、石英、透明高分子或其他適合的透明材料。再者,基底100與蓋板170之間具有一間隔層(或稱作圍堰(dam))160,覆蓋導電墊140而露出光學部件150。在本實施例中,間隔層160、蓋板170及絕緣層130在感測區120上共同圍繞出一空腔180,使得光學部件150
位於空腔180內。
在一實施例中,間隔層160大致上不吸收水氣。在一實施例中,間隔層160不具有黏性,因此可透過額外的黏著膠將蓋板170貼附於基底100上。在另一實施例中,間隔層160可具有黏性,因此可透過間隔層160將蓋板170貼附於基底100上,如此一來間隔層160可不與任何的黏著膠接觸,以確保間隔層160之位置不因黏著膠而移動。同時,由於不需使用黏著膠,可避免黏著膠溢流而污染光學部件150。
在本實施例中,間隔層160可包括環氧樹脂、無機材料(例如,氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如,聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene,BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))、光阻材料或其他適合的絕緣材料。
複數開口190貫穿基底100且延伸至絕緣層130內,進而自基底100的第二表面100b露出對應的導電墊140。在本實施例中,開口190鄰近於第一表面100a的口徑小於其鄰近於第二表面100b的口徑,因此開口190具有傾斜的側壁。再者,一開口200沿著基底100的側壁延伸且貫穿基底100。也就是說,相較於蓋板170,基底100具有內縮的邊緣側壁。在本實施例中,開口200具有傾斜的側壁,亦即基底100具有傾斜的邊緣側壁。
再者,複數開口190可沿著開口200間隔排列,如第3B圖所示,其中第3B圖係繪示出從基底100方向來看的晶片
封裝體的平面示意圖。在一實施例中,開口200可沿著基底100的全部側壁延伸而環繞開口190。在本實施例中,開口190的上視輪廓不同於開口200的上視輪廓,舉例來說,開口190具有圓形的上視輪廓,而開口200具有矩形的上視輪廓,如第3B圖所示。可以理解的是,開口190及開口200可具有其他形狀的上視輪廓及排列方式,而並不限定於此。
一絕緣層210設置於基底100的第二表面100b上,且順應性地延伸至開口190的側壁及開口200的側壁上,並露出導電墊140。在本實施例中,絕緣層210可包括環氧樹脂、無機材料(例如,氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如,聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
圖案化的重佈線層220設置於基底100的第二表面100b上,且順應性地延伸至開口190的側壁及底部,而未延伸至開口200內。重佈線層220可透過絕緣層210與基底100電性隔離,且可經由開口190直接電性接觸或間接電性連接露出的導電墊140。因此,開口190內的重佈線層220也稱為矽通孔電極(through silicon via,TSV7)。在其他實施例中,重佈線層220也可能以T型接觸(T-contact)的方式電性連接至對應的導電墊140。
在一實施例中,重佈線層220可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如,氧化銦錫或氧化銦鋅)或其他適合的導電材料。
一保護層230設置於基底100的第二表面100b上,且填入開口190及開口200,以覆蓋重佈線層220。在本實施例中,保護層230具有不平坦的表面,例如保護層230的表面具有對應於開口190及開口200的凹陷部。在一實施例中,保護層230可包括環氧樹脂、綠漆(solder mask)、無機材料(例如,氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如,聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
在本實施例中,保護層230未填滿開口190,使得一孔洞240形成於開口190內的重佈線層220與保護層230之間。由於保護層230部分填充於開口190而留下孔洞240,因此後續製程中遭遇熱循環(Thermal Cycle)時,孔洞240能夠作為保護層230與重佈線層220之間的緩衝,以降低保護層230與重佈線層220之間由於熱膨脹係數不匹配所引發不必要的應力,且防止外界溫度或壓力劇烈變化時保護層230會過度拉扯重佈線層220,進而可避免靠近導電墊結構的重佈線層220剝離甚至斷路的問題。在一實施例中,孔洞240與保護層230之間的界面具有拱形輪廓。
基底100的第二表面100b上的保護層230具有開口,露出重佈線層220的一部份。再者,複數導電結構280(例如,焊球、凸塊或導電柱)設置於保護層230的開口內,以與露出的重佈線層220電性連接。在一實施例中,導電結構280可包括錫、鉛、銅、金、鎳、或前述之組合。
在本實施例中,遮蔽層300具有遮光性。再者,遮
蔽層300由阻擋及/或吸收外界光線的膠材、光阻材料或其他適合的材料所構成。如第1I圖所示,遮蔽層300完全覆蓋蓋板170的側壁且朝基底100的第二表面100b延伸,進而覆蓋間隔層160的側壁。在本實施例中,遮蔽層300環繞蓋板170及空腔180而覆蓋蓋板170的所有側壁,如第3A圖所示,其中第3A圖係繪示出從蓋板170方向來看的晶片封裝體的平面示意圖。再者,遮蔽層300也環繞間隔層160而完全覆蓋間隔層160露出的側壁。
如第1I圖所示,遮蔽層300具有鄰近蓋板170的一內側表面300a及遠離蓋板170的一外側表面300b。內側表面300a及外側表面300b皆為平坦的表面。在一實施例中,內側表面300a及外側表面300b互相平行且垂直於第一表面100a及第二表面100b。在本實施例中,基底100的邊緣側壁(即,開口200的側壁)傾斜於遮蔽層300的內側表面300a及外側表面300b。再者,保護層230自第二表面100b延伸至基底100的邊緣側壁與內側表面300a之間。
在本實施例中,內側表面300a朝第二表面100b延伸的長度L1不小於蓋板170的側壁的長度L3,且外側表面300b朝第二表面100b延伸的長度L2也不小於長度L3。再者,長度L1不小於長度L3加上間隔層160的側壁的長度L4,且長度L2也不小於長度L3加上長度L4。在一實施例中,長度L2至少不小於長度L3加上長度L4。
在本實施例中,外側表面300b朝第二表面100b延伸的長度L2小於內側表面300a朝第二表面100b延伸的長度L1。在一實施例中,遮蔽層300沿著自內側表面300a朝外側表
面300b的方向漸進地變短(或變薄),也就是說,遮蔽層300鄰接內側表面300a及外側表面300b的一下表面300c具有曲面輪廓,且下表面300c的多個法向量互相不平行,如第2圖所示,其中第2圖係繪示出第1I圖中晶片封裝體400的局部P的剖面示意圖。
在本實施例中,遮蔽層300鄰接內側表面300a及外側表面300b的一上表面300d為平坦的。再者,遮蔽層300的上表面300d與蓋板170背向基底100的上表面共平面。
請參照第4圖,其繪示出本發明另一實施例之晶片封裝體500的剖面示意圖,其中相同於第1I圖中的部件係使用相同的標號並省略其說明。
第4圖中的晶片封裝體500之結構類似於第1I圖中的晶片封裝體400之結構,差異處在於晶片封裝體400中的遮蔽層300完全覆蓋間隔層160及蓋板170的側壁,而外側表面300b僅局部覆蓋絕緣層130的側壁,因此遮蔽層300露出保護層230的側壁。相較之下,晶片封裝體500中的遮蔽層300完全覆蓋絕緣層130、間隔層160及蓋板170的側壁,而外側表面300b僅局部覆蓋保護層230的側壁。在本實施例中,遮蔽層300大致上覆蓋晶片封裝體500的所有側壁。晶片封裝體500的平面示意圖大致上相同於晶片封裝體400的平面示意圖,如第3A及3B圖所示。
請參照第5A及5B圖,其分別繪示出本發明又另一實施例之晶片封裝體600的剖面示意圖及平面示意圖,其中相同於第1I圖中的部件係使用相同的標號並省略其說明。
第5A及5B圖中的晶片封裝體600之結構類似於第1I圖中的晶片封裝體400之結構,差異處在於晶片封裝體400中的遮蔽層300僅覆蓋絕緣層130、間隔層160及蓋板170的側壁,而露出保護層230的側壁。相較之下,晶片封裝體600中的遮蔽層300不僅完全覆蓋絕緣層130、間隔層160、蓋板170及保護層230的側壁,更延伸至基底100的第二表面100b上。如此一來,遮蔽層300充分地覆蓋晶片封裝體600的所有側壁。晶片封裝體600從蓋板170方向來看的平面示意圖大致上相同於晶片封裝體400從蓋板170方向來看的平面示意圖,如第3A圖所示。
在本實施例中,遮蔽層300包括一凸出部300’。凸出部300’自內側表面300a橫向地延伸於第二表面100b上及保護層230上,換句話說,凸出部300’自內側表面300a朝遠離外側表面300b的方向橫向地延伸。在一實施例中,一部分的保護層230夾設於凸出部300’與絕緣層210之間。在另一實施例中,一部分的保護層230夾設於凸出部300’與重佈線層220之間。
如第5B圖所示,凸出部300’自內側表面300a的延伸線300a’橫向地延伸且覆蓋保護層230,此延伸線300a’即等同於保護層230的邊緣。再者,凸出部300’可能局部覆蓋開口190。
在上述實施例中,晶片封裝體400、500及600皆包括前照式(front side illumination,FSI)感測裝置,然而在其他實施例中,晶片封裝體400、500及600亦可包括背照式(back side illumination,BSI)感測裝置。
以下配合第1A至1I圖說明本發明一實施例之晶片封裝體的製造方法,其中第1A至1I圖係繪示出根據本發明一實
施例之晶片封裝體400的製造方法的剖面示意圖。
請參照第1A圖,提供一基底100,其具有一第一表面100a及與其相對的一第二表面100b,且包括複數晶片區110。為簡化圖式,此處僅繪示出一完整的晶片區及與其相鄰的晶片區的一部分。在一實施例中,基底100可為一矽基底或其他半導體基底。在另一實施例中,基底100為一矽晶圓,以利於進行晶圓級封裝製程。
在本實施例中,每一晶片區110的基底100內具有一感測區120。感測區120可鄰近於第一表面100a,且感測區120內包括一感測元件。在一實施例中,感測區120內包括感光元件或其他適合的光電元件。在其他實施例中,感測區120內可包括感測生物特徵的元件(例如,一指紋辨識元件)、感測環境特徵的元件(例如,一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的感測元件。
基底100的第一表面100a上具有一絕緣層130。一般而言,絕緣層130可由層間介電層、金屬間介電層及覆蓋之鈍化層組成。為簡化圖式,此處僅繪示出單層絕緣層130。在本實施例中,絕緣層130可包括無機材料,例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
在本實施例中,每一晶片區110的絕緣層130內具有一個或一個以上的導電墊140。在一實施例中,導電墊140可為單層導電層或具有多層之導電層結構。為簡化圖式,此處僅以單層導電層作為範例說明,並以絕緣層130內的兩個導電墊
140作為範例說明。在本實施例中,每一晶片區110的絕緣層130內包括一個或一個以上的開口,露出對應的導電墊140。在一實施例中,感測區120內的感測元件可透過基底100內的內連線結構(未繪示)而與導電墊140電性連接。
在本實施例中,可依序進行半導體裝置的前段(front end)製程(例如,在基底100內製作感測區120)及後段(back end)製程(例如,在基底100上製作絕緣層130、內連線結構及導電墊140)來製作前述結構。換句話說,以下晶片封裝體的製造方法係用於對完成後段製程的基底進行後續的封裝製程。
在本實施例中,每一晶片區110內具有一光學部件150設置於基底100的第一表面100a上,且對應於感測區120。在本實施例中,光學部件150可為微透鏡陣列、濾光層、其組合或其他適合的光學部件。
接著,在一蓋板170上形成一間隔層160,透過間隔層160將蓋板170接合至基底100的第一表面100a上,且間隔層160在每一晶片區110內的基底100與蓋板170之間形成一空腔180,使得光學部件150位於空腔180內,並透過蓋板170保護空腔180內的光學部件150。在其他實施例中,可先在基底100上形成間隔層160,之後將蓋板170接合至基底100上。
在本實施例中,蓋板170可包括玻璃、石英、透明高分子或其他適合的透明材料。在本實施例中,可透過沉積製程(例如,塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)形成間隔層160。再者,間隔層160可包括
環氧樹脂、無機材料(例如,氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如,聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。或者,間隔層160可包括光阻材料,且可透過曝光及顯影製程而圖案化,以露出光學部件150。
請參照第1B圖,以蓋板170作為承載基板,對基底100的第二表面100b進行薄化製程(例如,蝕刻製程、銑削(milling)製程、磨削(grinding)製程或研磨(polishing)製程),以減少基底100的厚度。
接著,透過微影製程及蝕刻製程(例如,乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程),在每一晶片區110的基底100內同時形成複數開口190及開口200,開口190及開口200自基底100的第二表面100b露出絕緣層130。在其他實施例中,可分別透過刻痕(notching)製程以及微影及蝕刻製程形成開口200以及開口190。
在本實施例中,開口190對應於導電墊140而貫穿基底100,且開口190鄰近於第一表面100a的口徑小於其鄰近於第二表面100b的口徑,因此開口190具有傾斜的側壁,進而降低後續形成於開口190內的膜層的製程難度,並提高可靠度。舉例來說,由於開口190鄰近於第一表面100a的口徑小於其鄰近於第二表面100b的口徑,因此後續形成於開口190內的膜層(例如,絕緣層及重佈線層)能夠較輕易地沉積於開口190與絕緣層130之間的轉角,以避免影響電性連接路徑或產生漏電流的
問題。
開口200沿著相鄰晶片區110之間的切割道SC延伸且貫穿基底100,使得每一晶片區110內的基底100彼此分離。也就是說,每一晶片區110內的基底100具有內縮的邊緣側壁。在本實施例中,開口200具有傾斜的側壁,亦即每一晶片區110內的基底100具有傾斜的邊緣側壁。
在一實施例中,晶片區110內的複數開口190可沿著開口200間隔排列(如第3B圖所示),且開口190與開口200透過基底100的一部分(例如,側壁部分)互相間隔(如第1B圖所示)。在其他實施例中,開口190鄰近於第二表面100b的部分可與開口200鄰近於第二表面100b的部分彼此連通,使得基底100具有一側壁部分低於第二表面100b。換句話說,上述側壁部分的厚度小於基底100的厚度。當開口190與開口200彼此連通時,能夠防止應力累積於開口190與開口200之間的基底100,且可藉由開口200緩和及釋放應力,進而避免基底100的側壁部分出現破裂。
在一實施例中,開口200可沿著晶片區110延伸而環繞開口190。在本實施例中,開口190的上視輪廓不同於開口200的上視輪廓,舉例來說,開口190具有圓形的上視輪廓,而開口200具有矩形的上視輪廓,如第3B圖所示。可以理解的是,開口190及開口200可具有其他形狀的上視輪廓,而並不限定於此。
請參照第1C圖,可透過沉積製程(例如,塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製
程),在基底100的第二表面100b上形成一絕緣層210,絕緣層210順應性地沉積於開口190及開口200的側壁及底部上。在本實施例中,絕緣層210可包括環氧樹脂、無機材料(例如,氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如,聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
接著,可透過微影製程及蝕刻製程,去除開口190底部的絕緣層210及其下方的絕緣層130,使得開口190延伸至絕緣層130內而露出對應的導電墊140。再者,可透過微影製程及蝕刻製程,去除開口200底部的絕緣層210,以露出絕緣層130。
接著,可透過沉積製程(例如,塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程,在絕緣層210上形成圖案化的重佈線層220。重佈線層220順應性地延伸至開口190的側壁及底部,而未延伸至開口200內。在本實施例中,重佈線層220延伸至開口190與開口200之間的第二表面100b上。重佈線層220可透過絕緣層210與基底100電性隔離,且可經由開口190直接電性接觸或間接電性連接露出的導電墊140。因此,開口190內的重佈線層220也稱為矽通孔電極。在一實施例中,重佈線層220可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如,氧化銦錫或氧化銦鋅)或其他適合的導電材料。
請參照第1D圖,可透過沉積製程,在基底100的第
二表面100b上形成一保護層230,且填入開口190及開口200,以覆蓋重佈線層220。在一實施例中,保護層230可包括環氧樹脂、綠漆、無機材料(例如,氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如,聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
在本實施例中,保護層230填滿開口200,而僅部分填充開口190,使得一孔洞240形成於開口190內的重佈線層220與保護層230之間。在一實施例中,孔洞240與保護層230之間的界面具有拱形輪廓。在其他實施例中,保護層230亦可填滿開口190。
接著,可透過微影製程及蝕刻製程,在基底100的第二表面100b上的保護層230內形成複數開口250,以露出圖案化的重佈線層220的一部分。
請參照第1E圖,可透過暫時性的黏著層260將暫時性的一承載基底270接合至蓋板170背向基底100的上表面。在某些實施例中,也可在其他步驟中將承載基底270接合至蓋板170。在本實施例中,黏著層260包括黏著膠或其他適合的黏著材料。再者,承載基底270包括玻璃、矽或其他適合的支撐性基底材料。
接著,可透過電鍍製程、網版印刷製程或其他適合的製程,在保護層230的開口250內填入導電結構280(例如,焊球、凸塊或導電柱),以與露出的重佈線層220電性連接。在一實施例中,導電結構280可包括錫、鉛、銅、金、鎳、或前
述之組合。
請參照第1F圖,沿著切割道SC(等同於沿著開口200)切割保護層230、絕緣層130、間隔層160及蓋板170,以透過一溝槽290將每一晶片區110的保護層230、絕緣層130、間隔層160及蓋板170彼此分離。舉例來說,可使用切割刀具或雷射進行切割製程,其中使用雷射切割製程可以避免上下膜層發生位移。
在本實施例中,溝槽290位於相鄰的晶片區110之間。再者,溝槽290自保護層230的表面延伸而穿過保護層230,且進一步延伸直到完全穿過蓋板170,因而環繞基底100及蓋板170。在某些實施例中,溝槽290可更延伸至黏著層260內。在本實施例中,溝槽290具有平直的側壁。再者,溝槽290的口徑小於開口200的口徑,而溝槽290的深度大於開口200的深度,因此一部分的溝槽290位於開口200內。
在本實施例中,溝槽290至少未接觸基底100的邊緣側壁。在某些實施例中,絕緣層210及保護層230位於溝槽290與基底100的邊緣側壁之間。在其他實施例中,絕緣層210夾設於溝槽290與基底100的邊緣側壁之間。
請參照第1G圖,在溝槽290內填入一遮蔽層300。舉例來說,可使用點膠製程、塗佈製程(例如,旋轉塗佈製程或噴塗製程)、網版印刷製程或其他適合的製程來形成遮蔽層300。在本實施例中,遮蔽層300具有遮光性。再者,遮蔽層300由阻擋及/或吸收外界光線的膠材、光阻材料或其他適合的材料所構成。
在本實施例中,遮蔽層300局部填入溝槽290內,以覆蓋蓋板170的側壁。在某些實施例中,遮蔽層300至少完全覆蓋蓋板170的側壁。再者,遮蔽層300可朝第二表面100b延伸而進一步完全覆蓋間隔層160的側壁。在本實施例中,遮蔽層300露出的表面由於毛細現象而具有曲面輪廓,且該表面的多個法向量互相不平行。具體而言,遮蔽層300位於溝槽290之邊緣的一部份朝第二表面100b延伸的長度大於遮蔽層300位於溝槽290之中心的另一部份朝第二表面100b延伸的長度。再者,遮蔽層300沿著自溝槽290之一邊緣朝溝槽290之中心的方向漸進地變短(或變薄),且遮蔽層300更沿著自溝槽290之中心朝溝槽290之另一邊緣的方向漸進地變長(或變厚)。
在其他實施例中,遮蔽層300大致上填滿溝槽290,因而覆蓋絕緣層130、間隔層160、蓋板170及保護層230的側壁,如第4圖所示。遮蔽層300也可完全填滿溝槽290且延伸至保護層230上,此時遮蔽層300包括橫向地延伸的凸出部300’,如第5A圖所示。
請參照第1H圖,沿著切割道SC(等同於沿著溝槽290)切割遮蔽層300,且在遮蔽層300內形成一溝槽310,進而在承載基底270上形成複數獨立的晶片封裝體。舉例來說,可使用切割刀具或雷射進行切割製程。
在本實施例中,溝槽310位於相鄰的晶片區110之間,且自遮蔽層300露出的表面延伸直到完全穿過遮蔽層300。再者,溝槽310進一步延伸至黏著層260內,以確保複數晶片封裝體彼此分離。在本實施例中,溝槽310具有平直的側壁。再
者,溝槽310的口徑小於溝槽290的口徑,而溝槽310的深度小於溝槽290的深度,因此溝槽310完全位於溝槽290內。在某些實施例中,若遮蔽層300填滿溝槽290或進一步延伸至保護層230上,則溝槽310的深度可能等於或大於溝槽290的深度。在本實施例中,溝槽310至少未接觸間隔層160及蓋板170的側壁,以確保遮蔽層300能覆蓋間隔層160及蓋板170的側壁。
接著,將獨立的晶片封裝體與黏著層260及承載基底270分離,例如去除黏著層260的黏性而將晶片封裝體自承載基底270上取起,所形成的晶片封裝體400繪示於第1I圖中。
如第1I圖所示,在晶片封裝體400中,間隔層160及蓋板170的側壁由遮蔽層300所覆蓋。再者,遮蔽層300環繞蓋板170而覆蓋蓋板170的所有側壁(如第3A圖所示),且遮蔽層300也環繞間隔層160而完全覆蓋間隔層160露出的側壁。在本實施例中,由於溝槽290具有較高的深寬比,因此將遮蔽層300非順應性地填充於溝槽290內,即遮蔽層300填滿間隔層160及蓋板170內的溝槽290。如此一來,能夠有利於在遮蔽層300內形成溝槽310之後確保遮蔽層300完全覆蓋蓋板170的側壁,且使得遮蔽層300具有充足的厚度,以提升遮蔽層300的遮蔽效果。此外,遮蔽層300填滿間隔層160及蓋板170內的溝槽290亦能夠避免遮蔽層300內產生氣泡造成漏光(light leakage)的問題。
在某些實施例中,遮蔽層300還覆蓋保護層230的側壁(如第4圖所示),或更延伸至保護層230上(如第5A圖所示),此時遮蔽層300能夠加強阻隔水氣或侵蝕性物質進入晶片
封裝體(特別是感測區)內,進而增加晶片封裝體的可靠度及品質。
在本實施例中,溝槽310的形成使得遮蔽層300具有鄰近蓋板170的一內側表面300a及遠離蓋板170的外側表面300b,如第1I圖所示。內側表面300a及外側表面300b皆為平坦的表面。在一實施例中,內側表面300a及外側表面300b互相平行且垂直於第一表面100a及第二表面100b。在本實施例中,基底100的邊緣側壁傾斜於遮蔽層300的內側表面300a及外側表面300b。再者,保護層230自第二表面100b延伸至基底100的邊緣側壁與內側表面300a之間。
在本實施例中,內側表面300a朝第二表面100b延伸的長度L1不小於蓋板170的側壁的長度L3,且外側表面300b朝第二表面100b延伸的長度L2也不小於長度L3。再者,長度L1不小於長度L3加上間隔層160的側壁的長度L4,且長度L2也不小於長度L3加上長度L4。在一實施例中,長度L2至少不小於長度L3加上長度L4。
在本實施例中,外側表面300b朝第二表面100b延伸的長度L2小於內側表面300a朝第二表面100b延伸的長度L1。在一實施例中,遮蔽層300的長度沿著自內側表面300a朝外側表面300b的方向遞減,也就是說,遮蔽層300鄰接內側表面300a及外側表面300b的一下表面300c具有曲面輪廓,且下表面300c的多個法向量互相不平行,如第2圖所示。
在本實施例中,遮蔽層300鄰接內側表面300a及外側表面300b的一上表面300d為平坦的。再者,遮蔽層300的上
表面300d與蓋板170背向基底100的上表面共平面。
可以理解的是,雖然第1A至1I圖的實施例為具有前照式感測裝置之晶片封裝體的製造方法,然而關於晶片的外部電性連接路徑(例如,基底內的開口、重佈線層、保護層或其中的導電結構)及遮蔽層的製作方法亦可應用於背照式感測裝置的製程中。另外,第4圖及第5A圖所示之晶片封裝體的製造方法大致上類似於第1A至1I圖所述之晶片封裝體的製造方法。
根據本發明的上述實施例,晶片封裝體的側壁由具有遮光性的遮蔽層所覆蓋,遮蔽層可阻擋及/或吸收來自晶片封裝體外部的光線,尤其是來自晶片封裝體的橫向側面的光線,因此可避免晶片封裝體受到外界光線的影響,以有利於晶片封裝體的運作。如此一來,能夠有效解決由於側向漏光造成的眩光(petal flare)及光互擾雜訊(optical crosstalk)的問題。
具體而言,晶片封裝體內的可透光蓋板的側壁由遮蔽層所覆蓋,遮蔽層可阻隔來自蓋板的橫向側面的光線,進而提高感測晶片封裝體的感測精準度。再者,晶片封裝體內的間隔層的側壁也由遮蔽層所覆蓋,因此可避免水氣自間隔層進入晶片封裝體的內部,進而改善晶片封裝體的可靠度及品質。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可更動與組合上述各種實施例。
100‧‧‧基底
100a‧‧‧第一表面
100b‧‧‧第二表面
120‧‧‧感測區
130、210‧‧‧絕緣層
140‧‧‧導電墊
150‧‧‧光學部件
160‧‧‧間隔層
170‧‧‧蓋板
180‧‧‧空腔
190‧‧‧開口
200‧‧‧開口
220‧‧‧重佈線層
230‧‧‧保護層
240‧‧‧孔洞
280‧‧‧導電結構
300‧‧‧遮蔽層
300a‧‧‧內側表面
300b‧‧‧外側表面
300c‧‧‧下表面
300d‧‧‧上表面
400‧‧‧晶片封裝體
L1、L2、L3、L4‧‧‧長度
P‧‧‧局部
Claims (22)
- 一種晶片封裝體,包括:一基底,該基底具有一第一表面及與其相對的一第二表面,其中該基底內包括一感測區;一蓋板,該蓋板位於該第一表面上,且覆蓋該感測區;以及一遮蔽層,該遮蔽層覆蓋該蓋板的一側壁且朝該第二表面延伸,其中該遮蔽層具有鄰近該蓋板的一內側表面及遠離該蓋板的一外側表面,且該外側表面朝該第二表面延伸的長度小於該內側表面朝該第二表面延伸的長度而不小於該側壁的長度。
- 如申請專利範圍第1項所述之晶片封裝體,其中該遮蔽層沿著自該內側表面朝該外側表面的方向漸進地變短。
- 如申請專利範圍第1項所述之晶片封裝體,其中該遮蔽層具有鄰接該內側表面及該外側表面的一下表面,且該下表面具有曲面輪廓。
- 如申請專利範圍第1項所述之晶片封裝體,其中該遮蔽層具有鄰接該內側表面及該外側表面的一下表面,且該下表面的複數法向量互相不平行。
- 如申請專利範圍第1項所述之晶片封裝體,其中該遮蔽層具有鄰接該內側表面及該外側表面的一上表面,且該上表面為平坦的。
- 如申請專利範圍第1項所述之晶片封裝體,其中該遮蔽層具有鄰接該內側表面及該外側表面的一上表面,且該蓋板具 有背向該基底的一上表面,且其中該遮蔽層的該上表面與該蓋板的該上表面共平面。
- 如申請專利範圍第1項所述之晶片封裝體,其中該遮蔽層環繞該蓋板而覆蓋該蓋板的所有側壁。
- 如申請專利範圍第1項所述之晶片封裝體,更包括一間隔層,該間隔層位於該基底與該蓋板之間,其中該遮蔽層覆蓋該間隔層的一側壁。
- 如申請專利範圍第1項所述之晶片封裝體,其中該基底的一邊緣側壁傾斜於該遮蔽層的該內側表面。
- 如申請專利範圍第1項所述之晶片封裝體,更包括一保護層,該保護層位於該基底的該第二表面上,且延伸至該基底的一邊緣側壁與該遮蔽層的該內側表面之間。
- 如申請專利範圍第1項所述之晶片封裝體,其中該遮蔽層包括一凸出部,該凸出部自該內側表面橫向地延伸至該第二表面上。
- 一種晶片封裝體的製造方法,包括:提供一基底,其中該基底具有一第一表面及與其相對的一第二表面,且該基底內包括一感測區;在該第一表面上提供一蓋板,以覆蓋該感測區;以及形成一遮蔽層,以覆蓋該蓋板的一側壁,並朝該第二表面延伸,其中該遮蔽層具有鄰近該蓋板的一內側表面及遠離該蓋板的一外側表面,且該外側表面朝該第二表面延伸的長度小於該內側表面朝該第二表面延伸的長度而不小於該側壁的長度。
- 如申請專利範圍第12項所述之晶片封裝體的製造方法,更包括在形成該遮蔽層之前切割該蓋板,以形成一溝槽,其中該遮蔽層填入該溝槽,以覆蓋該蓋板的該側壁。
- 如申請專利範圍第13項所述之晶片封裝體的製造方法,更包括在切割該蓋板之前在該基底內形成一開口,且該開口貫穿該基底,其中沿著該開口切割該蓋板。
- 如申請專利範圍第14項所述之晶片封裝體的製造方法,更包括在形成該開口之後及在切割該蓋板之前,在該基底的該第二表面上形成一保護層,且該保護層延伸至該開口內,其中沿著該開口切割該保護層及該蓋板,使得該溝槽穿過該保護層,且其中在形成該遮蔽層之後該保護層位於該遮蔽層與該基底之間。
- 如申請專利範圍第13項所述之晶片封裝體的製造方法,更包括在切割該蓋板之前,在該蓋板背向該基底的一上表面上提供一承載基底。
- 如申請專利範圍第13項所述之晶片封裝體的製造方法,更包括在將該遮蔽層填入該溝槽之後,沿著該溝槽切割該遮蔽層,使得該遮蔽層具有鄰近該蓋板的該內側表面及遠離該蓋板的該外側表面。
- 如申請專利範圍第17項所述之晶片封裝體的製造方法,其中在切割該遮蔽層之前,該遮蔽層位於該溝槽之邊緣的一部份朝該第二表面延伸的長度大於該遮蔽層位於該溝槽之中心的另一部分朝該第二表面延伸的長度。
- 如申請專利範圍第17項所述之晶片封裝體的製造方法,其 中在切割該遮蔽層之前,該遮蔽層沿著自該溝槽之邊緣朝該溝槽之中心的方向漸進地變短。
- 如申請專利範圍第17項所述之晶片封裝體的製造方法,其中在切割該遮蔽層之前,該遮蔽層的一表面的複數法向量互相不平行。
- 如申請專利範圍第17項所述之晶片封裝體的製造方法,其中切割該遮蔽層的步驟包括使用切割刀具或雷射進行切割製程。
- 如申請專利範圍第12項所述之晶片封裝體的製造方法,其中形成該遮蔽層的步驟包括進行點膠製程、塗佈製程或網版印刷製程。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562216877P | 2015-09-10 | 2015-09-10 | |
US62/216,877 | 2015-09-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201711148A TW201711148A (zh) | 2017-03-16 |
TWI614852B true TWI614852B (zh) | 2018-02-11 |
Family
ID=58237162
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105129059A TWI614852B (zh) | 2015-09-10 | 2016-09-08 | 晶片封裝體及其製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10109663B2 (zh) |
CN (1) | CN106531641B (zh) |
TW (1) | TWI614852B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI600125B (zh) * | 2015-05-01 | 2017-09-21 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
TWI649856B (zh) * | 2016-05-13 | 2019-02-01 | 精材科技股份有限公司 | 晶片封裝體與其製造方法 |
KR102051373B1 (ko) | 2016-09-23 | 2019-12-04 | 삼성전자주식회사 | 팬-아웃 센서 패키지 및 이를 포함하는 카메라 모듈 |
TWI637469B (zh) * | 2017-06-12 | 2018-10-01 | 晶相光電股份有限公司 | 生物感測器封裝結構及其製造方法 |
US10373883B2 (en) * | 2017-10-26 | 2019-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
SE1751447A1 (en) * | 2017-11-24 | 2019-05-25 | Fingerprint Cards Ab | Cost-efficient fingerprint sensor component and manufacturing method |
US10950738B2 (en) | 2018-08-02 | 2021-03-16 | Xintec Inc. | Chip package and method for forming the same |
CN111863843B (zh) * | 2019-04-30 | 2024-03-01 | 同欣电子工业股份有限公司 | 感测器封装结构及其感测模块 |
CN110649055A (zh) * | 2019-09-27 | 2020-01-03 | 华天科技(昆山)电子有限公司 | 改善cis芯片炫光问题的晶圆级封装方法以及封装结构 |
CN110676244B (zh) | 2019-10-15 | 2020-06-16 | 杭州见闻录科技有限公司 | 一种芯片封装方法及封装结构 |
KR20220021238A (ko) * | 2020-08-13 | 2022-02-22 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
TWI824622B (zh) * | 2022-07-15 | 2023-12-01 | 力成科技股份有限公司 | 影像感測器封裝結構 |
US20240178164A1 (en) * | 2022-11-28 | 2024-05-30 | Texas Instruments Incorporated | Sensor package with low aspect ratio through silicon via |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6262479B1 (en) * | 1999-10-05 | 2001-07-17 | Pan Pacific Semiconductor Co., Ltd. | Semiconductor packaging structure |
TWI305036B (en) * | 2006-09-28 | 2009-01-01 | Siliconware Precision Industries Co Ltd | Sensor-type package structure and fabrication method thereof |
TWI344694B (en) * | 2007-08-06 | 2011-07-01 | Siliconware Precision Industries Co Ltd | Sensor-type package and method for fabricating the same |
US20130056844A1 (en) * | 2011-09-02 | 2013-03-07 | Vage Oganesian | Stepped Package For Image Sensor And Method Of Making Same |
TWI492337B (zh) * | 2011-12-19 | 2015-07-11 | Xintec Inc | 晶片封裝體及其形成方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8854526B2 (en) * | 2008-10-02 | 2014-10-07 | Visera Technologies Company Limited | Image sensor device with opaque coating |
US8952519B2 (en) * | 2010-01-13 | 2015-02-10 | Chia-Sheng Lin | Chip package and fabrication method thereof |
JP5422484B2 (ja) * | 2010-05-20 | 2014-02-19 | 株式会社東芝 | カメラモジュール |
US8431946B2 (en) * | 2010-05-26 | 2013-04-30 | Hsin-Chih CHIU | Chip package and method for forming the same |
US8536671B2 (en) | 2010-06-07 | 2013-09-17 | Tsang-Yu Liu | Chip package |
US8779452B2 (en) * | 2010-09-02 | 2014-07-15 | Tzu-Hsiang HUNG | Chip package |
US8604578B2 (en) * | 2010-10-25 | 2013-12-10 | Hsin-Chih CHIU | Chip package |
US8643070B2 (en) * | 2010-12-08 | 2014-02-04 | Shu-Ming Chang | Chip package and method for forming the same |
CN204632759U (zh) | 2015-03-25 | 2015-09-09 | 精材科技股份有限公司 | 一种芯片尺寸等级的感测芯片封装体 |
-
2016
- 2016-09-07 US US15/258,594 patent/US10109663B2/en active Active
- 2016-09-08 TW TW105129059A patent/TWI614852B/zh active
- 2016-09-08 CN CN201610809562.XA patent/CN106531641B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6262479B1 (en) * | 1999-10-05 | 2001-07-17 | Pan Pacific Semiconductor Co., Ltd. | Semiconductor packaging structure |
TWI305036B (en) * | 2006-09-28 | 2009-01-01 | Siliconware Precision Industries Co Ltd | Sensor-type package structure and fabrication method thereof |
TWI344694B (en) * | 2007-08-06 | 2011-07-01 | Siliconware Precision Industries Co Ltd | Sensor-type package and method for fabricating the same |
US20130056844A1 (en) * | 2011-09-02 | 2013-03-07 | Vage Oganesian | Stepped Package For Image Sensor And Method Of Making Same |
US20150200219A1 (en) * | 2011-09-02 | 2015-07-16 | Optiz, Inc. | Stepped Package For Image Sensor |
TWI492337B (zh) * | 2011-12-19 | 2015-07-11 | Xintec Inc | 晶片封裝體及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN106531641B (zh) | 2019-06-11 |
TW201711148A (zh) | 2017-03-16 |
US20170077158A1 (en) | 2017-03-16 |
US10109663B2 (en) | 2018-10-23 |
CN106531641A (zh) | 2017-03-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI614852B (zh) | 晶片封裝體及其製造方法 | |
TWI629759B (zh) | 晶片封裝體及其製造方法 | |
US10157811B2 (en) | Chip package and method for forming the same | |
TWI597813B (zh) | 晶片封裝體及其製造方法 | |
TWI646671B (zh) | 晶片封裝體及其製造方法 | |
US9997473B2 (en) | Chip package and method for forming the same | |
US10153237B2 (en) | Chip package and method for forming the same | |
US10157875B2 (en) | Chip package and method for forming the same | |
TWI642149B (zh) | 晶片封裝體及其製造方法 | |
TWI717846B (zh) | 晶片封裝體及其製造方法 | |
TW201624683A (zh) | 感光模組及其製造方法 | |
TWI550794B (zh) | 晶片封裝體及其製造方法 | |
US20170186712A1 (en) | Chip package and method for forming the same | |
TWI620284B (zh) | 晶片封裝體及其製造方法 | |
TWI741327B (zh) | 晶片封裝體及其製造方法 |