TWI613834B - Materials, fabrication equipment, and methods for stable, sensitive photodetectors and image sensors made therefrom - Google Patents

Materials, fabrication equipment, and methods for stable, sensitive photodetectors and image sensors made therefrom Download PDF

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TWI613834B
TWI613834B TW105111632A TW105111632A TWI613834B TW I613834 B TWI613834 B TW I613834B TW 105111632 A TW105111632 A TW 105111632A TW 105111632 A TW105111632 A TW 105111632A TW I613834 B TWI613834 B TW I613834B
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optically sensitive
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伊果Ｃ 伊凡諾夫
愛德華Ｈ 沙真特
田輝
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量宏科技股份有限公司
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Abstract

光學敏感性裝置包含一裝置，其包含一第一觸點及一第二觸點，每一者具有一功函數，及一位於第一觸點與該第二觸點間之光學敏感性材料。光學敏感性材料包含一p-型半導體，且光學敏感性材料具有一功函數。電路於第一觸點及第二電路間施用一偏電壓。光學敏感性材料具有一大於當偏電壓施用於第一觸點及第二觸點間從第一觸點至第二觸點之電子運行時間之電子壽命。第一觸點提供電子之注射及阻絕電洞之擷取。第一觸點與光學敏感性材料間之界面提供一少於1cm/s之表面重組速率。 The optically sensitive device includes a device that includes a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material includes a p-type semiconductor, and the optically sensitive material has a work function. The circuit applies a bias voltage between the first contact and the second circuit. The optically sensitive material has an electronic lifetime that is greater than the electronic operating time from the first contact to the second contact between the first contact and the second contact when the bias voltage is applied. The first contact provides injection of electrons and blocking of electrical holes. The interface between the first contact and the optically sensitive material provides a surface recombination rate of less than 1 cm / s.

Description

用於安定、敏感性光檢測器的材料、製造設備與方法及由其等製成之影像感應器 Materials, manufacturing equipment and methods for stable and sensitive photodetectors and image sensors made from them

本申請案係美國專利申請案第12/106,256號案(2008年4月18日申請)之部份繼續案。 This application is a partial continuation of US Patent Application No. 12 / 106,256 (applied on April 18, 2008).

本申請案請求美國專利申請案第61/082,473號案(2008年7月21日申請)之利益。 This application requests the benefit of US Patent Application No. 61 / 082,473 (filed on July 21, 2008).

本申請案請求美國專利申請案第61/154,751號案(2009年2月23日申請)之利益。 This application requests the benefit of US Patent Application No. 61 / 154,751 (applied on February 23, 2009).

本發明一般係有關於包含光學敏感性材料(諸如，奈米結晶及其它光學敏感性材料)之光學及電子裝置、系統及方法，及製造及使用此等裝置及系統之方法。 The present invention generally relates to optical and electronic devices, systems and methods that include optically sensitive materials, such as nanocrystals and other optically sensitive materials, and methods of making and using such devices and systems.

光電裝置(諸如，影像感應器及光伏打裝置)可包含光學敏感性材料。例示之影像感應器包含使用矽用於感應功能及讀取電子及多工功能之裝置。於某些影像感應器，光學敏感性矽光二極體及電子裝置可形成於一單矽晶圓上。其它例示之影像感應器可使用一不同材料，諸如，InGaAs(用於短波IR感應)，或非結晶之硒(用於x-射線感應)，用於感應(光子轉化成電子)功 能。例示之光伏打裝置包含太陽能電池，其使用結晶矽晶圓用於光子團化成電子。其它例示之光伏打裝置可使用一個別材料層(諸如，非結晶之矽或聚結晶矽)或一個別材料用於光子轉化成電子。但是，此等影像感應器及光伏打裝置已知具有數種限制。 Optoelectronic devices (such as image sensors and photovoltaic devices) may include optically sensitive materials. The exemplified image sensors include devices that use silicon for sensing functions and reading electronics and multiplexing functions. For some image sensors, optically sensitive silicon photodiodes and electronic devices can be formed on a single silicon wafer. Other exemplified image sensors can use a different material, such as InGaAs (for short-wave IR induction), or amorphous selenium (for x-ray induction), for sensing (photon to electron) work can. The illustrated photovoltaic device includes a solar cell, which uses a crystalline silicon wafer for photon grouping into electrons. Other exemplary photovoltaic devices may use a different material layer (such as amorphous silicon or polycrystalline silicon) or a different material for the conversion of photons into electrons. However, these image sensors and photovoltaic devices are known to have several limitations.

一種光學敏感性裝置，包含：一第一觸點及一第二觸點，每一者具有一功函數；一位於該第一觸點與該第二觸點間之光學敏感性材料，該光學敏感性材料包含一p-型半導體，且該光學敏感性材料具有一功函數；電路被建構以於該第一觸點與該第二觸點間施加一偏電壓；該光學敏感性材料之該功函數之數量係比該第一觸點之該功函數之數量大至少0.4eV，且亦比該第二觸點之該功函數之數量大至少0.4eV；該光學敏感性材料具有一比當該偏電壓施加於該第一觸點與該第二觸點時從該第一觸點至該第二觸點之電子運行時間更大之電子壽命；該第一觸點提供電子之注射及阻絕電洞之擷取；且該第一觸點與該光學敏感性材料之界面提供一少於1cm/s之表面重組速率。 An optically sensitive device includes: a first contact and a second contact, each of which has a work function; an optically sensitive material between the first contact and the second contact, the optical The sensitive material includes a p-type semiconductor, and the optically sensitive material has a work function; the circuit is constructed to apply a bias voltage between the first contact and the second contact; the optically sensitive material The number of work functions is at least 0.4 eV greater than the number of work functions of the first contact, and also at least 0.4 eV greater than the number of work functions of the second contact; the optically sensitive material has a When the bias voltage is applied to the first contact and the second contact, the electron running time from the first contact to the second contact is longer; the first contact provides electron injection and blocking Extraction of holes; and the interface between the first contact and the optically sensitive material provides a surface recombination rate of less than 1 cm / s.

本說明書中述及之每一專利案、專利申請案及/或公告案在此被全部併入以供參考至如同每一專利案、專利申請案及/或公告案被特別且個別指示被併入以供參考之程度。 Each patent case, patent application, and / or publication mentioned in this specification is hereby incorporated by reference for the same purpose as if each patent case, patent application, and / or publication were specifically and individually directed The degree of entry for reference.

1‧‧‧材料/材料金屬/金屬/層 1‧‧‧material / material metal / metal / layer

2,3‧‧‧材料/層/界面層 2,3‧‧‧material / layer / interface layer

4‧‧‧材料/層/光敏性層/吸光層 4‧‧‧material / layer / photosensitive layer / absorptive layer

5‧‧‧材料/層 5‧‧‧material / layer

6,7‧‧‧材料 6,7‧‧‧Material

8‧‧‧材料/界面材料/層 8‧‧‧material / interface material / layer

9‧‧‧材料/金屬/接觸層 9‧‧‧material / metal / contact layer

1220‧‧‧量子點 1220‧‧‧ Quantum dots

1221‧‧‧殼 1221‧‧‧Shell

第1圖顯示一實施例之一材料堆疊物。 Figure 1 shows a material stack of one embodiment.

第2圖顯示一實施例之於一像素之一部份上之材料堆疊物之截面圖。 Figure 2 shows a cross-sectional view of a material stack on a portion of a pixel according to an embodiment.

第3圖顯示一實施例之於一像素上之材料堆疊物之截面圖。 Figure 3 shows a cross-sectional view of a material stack on a pixel according to an embodiment.

一種光學敏感性裝置係於下描述。此裝置包含一第一觸點及一第二觸點，每一者具有一功函數，及一位於第一觸點及第二觸點間之光學敏感性材料。此光學敏感性材料包含一p-型半導體，且此光學敏感性材料具有一功函數。此裝置包含於第一觸點及第二觸點間施加一偏電壓之電路。此光學敏感性材料之功函數之數量係比第一觸點之功函數之數量大至少0.4eV，且亦比第二觸點之功函數之數量大至少0.4eV。光學敏感性材料具有一大於當此偏電壓施加於第一觸點及第二觸點之間時從第一觸點至第二觸點之電子轉移時間之電子壽命。第一觸點提供電子注射及阻絕電洞擷取。第一觸點與光學敏感性材料間之界面提供一少於1cm/s之一表面重組速率。 An optically sensitive device is described below. The device includes a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material includes a p-type semiconductor, and the optically sensitive material has a work function. The device includes a circuit for applying a bias voltage between the first contact and the second contact. The number of work functions of the optically sensitive material is at least 0.4 eV greater than the number of work functions of the first contact, and also at least 0.4 eV greater than the number of work functions of the second contact. The optically sensitive material has an electron lifetime greater than the electron transfer time from the first contact to the second contact when the bias voltage is applied between the first contact and the second contact. The first contact provides electron injection and blocking hole extraction. The interface between the first contact and the optically sensitive material provides a surface recombination rate of less than 1 cm / s.

一種光學敏感性裝置係於下描述。此裝置包含一第一觸點、一n-型半導體、一包含一p-型半導體之光學敏感性材料，及一第二觸點。此光學敏感性材料及第二觸點每一者具有一比4.5ev更淺之功函數。此裝置包含於第一觸點及第二觸點間施加一偏電壓之電路。光學敏感性材料具有一大於當此偏電壓施加於第一觸點及第二觸點之間時從第一觸點至第二觸點之電子轉移時間之電子壽命。第一觸點提供電子注射及阻絕電洞擷取。第一觸點與光學敏感性材料間之界面提供一少於1cm/s之一表面重組速率。 An optically sensitive device is described below. The device includes a first contact, an n-type semiconductor, an optically sensitive material including a p-type semiconductor, and a second contact. Each of the optically sensitive material and the second contact has a shallower work function than 4.5ev. The device includes a circuit for applying a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime greater than the electron transfer time from the first contact to the second contact when the bias voltage is applied between the first contact and the second contact. The first contact provides electron injection and blocking hole extraction. The interface between the first contact and the optically sensitive material provides a surface recombination rate of less than 1 cm / s.

一光檢測器係於下描述。此光檢測器包含一第一觸點及一第二觸點，每一者具有一功函數。此光檢測器包含一於第一觸點及第二觸點間之光學敏感性材料，光學敏感性材料包含一p-型半導體，且光學敏感性材料具有一功函數。此光檢測器包含於第一觸點及第二觸點間施加一偏電壓之電路。 此光學敏感性材料之功函數之數量係比第一觸點之功函數之數量大至少0.4eV，且亦比第二觸點之功函數之數量大至少0.4eV。此光檢測器包含於第一觸點及第二觸點間施加一偏電壓之電路。當此偏壓施加於第一觸點及第二觸點之間時，此光學敏感性材料提供至少0.8A/W之響應度。 A photodetector is described below. The photodetector includes a first contact and a second contact, each of which has a work function. The photodetector includes an optically sensitive material between the first contact and the second contact. The optically sensitive material includes a p-type semiconductor and the optically sensitive material has a work function. The photodetector includes a circuit that applies a bias voltage between the first contact and the second contact. The number of work functions of the optically sensitive material is at least 0.4 eV greater than the number of work functions of the first contact, and also at least 0.4 eV greater than the number of work functions of the second contact. The photodetector includes a circuit that applies a bias voltage between the first contact and the second contact. When the bias voltage is applied between the first contact and the second contact, the optically sensitive material provides a responsivity of at least 0.8 A / W.

於下列描述，數種特別詳情被引入以提供充份瞭解及能描述此等系統及方法之實施例。但是，熟習此項技藝者會瞭解此等實施例可於無此等特別詳情之一或多者或以其它組份、系統等而實施。於其它例子，已知之結構或操作未被顯示，或未被詳細描述，以避免混淆揭露實施例之觀點。 In the following description, several specific details are introduced to provide sufficient understanding and to describe embodiments of these systems and methods. However, those skilled in the art will understand that these embodiments can be implemented without one or more of these special details or with other components, systems, etc. In other examples, known structures or operations are not shown or described in detail in order to avoid confusing disclosure of the embodiments.

影像感應器併納光檢測器陣列。此等光檢測器感應光線，使其從一光學信號轉化成一電子信號。其下係數種特徵之說明，其等任一者或組合可於一實施例之光檢測器中發現；但是，此間之實施例並非僅限於此等特徵。 Image sensor and photodetector array. These light detectors sense light and convert it from an optical signal to an electronic signal. The description of the characteristics of the following coefficients, any one or a combination of these can be found in the photodetector of an embodiment; however, the embodiments here are not limited to these characteristics.

一實施例之光檢測器係可輕易地與和影像感應功能有關之其它電路(諸如，貯存電荷之電路、延遲至陣列周邊之信號量之電路、於類比領域操緃此等信號量之電路、將類比轉化成數位信號之電路，及將與影像有關之數據處理成數位領域之電路)積體化。 The photodetector of an embodiment can be easily related to other circuits related to the image sensing function (such as a circuit that stores charge, a circuit that delays the amount of signal around the array, a circuit that operates in the analog field, Circuits that convert analogies into digital signals, and circuits that process image-related data into the digital domain) are integrated.

一實施例之光檢測器提供對一波長帶譜或與低暗電路一起之感興趣之帶譜內之光線之最大敏感度。敏感度通當係使用於特定照明度之測量信號雜訊比(SNR)量化。當裝置之響應度、量子效率，或增益最大時，信號係最大。當電子信號內之隨機變動最小時，雜訊係最小，易遭受特定溫度之電流及電壓之自然變動所規定之限制。相關地，背景信號之雜訊及其它未受控制或難以預期之變化一般係於暗電路之數量最小時達最小。 The photodetector of an embodiment provides maximum sensitivity to light in a wavelength band spectrum or band spectrum of interest along with a low-dark circuit. Sensitivity is generally used to quantify the measured signal-to-noise ratio (SNR) of a specific illuminance. When the response, quantum efficiency, or gain of the device is maximum, the signal is the largest. When the random variation in the electronic signal is the smallest, the noise is the smallest, and it is susceptible to the limitation imposed by the natural variation of the current and voltage at a specific temperature. Relatedly, noise and other uncontrolled or unpredictable changes in the background signal are generally minimized when the number of dark circuits is minimum.

一實施例之光檢測器提供一與使用傳統處理方法形成之傳統光檢測器 相比較時相對較快之響應時間。諸如錄影成像及無快門靜像擷取之應用典型上需要信號量實質上完全改變以響應於少於100毫秒(10個畫格/秒)，或少於33毫秒(30個畫格/秒)，或甚至1毫秒(1/1000秒曝光一靜像)內之瞬變之光檢測器。 The photodetector of an embodiment provides a conventional photodetector formed using a conventional processing method The response time is relatively fast when compared. Applications such as video imaging and shutterless still image capture typically require a substantially complete change in signal volume in response to less than 100 milliseconds (10 frames / second), or less than 33 milliseconds (30 frames / second) , Or even a transient light detector within 1 millisecond (1/1000 second exposure to a still image).

一實施例之光檢測器提供以可藉由傳統電子電路方便地處理之方式檢測一廣範圍之光強度。此特徵係以提供高動態範圍而著稱。提供高動態範圍之一方法係壓縮為入射光刺激之函數之測得之電子響應。此壓縮可被稱為次線性，即，具減少之斜率之非線性，電信號係依入射強度而定。高動態範圍亦可藉由使用增益可被控制之光檢測器而促進，諸如，經由選擇已知用以產生一特定增益之電壓偏差。 The light detector of an embodiment provides a wide range of light intensities that can be conveniently handled by conventional electronic circuits. This feature is known for providing high dynamic range. One way to provide high dynamic range is to compress the measured electronic response as a function of incident light stimulation. This compression can be referred to as sub-linear, ie, non-linear with a reduced slope, and the electrical signal depends on the incident intensity. High dynamic range can also be promoted by using a photodetector whose gain can be controlled, such as by selecting a voltage deviation known to produce a specific gain.

一實施例之光檢測器可提供沿電磁輻射之不同光譜帶之識別。特別感興趣係x-射線、紫外線、可見光(包含藍、綠，及紅)、近紅外線，及短波紅外線帶譜。 The photodetector of an embodiment can provide identification along different spectral bands of electromagnetic radiation. Of particular interest are x-rays, ultraviolet light, visible light (including blue, green, and red), near infrared, and short-wave infrared band spectrum.

以下係描述於各種應用產生、積體化(例如，與電路)，及開拓上表面光檢測器或光檢測器陣列之方法及處理。 The following describes methods and processes for generating, integrating (for example, with circuits) in various applications, and developing upper surface photodetectors or photodetector arrays.

此間所述之光檢測器及光檢測器陣列可輕易地與影像感應器電路及系統之其它部份藉由諸如旋轉塗覆、噴灑塗覆、滴液塗覆、噴濺、物理蒸氣沈積、化學蒸氣沈積，及自行組合等之方法積體化。實施例包含以鈍化奈米顆粒表面之配位體替換較短之配位體，其於一旦膜形成時會提供適當電荷載體移動性。實施例包含溶液相替換，其能實現用以實現於一陣列上具有可接受之一致暗電流及光響應性之影像感應器所需平滑形態膜。 The photodetectors and photodetector arrays described here can be easily combined with other parts of the image sensor circuits and systems by methods such as spin coating, spray coating, drip coating, splashing, physical vapor deposition, and chemical Vapor deposition and self-assembly methods are integrated. Examples include replacing the shorter ligands with ligands that passivate the surface of the nanoparticles, which will provide proper charge carrier mobility once the film is formed. Embodiments include solution phase replacement, which can achieve the smooth morphology film required for image sensors with acceptable uniform dark current and light responsiveness on an array.

此間所述之光檢測器提供相對最大之敏感性。其藉由提供光導增益而 使信號達最大。光導增益之值範圍係1-50，造成，例如，於可見波長之範圍為從0.4A/W至20A/W之響應度。於實施例中，此間所述之光檢測器藉由熔合奈米結晶核使雜訊達最小，以確保於構成使電流經其流過之光學敏感性層之顆粒間實質上無雜訊降解之電通訊。於實施例中，此間所述之光檢測器藉由使活性層之淨摻雜達最小而使暗電流達最小，因此確保此等光學敏感性材料之暗載體密度及因而之暗導性達最小。於實施例中，此間所述之光檢測器藉由提供一電極與奈米結晶層電連接(其阻絕，例如，一種載體，可能包含平衡之主要載體)而使暗電流達最小。於實施例中，交聯分子被使用，其利用化學官能性移除造成p-型摻雜之氧化物、硫酸鹽，及/或氫氧化物。因此，於實施例中，一更為本質性或平坦之n-型光學敏感性層可被提供，導致降低之暗電流。於實施例中，量子點合成及/或加工處理及/或裝置封裝之許多步驟可於受控制之環境(諸如，Schlenk line或Glove Box)中實施；且光學敏感性層可使用實質上不可滲透之層(諸如，氧化物、氧氮化物，或聚合物，諸如，聚二甲苯，或環氧化物)封裝，以避免反應性氣體(諸如，氧或水)顯著滲透光學敏感性層。以此方式，諸如，增益、暗電流，及滯後之性質之組合可於一影像感應器之使用壽命保持。 The photodetectors described here provide relatively maximum sensitivity. By providing light guide gain Maximize the signal. The value range of the light guide gain is 1-50, resulting, for example, in the visible wavelength range from 0.4A / W to 20A / W responsivity. In the embodiment, the photodetector described here minimizes noise by fusing nanocrystalline nuclei to ensure that there is substantially no noise degradation between the particles constituting the optically sensitive layer through which current flows Telecommunications. In an embodiment, the photodetector described here minimizes the dark current by minimizing the net doping of the active layer, thus ensuring that the density of dark carriers and thus the dark conductivity of these optically sensitive materials is minimized . In an embodiment, the photodetector described here minimizes dark current by providing an electrode electrically connected to the nanocrystalline layer (which blocks, for example, a carrier, which may include a balanced primary carrier). In embodiments, cross-linked molecules are used that utilize chemical functionalities to remove oxides, sulfates, and / or hydroxides that cause p-type doping. Therefore, in an embodiment, a more essential or flat n-type optically sensitive layer may be provided, resulting in reduced dark current. In an embodiment, many steps of quantum dot synthesis and / or processing and / or device packaging may be implemented in a controlled environment (such as Schlenk line or Glove Box); and the optically sensitive layer may use substantially impermeable A layer (such as oxide, oxynitride, or polymer, such as polyxylene, or epoxide) is encapsulated to avoid significant penetration of the reactive gas (such as oxygen or water) into the optically sensitive layer. In this way, a combination of properties such as gain, dark current, and hysteresis can be maintained over the life of an image sensor.

此間所述之光檢測器提供可快達約sub-100毫秒，sub-30-毫秒，及sub-1-毫秒之時域響應。於實施例中，此可藉由提供與光學敏感性層有關之提供增益(及提供暫留)之捕捉態而達成，其可捉至少一種載體僅持續諸如100毫秒，30毫秒，或sub-1毫秒之有限時間。於實施例中，PbS奈米顆粒係以PbSO3(PbS之氧化物)裝點，顯示具有約20-30毫秒附近之捕捉態壽命，提供適於許多錄影成像應用之暫態響應。於實施例，光二極體係以膠體量子點 層為主替代地提供，具有可察覺出之不同功函數之二電觸點被用以接觸此活性層。於實施例中，暗電流可於無需施用可察覺之外部電壓偏差經由操作此等裝置而達最小，於實施例，交聯部份(諸如，苯二硫醇、二齒連接劑)可用以移除及/或鈍化可於此等材料中存在或發展之某些捕捉態。 The photodetectors described here provide time-domain responses that can be as fast as about sub-100 ms, sub-30-ms, and sub-1-ms. In an embodiment, this can be achieved by providing a capture state that provides gain (and provides persistence) related to the optically sensitive layer, which can capture at least one carrier lasting only such as 100 ms, 30 ms, or sub-1 Limited time in milliseconds. In an embodiment, PbS nanoparticles are decorated with PbSO3 (PbS oxide), which shows a capture state lifetime of around 20-30 milliseconds, providing a transient response suitable for many video imaging applications. In the example, the photodiode system uses colloidal quantum dots The layer is provided as an alternative to the main, and two electrical contacts with perceptible different work functions are used to contact the active layer. In the embodiment, the dark current can be minimized by operating these devices without applying a noticeable external voltage deviation. In the embodiment, the cross-linking part (such as benzenedithiol, bidentate linker) can be used to shift Exclusion and / or passivation can exist or develop in certain capture states in these materials.

此間所述之光檢測器藉由產生電信號(諸如，光電流)之次線性相依性而提供促進之動態範圍。於低至中強度之範圍，捕捉態可被填充，且於某一適度暫留(或捕捉態)壽命(諸如，30毫秒)後發生逃離。於更高強度，此等捕捉態被實質上填充，因此，電荷載體遭遇相對應於較低差異之增益之較短壽命(或暫留時間)。因此，此等裝置於低至中強度範圍展現實質上固定之增益，其後，於更高強度之增益係溫和下降。換言之，於低至中強度，光電流係約線性地依強度而定，但於更高強度，光電流展現對強度之次線性相似性。於實施例，其中光導增益係依施加至裝置之偏差而定之光檢測器被提供。此係因為增益係與載體壽命除以載體轉移時間呈比例而發生，且轉移時間係與施加之場呈反比例改變。於實施例，拓展增益對偏差之相似性以增加動態範圍之電路被發展。 The photodetectors described here provide an accelerated dynamic range by generating sub-linear dependencies of electrical signals (such as photocurrent). In the low-to-medium intensity range, the capture state can be filled, and escape occurs after a certain duration of retention (or capture state) life (such as 30 milliseconds). At higher intensities, these trapped states are substantially filled, therefore, the charge carrier encounters a shorter lifetime (or dwell time) corresponding to a gain with a lower difference. Therefore, these devices exhibit a substantially fixed gain in the low-to-medium intensity range, and thereafter, the gain at higher intensities decreases gently. In other words, at low to medium intensity, the photocurrent is approximately linearly dependent on intensity, but at higher intensity, the photocurrent exhibits a second linear similarity to intensity. In an embodiment, a light detector in which the light guide gain is dependent on the deviation applied to the device is provided. This occurs because the gain is proportional to the carrier life divided by the carrier transfer time, and the transfer time changes in inverse proportion to the applied field. In an embodiment, a circuit that expands the similarity of gain to deviation to increase the dynamic range is developed.

於實施例，此間所述之光檢測器可被輕易改變或”調整”，以提供對不同光譜帶之敏感性。調整於此係經由量子尺寸效應而提供，藉此，奈米顆粒直徑減少，於經由合成控制之情況，增加形成量子點之有效能隙。另一調整方法係經由選擇材料組成而提供，其中，使用具有較大總能隙之材料一般係促進具有於相對較高光子能量之響應度開始之光檢測器之實現。於實施例，具有不同吸收開始之光檢測器可被疊置以形成垂直像素，其中較接近光學信號來源之像素吸收且感應較高能帶之電磁輻射，而較遠離光學 信號來源之像素吸收及感應較低能帶。 In an embodiment, the photodetectors described herein can be easily changed or "adjusted" to provide sensitivity to different spectral bands. The adjustment is provided by the quantum size effect, whereby the diameter of the nanoparticles is reduced, and in the case of being controlled by synthesis, the effective energy gap for forming quantum dots is increased. Another adjustment method is provided by selecting a material composition, wherein the use of a material with a larger total energy gap generally facilitates the realization of a photodetector that starts with a relatively high photon energy response. In an embodiment, photodetectors with different start of absorption can be stacked to form vertical pixels, where pixels closer to the source of the optical signal absorb and sense higher energy band electromagnetic radiation and are further away from the optical The pixel of the signal source absorbs and senses a lower energy band.

第1圖顯示一實施例之材料堆疊物。材料堆疊物係與互補之金屬氧化物半導體(CMOS)矽電路(但不限於此)積體化。使用CMOS矽電路讀取藉由光導性光檢測器(包含上表面光檢測器，且包含以膠體量子點為主者，包含PbS)轉換之信號包含使上表面光導性材料與矽CMOS電子器件積體化。光導性光檢測器之結構及組成係於下詳細描述。 Figure 1 shows a material stack of an embodiment. The material stack is integrated with a complementary metal oxide semiconductor (CMOS) silicon circuit (but not limited to this). Using a CMOS silicon circuit to read the signal converted by a photoconductive photodetector (including the upper surface photodetector, and including colloidal quantum dots, including PbS) includes integrating the upper surface photoconductive material with the silicon CMOS electronic device Change. The structure and composition of the photoconductive photodetector are described in detail below.

第2圖顯示一實施例之於一部份像素上之材料堆疊物截面。此圖式於左手及右手側或區域描述參考第1圖之相同材料之堆疊物。於此裝置之側中部係於材料金屬'1'以材料'7'替代而併入一不連續性。材料'7'一般可為一絕緣物，諸如，SiO2或SiOxNy。第2圖之實施例可被稱為一側像素之一部份。於實施例，電流係經由材料'2'(界面)、材料'3'(黏著)，及材料'4'(光敏性層)於金屬'1'間大量流動。此間所述之材料堆疊物之不同部份或區域在此被稱為"材料"或"層"，但並不限於此。 Figure 2 shows a cross-section of a material stack on a portion of pixels according to an embodiment. This drawing describes the stack of the same material with reference to Figure 1 on the left or right hand side or area. In the middle of the side of the device, the material metal '1' is replaced with the material '7' to incorporate a discontinuity. The material '7' can generally be an insulator, such as SiO2 or SiOxNy. The embodiment of FIG. 2 may be referred to as a part of one side pixel. In the embodiment, the current flows through the metal '1' through the material '2' (interface), the material '3' (adhesion), and the material '4' (photosensitive layer). The different parts or regions of the material stack described herein are referred to herein as "materials" or "layers", but are not limited thereto.

第3圖顯示一實施例之於一像素上之材料堆疊物之截面。第3圖之實施例可被稱為一垂直像素之一部份。此圖式一般係以材料'1','2','3','4','5','6'描述如上參考第1圖所述之相同材料之堆疊物。一界面材料或層'8'係被併納或積體化於此裝置之頂部或區域上。材料'8'包含於此以材料’2’描述之材料組之一員或多員。一金屬或接觸層或材料’9’被併納或積體化於此裝置之一頂部或區域上。此金屬或接觸層’9’包含此間以材料’1’所述之材料組之一員或多員。實施例中，材料'9'包含一透明導性材料，諸如，氧化銦錫、氧化錫，或一薄(對可見光係實質上不吸收)金屬(諸如，TiN、Al、TaN)，或於上以材料’1’描述之其它金屬。 Figure 3 shows a cross-section of a material stack on a pixel according to an embodiment. The embodiment of FIG. 3 may be referred to as a part of a vertical pixel. This scheme is generally described by the materials '1', '2', '3', '4', '5', and '6' as described above with reference to Figure 1 of the same material stack. An interface material or layer '8' is incorporated or integrated on the top or area of the device. The material '8' is included in one or more of the material groups described here as material '2'. A metal or contact layer or material '9' is incorporated or integrated on a top or area of the device. This metal or contact layer '9' contains one or more members of the material group described here with the material '1'. In an embodiment, the material '9' includes a transparent conductive material, such as indium tin oxide, tin oxide, or a thin (substantially non-absorbable to visible light system) metal (such as TiN, Al, TaN), or above Other metals described by the material '1'.

材料"1"係一位於基材(未示出)上且可為一矽CMOS積體化電路之金屬，其係。於加工處理期間，其可為一200mm或300mm之晶圓，即，尚未被單一化形成晶粒之晶圓。材料"1"係指一存在於CMOS積體電路晶圓之頂面之金屬，其被呈現且用於與其後層之物理、化學及電連接。金屬可包含：TiN、TiO2、TixNy、Al、Au、Pt、Ni、Pd、ITO、Cu、Ru、TiSi、WSi2，及其等之組合。材料"1"係被稱為觸點，或電極，即此於此間將探討此觸點之行為係受可位於此金屬及材料"4"(光導性量子點層)間之薄層影響。 Material "1" is a metal on a substrate (not shown) and can be a silicon CMOS integrated circuit. During processing, it may be a 200 mm or 300 mm wafer, that is, a wafer that has not been singulated to form a die. The material "1" refers to a metal present on the top surface of a CMOS integrated circuit wafer, which is presented and used for physical, chemical, and electrical connections to its subsequent layers. The metal may include: TiN, TiO 2 , Ti x N y , Al, Au, Pt, Ni, Pd, ITO, Cu, Ru, TiSi, WSi 2 , and combinations thereof. The material "1" is called a contact, or electrode, that is, the behavior of this contact will be discussed here by the thin layer that can be located between the metal and the material "4" (photoconductive quantum dot layer).

金屬可被選擇以達一特殊功函數，且會影響歐姆或非歐姆(例如，肖特基(Schottky))接觸係關於其接近之層形成。例如，金屬被選擇以提供一淺功函數，諸如，一般係於-2.0eV與-4.5eV間之值，例如，位於-2.0eV與-4.2eV間之值。 The metal can be selected to achieve a particular work function, and will affect ohmic or non-ohmic (eg, Schottky) contact formation with respect to its proximity. For example, the metal is selected to provide a shallow work function, such as a value generally between -2.0 eV and -4.5 eV, for example, a value between -2.0 eV and -4.2 eV.

此金屬可達少於5nm之均方根值之表面粗糙度。 This metal can achieve a surface roughness of less than 5nm rms.

此金屬可以0.18微米或更小之臨界尺寸形成圖案。此金屬可被形成圖案以使，像素對像素，電極之間隔(諸如，一像素中間電極及一格柵之間)不會以多於1%之標準偏差改變。 The metal can be patterned with a critical dimension of 0.18 microns or less. The metal can be patterned so that the pixel-to-pixel, electrode spacing (such as between a pixel intermediate electrode and a grid) does not change with a standard deviation of more than 1%.

金屬可以一氧化物(諸如，自然氧化物-諸如，於TiN之情況係TiOxNy)終結。一般，此氧化物或於其上之其它材料(諸如，有機殘質、無機殘質，諸如，'聚合物'等)係具有一致且已知之組成物厚度。 The metal can be terminated with an oxide (such as a natural oxide-such as TiO x N y in the case of TiN). Generally, this oxide or other materials on it (such as organic residues, inorganic residues, such as 'polymer', etc.) have a uniform and known composition thickness.

此金屬係一導性材料，其中，構成此金屬之此材料主體可具有少於100微歐姆*公分之電阻。 The metal is a conductive material, wherein the body of the material constituting the metal may have a resistance of less than 100 microohms * cm.

金屬可被加工處理如此，於晶圓上，於欲形成光敏性像素之所有區域，係未以任何另外之氧化物或有機物或污染物封蓋。 The metal can be processed so that all areas on the wafer where the photosensitive pixels are to be formed are not covered with any additional oxides or organic substances or contaminants.

於形成界面層之前或之後，晶圓之上表面可包含金屬及絕緣材料(諸如，絕緣氧化物)之區域，如此，此表面上之特徵之峰谷距離係少於50nm。 Before or after the formation of the interface layer, the upper surface of the wafer may include regions of metal and insulating materials (such as insulating oxides). Thus, the peak-valley distance of the features on this surface is less than 50 nm.

於引入光敏性半導體層前，於1.1x1.1um或1.4x].4um矩形柵極中央之一像素電極間流動之漏電流於3V偏差需少於0.1fA。 Before introducing the photosensitive semiconductor layer, the leakage current flowing between one pixel electrode in the center of the 1.1x1.1um or 1.4x] .4um rectangular gate must be less than 0.1fA at 3V.

材料'1'上之層或材料形成一界面或界面層。形成此界面之層之每一者係依序於下詳細描述。 The layer or material on the material '1' forms an interface or interface layer. Each of the layers forming this interface is described in detail below in order.

材料"2"係此界面層之第一部份或第一片段，且包含位於金屬上之材料。材料'2'可包含此金屬之一純淨表面。此層之材料可包含氧化物，其包含經由曝置於水、氧，或其它氧化物質，因被曝置金屬存在而一般形成者；或可有計劃地形成，諸如，曝置於一受控制之環境及曝置於高溫，諸如，於快速熱處理。自然氧化物包含，例如，下列者：於TiN上之TiO2及TiOxNy；於Al上之Al2O3；於Au上之Au2O3；於Pt上之PtO或PtO2；於Ni上之Ni2O3；於W上之WO3；於Pd上之PdO；及於ITO上之富氧之ITO。此一自然氧化物可被移除，諸如，使用蝕刻，及以另一層替換。例如，諸如TiOxNy之自然氧化物可被蝕刻(使用諸如氬噴測之方法)，然後，一層可沈積於其上，諸如，一受控制之氧化物，諸如，TiO2、TiOx，或TiOxNy。自然氧化物及有計劃沈積之氧化物之厚度總和可為2與20nm之間。 The material "2" is the first part or the first segment of this interface layer and contains the material on the metal. Material '2' may contain one of the pure surfaces of this metal. The material of this layer may contain oxides, which include those that are generally formed by the presence of exposed metals through exposure to water, oxygen, or other oxidizing substances; or may be formed systematically, such as exposure to a controlled The environment and exposure to high temperatures, such as rapid heat treatment. Natural oxides include, for example, the following: TiO 2 and TiO x N y on TiN; Al 2 O 3 on Al; Au 2 O 3 on Au; PtO or PtO 2 on Pt; Ni 2 O 3 on Ni; WO 3 on W; PdO on Pd; and oxygen-rich ITO on ITO. This natural oxide can be removed, such as using etching, and replacing with another layer. For example, a natural oxide such as TiO x N y can be etched (using a method such as argon sputtering), and then a layer can be deposited thereon, such as a controlled oxide such as TiO 2 , TiO x , Or TiO x N y . The total thickness of the natural oxide and the planned oxide can be between 2 and 20 nm.

材料'2'之一部份可為一對大部份或所有波長之可見光係實質上透明之材料。其可具有大於2eV或大於2.5eV或大於3eV之能隙。其可為一大能隙之摻雜半導體。亦可經由化學計量而達成摻雜，諸如，於材料2之下或之上之其中x被改變TiOx之情況，以達成淨摻雜。x之值典型上係1.9，以達超過化學計量之TiO2之過量之Ti。x之值典型上可為2.1，以達成超過化學計量之 TiO2之過量之O。其中x<~2之TiOx可藉由使化學計量之TiO2曝置於一還原環境而達成。游離電子之密度可藉由增加起始化學計量之TiO2被減少之程度而增加(其相對應於較大之n-型摻雜)，即，相較於數值2係更大量地減少TiOx中之x。TiO2可與氮摻雜以改良其游離載體濃度、功函數，及電子親和性。TiO2或TiOx可與B、C、Co、Fe摻雜。其可為一稍微之n-型材料，諸如，具有10^10cm-3之平衡載體密度之輕度摻雜之TiOx。其可為適中摻雜之n-型材料，諸如，具有10^16cm-3之平衡載體密度之TiOx。其可為一更強烈摻雜之n-型材料，諸如，具有10^18或10^19cm-3之平衡載體密度之TiOx。其電子親和性係積極地實質上緊密地相對應於此等材料之功函數。其功函數可實質上緊密地相對應於此等材料之功函數。其離子化電勢可位於比吸光層(此間所述之材料’4’)之離子電勢更深之能量。其可經由退火方法、氣相處理，或化學處理(諸如，曝置於有機分子)處理，以便使電洞於與一相鄰之半導體層(諸如，吸光層(即下探討之’4’)接觸時達到低表面重組速率。 A part of the material '2' may be a pair of materials that are substantially transparent for most or all wavelengths of visible light. It may have an energy gap greater than 2eV or greater than 2.5eV or greater than 3eV. It can be a doped semiconductor with a large energy gap. Doping can also be achieved through stoichiometry, such as a situation where x is changed to TiO x below or above material 2 to achieve net doping. The value of x is typically 1.9, in excess of Ti that exceeds the stoichiometric amount of TiO 2 . The value of x can typically be 2.1 to achieve an excess of O in excess of stoichiometric TiO 2 . TiO x where x <~ 2 can be achieved by exposing stoichiometric TiO 2 to a reducing environment. The density of free electrons can be increased by increasing the degree to which the initial stoichiometric amount of TiO2 is reduced (which corresponds to a larger n-type doping), that is, the TiO x is reduced in a larger amount than the value 2 Of x. TiO 2 can be doped with nitrogen to improve its free carrier concentration, work function, and electron affinity. TiO 2 or TiO x can be doped with B, C, Co, Fe. Which may be of a slight n- type materials, such as having 10 ^ 10cm mild equilibrium carrier density of the doped -3 of TiO x. It can be a moderately doped n-type material, such as TiOx with a balanced carrier density of 10 ^ 16 cm-3. It may be a more strongly doped n-type material, such as TiOx with a balanced carrier density of 10 ^ 18 or 10 ^ 19 cm -3 . Its electron affinity is positively and closely corresponding to the work function of these materials. Its work function can correspond to the work function of these materials substantially closely. The ionization potential can be located at a deeper energy than the ion potential of the light-absorbing layer (material '4' described here). It can be processed by annealing, gas-phase treatment, or chemical treatment (such as exposure to organic molecules), so that the holes are adjacent to a semiconductor layer (such as the light-absorbing layer (ie, the '4' discussed below) A low surface recombination rate is reached on contact.

材料'3'亦可存在於此界面層，且包含一可置於或位於此界面層之第一部份之上之材料。材料'3'包含吸附之有機物(諸如，有機分子)，其係有計劃或偶然地或經由此等之組合而引入，其係位於金屬上，與此金屬直接接觸，或與金屬氧化物直接接觸。此等分子於此間被詳細探討。 The material '3' can also be present in this interface layer and include a material that can be placed on or above the first portion of this interface layer. Material '3' contains adsorbed organic matter (such as organic molecules), which was introduced intentionally or accidentally or through a combination of these, it is located on the metal, in direct contact with the metal, or in direct contact with the metal oxide . These molecules are discussed in detail here.

實施例包含材料'2'但缺乏材料'3'者。此等實施例包含選擇其間無需諸如藉由材料’3’提供者之黏著層之材料。舉例而言，若材料'2'併納諸如鈦之金屬(諸如，若材料'2'併納TiOx)，及若材料'4'併納一交聯劑(諸如，巰苯甲酸，其間巰苯甲酸上之一官能基結合TiOx)，則材料'4'及材料'2'間之黏著可於無明確包含材料'3'而提供。 The embodiment includes material '2' but lacks material '3'. These embodiments include selecting materials that do not require adhesive layers such as those provided by the material '3'. For example, if the material '2' contains a metal such as titanium (such as, if the material '2' contains TiO x ), and if the material '4' contains a cross-linking agent (such as, mercaptobenzoic acid, during which mercapto If a functional group on benzoic acid is combined with TiO x ), the adhesion between the material '4' and the material '2' can be provided without explicitly including the material '3'.

於實施例，材料’1’、材料'2'及材料’3’之所有者可存在。實施例包含其中肖特基接觸係無有計劃地引入一異質接面下經由金屬'1'與材料’4’而為之情況。實施例包含一其中TiN或TiOxNy形成金屬'1'，層'2'係金屬'1'之純淨終結而無大量形成自然氧化物，一黏著層(諸如，六甲基二矽氮烷)可於材料’3’提供之裝置。 In an embodiment, the owners of material '1', material '2' and material '3' may exist. Embodiments include the case where the Schottky contact is unintentionally introduced under a heterojunction via the metal '1' and the material '4'. The embodiment includes one in which TiN or TiO x N y forms the metal '1', the layer '2' is the pure end of the metal '1' without forming a large amount of natural oxide, and an adhesive layer (such as hexamethyldisilazane ) Device available in material '3'.

於實施例材料’1’、材料’2’及材料’3’之所有者可存在。實施例包含其中一與光敏性層'4'之異質接面係經由於材料’2’使用大能隙之氧化物而形成之情況。實施例包含一其中TiN或TiOxNy形成金屬'1'，層'2'包含一大能隙之半導體(諸如，TiOx(其可經結構性摻雜、雜質摻雜，或二者，或非任一者))，且一黏著層(諸如六甲基二矽氮烷)可於材料'3'提供之裝置。 In the embodiment, the owner of the material '1', the material '2' and the material '3' may exist. The embodiment includes a case where a heterojunction with the photosensitive layer '4' is formed by using a large energy gap oxide for the material '2'. Embodiments include a semiconductor in which TiN or TiO x N y forms a metal '1', and the layer '2' contains a semiconductor with a large energy gap (such as TiO x (which can be doped by structure, impurities, or both, Or neither)), and an adhesive layer (such as hexamethyldisilazane) can be provided in the material '3'.

於實施例，材料'1'可為鋁金屬，材料'2'可包含鋁之自然氧化物，且可包含一經摻雜之導性氧化物(諸如，經摻雜之Al2O3)，及/或可包含一大能隙之半導體，諸如，TiOx(其可經結構性摻雜、雜質摻雜，或二者，或非任一者)，且材料'3'可包含一黏著層(諸如，六甲基二矽氮烷)。 In an embodiment, the material '1' may be aluminum metal, the material '2' may include a natural oxide of aluminum, and may include a doped conductive oxide (such as doped Al2O3), and / or may A semiconductor containing a large energy gap, such as TiO x (which can be doped with structure, impurities, or both, or neither), and the material '3' can include an adhesive layer (such as six Methyldisilazane).

於實施例，材料'1'可包含鋁、鎵、銦、錫、鉛、鉍、鎂、鈣、鋅、鉬、鈦、釩、鑭、鉻、錳、鐵、鈷、鎳、銅、鋯、鈮、鈀、銀、鉿、鉭、鎢、銥、鉑、金。於實施例，用於標準CMOS之金屬(諸如，鋁、鎢、鉭、鈦、銅)係較佳。 In an embodiment, the material '1' may include aluminum, gallium, indium, tin, lead, bismuth, magnesium, calcium, zinc, molybdenum, titanium, vanadium, lanthanum, chromium, manganese, iron, cobalt, nickel, copper, zirconium, Niobium, palladium, silver, hafnium, tantalum, tungsten, iridium, platinum, gold. In the embodiment, metals used in standard CMOS (such as aluminum, tungsten, tantalum, titanium, and copper) are preferred.

於實施例，材料'2'可包含此金屬之表面，且可包含鋁、鎵、銦、錫、鉛、鉍、鎂、鈣、鋅、鉬、鈦、釩、鑭、鉻、錳、鐵、鈷、鎳、銅、鋯、鈮、鈀、銀、鉿、鉭、鎢、銥、鉑、金之氧化物、氮化物，或氧氮化物。於實施例，較佳係可使其包含用於標準CMOS之金屬(諸如，鋁、鎢、鉭、鈦、 銅)之氧化物、氮化物，或氧氮化物。 In an embodiment, the material '2' may include the surface of this metal, and may include aluminum, gallium, indium, tin, lead, bismuth, magnesium, calcium, zinc, molybdenum, titanium, vanadium, lanthanum, chromium, manganese, iron, Cobalt, nickel, copper, zirconium, niobium, palladium, silver, hafnium, tantalum, tungsten, iridium, platinum, gold oxide, nitride, or oxynitride. In an embodiment, it is preferable that it can contain metals for standard CMOS (such as aluminum, tungsten, tantalum, titanium, Copper) oxides, nitrides, or oxynitrides.

於實施例，材料'2'可包含多個次層。於實施例，其可包含一由諸如鋁、鎵、銦、錫、鉛、鉍、鎂、鈣、鋅、鉬、鈦、釩、鑭、鉻、錳、鐵、鈷、鎳、銅、鋯、鈮、鈀、銀、鉿、鉭、鎢、銥、鉑、金之金屬組成之次層。於實施例，較佳係此次層可包含用於標準CMOS之金屬(諸如，鋁、鎢、鉭、鈦、、銅)。於實施例，材料'2'可包含一由鋁、鎵、銦、錫、鉛、鉍、鎂、鈣、鋅、鉬、鈦、釩、鑭、鉻、錳、鐵、鈷、鎳、銅、鋯、鈮、鈀、銀、鉿、鉭、鎢、銥、鉑、金之氧化物、氮化物，或氧氮化物所組成之另外之次層。於實施例，較佳係此另外之次層包含用於標準CMOS之金屬(諸如，鋁、鎢、鉭、鈦、、銅)之氧化物、氮化物，或氧氮化物。 In an embodiment, the material '2' may include multiple sub-layers. In an embodiment, it may include a material such as aluminum, gallium, indium, tin, lead, bismuth, magnesium, calcium, zinc, molybdenum, titanium, vanadium, lanthanum, chromium, manganese, iron, cobalt, nickel, copper, zirconium, Sublayers composed of metals such as niobium, palladium, silver, hafnium, tantalum, tungsten, iridium, platinum, and gold. In an embodiment, it is preferable that the current layer may include metals for standard CMOS (such as aluminum, tungsten, tantalum, titanium, and copper). In an embodiment, the material '2' may include an aluminum, gallium, indium, tin, lead, bismuth, magnesium, calcium, zinc, molybdenum, titanium, vanadium, lanthanum, chromium, manganese, iron, cobalt, nickel, copper, Another sublayer of oxides, nitrides, or oxynitrides of zirconium, niobium, palladium, silver, hafnium, tantalum, tungsten, iridium, platinum, gold. In an embodiment, it is preferred that this additional sublayer contains oxides, nitrides, or oxynitrides of metals (such as aluminum, tungsten, tantalum, titanium, and copper) for standard CMOS.

稱為材料’4’之層係指一吸光層，其包含奈米結晶或石英點。量子點(QD)(第1圖中以'1220'描述)可為一奈米結構，例如，一半導體奈米結構，其限制所有三個空間方向之導電帶電子、價電帶電洞，或激子(導電帶電子及價電帶電洞之結合對)。此限制可能係由於靜電勢(例如，藉由外部電極、摻雜、應變、雜質而產生)，不同半導體材料(例如，核殼奈米結晶系統，其係併納於第1圖之'1221'內)或一半導體與另一材料(例如，藉由有機配位子；或藉由介電物質(諸如，氧化物(諸如，PbO)，硫化物(諸如，PbSO3)，硫酸鹽(諸如，PbSO4)，或SiO2)裝點之半導體，其係併納於第1圖中之'1221’內)間之一界面之存在，併納於第1圖之’1221’內之一半導體表面之存在，或此等之一或多數之組合。一量子點於其吸收光譜展現一理想化零尺寸系統之個別量化能譜之作用。相對應於此個別能譜之波函數係於量子點內被實質上空間局部化，但於此材料之晶格之許多期間擴展。於一例示實施例，QD可具 有一半導體或化合物半導體材料之核(諸如，PbS)。配位子可附接至一些或全部之外表面，或於某些實施例可被移除。於某些實施例，相鄰QD之核可熔合在一起形成具奈米規格特徵之奈米材料之連續膜。於其它實施例，核可藉由連接劑分子彼此連接。於某些實施例，，捕捉態可於奈米材料之外表面上發現。於某些實施例，，核可為PbS且捕捉態可藉由於核外表面上形成之諸如PbSO3之氧化物形成。 The layer called material '4' refers to a light absorbing layer, which contains nanocrystals or quartz dots. Quantum dots (QD) (described as '1220' in Figure 1) can be a nanostructure, for example, a semiconductor nanostructure, which limits the conduction band electrons, valence band holes, or excitation in all three spatial directions Child (combined pair of conductive band electrons and valence band holes). This limitation may be due to electrostatic potential (e.g., generated by external electrodes, doping, strain, impurities), different semiconductor materials (e.g., core-shell nanocrystal system, which is included in '1221' in Figure 1 Internal) or a semiconductor and another material (for example, by organic ligands; or by dielectric substances (such as oxides (such as PbO), sulfides (such as PbSO 3 ), sulfates (such as, PbSO4), or SiO2) dotted semiconductor, which is included in the presence of an interface between '1221' in Figure 1 and contained in the presence of a semiconductor surface in '1221' in Figure 1, Or a combination of one or more of these. A quantum dot exhibits the role of an individualized quantitative energy spectrum of an idealized zero-size system in its absorption spectrum. The wave function corresponding to this individual energy spectrum is substantially spatially localized within the quantum dots, but expands during many periods of the lattice of this material. In an exemplary embodiment, the QD may have a core of semiconductor or compound semiconductor material (such as PbS). The ligand may be attached to some or all of the outer surface, or in some embodiments may be removed. In some embodiments, the cores of adjacent QDs may be fused together to form a continuous film of nanomaterials with nanometer-scale features. In other embodiments, the cores can be linked to each other by linker molecules. In some embodiments, the captured state can be found on the outer surface of the nanomaterial. In some embodiments, the core may be PbS and the trapped state may be formed by an oxide such as PbSO 3 formed on the outer surface of the core.

一QD層可具有熔融QD核之一連續網絡，其具有具與核者不同組成，例如，氧化核材料(諸如，PbSO3)，或不同種類之半導體之外表面。此膜之個別QD核係緻密接觸，但持續展現個別量子點之許多性質。例如，一單獨(未經熔融)之量子點具有一自與其尺寸(例如，1-10nm)有關之量子效應產生之充份特徵化之激子吸收波長峰值。此膜內之熔融QD之激子吸收波長峰值未顯著地自熔融前存在之中央吸收波長位移。例如，熔融時中央吸收波長可以約10%或更少而改變。因此，膜內之QD保持其量子效應，即使其可能為一巨觀結構之一積分部份。於某些實施例，QD核係藉由如下進一步描述之連接劑分子連接。此使電沆能比經由未經連接未續熔融之QD者更輕易地流動。但是，使用連接劑分子形成QD之一連續膜而替代使此等核熔融會降低某些光導體及影像感應器實施例之暗電流。 A QD layer may have a continuous network of fused QD cores with a different composition from the core, for example, oxidized core materials (such as PbSO 3 ), or different types of semiconductor outer surfaces. The individual QD cores of this film are in close contact, but continue to exhibit many properties of individual quantum dots. For example, a single (unmelted) quantum dot has a fully characterized exciton absorption wavelength peak resulting from quantum effects related to its size (eg, 1-10 nm). The exciton absorption wavelength peak of the molten QD in this film does not significantly shift from the central absorption wavelength existing before melting. For example, the central absorption wavelength can be changed by about 10% or less when melting. Therefore, the QD in the film maintains its quantum effect, even though it may be an integral part of a macroscopic structure. In some embodiments, the QD cores are linked by linker molecules as described further below. This allows electric flow to flow more easily than QDs that do not continue to melt through connection. However, the use of linker molecules to form a continuous film of QD instead of melting these nuclei reduces the dark current of certain photoconductor and image sensor embodiments.

於某些實施例，QD層係例外地具輻射敏感性。此敏感性對於低輻射成像應用係特別有用。同時，此裝置之增益可被動態調整以使QDPC飽和，即，另外之光子持續提供可藉由讀出電子電路識別之另外有用資訊。增益之調整可藉由改變於一特定裝置(例如，一像素)之電壓偏差及因而之形成電場而方便地達成。QD裝置之一些實施例包含一QD層及一經專門設計或預先製造 之它子讀出積體電路。然後，QD層係直接形成於此經專門設計或預先製造之電子讀出積體電路上。QD層可另外被形成圖案以使其形成個別之島狀物。於某些實施例，QD層疊置於電路上，其持績重疊及接觸此電路之至少一些特徵。於某些實施例，若QD層疊置此電路之三維特徵，QD層可順應此等特徵。換言之，於QD層與下面之電子讀出積體電路間存在一實質上緊鄰之界面。此電路之一或多個電極接觸此QD層，且能續電保護有關於QD層之資訊，例如，與QD層上之與輻射量有關之電子信號，至一讀出電路。QD層可以連續方式提供以覆蓋整個底下之電路(諸如，一讀出電路)，或形成圖案。若QD層係以連續方式提供，填充因子可達約100%，形成圖案時，此填充因子被降低，但對於某些使用矽光二極體之例示CMOS感應器仍可遠大於典型之35%。於許多實施例，QD光學裝置係使用可用於一般用以製造傳統CMOS裝置之設備之技術輕易製造。例如，一QD層可使用旋轉塗覆(其係一種標準CMOS方法)以溶液塗覆於一預先製造之電子讀出電路上，及選擇性地以其它之CMOS可相容之技術進一步處理，以提供用於此裝置之最終QD層。因為QD層無需以奇特或困難之技術製造，而可替代地使用標準CMOS方法製造，QD光學裝置可以高體積製造，且相較於現今之CMOS處理步驟於資本成本(非材料上)無顯著增加。 In some embodiments, the QD layer is exceptionally radiation sensitive. This sensitivity is particularly useful for low radiation imaging applications. At the same time, the gain of this device can be dynamically adjusted to saturate the QDPC, that is, additional photons continue to provide additional useful information that can be identified by reading out electronic circuits. The adjustment of the gain can be conveniently achieved by changing the voltage deviation of a specific device (for example, a pixel) and thus forming an electric field. Some embodiments of QD devices include a QD layer and a specially designed or pre-manufactured The other reads the integrated circuit. Then, the QD layer is directly formed on this specially designed or pre-manufactured electronic readout integrated circuit. The QD layer can be additionally patterned to form individual islands. In some embodiments, the QD stack is placed on the circuit, and its performance overlaps and contacts at least some features of the circuit. In some embodiments, if the QD stacks the three-dimensional features of the circuit, the QD layer can conform to these features. In other words, there is a substantially close interface between the QD layer and the underlying electronic readout integrated circuit. One or more electrodes of this circuit are in contact with this QD layer, and can continue to protect information about the QD layer, for example, electronic signals related to the amount of radiation on the QD layer, to a readout circuit. The QD layer may be provided in a continuous manner to cover the entire underlying circuit (such as a readout circuit), or patterned. If the QD layer is provided in a continuous manner, the fill factor can be up to about 100%. This fill factor is reduced when forming a pattern, but for some exemplary CMOS sensors using silicon photodiodes, it can still be much larger than the typical 35%. In many embodiments, QD optical devices are easily manufactured using techniques that can be used in equipment commonly used to manufacture traditional CMOS devices. For example, a QD layer can be applied to a pre-fabricated electronic readout circuit using spin coating (which is a standard CMOS method), and optionally further processed with other CMOS compatible technologies to Provide the final QD layer for this device. Because the QD layer does not need to be manufactured with strange or difficult technology, but can be manufactured using standard CMOS methods, the QD optical device can be manufactured with high volume, and there is no significant increase in capital cost (non-material) compared to the current CMOS processing steps .

QD材料於約可見光之端緣(諸如，約650nm)具一吸收截斷。QD材料可於較長波長具有一吸收截斷，以確保於整個可見光之高吸收率，諸如，當於700-900nm範圍之吸收截斷。 The QD material has an absorption cutoff at the edge of about visible light (such as about 650 nm). QD materials can have an absorption cutoff at longer wavelengths to ensure high absorption of the entire visible light, such as when the absorption cutoff is in the 700-900 nm range.

QD膜可使用傳統之旋轉方法、噴墨印刷方法、Langmuir-Blodgett膜沈積、電動噴灑，或奈米壓印沈積。.QD膜可使用使QD溶液以30RPM分配於 一晶圓上及其後以三步驟旋轉方法而沈積。 The QD film can be deposited using conventional rotary methods, inkjet printing methods, Langmuir-Blodgett film deposition, electric spray, or nanoimprint. .QD membrane can be used to dispense QD solution at 30RPM in It is deposited on and after a wafer in a three-step rotation method.

QD溶液吸收波峰之光譜位置可被特定而位於740nm,+/- 10nm。接近740nm之QD吸收波峰及稍向此波峰之藍色之波谷之吸收率比值可被特定為1.2。 The spectral position of the absorption peak of the QD solution can be specifically located at 740nm, +/- 10nm. The absorption ratio of the QD absorption peak near 740 nm and the blue valley slightly toward this peak can be specified as 1.2.

量子點層之厚度可被特定為300nm.+/- 50nm。量子點層層之厚度可被選擇以確保於400-640nm之光譜範圍，入射於此膜上之所有光線之大於90%被吸收。量子點膜之粗糙度(均方根值)可被特定為少於5nm。 The thickness of the quantum dot layer may be specified as 300nm. +/- 50nm. The thickness of the quantum dot layer can be selected to ensure that in the 400-640nm spectral range, more than 90% of all light incident on the film is absorbed. The roughness (root mean square value) of the quantum dot film can be specified to be less than 5 nm.

於適當偏差(諸如，3V偏差)下之1.1x1.1um像素之暗電流可為少於0.5fA。增益於1.1x1.1um之像素可大於10。 The dark current of a 1.1x1.1um pixel under an appropriate deviation (such as a 3V deviation) may be less than 0.5fA. Pixels with a gain of 1.1x1.1um can be greater than 10.

鹼金屬雜質可以低於5E17cm-3濃度存在於量子點膜。尺寸大於0.16微米之缺陷於一200mm晶圓可少於20。流動載體之移動性可超過1E-5cm2/Vs。此膜內之奈米結晶之裝載分率可超過30體積%。 Alkali metal impurities can be present in the quantum dot film at a concentration lower than 5E17cm-3. Defects larger than 0.16 microns can be less than 20 on a 200mm wafer. The mobility of the flow carrier can exceed 1E-5cm 2 / Vs. The loading fraction of nanocrystals in this film can exceed 30% by volume.

併納於材料’4’內係諸如PbO、PbSO4、PbSO3、聚硫酸鹽之化學物種；且其亦可包含諸如O2、N2、Ar、H2、CO2、H2O，及H2S之物理吸附物種。 Contained in the material '4' are chemical species such as PbO, PbSO 4 , PbSO 3 , and polysulfate; and they may also contain such as O 2 , N 2 , Ar, H 2 , CO 2 , H 2 O, and Physically adsorbed species of H 2 S.

併納於材料’4’內可為與至少一奈米顆粒，或奈米結晶，或量子點之表面結合之分子。此等可包含以硫醇終結之配位體，諸如，苯硫醇、乙烷硫醇；以羧酸酯終結之分子，諸如，油酸及甲酸；以胺終結之配位體，諸如，吡啶、丁胺、辛胺。其亦可包含二齒交聯劑，諸如，苯二硫醇、乙烷二硫醇，及丁烷二硫醇。其亦可包含包含(1)一主幹；(2)與奈米顆粒表面結合之特定側基團及/或端基團，包含硫醇、胺、羧酸酯；及(3)其它官能基，諸如，賦予於極性、非極性，及部份極性之溶劑內之可溶性者之多齒分子。 The material contained in the material '4' may be a molecule bonded to the surface of at least one nanoparticle, or nanocrystal, or quantum dot. These may include thiol terminated ligands such as benzenethiol and ethanethiol; carboxylate terminated molecules such as oleic acid and formic acid; amine terminated ligands such as pyridine , Butylamine, octylamine. It may also contain bidentate crosslinking agents, such as benzene dithiol, ethane dithiol, and butane dithiol. It may also contain (1) a backbone; (2) specific side groups and / or end groups bonded to the surface of the nanoparticles, including thiols, amines, carboxylates; and (3) other functional groups, Such as multi-dentate molecules conferring solubility in polar, non-polar, and partially polar solvents.

材料’5’可包含於’4’之頂部上之層，其可提供底下材料之鈍化，包含使 物種於此材料堆疊物之層’1’-‘4’及此材料堆疊物之外側間之移動程度達最小。此層亦可促進與疊置層(諸如，封裝層)之良好物理性黏著。 The material '5' can be contained on the top layer of '4', which can provide passivation of the underlying material, including Species move between layers '1'-'4' of this material stack and the outside of this material stack to a minimum. This layer can also promote good physical adhesion to the overlay layer (such as the encapsulation layer).

材料'6'係指可被包含於材料堆疊物之頂部上且可用以使物種於此材料堆疊物之層’1’-‘4’及此材料堆疊物之外側間之移動程度達最小之一層或多層。於一平面電池結構，量子點膜層可使用低溫(少於100℃)之電漿加強化學蒸氣沈積(PECVD)SiO2、SiN，或SiOCN之方法提供適於與彩色濾波陣列(CFA)進一步積體化之光學透明性膜而封裝以抗氧及水份之擴散。此膜可被特定而具有200nm+/-10nm之厚度。其可被特定而具有少於5nm rms之表面粗糙度。光學透射率可超過99%。黏著可對底下之層提供。一實施例於一200mm晶圓上具有少於20個大於0.1um顆粒缺陷。一實施例可於一200mm晶圓上具有少於20個大於0.1um針孔。 Material '6' refers to a layer that can be included on top of the material stack and can be used to minimize the movement of species between layers '1'-'4' of the material stack and the outer sides of the material stack Or multiple layers. In a planar cell structure, the quantum dot film layer can use low temperature (less than 100 ℃) plasma enhanced chemical vapor deposition (PECVD) SiO 2 , SiN, or SiOCN method to provide suitable for further integration with color filter array (CFA) The integrated optically transparent film is encapsulated to prevent the diffusion of oxygen and moisture. This film can be specified to have a thickness of 200 nm +/- 10 nm. It can be specified to have a surface roughness of less than 5nm rms. Optical transmittance can exceed 99%. Adhesion can be provided to the underlying layer. An embodiment has less than 20 particle defects larger than 0.1um on a 200mm wafer. An embodiment can have less than 20 pinholes larger than 0.1um on a 200mm wafer.

電觸點及光敏性半導體間之界面之性質係裝置穩定性及性能之一重要決定因素。例如，無論此觸點係歐姆對肖特基，及無論此觸點及半導體係以一使{半導體及觸點}之至少一者鈍化之薄界面層分離於穩定性及性能係重要。 The nature of the interface between the electrical contact and the photosensitive semiconductor is an important determinant of device stability and performance. For example, regardless of whether the contact is ohmic to Schottky, and whether the contact and semiconductor are separated by a thin interface layer passivating at least one of {semiconductor and contact}, stability and performance are important.

光導層之組成-例如，於構成光導體之半導體材料上之表面捕捉態之存在-係裝置之性能及穩定性之一重要決定因素。特別地，光導性材料通常對於奈米顆粒表面上之經物理吸收或化學吸收之物種(可能源始係以氣體存在(諸如，O2、H2O、CO2))之存在具敏感性-此等因而於加工處理期間需小心控制，且一封裝及/或鈍化層可用於此光導層之上及/或之下，以避免隨時間之固定光導性故障。進一步描述係於一實施例之金屬及半導體間之界面與一實施例之封裝之後。 The composition of the light guide layer-for example, the presence of surface trapping states on the semiconductor material that constitutes the light conductor-is an important determinant of the performance and stability of the device. In particular, photoconductive materials are generally sensitive to the presence of physically absorbed or chemically absorbed species on the surface of nanoparticles (possibly originating in the presence of gas (such as O 2 , H 2 O, CO 2 ))- These are therefore carefully controlled during processing, and an encapsulation and / or passivation layer can be used above and / or below this light guide layer to avoid fixed light guide failures over time. Further description follows after the interface between the metal and semiconductor of an embodiment and the packaging of an embodiment.

層'4'可自矽(包含單結晶矽、多結晶矽、奈米結晶矽，或非結晶矽(包含氫化之非結晶矽))製成。 Layer '4' can be made from silicon (including single crystalline silicon, polycrystalline silicon, nanocrystalline silicon, or amorphous silicon (including hydrogenated amorphous silicon)).

層'4'可包含非實質上量子限制，相反地係實質上保持一本體半導體之能隙之材料。實施例包含諸如矽、鎵、砷、碳、PbS、PbSe、PbTe、Bi2S3、In2S3、銅-銦-鎵-硒化物(或硫化物)、SnS、SnSe、SnTe之材料之結晶或多結晶或奈米結晶或非結晶之實施例，其中，其中，任何結晶或部份結晶次單元之特性尺寸典型上係不小於使用之半導體材料之Bohr激子半徑(電子-電洞對之特性空間程度)。 Layer '4' may include non-substantial quantum confinement, but instead material that substantially maintains the energy gap of a bulk semiconductor. Examples include materials such as silicon, gallium, arsenic, carbon, PbS, PbSe, PbTe, Bi 2 S 3 , In 2 S 3 , copper-indium-gallium-selenide (or sulfide), SnS, SnSe, SnTe Crystalline or polycrystalline or nanocrystalline or non-crystalline embodiments, wherein the characteristic size of any crystalline or partially crystalline subunit is typically not less than the Bohr exciton radius (electron-hole pair) of the semiconductor material used Degree of characteristic space).

一實施例之界面形成可包含材料’1’之清理及終結。 The interface formation of one embodiment may include the cleaning and termination of the material '1'.

一實施例之界面可包含於材料'1'上形成之氧化物，包含作為材料7之一部份之自然氧化物。此氧化物之厚度係裝置性能之一重要決定因素。過度之氧化物厚度(例如，超過10-20nm之厚度)會提供與此光導體膜呈串聯之一過度接觸電阻，需應用非所欲之增加偏差c/o偏電流。於實施例，此自然氧化物之厚度被保持於少於5nm之範圍。 The interface of an embodiment may include an oxide formed on the material '1', including a natural oxide as a part of the material 7. The thickness of this oxide is an important determinant of device performance. Excessive oxide thickness (for example, a thickness exceeding 10-20 nm) will provide an excessive contact resistance in series with the photoconductor film, which requires an undesirable increase in bias c / o bias current. In the embodiment, the thickness of the natural oxide is kept within a range of less than 5 nm.

一實施例之界面可包含作為材料'2'之一部份之另一薄層，諸如，TiO2，其一般被包含以改良與欲置於上之半導體之界面之功函數。此層於實施例可提供有利於一種電荷載體之敏感性：例如，TiO2可被建構以便於操作偏壓時，使電子有效率地注射於光導性半導性層之導電帶內，但於此相同偏壓，係以遠較低之功效自此光導性半導性層之價電帶取得電洞。TiO2可被建構以便於操作偏壓時，可有效率地自光導性半導性層之導電帶擷取電子，但於此相同偏壓，係以遠較低之功效使電洞注射於此光導性半導性層之價電帶內。 The interface of an embodiment may include another thin layer as part of the material '2', such as TiO 2 , which is generally included to improve the work function of the interface with the semiconductor to be placed. In this embodiment, this layer can provide sensitivity to a charge carrier: for example, TiO 2 can be constructed to facilitate the injection of electrons into the conductive band of the photoconductive semiconducting layer when the bias voltage is manipulated, but This same bias voltage obtains holes from the valence band of the photoconductive semiconductive layer with far lower efficiency. TiO 2 can be constructed so as to efficiently extract electrons from the conductive band of the photoconductive semiconducting layer when operating the bias voltage, but here the same bias voltage is used to inject holes into the light guide with far lower efficiency Within the valence band of the conductive semiconducting layer.

一實施例之界面可為作為材料'2'之一部份之另一薄層，諸如，聚[2-甲氧基-5-(2'-乙基己氧基)對伸苯伸乙烯](MEH-PPV)，一般被包含以使一種電荷載體(諸如，電洞)流動，同時阻絕另一種(諸如，電子)之流動。 The interface of an embodiment may be another thin layer as part of the material '2', such as poly [2-methoxy-5- (2'-ethylhexyloxy) p-phenylene vinylene] (MEH-PPV), is generally included to flow one charge carrier (such as a hole) while blocking the flow of another (such as an electron).

一實施例之界面可包含作為材料'3'之一部份之一薄層，可能為一自行組織之分子單層，其被設計使分子之一側與底下之層結合，且於此分子之另一終端，結合欲被置於其上之半導體，且確保受控制之電子通訊，亦確保機械穩定性，例如，構成多層裝置之材料間之良好黏著。 The interface of an embodiment may include a thin layer as part of the material '3', which may be a self-organized molecular monolayer, which is designed to combine one side of the molecule with the underlying layer, and The other terminal, in combination with the semiconductor to be placed on it and ensures controlled electronic communication, also ensures mechanical stability, for example, good adhesion between the materials constituting the multilayer device.

一實施例之層狀結構提供經由一界面之有效率電荷載體轉移。於實施例，此層狀結構可與光導性半導體層形成實質上歐姆接觸，提供於接近此界面處之極少或無半導體耗損，且提供至少一種電荷載體(例如，電子、電洞)之有效率注射及擷取。於實施例，此層狀結構可與此光導性半導體層形成肖特基接觸，提供欲被注射及/或取得之電荷載體欲克服之能量障壁。於實施例，此層狀結構可形成一選擇性接觸，提供比提供另一種(例如，電洞)之擷取更有效率之一種電荷載體(例如，電子)之注射；及/或提供比提供另一種(例如，電洞)之注射更有效率之一種電荷載體之取得。 The layered structure of an embodiment provides efficient charge carrier transfer through an interface. In an embodiment, the layered structure can form a substantially ohmic contact with the photoconductive semiconductor layer, provide little or no semiconductor wear near the interface, and provide the efficiency of at least one charge carrier (eg, electron, hole) Injection and retrieval. In an embodiment, the layered structure may form a Schottky contact with the photoconductive semiconductor layer to provide an energy barrier to be overcome by charge carriers to be injected and / or obtained. In an embodiment, the layered structure may form a selective contact to provide an injection of a charge carrier (eg, electron) that is more efficient than providing another (eg, hole) extraction; and / or provide a ratio The injection of another type (for example, a hole) is more efficient in obtaining a charge carrier.

一實施例之層狀結構提供此接觸表面之功函數，其中，有效功函數係藉由電極之材料、界面層之材料，及其厚度決定。 The layered structure of an embodiment provides the work function of the contact surface, wherein the effective work function is determined by the material of the electrode, the material of the interface layer, and its thickness.

一實施例之層狀結構提供用以抑制非所欲之載體轉移之阻絕能力，例如，於p-半導體光檢測器裝置之情況之於金屬電極之表面上提供電子捕捉態之層。 The layered structure of an embodiment provides a blocking capability for suppressing undesired carrier transfer, for example, in the case of a p-semiconductor photodetector device, a layer that provides an electron-trapping state on the surface of a metal electrode.

一實施例之層狀結構提供光敏性半導體材料與金屬電極之強烈鍵結。 The layered structure of an embodiment provides strong bonding between the photosensitive semiconductor material and the metal electrode.

一實施例之層狀結構提供金屬電極-半導體材料之界面高溫穩定性。 The layered structure of an embodiment provides high temperature stability of the metal electrode-semiconductor material interface.

具一工程界面層之一實施例之電子裝置之結構及組成物不受限地包含一金屬電極，其包含一用於半導體製造之傳統材料，其係於一選擇之化學計量混合物中被輕易氧化或氮化或二者，諸如，Ti、W、Ta、Hf、Al、Cu、Cr、Ag；或對氧化或氮化具敏感性者，諸如，Au、Pt、Rh、Ir、Ru、石墨、非結晶之碳、石墨烯，或碳奈米管。此等金屬電極亦可自合金、導性玻璃，及各種導性介金屬合金形成。形成電極之功函數可經由曝置於在特定溫度之氧、氮，或此等之混合物持續一特定時間而調整。 The structure and composition of an electronic device with an embodiment of an engineering interface layer include, without limitation, a metal electrode, which includes a traditional material for semiconductor manufacturing, which is easily oxidized in a selected stoichiometric mixture Or nitridation or both, such as Ti, W, Ta, Hf, Al, Cu, Cr, Ag; or those sensitive to oxidation or nitridation, such as Au, Pt, Rh, Ir, Ru, graphite, Amorphous carbon, graphene, or carbon nanotubes. These metal electrodes can also be formed from alloys, conductive glass, and various conductive intermetallic alloys. The work function of forming the electrode can be adjusted by exposure to oxygen, nitrogen, or a mixture of these at a specific temperature for a specific time.

一實施例之電子裝置之結構及組成物包含一於金屬觸點之表面上之界面層。一實施例之界面層包含此電極之元素之氧化物或介金屬合金，其具有足以維持觸點之歐姆特性之最大厚度，但具有足以產生電子捕捉態之最小厚度。此結構可使用PVD(物理蒸氣沈積)、ALD(原子層沈積)、CVD(化學蒸氣沈積)、離子簇、離子束沈積、離子植入、退火，或其它膜沈積方法產生或生成。另外，此等膜可自水性及非水性之液體組成物形成，其可包含電化學技術，形成該等金屬之氫氧化物、氧化物、氟化物、硫化物、硫酸鹽、亞硫酸鹽、磺酸鹽、磷酸鹽、膦酸鹽、亞磷酸鹽、硝酸鹽、亞硝酸鹽、氮化物、碳酸鹽、碳化物，及其它型式之鹽類或錯合物。界面層之平均厚度可依最終界面層之導性及金屬電極本身之功函數而於0.1nm-0.2nm至10nm-50nm改變。 The structure and composition of the electronic device of an embodiment include an interface layer on the surface of the metal contact. The interface layer of an embodiment includes an oxide or a dielectric metal alloy of elements of this electrode, which has a maximum thickness sufficient to maintain the ohmic characteristics of the contact, but has a minimum thickness sufficient to generate an electron trapping state. This structure can be generated or generated using PVD (physical vapor deposition), ALD (atomic layer deposition), CVD (chemical vapor deposition), ion clusters, ion beam deposition, ion implantation, annealing, or other film deposition methods. In addition, these films can be formed from aqueous and non-aqueous liquid compositions, which can include electrochemical techniques to form hydroxides, oxides, fluorides, sulfides, sulfates, sulfites, sulfonates of these metals Salts, phosphates, phosphonates, phosphites, nitrates, nitrites, nitrides, carbonates, carbides, and other types of salts or complexes. The average thickness of the interface layer can vary from 0.1 nm-0.2 nm to 10 nm-50 nm according to the conductivity of the final interface layer and the work function of the metal electrode itself.

一實施例之界面層包含沈積於電極表面上另外氧化物，該氧化物係經摻雜之TiO2、HfO2、Al2O3、SiO2、Ta2O5、ZnxAlyO、ZnxGayO、ZnInxSnyO，及相似之p-導性材料。再者，此等材料可使用先前所述之方法沈積。 The interface layer of an embodiment includes additional oxides deposited on the electrode surface, the oxides being doped TiO 2 , HfO 2 , Al 2 O 3 , SiO 2 , Ta 2 O 5 , Zn x Al y O, Zn x Ga y O, ZnIn x Sn y O, and similar p-conducting materials. Furthermore, these materials can be deposited using the methods previously described.

界面層之另外性質係藉由與半導體光敏性層之組份形成相對較強之化 學鍵結(較佳係共價)之必要性而決定。若光敏性層無一組份提供與界面層之化學鍵結，此界面層之表面係使用有機二官能性分子改質，其中，一種官能基提供與界面層表面之選擇性鍵結，而第二種官能基提供與配位體之鍵結或直接與半導體奈米結晶鍵結。此等鍵結分子可於非導性之烷或芳基主幹上形成，或可於包含苯胺、乙炔，或其它型式之sp2混雜之碳之導性主幹上形成。提供與電極之氧化表面或界面層之表面鍵結之官能基不受限地包含矽烷、矽氧烷、矽氮烷、一級，二級，或三級之胺、醯亞胺、磷酸鹽、肟、羧酸酯。形成界面層之有機分子之平均長度典型上可從2至16個碳原子變化。 The other properties of the interface layer are formed by the formation of relatively strong components with the semiconductor photosensitive layer Determined by the necessity of learning to bond (preferably covalent). If no component of the photosensitive layer provides chemical bonding with the interface layer, the surface of the interface layer is modified with organic difunctional molecules, wherein one functional group provides selective bonding with the surface of the interface layer, and the second This functional group provides bonding to the ligand or directly to the semiconductor nanocrystal. These bonding molecules can be formed on a non-conductive alkane or aryl backbone, or can be formed on a conductive backbone containing aniline, acetylene, or other types of sp2 hybrid carbon. Functional groups that provide bonding to the oxidized surface of the electrode or the surface of the interface layer include, without limitation, silane, siloxane, silazane, primary, secondary, or tertiary amines, amides, phosphates, oximes 、 Carboxylic acid ester. The average length of the organic molecules forming the interface layer can typically vary from 2 to 16 carbon atoms.

若電極之金屬係鈍性(例如，Au、Pt、Cu、Ag等)，界面層可自包含提供與一邊之金屬表面及與另一邊之奈米結晶直接鍵結之二相似官能基之分子形成。一例子係形成Au-S-R-S-NC鍵。再者，有機界面層之厚度及導性係以所需之電子裝置性質界定。 If the metal of the electrode is passive (for example, Au, Pt, Cu, Ag, etc.), the interface layer can be formed from a molecule containing two similar functional groups that provide direct bonding with the metal surface on one side and the nanocrystal on the other side . An example is the formation of Au-S-R-S-NC bond. Furthermore, the thickness and conductivity of the organic interface layer are defined by the required properties of the electronic device.

若界面層之導性超過電子裝置參數所需之可容許極限(對於平面電極元素)，連續膜可使用傳統形成圖案之技術形成圖案。 If the conductivity of the interface layer exceeds the allowable limit required for electronic device parameters (for planar electrode elements), the continuous film can be patterned using conventional patterning techniques.

於具有至少二電極之每一電子裝置，此等電極之一係由具有一功函數之金屬製成，而另一電極可具有不同功函數及/或不同導性型式(電子或電洞)。 In each electronic device having at least two electrodes, one of these electrodes is made of a metal having a work function, and the other electrode may have a different work function and / or different conductivity types (electrons or holes).

對於一垂直結構之電子裝置，如上之相同方式被用於底部電極，而頂面上之界面層係藉由沈積有機分子或半導體材料之薄透明層而形成。 For an electronic device with a vertical structure, the bottom electrode is used in the same manner as above, and the interface layer on the top surface is formed by depositing a thin transparent layer of organic molecules or semiconductor materials.

如上之分子係具有從約1至約10,000之聚合度之聚合物。 The molecule as above is a polymer having a degree of polymerization from about 1 to about 10,000.

於形成一此間所述之裝置，一般，此裝置可被形成而包含材料'1'及材料 '2'之一致、可靠之結合，其後可控制式地形成材料'3'及吸光層'4'。例如，一實施例可經由具有少於100微歐姆*公分之電阻及位於-2eV與-4.5之間及位於-2eV與-4.2eV之間之功函數之高導性觸點之材料'1'提供。一實施例可經由具有能使電子注射於隨後之光敏性半導體層內但阻絕電洞自此層擷取之材料'2'提供。一實施例可達成一受控制厚度之經摻雜之實質上透明之氧化物，諸如，n-型TiOx，作為材料'2'之第一部份之一部份。例如，一實施例可達成2-20範圍之TiOx厚度，其被控制於1-5nm內；且其中，TiOx具有1x1018cm-3之經特別選擇之載體密度，且於載體密度具有嚴格之控制帶譜，諸如，+/-10%。 In forming a device described here, in general, this device can be formed to include a consistent and reliable combination of the material '1' and the material '2', after which the material '3' and the light-absorbing layer '4 can be controlledly formed '. For example, an embodiment may pass the material '1' of a highly conductive contact with a resistance of less than 100 microohms * cm and a work function between -2eV and -4.5 and between -2eV and -4.2eV provide. An embodiment may be provided by having a material '2' that enables electron injection into the subsequent photosensitive semiconductor layer but blocks holes from being extracted from this layer. One embodiment can achieve a controlled thickness of doped, substantially transparent oxide, such as n-type TiOx, as part of the first part of the material '2'. For example, an embodiment can achieve a TiOx thickness in the range of 2-20, which is controlled within 1-5 nm; and wherein TiO x has a specially selected carrier density of 1 x 10 18 cm -3 , and has a carrier density of Strictly control the band spectrum, such as +/- 10%.

此間所述裝置之層堆疊物或結構之製造包含：(1)形成金屬，諸如，經料於氮氛圍噴濺鈦，造成TiN之形成；(2)其後加工處理，造成界面層(諸如，自然氧化物，諸如，TiOxNy或TiOx)之形成(此其後之加工處理可造成一範圍之可能氧化物厚度及摻雜物與載體載體)；(3)經由蝕刻，諸如，硫酸-過氧化物-去離子水蝕刻，或過氧化銨蝕刻，或物理性蝕刻(諸，氬氣噴濺)，或反應性噴濺蝕刻(諸如，氬氣及氫氣)，移除自然氧化物層；於一實施例，此蝕刻完全移除此氧化物；用以確保完全移除之有節制之過度蝕刻可***作；(4)一實施例沈積受控制之厚度，受控制之摻雜，及受控制表面終結之氧化物層，諸如，TiOx、TiOxNy，或其它界面層。諸如物理蒸氣沈積之方法(包含於O2、N2，或其等之混合物存在中之TiOx源、TN源，或Ti源之DC噴濺、RF噴濺)可用以沈積此等層。方法亦包含CVD及ALD，其中，一先質先沈積於晶圓之表面上，且一反應係於受控制之溫度進行。於其中TiOx欲被形成之情況，先質可被使用。 The fabrication of the layer stack or structure of the device described here includes: (1) forming a metal, such as sputtering titanium in a nitrogen atmosphere, resulting in the formation of TiN; (2) subsequent processing, causing an interface layer (such as The formation of natural oxides, such as TiO x N y or TiO x (the subsequent processing can result in a range of possible oxide thicknesses and dopants and carrier supports); (3) by etching, such as sulfuric acid -Peroxide-deionized water etching, or ammonium peroxide etching, or physical etching (all, argon sputtering), or reactive sputtering etching (such as argon and hydrogen), to remove the natural oxide layer ; In one embodiment, the etching completely removes the oxide; to ensure that the excessive over-etching that is completely removed can be operated; (4) one embodiment deposits controlled thickness, controlled doping, and controlled by the end surface of the oxide layer, such as, TiO x, TiO x N y , or other interface layer. Methods such as physical vapor deposition (DC sputtering, RF sputtering of TiO x source, TN source, or Ti source contained in the presence of O 2 , N 2 , or a mixture of these) can be used to deposit these layers. The method also includes CVD and ALD, where a precursor is deposited on the surface of the wafer and a reaction is performed at a controlled temperature. In the case where TiO x is to be formed, the precursor can be used.

此間所述裝置之層之堆疊物或結構之製造可包含：(1)形成金屬，諸如，經由於氮氛圍中之鈦噴濺，造成TiN之形成；(2)於此金屬頂部上原位轉移沈積一界面層。此可包含TiOx或TiOxNy。此等層可擁有受控制之厚度，受控制之摻雜，及受控制表面終結之氧化物層，諸如，TiOx、TiOxNy，或其它界面層。諸如物理蒸氣沈積之方法(包含於O2、N2，或其等之混合物存在中之TiOx源、TN源，或Ti源之DC噴濺、RF噴濺)可用以沈積此等層。方法亦包含CVD及ALD，其中，一先質先沈積於晶圓之表面上，且一反應係於受控制之溫度進行。於其中TiOx欲被形成之情況，化學先質可被使用。 The fabrication of the stack or structure of the layers of the device described here may include: (1) forming a metal, such as titanium sputtering in a nitrogen atmosphere, causing the formation of TiN; (2) in-situ transfer on top of this metal An interface layer is deposited. This may include TiO x or TiO x N y . These layers may have a controlled thickness, controlled doping, and controlled surface termination oxide layers, such as TiO x , TiO x N y , or other interface layers. Methods such as physical vapor deposition (DC sputtering, RF sputtering of TiO x source, TN source, or Ti source contained in the presence of O 2 , N 2 , or a mixture of these) can be used to deposit these layers. The method also includes CVD and ALD, where a precursor is deposited on the surface of the wafer and a reaction is performed at a controlled temperature. In the case where TiO x is to be formed, chemical precursors can be used.

如上所述，封裝及/或鈍化之層可被用於光導層之上及/或之下，保持隨時間之一致光導特徵。此間所述之實施例確保光導層內之一致之氣體環境(或無大量氣體存在)。例如，真空、氬、氮、氧、氫、二氧化碳可被包含或被排除，以各種比例及達各種程度。實施例可排除氧、H2O、CO2，且可無氣體分子，或僅包含非反應性之材料，諸如，氬及/或氮。為保持隨時間之一致光導特徵，一封裝層可被包含，其目的係避免光導層及此膜外部區域間之氣體交換。一實施例之用於此目的之材料不受限地包含：聚二甲苯；As2S3或As2Se3；Si3N4、SiO2，及此等之混合物，即，SiOxNy；諸如TiO2、HfO2、Al2O3、SiO2、Ta2O5、ZnxAlyO、ZnxGayO、ZnInxSny之氧化物。 As mentioned above, encapsulated and / or passivated layers can be used above and / or below the light guide layer to maintain consistent light guide characteristics over time. The embodiments described herein ensure a consistent gas environment (or no large amount of gas) in the light guide layer. For example, vacuum, argon, nitrogen, oxygen, hydrogen, carbon dioxide can be included or excluded, in various proportions and to various degrees. Embodiments may exclude oxygen, H 2 O, CO 2 , and may be free of gas molecules, or contain only non-reactive materials, such as argon and / or nitrogen. In order to maintain consistent light guide characteristics over time, an encapsulation layer can be included for the purpose of avoiding gas exchange between the light guide layer and the outer area of the film. The materials used for this purpose in one embodiment include without limitation: polyxylene; As 2 S 3 or As 2 Se 3 ; Si 3 N 4 , SiO 2 , and mixtures of these, ie, SiO x N y ; TiO 2, HfO 2, Al 2 O 3, SiO 2, Ta 2 O 5, Zn x Al y O, Zn x Ga y O, such as oxides of ZnIn x Sn y.

封裝材料可藉由一鈍化層提供，其可能呈一實質上單分子單層之型式。此第一層可於沈積此封裝劑期間用以保護被封裝之結構：例如，一諸如聚二甲苯之材料層可使用一不會不利地改變光導層之光電行為之程序先被沈積，且於隨後之封裝方法期間提供光導層保護。其可，例如，保護此膜免於自氧及用於沈積含氧之封裝劑(諸如，SiOx、SiOxNy等)之某些方法期 間存在之其基而造成之反應。 The packaging material may be provided by a passivation layer, which may be in the form of a substantially monomolecular monolayer. This first layer can be used to protect the encapsulated structure during the deposition of the encapsulant: for example, a layer of material such as polyxylene can be deposited first using a procedure that does not adversely change the photoelectric behavior of the light guide layer Provide light guide layer protection during subsequent packaging methods. The presence of certain groups which during the process which may, for example, from the protection against oxygen, and the film deposition for the oxygen-containing encapsulant (such as, SiO x, SiO x N y, etc.) are caused to react.

於實施例，總封裝劑堆疊物(可包含多數層)之典型厚度範圍可為單一單層(典型上~nm或些微之次-nm，例如，5A)至典型上係1微米。於實施例，總封裝劑堆疊物之總厚度所欲地可為少於1-2微米，以使此陣列之光學性質干擾達最小。 In an embodiment, the typical thickness of the total encapsulant stack (which may include multiple layers) may range from a single single layer (typically ~ nm or slightly sub-nm, for example, 5A) to typically 1 micron. In an embodiment, the total thickness of the total encapsulant stack may desirably be less than 1-2 microns to minimize interference with the optical properties of the array.

於實施例，包含於層'1','2','3','4','5'之至少一者內可為用以清除可與此裝置內之材料(包含若反應會改變裝置之光電性質之材料)反應之材料。會進入此裝置之反應性分子之例子包含O2及H2O及O3。可具有藉由此等反應改變之光電性質之於此裝置內之材料之例子包含材料'4' NC、材料'3'黏著、材料'2'界面，及'1'金屬。清除作用之部份之例子包含氮化硼、硼氫化物(包含四氫硼酸鹽)、兒茶素硼烷、三仲丁基硼氫化鋰、硼氫化鋰、三乙基硼氫化鋰、硼氫化鈉，及硼氫化鈾。清除作用之部份之例子包含可水解之矽氧烷。 In an embodiment, at least one of the layers '1', '2', '3', '4', and '5' can be used to remove materials that can interact with the device (including changing the device if reacted) Materials with photoelectric properties) materials that react. Examples of reactive molecules that will enter this device include O 2 and H 2 O and O 3 . Examples of materials within this device that can have photoelectric properties changed by these reactions include material '4' NC, material '3' adhesion, material '2' interface, and '1' metal. Examples of the scavenging part include boron nitride, borohydride (including tetrahydroborate), catechin borane, lithium tri-sec-butylborohydride, lithium borohydride, lithium triethylborohydride, borohydride Sodium, and uranium borohydride. Examples of scavenging components include hydrolyzable silicones.

一實施例之裝置可包含一與半導體光敏性層之組份之強烈化學鍵(例如，共價)。於光敏性層無一組份提供與界面層化學鍵結之情況，界面層之表屇係使用有機二官能性部份改質，其中，一種官能基提供與界面層表面之選擇性鍵結，而第二種官能基提供與配位體或直接與半導體奈米結晶之鍵結。此等鍵結分子可於非導性之烷或芳基主幹上形成，或可於包含苯胺、乙炔，或其它型式之sp2混雜碳之導性主幹上形成。提供與氧化物鍵結之官能基可包含矽烷、矽氧烷、矽氮烷、一級，二級，或三級之胺、醯亞胺、磷酸鹽、肟、羧酸酯。 The device of an embodiment may include a strong chemical bond (eg, covalent) with the component of the semiconductor photosensitive layer. In the case where no component of the photosensitive layer provides chemical bonding with the interface layer, the surface of the interface layer is modified with an organic difunctional part, in which a functional group provides selective bonding with the surface of the interface layer, and The second functional group provides a bond with the ligand or directly with the semiconductor nanocrystal. These bonding molecules can be formed on a non-conductive alkane or aryl backbone, or can be formed on a conductive backbone containing aniline, acetylene, or other types of sp2 hybrid carbon. The functional group that provides the bond with the oxide may include silane, siloxane, silazane, primary, secondary, or tertiary amine, amide imine, phosphate, oxime, carboxylate.

一實施例之裝置之製造方法可包含於乾淨之乾燥空氣氛圍內於20℃使用SCI預清理晶圓30秒。一實施例之裝置之製造方法可包含於乾淨之乾燥空 氣氛圍於20℃於去離子水中沖洗30秒。一實施例之裝置之製造方法可包含使晶圓乾燥，其包含於一指定環境(諸如，乾淨之乾燥空氣、真空、氮、氬，或還原氛圍(諸如，氫)，或含有惰性氣體(諸如，N2或Ar)之控制式氧化氛圍及氧化氣體(諸如，O2))，於指定溫度(諸如，20、70、150，或200℃)烘烤一指定時間(諸如，30秒-24小時)。 The manufacturing method of the device of an embodiment may include pre-cleaning the wafer using SCI at 20 ° C for 30 seconds in a clean dry air atmosphere. The manufacturing method of the device of an embodiment may include rinsing in deionized water at 20 ° C for 30 seconds in a clean dry air atmosphere. The manufacturing method of the device of an embodiment may include drying the wafer in a specified environment (such as clean dry air, vacuum, nitrogen, argon, or a reducing atmosphere (such as hydrogen), or containing an inert gas (such as , N2 or Ar) controlled oxidizing atmosphere and oxidizing gas (such as O 2 )), baking at a specified temperature (such as 20, 70, 150, or 200 ℃) for a specified time (such as 30 seconds -24 hours ).

一實施例之裝置之製造方法可包含指定其它處理方法間之最大及最小與平均之等待時間。 The manufacturing method of the device of an embodiment may include specifying the maximum and minimum and average latency between other processing methods.

一實施例之裝置之製造方法可包含處理基材及量子點膜，其包含曝置於在一指定氛圍(諸如，N2)之於指定溫度(諸如，25℃)之乙腈內之乙烷二硫醇一指定時間(諸如，20秒)。一實施例之裝置之製造方法可包含處理基材及量子點膜，其包含曝置於在一指定氛圍(諸如，N2)之於指定溫度(諸如，25℃)之乙腈內之己烷二硫醇一指定時間(諸如，20秒)。 An apparatus manufacturing method of an embodiment may include processing a substrate and a quantum dot film including ethane dicarbonate exposed to acetonitrile in a specified atmosphere (such as N 2 ) at a specified temperature (such as 25 ° C) Mercaptan for a specified time (such as 20 seconds). An apparatus manufacturing method of an embodiment may include processing a substrate and a quantum dot film including hexane dicarbonate exposed to acetonitrile in a specified atmosphere (such as N 2 ) at a specified temperature (such as 25 ° C.) Mercaptan for a specified time (such as 20 seconds).

一實施例之裝置之製造方法可包含於特定溫度(諸如，100℃)或低於此溫度沈積一介電封蓋層(諸如，SiO2)，且於諸如100℃達一特定厚度之介電封蓋層。 The manufacturing method of the device of an embodiment may include depositing a dielectric capping layer (such as SiO 2 ) at or below a specific temperature (such as 100 ° C.), and at a specific thickness of the dielectric such as 100 ° C. Cover layer.

一實施例之裝置之製造方法包含微影界定欲被蝕刻之區域，其後蝕刻包含SiO2之材料。 The manufacturing method of the device of one embodiment includes lithography to define the area to be etched, and then etching the material containing SiO 2 .

一實施例之裝置之製造方法可包含於特定溫度(諸如，100℃)或低於此溫度沈積一介電封蓋層(諸如，SiN)，且於諸如100℃達一特定厚度之介電封蓋層。 The manufacturing method of the device of an embodiment may include depositing a dielectric capping layer (such as SiN) at or below a specific temperature (such as 100 ° C), and at a specific thickness such as 100 ° C Cap layer.

一實施例之裝置之製造方法包含微影界定欲被蝕刻之區域，其後蝕刻包含SiN之材料。 The manufacturing method of the device of one embodiment includes lithography to define the area to be etched, and then etching the material containing SiN.

一實施例之裝置之製造方法可包含矽CMOS之製造，包含於沈積量子點層前於200nm Si晶圓上加工處理及以0.11微米節點之標準Al/SiO2材料之技術。CMOS製造流可以一具圖案之金屬觸點(諸如，TiN)而完成。 The manufacturing method of the device of one embodiment may include the fabrication of silicon CMOS, which includes processing on a 200nm Si wafer before depositing the quantum dot layer and a standard Al / SiO 2 material with a 0.11 micron node. The CMOS manufacturing flow can be accomplished with a patterned metal contact (such as TiN).

一實施例之裝置之製造方法可包含使一Cu/TEOS/SiN HM單一波紋層於一通孔層上積體化，其後選擇性無電沈積Ni/Au堆疊物。 The manufacturing method of the device of an embodiment may include integrating a Cu / TEOS / SiN HM single corrugated layer on a via layer, and then selectively electrolessly depositing a Ni / Au stack.

一實施例之裝置之製造方法可包含基材之預處理。金屬電極及/或介電表面之改質可能需要以改良層間之電接觸或黏著。替代濕後預清理，晶圓可藉由電漿或藉由液相或蒸氣相之方法處理形成具受控制之障壁厚度及表面狀態密度之黏著單層。 The manufacturing method of the device of an embodiment may include pretreatment of the substrate. The modification of metal electrodes and / or dielectric surfaces may be required to improve electrical contact or adhesion between layers. Instead of pre-wetting after wet cleaning, wafers can be processed by plasma or by liquid or vapor phase methods to form an adhesive monolayer with controlled barrier thickness and surface state density.

一實施例之裝置之製造方法可包含沈積光敏性膜，其中，周圍氛圍之緊密控制被提供以使氧及水份對膜性能之衝擊達最小及/或受控制。其可包含使用裝設O2及H2O處理監視器之生產工具。標準操作程序可被提供而確保最小，或受控制及一致之材料(諸如，量子點及其層)曝置於空氣，包含於化學品貯存期間，及流體自貯存容器轉移至處理工具槽。製造方法可與氯仿及其它溶劑相容。 The method of manufacturing the device of an embodiment may include depositing a photosensitive film, wherein tight control of the surrounding atmosphere is provided to minimize and / or control the impact of oxygen and moisture on film performance. It can include production tools using O 2 and H 2 O process monitors. Standard operating procedures can be provided to ensure minimal, or controlled and consistent materials (such as quantum dots and their layers) are exposed to air, contained during chemical storage, and fluid is transferred from the storage container to the processing tool tank. The manufacturing method is compatible with chloroform and other solvents.

一實施例之裝置之製造方法可包含使量子點層安定化。此等可包含使用於乙腈內之二硫醇稀釋溶液之化學後處理。 The manufacturing method of the device of an embodiment may include stabilizing the quantum dot layer. These may include chemical post-treatment of dithiol diluted solutions used in acetonitrile.

由於QF對周圍之氧及水份之高敏感性，QF沈積與後處理間之等待時間需達最小且於N2層下為之。相同條件應用於後處理B與介電封蓋沈積間之等待時間。 Due to the high sensitivity of QF to the surrounding oxygen and water, the waiting time between QF deposition and post-treatment needs to be minimal and under the N2 layer. The same conditions apply to the waiting time between post-processing B and the deposition of the dielectric cap.

一實施例之裝置之製造方法可包含QF膜之密封以於此裝置之壽命期間免於氧及水份之擴散。SiO2/SiN堆疊物之低溫沈積可被使用。此等方法需於 低於100℃之基材溫度且於大氣壓或於儘可能高之壓力實施。其它方法之選擇可包含低溫旋塗式玻璃方法或超薄金屬膜，其不會影響封蓋層之光學透射性。 The manufacturing method of the device of an embodiment may include sealing of the QF film to prevent diffusion of oxygen and moisture during the life of the device. Low temperature deposition of SiO 2 / SiN stack can be used. These methods need to be carried out at a substrate temperature below 100 ° C and at atmospheric pressure or at the highest possible pressure. The choice of other methods may include a low-temperature spin-on glass method or an ultra-thin metal film, which does not affect the optical transmission of the capping layer.

一實施例之裝置之方法控制可包含於量子點沈積前之進料晶圓檢測。一實施例之檢測步驟包含：a)檢測缺陷密度，諸如，使用明視場檢測；b)金屬電極功函數檢測，諸如，使用紫外線光電子光譜術(UPS)(UPS方法處理控制程序可於覆蓋層處理監視晶圓)；c)漏電流及介電電壓破壞於TLM(測試像素陣列)結構上實施。裝置之光電響應及膜性質可被實施作為一處理控制之一部份。 The method control of the device of an embodiment may include the inspection of the feed wafer before the quantum dot deposition. The inspection steps of an embodiment include: a) inspection of defect density, such as using bright field inspection; b) metal electrode work function inspection, such as using ultraviolet photoelectron spectroscopy (UPS) (UPS method processing control program can be applied to the cover layer Process monitoring wafer); c) Leakage current and dielectric voltage destruction are implemented on the TLM (Test Pixel Array) structure. The photoelectric response and film properties of the device can be implemented as part of a process control.

於實施例，材料'4'可包含一具有一能隙且提供於感興趣之波長範圍內之光線之吸收之材料。於實施例，光敏性層可包含諸如Si、PbS、PbSe、CdS、CdSe、GaAs、InP、InAs、PbTe、CdTe、Ge、In2S3、Bi2S3，及其等之混合物之材料。於實施例，光敏性層可包含強烈吸光材料，諸如，卟啉。於實施例，光敏性層可包含鈍化有機配位體，諸如，乙烷硫醇、乙烷二硫醇、苯硫醇、苯二硫醇、二苯二硫醇、吡啶、丁胺。 In an embodiment, the material '4' may include a material having an energy gap and providing absorption of light in the wavelength range of interest. In an embodiment, the photosensitive layer may include materials such as Si, PbS, PbSe, CdS, CdSe, GaAs, InP, InAs, PbTe, CdTe, Ge, In 2 S 3 , Bi 2 S 3 , and mixtures thereof. In an embodiment, the photosensitive layer may contain a strong light-absorbing material, such as porphyrin. In an embodiment, the photosensitive layer may include a passivating organic ligand, such as ethanethiol, ethanedithiol, benzenethiol, benzenedithiol, diphenyldithiol, pyridine, and butylamine.

實施例，一實施例之光檢測器包含使用一光敏性能量障壁控制至少一種電荷載體之流動之光敏性裝置。 Embodiments. The photodetector of an embodiment includes a photosensitive device that uses a photosensitive energy barrier to control the flow of at least one charge carrier.

於實施例，光檢測器可展現增益，其中，每一秒流動之額外電荷單元數對每秒衝擊於一裝置止之光子數之比率會超過1，例如，位於約2-60範圍之值。 In an embodiment, the photodetector may exhibit gain, wherein the ratio of the number of extra charge units flowing per second to the number of photons impacting a device per second will exceed 1, for example, a value in the range of about 2-60.

於實施例，光檢測器可展現高的正規化響應，即，高的光電流對暗電流之比例，即使於低光量時。例如，當150nW/cm2之可見光衝擊於光檢測 器，光電流對發光電流之比率可超過20。一般，此值需儘可能地高(同時符合其它規定，諸如，滯後(on lag)及暗電流均一性及光響應均一性)。高達100及更高之值對於150nW/cm2之正規化響應係可能。 In an embodiment, the photodetector may exhibit a high normalized response, that is, a high ratio of photocurrent to dark current, even when the amount of light is low. For example, when 150nW / cm 2 of visible light impinges on the photodetector, the ratio of photocurrent to luminous current can exceed 20. In general, this value needs to be as high as possible (while meeting other regulations, such as on lag and uniformity of dark current and uniformity of light response). Values up to 100 and higher are possible for a normalized response of 150nW / cm 2 .

於實施例，光檢測器可展現快速之時間響應，且光電流(包含下列強烈照明，諸如，於像素上之1uW/cm2及更大)於少於1秒內停留於接近暗電流之值(諸如，距暗電流一最低有效位元)。理想上，光電流係於一曝光期(可為1/15s、1/30s、1/200s、1/1000s，或相似者)內停留於此值。 In an embodiment, the photodetector can exhibit a fast time response, and the photocurrent (including the following intense illumination, such as 1 uW / cm 2 and more on the pixel) stays at a value close to the dark current in less than 1 second (Such as the least significant bit from the dark current). Ideally, the photocurrent stays at this value during an exposure period (which can be 1 / 15s, 1 / 30s, 1 / 200s, 1 / 1000s, or the like).

於實施例，黑暗內之電流-電壓特性於零與第一電壓(稱為飽和電壓)間可展現單調增加之函數關係。此範圍可被稱為觸發相。電流-電壓可於第一電壓與第二之較大電壓(稱為穿通電壓)間展現具有比零至第一電壓範圍期間更低之平均斜率之單調增加之函數。此第一至第二電壓範圍可被稱為飽和範圍。於大於第二(或穿通)電壓之電壓，電流-電壓關係可展現相較於第一電壓至第二電壓範圍係增加之斜率。此最高電壓範圍可被稱為穿通後範圍。 In an embodiment, the current-voltage characteristic in the dark may exhibit a monotonically increasing functional relationship between zero and the first voltage (referred to as saturation voltage). This range can be referred to as the trigger phase. The current-voltage can exhibit a function of a monotonic increase between the first voltage and the second larger voltage (called the punch-through voltage) with a lower average slope than during the period from zero to the first voltage. This first to second voltage range may be referred to as the saturation range. At voltages greater than the second (or punch-through) voltage, the current-voltage relationship can exhibit an increasing slope compared to the first voltage to the second voltage range. This highest voltage range may be referred to as the post-punch range.

於實施例，增益可於當於偏差下使電荷載體(例如，電子)流動通過此裝置之時間(即，於二觸點間(諸如，於第2圖之左側材料'1'及右側材料'1'間)運行之時間，或第3圖之材料'1'與材料'9'間運行之時間)超過電荷載體之平均壽命時，當注射流動電荷載體(例如，電子)之觸點亦避免擷取其它型式之電荷載體(可被稱為經阻絕之載體(例如，電洞))時，及當提供流動電荷載體(例如，電子)之觸點與半導體膜間之界面提供經阻絕載體(例如，電洞)低的表面重組速率時達成。此界面係於第1圖之材料'2'及材料'3'，第2圖之材料'2'及材料'3'，及第2圖之材料'7'及材料'3'，及第3圖之材料'2'、材料'3'、材料'5' 及材料'8'實施。 In an embodiment, the gain may be the time when charge carriers (eg, electrons) flow through the device under a deviation (ie, between two contacts (such as the left side material '1' and the right side material in Figure 2 1 ') The running time, or the running time between the material' 1 'and the material' 9 'in Figure 3) When the average life of charge carriers is exceeded, the contact of the injection of flowing charge carriers (for example, electrons) is also avoided When capturing other types of charge carriers (which may be referred to as blocked carriers (eg, holes)), and when the interface between the contacts of the mobile charge carriers (eg, electrons) and the semiconductor film is provided, the blocked carriers ( For example, holes) are achieved at low surface reorganization rates. This interface is in the material '2' and material '3' in Figure 1, the material '2' and material '3' in Figure 2, and the material '7' and material '3' in Figure 2, and the third Picture material '2', material '3', material '5' And material '8' implementation.

更特別地，增益可於在偏差下流動電荷載體(例如，電子)通過此裝置之時間超過電荷載體之平均壽命時達成。量化地，亦可認為基本運送因子(α-t)係少於但接近1。此可於小量之用於流動載體之載體擴散長度超過界面層間之分隔時達成。 More specifically, the gain can be achieved when the time that the flowing charge carriers (eg, electrons) pass through the device under deviation exceeds the average lifetime of the charge carriers. Quantitatively, it can also be considered that the basic transport factor (α-t) is less than but close to unity. This can be achieved when a small amount of carrier diffusion length for the flow carrier exceeds the separation between the interface layers.

再者，增益可於在偏差下注射流動電荷載體(例如，電子)之觸點亦避免擷取其它型式之電荷載體(可被稱為經阻絕之載體(例如，電洞))時達成。量化地，可認為發射體注射效率(γ)係少於但接近1。此可藉由使用一接近阻絕擷取其它型式之電荷載體之流動載體注射觸點之界面層而達成。此可藉由自一其中一帶譜(諸如，導電帶)於能量係與和其接近之金屬觸點之功函數實質上接近校準；且於能量係與阻絕擷取電荷載體之半導體之帶譜實質上不校準之大能隙材料製造此界面層而達成。 Furthermore, the gain can be achieved when the contacts of the flowing charge carriers (for example, electrons) are injected with a deviation and other types of charge carriers (which can be called blocked carriers (for example, holes)) are prevented from being captured. Quantitatively, it can be considered that the emitter injection efficiency (γ) is less than but close to unity. This can be achieved by injecting the interface layer of the contacts with a flow carrier that closes to capture other types of charge carriers. This can be achieved by substantially calibrating the work function of one of the band spectra (such as the conductive band) in the energy system and the metal contacts close to it; and in the energy system and the band spectrum of the semiconductor that blocks charge carriers This interface layer is achieved by using a large energy gap material that is not calibrated.

再者，增益可於在偏壓下提供流動電荷載體(例如，電子)之觸點及半導體膜間之界面提供經阻絕之載體(例如，電洞)低的表面重組速率時達成。量化地，可認為重組因子係少於但接近1。此可於在流動載體(例如，電子)之小量載體壽命內，僅小分率之經阻絕載體(例如，電洞)於提供流動電荷載體(例如，電子)之觸點及半導體膜間之界面附近重組。此可能需使經阻絕之載體之表面重組速率少於0.1cm/s，例如，0.01cm/s或更少。 Furthermore, the gain can be achieved when the interface between the contact of the mobile charge carrier (eg, electrons) and the semiconductor film under bias provides a low surface recombination rate of the blocked carrier (eg, holes). Quantitatively, it can be considered that the recombination factor system is less than but close to 1. This can be between the contact of the mobile carrier (e.g. electrons) and the semiconductor film for only a small fraction of the blocked carrier (e.g. holes) within the lifetime of the small carrier of the mobile carrier (e.g. electrons) Reorganized near the interface. This may require the surface reorganization rate of the blocked carrier to be less than 0.1 cm / s, for example, 0.01 cm / s or less.

參考第2圖，實施例可包含用以降低於最左之材料'1'與最右之材料'1'間通過之暗電流之方法及結構。實施例可包含移除位於最左之材料'1'及最右之材料'1'之觸點間之材料'3'之部份內之導性部份。實施例可包含移除位於最左之材料'1'及最右之材料'1'之觸點間之諸如金屬氧化物、金屬氫氧化物、有機 污染、聚合物、導性氧化物之導性部份。參考第2圖，實施例可包含改良材料'7'與材料'4'間之界面，以控制於此界面之重組速率、被捕捉之電荷、黏著，或數個此等性質。 Referring to FIG. 2, the embodiment may include a method and structure for reducing the dark current passing between the leftmost material '1' and the rightmost material '1'. Embodiments may include removing conductive portions within the portion of material '3' between the contacts of the leftmost material '1' and the rightmost material '1'. Embodiments may include removing such as metal oxide, metal hydroxide, organic between the contacts of the leftmost material '1' and the rightmost material '1' Conductive parts of pollution, polymers and conductive oxides. Referring to FIG. 2, an embodiment may include an improved interface between the material '7' and the material '4' to control the recombination rate, trapped charge, adhesion, or several of these properties at this interface.

參考第1圖，實施例包含控制諸如存在於界面層'2'及'3'者之表面狀態。實施例包含以氙或其它物種或使用氬噴濺撞擊金屬(諸如，材料'1'之Tin)或金屬氧氫化物(諸如，材料'2'之TiOx)，以便控制或改良表面上之重組速率。實施例可包含使一種電荷載體之表面重組速率於此界面降至少於0.1cm/s或至少於0.01cm/s。 Referring to FIG. 1, the embodiment includes controlling the surface state such as those present in the interface layers '2' and '3'. Example contains xenon or argon or other species impinging metal sputtering (such as the material '1' of Tin) oxide or a metal hydride (such as, material '2' of TiO x), in order to control the modified or recombinant upper surface rate. Embodiments may include reducing the surface recombination rate of a charge carrier at this interface to less than 0.1 cm / s or at least 0.01 cm / s.

實施例包含實現於每一側尺寸具0.9um之像素間距之小像素。實施例包含使用窄通孔(諸如，0.15um)。實施例包含使用14um之金屬與金屬之間隔。 Embodiments include small pixels implemented with a pixel pitch of 0.9um on each side. Embodiments include the use of narrow vias (such as 0.15um). Examples include the use of 14um metal-to-metal spacing.

此間所述之實施例包含一種光學敏感性裝置，包含：一第一觸點及一第二觸點；每一者具有一功函數；一位於第一觸點與第二觸點間之光學敏感性材料，此光學敏感性材料包含一p-型半導體，且此光學敏感性材料具有一功函數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；光學敏感性材料之功函數之數量係比第一觸點之功函數之數量大至少0.4eV，且亦比第二觸點之功函數之數量大至少0.4eV；光學敏感性材料具有大於當偏電壓施加於第一觸點與第二觸點之間時從第一觸點至第二觸點之電子運行時間之電子壽命；第一觸點提供電子之注射及阻絕電洞之擷取；第一觸點與光學敏感性材料間之界面提供少於1cm/s之表面重組速率。 The embodiments described herein include an optically sensitive device, including: a first contact and a second contact; each having a work function; an optical sensitivity between the first contact and the second contact Material, the optically sensitive material includes a p-type semiconductor, and the optically sensitive material has a work function; the circuit is constructed to apply a bias voltage between the first contact and the second contact; the optically sensitive material The number of work functions is at least 0.4 eV greater than the number of work functions of the first contact, and also at least 0.4 eV greater than the number of work functions of the second contact; the optically sensitive material has a greater The electronic life time of the electronic running time from the first contact to the second contact between a contact and the second contact; the first contact provides the injection of electrons and the extraction of blocking holes; the first contact and The interface between optically sensitive materials provides a surface recombination rate of less than 1 cm / s.

此間所述之實施例包含一種光學敏感性裝置，其包含一第一觸點；一n-型半導體；一包含一p-型半導體之光學敏感性材料；一第二觸點；光學敏感性材料及第二觸點每一者具有一比4.5ev淺之功函數；電路被建構以於第 一觸點與第二觸點間施加一偏電壓；光學敏感性材料具有大於當偏電壓施加於第一觸點與第二觸點之間時從第一觸點至第二觸點之電子運行時間之電子壽命；第一觸點提供電子之注射及阻絕電洞之擷取；第一觸點與光學敏感性材料間之界面提供少於1cm/s之表面重組速率。 The embodiments described herein include an optically sensitive device including a first contact; an n-type semiconductor; an optically sensitive material including a p-type semiconductor; a second contact; an optically sensitive material And the second contact each have a work function shallower than 4.5 ev; the circuit is constructed to A bias voltage is applied between one contact and the second contact; the optically sensitive material has greater electrical operation from the first contact to the second contact when the bias voltage is applied between the first contact and the second contact The electronic lifetime of time; the first contact provides injection of electrons and the extraction of blocked holes; the interface between the first contact and the optically sensitive material provides a surface reorganization rate of less than 1 cm / s.

此間所述之實施例包含一種光檢測器，其包含：一第一觸點及一第二觸點，每一者具有一功函數；一位於第一觸點與第二觸點間之光學敏感性材料，光學敏感性材料包含一p-型半導體，且光學敏感性材料具有一功函數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；光學敏感性材料之功函數之數量係比第一觸點之功函數之數量大至少0.4eV，且亦比第二觸點之功函數之數量大至少0.4eV；電流被建構以於第一觸點與第二觸點間施加一偏電壓；且光學敏感性材料被建構以於偏電壓施加於第一觸點與第二觸點時提供至少0.8A/W之響應度。 The embodiments described herein include a photodetector, which includes: a first contact and a second contact, each of which has a work function; an optical sensitivity between the first contact and the second contact Material, the optically sensitive material includes a p-type semiconductor, and the optically sensitive material has a work function; the circuit is constructed to apply a bias voltage between the first contact and the second contact; the work of the optically sensitive material The number of functions is at least 0.4 eV greater than the number of work functions of the first contact, and also at least 0.4 eV greater than the number of work functions of the second contact; the current is constructed between the first contact and the second contact A bias voltage is applied between them; and the optically sensitive material is constructed to provide a response of at least 0.8 A / W when the bias voltage is applied to the first contact and the second contact.

一實施例之光檢測器之第一觸點係一注射觸點，且第二觸點係一拉取觸點。 In one embodiment of the photodetector, the first contact is an injection contact, and the second contact is a pull contact.

一實施例之光檢測器之注射觸點被建構而以比注射觸點自光學敏感性材料取得一經捕捉之載體者更大效率使一流動電流注射於光學敏感性材料內。 The injection contact of the photodetector of one embodiment is constructed to inject a flowing current into the optically sensitive material with greater efficiency than the injection contact to obtain a captured carrier from the optically sensitive material.

一實施例之光檢測器之注射觸點被建構而以比取得之載體注射一經捕捉之載體注射於光學敏感性材料內者更大之效率自光學敏感性材料取得一流動載體。 The injection contact of the photodetector of an embodiment is constructed to obtain a flow carrier from the optically sensitive material with greater efficiency than the obtained carrier injection once the captured carrier is injected into the optically sensitive material.

一實施例之光檢測器之光學敏感性材料係一種p-型半導體材料。 The optically sensitive material of the photodetector of an embodiment is a p-type semiconductor material.

一實施例之光檢測器之第一觸點包含金屬，且其中第二第二觸點包含 金屬。 In one embodiment, the first contact of the photodetector includes metal, and the second second contact includes metal.

一實施例之光檢測器之偏電壓係於約-0.1伏特至-2.8伏特之範圍，且流動載體係電子。 The bias voltage of the photodetector of an embodiment is in the range of about -0.1 volts to -2.8 volts, and the flow carrier is electrons.

一實施例之光檢測器之光學敏感性材料包含選自PbS、PbSe、PbTe、CdS、CdSe、CdTe、Si、Ge，或C所組成族群之奈米顆粒。 The optically sensitive material of the photodetector according to an embodiment includes nanoparticles selected from the group consisting of PbS, PbSe, PbTe, CdS, CdSe, CdTe, Si, Ge, or C.

一實施例之光檢測器之每一奈米顆粒包含於此奈米顆粒之表面上之氧化物。 Each nanoparticle of the photodetector of an embodiment includes an oxide on the surface of the nanoparticle.

一實施例之光檢測器之光學敏感性層包含選自PbSO4、PbO、PbSeO4、PbTeO4、SiOxNy、In2O3、硫、硫酸鹽、亞碸、碳，及碳酸鹽所組成族群之材料。 The optically sensitive layer of the photodetector of an embodiment includes a material selected from the group consisting of PbSO 4 , PbO, PbSeO 4 , PbTeO 4 , SiO x N y , In 2 O 3 , sulfur, sulfate, sulfonate, carbon, and carbonate. The materials that make up the ethnic group.

一實施例之光檢測器之奈米顆粒係相互連接。 The nanoparticles of the photodetector of one embodiment are connected to each other.

一實施例之光檢測器之注射觸點及拉取觸點每一者包含選自Al、Ag、In、Mg、Ca、Li、Cu、Ni、NiS、TiN，或TaN所組成族群之材料。 Each of the injection contact and the pull contact of the photodetector of an embodiment includes a material selected from the group consisting of Al, Ag, In, Mg, Ca, Li, Cu, Ni, NiS, TiN, or TaN.

一實施例之光檢測器之光學敏感性層具有100至3000nm範圍之與光線之入射方向垂直之尺寸。 The optically sensitive layer of the photodetector of an embodiment has a size in the range of 100 to 3000 nm perpendicular to the incident direction of light.

一實施例之光檢測器之第一載體型式係於黑暗中之主要者，且第二載體型式於照明下係主要者。 The first carrier type of the light detector of one embodiment is the main one in the dark, and the second carrier type is the main one under the illumination.

一實施例之光檢測器之第一載體型式係電洞，且第二載體型式係電子。 In one embodiment of the photodetector, the first carrier type is a hole, and the second carrier type is an electron.

一實施例之光檢測器之第一觸點及第二觸點包含淺功函數之金屬。 The first contact and the second contact of the photodetector of an embodiment include a shallow work function metal.

一實施例之光檢測器之第一觸點及第二觸點每一者具有比4.5ev更淺之功函數。 The first contact and the second contact of the photodetector of an embodiment each have a shallower work function than 4.5ev.

一實施例之光檢測器之第一觸點與第二觸點間之距離係於200nm至2 um之範圍。 The distance between the first contact and the second contact of the photodetector of an embodiment is 200nm to 2 um range.

一實施例之光檢測器之流動載體具有至少1E-5cm2/Vs之移動性。 The flow carrier of the photodetector of an embodiment has a mobility of at least 1E-5cm 2 / Vs.

一實施例之光檢測器之p-型半導體材料係經摻雜之p-型材料。 The p-type semiconductor material of the photodetector of an embodiment is a doped p-type material.

一實施例之光檢測器之偏電壓係於約+0.1伏特至+2.8伏特之範圍，且流動載體係電洞。 The bias voltage of the photodetector of an embodiment is in the range of about +0.1 volts to +2.8 volts, and the flow carrier is a hole.

一實施例之光檢測器之注射觸點及拉取觸點每一者包含選自An、Pt、Pd、Cu、Ni、NiS、TiN及TaN所組成族群之材料。 Each of the injection contact and the pull contact of the photodetector of an embodiment includes a material selected from the group consisting of An, Pt, Pd, Cu, Ni, NiS, TiN, and TaN.

一實施例之光檢測器之第一載體型式係黑暗之主要者，且一實施例之光檢測器之第二載體型式係照明下之主要者。 The first carrier type of the photodetector of one embodiment is the main one in darkness, and the second carrier type of the photodetector of one embodiment is the main one under illumination.

一實施例之光檢測器之第一載體型式係電極，且第二載體型式係電洞。 In one embodiment of the photodetector, the first carrier type is an electrode, and the second carrier type is a hole.

一實施例之光檢測器之第一觸點及第二觸點包含深功函數之金屬。 In one embodiment, the first contact and the second contact of the photodetector include a deep work function metal.

一實施例之光檢測器之第一觸點及第二觸點每一者具有比4.5ev更深之功函數。 Each of the first contact and the second contact of the photodetector of an embodiment has a deeper work function than 4.5ev.

一實施例之光檢測器n-型半導體材料係經摻雜之n-型材料。 One embodiment of the photodetector n-type semiconductor material is a doped n-type material.

一實施例之光檢測器之光學敏感性材料具有比第一觸點及第二觸點之功函數更深至少0.3ev之功函數。 The optically sensitive material of the photodetector of an embodiment has a work function that is at least 0.3 ev deeper than the work functions of the first contact and the second contact.

一實施例之光檢測器之第一觸點及第二觸點每一者包含選自Al、Ag、In、Mg、Ca、Li、Cu、Ni、NiS、TiN、TaN、n-型聚矽及n-型非結晶矽所組成族群之材料。 Each of the first contact and the second contact of the photodetector of an embodiment includes a polysilicon selected from Al, Ag, In, Mg, Ca, Li, Cu, Ni, NiS, TiN, TaN, n-type And n-type amorphous silicon group materials.

此間所述之實施例包含一種光檢測器，其包含：一第一觸點及一第二觸點；一位於第一觸點與第二觸點間之光學敏感性材料，光學敏感性材料包含一n-型半導體；第一觸點及第二觸點每一者具有比4.5ev更深之功函 數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；且光學敏感性材料被建構以於偏電壓施加於第一觸點與第二觸點間時提供光導性增益及至少0.4A/W之響應度。 The embodiment described herein includes a photodetector including: a first contact and a second contact; an optically sensitive material between the first contact and the second contact, the optically sensitive material including An n-type semiconductor; each of the first contact and the second contact has a deeper work function than 4.5ev The circuit is constructed to apply a bias voltage between the first contact and the second contact; and the optically sensitive material is constructed to provide a photoconductive gain when the bias voltage is applied between the first contact and the second contact And a response of at least 0.4A / W.

一實施例之光檢測器之光學敏感性材料具有比第一觸點及第二觸點之功函數更淺至少0.3ev之功函數。 The optically sensitive material of the photodetector of an embodiment has a work function that is shallower than that of the first contact and the second contact by at least 0.3 ev.

一實施例之光檢測器之第一觸點及第二觸點每一者包含選自Au、Pt、Pd、Cu、Ni、NiS、TiN、TaN、p-型聚矽，及p-型非結晶矽所組成族群之材料。 The first contact and the second contact of the photodetector of an embodiment each include a member selected from Au, Pt, Pd, Cu, Ni, NiS, TiN, TaN, p-type polysilicon, and p-type Material of ethnic groups composed of crystalline silicon.

此間所述之實施例包含一種光電晶體，包含：一第一觸點及一第二觸點；一位於第一觸點與第二觸點間之光學敏感性材料，光學敏感性材料包含一n-型半導體；第一觸點及第二觸點每一者具有肖特基接觸或比4.5ev更深之功函數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；且光學敏感性材料具有一大於當偏電壓施加於第一觸點與第二觸點間時從第一觸點至第二觸點之電洞運行時間之電洞壽命。 The embodiment described here includes a photoelectric crystal, including: a first contact and a second contact; an optically sensitive material between the first contact and the second contact, the optically sensitive material including an n -Type semiconductor; each of the first contact and the second contact has a Schottky contact or a deeper work function than 4.5ev; the circuit is constructed to apply a bias voltage between the first contact and the second contact; Moreover, the optically sensitive material has a hole lifetime that is greater than the running time of the hole from the first contact to the second contact when a bias voltage is applied between the first contact and the second contact.

一實施例之光檢測器之流動載體係電洞，且經捕捉之載體係電子。 In one embodiment, the flow carrier of the photodetector is a hole, and the captured carrier is an electron.

此間所述之實施例包含一種光電晶體，其包含：一第一觸點及一第二觸點；一位於第一觸點與第二觸點間之光學敏感性材料，光學敏感性材料包含一p-型半導體；第一觸點及第二觸點每一者具有肖特基接觸或比4.5eV更淺之功函數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；且當此偏電壓施加於第一觸點與第二觸點間時，光學敏感性材料具有一電子壽命；其中，光學敏感性材料之電子移動性、第一觸點與第二觸點間之距離，及偏電壓被選擇以使當此偏電壓被施加於第一觸點與第二觸點間時， 從第一觸點至第二觸點之電子運行時間係少於電子壽命。 The embodiment described herein includes a photoelectric crystal including: a first contact and a second contact; an optically sensitive material between the first contact and the second contact, the optically sensitive material including a p-type semiconductor; each of the first contact and the second contact has a Schottky contact or a work function shallower than 4.5 eV; the circuit is constructed to apply a bias between the first contact and the second contact Voltage; and when this bias voltage is applied between the first contact and the second contact, the optically sensitive material has an electron lifetime; wherein, the electron mobility of the optically sensitive material, the first contact and the second contact The distance between, and the bias voltage is selected so that when this bias voltage is applied between the first contact and the second contact, The electronic running time from the first contact to the second contact is less than the electronic lifetime.

一實施例之光檢測器之流動電荷係電子，且經捕捉之載體係電洞。 In one embodiment of the photodetector, the mobile charges are electrons, and the captured carriers are holes.

此間所述之實施例包含一種光電晶體，其包含：一第一觸點及一第二觸點；一位於第一觸點與第二觸點間之光學敏感性材料，光學敏感性材料包含一n-型半導體；第一觸點及第二觸點每一者具有肖特基接觸或比4.5ev更深之功函數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；當偏電壓施加於第一觸點與第二觸點間時，光學敏感性材料具有一電洞壽命；其中，光學敏感性材料之電洞移動性、第一觸點與第二觸點間之距離，及偏電壓被選擇以便當偏電壓施加於第一觸點與第二觸點間時，從第一觸點至第二觸點之電洞運行時間少於電洞壽命。 The embodiment described herein includes a photoelectric crystal including: a first contact and a second contact; an optically sensitive material between the first contact and the second contact, the optically sensitive material including a n-type semiconductor; each of the first contact and the second contact has a Schottky contact or a deeper work function than 4.5ev; the circuit is constructed to apply a bias voltage between the first contact and the second contact ; When a bias voltage is applied between the first contact and the second contact, the optically sensitive material has a hole life; wherein, the hole mobility of the optically sensitive material, between the first contact and the second contact The distance and the bias voltage are selected so that when the bias voltage is applied between the first contact and the second contact, the hole running time from the first contact to the second contact is less than the hole lifetime.

一實施例之光檢測器之流動載體係電洞，且經捕捉之載體係電子。 In one embodiment, the flow carrier of the photodetector is a hole, and the captured carrier is an electron.

一實施例之光檢測器包含一包含p-摻雜之矽之p-型半導體。 The photodetector of an embodiment includes a p-type semiconductor including p-doped silicon.

一實施例之光檢測器包含一包含GaAs之p-型半導體。 The photodetector of an embodiment includes a p-type semiconductor including GaAs.

一實施例之光檢測器包含一包含量子點/奈米結晶之p-型半導體。 The photodetector of an embodiment includes a p-type semiconductor including quantum dots / nanocrystals.

一實施例之光檢測器包含一包含一相互連接奈米結晶網絡之p-型半導體。 An embodiment of the photodetector includes a p-type semiconductor including a nanocrystal network interconnected.

一實施例之光檢測器包含一包含奈米結晶及結合劑分子之p-型半導體。 The photodetector of an embodiment includes a p-type semiconductor including nanocrystals and binder molecules.

一實施例之光檢測器包含一包含一化合物半導體之p-型半導體。 The photodetector of an embodiment includes a p-type semiconductor including a compound semiconductor.

一實施例之光檢測器包含一包含PbS、具PbSO3之PbS之p-型半導體。 An embodiment of the photodetector includes a p-type semiconductor including PbS and PbS with PbSO 3 .

此間所述之實施例包含一種光學敏感性裝置，其包含：一第一觸點及一第二觸點，每一者具有一功函數；一位於第一觸點與第二觸點間之光學敏感性材料；光學敏感性材料包含一p-型半導體，且光學敏感性材料具有一 功函數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；光學敏感性材料之功函數之數量係比第一觸點之功函數之數量大至少0.4eV；且亦比第二觸點之功函數之數量大至少0.4eV；光學敏感性材料具有一大於當偏電壓施加於第一觸點與第二觸點之間時從第一觸點至第二觸點之電子運行時間之電子壽命；第一觸點提供電子之注射及阻絕電洞之擷取；且第一觸點與光學敏感性材料間之界面提供少於1cm/s之表面重組速率。 The embodiment described herein includes an optically sensitive device including: a first contact and a second contact, each having a work function; an optical between the first contact and the second contact Sensitive material; the optically sensitive material includes a p-type semiconductor, and the optically sensitive material has a Work function; the circuit is constructed to apply a bias voltage between the first contact and the second contact; the number of work functions of the optically sensitive material is at least 0.4 eV greater than the number of work functions of the first contact; and At least 0.4 eV greater than the number of work functions of the second contact; the optically sensitive material has a value greater than that from the first contact to the second contact when a bias voltage is applied between the first contact and the second contact The electron lifetime of the electronic run time; the first contact provides injection of electrons and the blocking of holes; and the interface between the first contact and the optically sensitive material provides a surface reorganization rate of less than 1 cm / s.

一實施例之裝置之第一觸點及第二觸點之功函數每一者係比4.5ev更淺。 The work function of the first contact and the second contact of the device of an embodiment are each shallower than 4.5 ev.

一實施例之裝置之偏電壓係於約-0.1伏特至-2.8伏特之範圍。 The bias voltage of the device of one embodiment is in the range of about -0.1 volts to -2.8 volts.

一實施例之裝置之光學敏感性材料包含多數個奈米顆粒，其中，每一奈米顆粒具有於個別奈米顆粒之表面上之氧化物。 The optically sensitive material of the device of an embodiment includes a plurality of nanoparticles, wherein each nanoparticle has an oxide on the surface of the individual nanoparticles.

一實施例之裝置之光學敏感性材料包含選自PbS、PbSe、PbTe、CdS、CdSe、CdTe、Si、Ge，或C所組成族群之奈米顆粒。 The optically sensitive material of the device of one embodiment includes nanoparticles selected from the group consisting of PbS, PbSe, PbTe, CdS, CdSe, CdTe, Si, Ge, or C.

一實施例之裝置之光學敏感性層包含選自PbSO4、PbO、PbSeO4、PbTeO4、SiOxNy、In2O3、硫、硫酸鹽、亞碸、碳，及碳酸鹽所組成族群之材料。 The optically sensitive layer of the device of an embodiment includes a group selected from the group consisting of PbSO 4 , PbO, PbSeO 4 , PbTeO 4 , SiO x N y , In 2 O 3 , sulfur, sulfate, sulfonate, carbon, and carbonate Of material.

一實施例之裝置之光學敏感性材料包含多數個相互連接之奈米顆粒。 The optically sensitive material of the device of one embodiment includes a plurality of interconnected nanoparticles.

一實施例之裝置之第一觸點及第二觸點每一者包含選自Al、Ag、In、Mg、Ca、Li、Cu、Ni、NiS、TiN，或TaN所組成族群之材料。 Each of the first contact and the second contact of the device of one embodiment includes a material selected from the group consisting of Al, Ag, In, Mg, Ca, Li, Cu, Ni, NiS, TiN, or TaN.

一實施例之裝置之第一觸點及第二觸點係以200nm至2um範圍之距離間隔，且光學敏感性材料內之電子移動性係至少1E-5cm2/Vs。 The first contact and the second contact of the device of an embodiment are separated by a distance ranging from 200 nm to 2 um, and the electron mobility in the optically sensitive material is at least 1E-5 cm 2 / Vs.

一實施例之裝置之光學敏感性材料被建構以於偏電壓施加於第一觸點 與第二觸點間時提供至少0.8A/W之響應度。 The optically sensitive material of the device of an embodiment is constructed to apply a bias voltage to the first contact Provide a response of at least 0.8A / W with the second contact.

此間所述之實施例包含一種光學敏感性裝置，其包含：一第一觸點；一n-型半導體；一包含一p-型半導體之光學敏感性材料；一第二觸點；光學敏感性材料及第二觸點每一者具有一比4.5ev更淺之功函數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；光學敏感性材料具有一大於當偏電壓施加於第一觸點與第二觸點間時從第一觸點至第二觸點之電子運行時間之電子壽命；第一觸點提供電子之注射及阻絕電洞之擷取；且第一觸點與光學敏感性材料間之界面提供少於1cm/s之表面重組速率。 The embodiments described herein include an optically sensitive device including: a first contact; an n-type semiconductor; an optically sensitive material including a p-type semiconductor; a second contact; optical sensitivity The material and the second contact each have a shallower work function than 4.5ev; the circuit is constructed to apply a bias voltage between the first contact and the second contact; the optically sensitive material has a greater than the current bias voltage The electronic lifetime of the electron running time from the first contact to the second contact when applied between the first contact and the second contact; the first contact provides injection of electrons and blocking of the extraction of holes; and the first The interface between the contact and the optically sensitive material provides a surface reorganization rate of less than 1 cm / s.

一實施例之裝置之n-型半導體包含選自TiO2、經化學還原之TiO2、經氧化之TiO2、CdTe、CdS、CdSe、Si，或選自PbS、PbSe、PbTe、CdS、CdSe、CdTe、Si、Ge，或C所組成族群之奈米顆粒所組成族群之材料。 The n-type semiconductor of the device of an embodiment includes TiO 2 , chemically reduced TiO 2 , oxidized TiO 2 , CdTe, CdS, CdSe, Si, or PbS, PbSe, PbTe, CdS, CdSe, CdTe, Si, Ge, or C group of nano-particles composed of materials.

一實施例之裝置之偏電壓係於約-0.1伏特至-2.8伏特之範圍。 The bias voltage of the device of one embodiment is in the range of about -0.1 volts to -2.8 volts.

一實施例之裝置之光學敏感性材料包含多數個奈米顆粒，其中，每一奈米顆粒具有於個別奈米顆粒之表面上之氧化物。 The optically sensitive material of the device of an embodiment includes a plurality of nanoparticles, wherein each nanoparticle has an oxide on the surface of the individual nanoparticles.

一實施例之裝置之光學敏感性材料包含選自PbS、PbSe、PbTe、CdS、CdSe、CdTe、Si、Ge，或C所組成族群之奈米顆粒。 The optically sensitive material of the device of one embodiment includes nanoparticles selected from the group consisting of PbS, PbSe, PbTe, CdS, CdSe, CdTe, Si, Ge, or C.

一實施例之裝置之光學敏感性材料包含多數個相互連接之奈米顆粒。 The optically sensitive material of the device of one embodiment includes a plurality of interconnected nanoparticles.

一實施例之裝置之第一觸點及第二觸點係以200nm至2um範圍之距離分隔。 The first contact and the second contact of the device of an embodiment are separated by a distance ranging from 200 nm to 2 um.

此間所述之實施例包含一種光檢測器，其包含：一第一觸點及一第二觸點，每一者具有一功函數；一位於第一觸點及第二觸點間之光學敏感性材料，光學敏感性材料包含一p-型半導體，且光學敏感性材料具有一功函 數；電路被建構以於第一觸點與第二觸點間施加一偏電壓；光學敏感性材料之功函數之數量係比第一觸點之功函數之數量大至少0.4eV，且亦比第二觸點之功函數之數量大至少0.4eV；電路被建構以於第一觸點與第二觸點間施加一偏電壓；且光學敏感性材料被建構以於偏電壓施加於第一觸點與第二觸點間時提供至少0.8A/W之響應度。 The embodiments described herein include a photodetector, which includes: a first contact and a second contact, each of which has a work function; an optical sensitivity between the first contact and the second contact Material, the optically sensitive material includes a p-type semiconductor, and the optically sensitive material has a work function The circuit is constructed to apply a bias voltage between the first contact and the second contact; the number of work functions of the optically sensitive material is at least 0.4 eV greater than the number of work functions of the first contact, and is also The number of work functions of the second contact is at least 0.4 eV; the circuit is constructed to apply a bias voltage between the first contact and the second contact; and the optically sensitive material is constructed to apply the bias voltage to the first contact Provide a response of at least 0.8A / W between the point and the second contact.

一實施例之光檢測器之第一觸點及第二觸點之功函數每一者係比4.5ev更淺。 The work function of the first contact and the second contact of the photodetector of an embodiment are each shallower than 4.5 ev.

一實施例之光檢測器之偏電壓係約-0.1伏特至-2.8伏特之範圍。 The bias voltage of the photodetector of an embodiment is in the range of about -0.1 volts to -2.8 volts.

一實施例之光檢測器之光學敏感性材料包含選自PbS、PbSe、PbTe、CdS、CdSe、CdTe、Si、Ge，或C所組成族群之奈米顆粒。 The optically sensitive material of the photodetector according to an embodiment includes nanoparticles selected from the group consisting of PbS, PbSe, PbTe, CdS, CdSe, CdTe, Si, Ge, or C.

一實施例之光檢測器之光學敏感性層包含選自PbSO4、PbO、PbSeO4、PbTeO4、SiOxNy、In2O3、硫、硫酸鹽、亞碸、碳，及碳酸鹽所組成族群之材料。 The optically sensitive layer of the photodetector of an embodiment includes a material selected from the group consisting of PbSO 4 , PbO, PbSeO 4 , PbTeO 4 , SiO x N y , In 2 O 3 , sulfur, sulfate, sulfonate, carbon, and carbonate. The materials that make up the ethnic group.

一實施例之光檢測器之第一觸點及第二觸點每一者包含選自Al、Ag、In、Mg、Ca、Li、Cu、Ni、NiS、TiN，或TaN所組成族群之材料。 Each of the first contact and the second contact of the photodetector of an embodiment includes a material selected from the group consisting of Al, Ag, In, Mg, Ca, Li, Cu, Ni, NiS, TiN, or TaN .

一實施例之光檢測器之第一觸點及第二觸點係以200nm至2um範圍之距離分隔，且光學敏感性材料內之電子移動性係至少1E-5cm2/Vs。 The first contact and the second contact of the photodetector of an embodiment are separated by a distance ranging from 200 nm to 2 um, and the electron mobility in the optically sensitive material is at least 1E-5cm 2 / Vs.

除非此內容明確需要其它外，於全部之說明內容及申請專利範圍中，”包含”一辭係以與排除或詳盡之意思相反之含有之意思解釋；即，以"不受限地包含"之意思。使用單數或複數之字亦個別包含複數或單數。另外，"此間"、"於下"、"之上"、"之下"之字及相似含意之字當用於本申請案時係指本申請案之全部且非指此申請案之任何特別部份。當"或"一字係用以指二或更多 項目之列示時，此字包含此字之所有下列解釋：此列示中之項目之任一者，此列示中之項目之所有者，及此列示中之項目之任何組合。 Unless the content clearly requires anything else, in all descriptions and patent applications, the word "include" is interpreted with the meaning of inclusion contrary to the meaning of exclusion or exhaustion; that is, with "without limitation" meaning. Words using the singular or plural number also individually include the plural or singular number. In addition, the words "here", "below", "above", "below" and similar meanings when used in this application refer to the entirety of this application and do not refer to any special features of this application Partly. When the word "or" is used to refer to two or more When listing items, this word includes all the following interpretations of the word: any of the items in this list, the owner of the items in this list, and any combination of the items in this list.

如上之實施例說明非意指係詳盡或使此等系統或方法限於所揭露之確切型式。雖然特別實施例及此等實施例之範例於此用以例示說明而被描，如熟習此項技藝者所認知，各種相等之改良於此等系統及方法之範圍內係可能。此間提供之實施例之教示可應用於其它系統及方法，而非僅於如上所述之系統及方法。 The above embodiment description is not meant to be exhaustive or to limit such systems or methods to the exact type disclosed. Although specific embodiments and examples of these embodiments are described herein for illustrative purposes, as those skilled in the art recognize, various equivalent improvements are possible within the scope of these systems and methods. The teachings of the embodiments provided herein can be applied to other systems and methods, not just the systems and methods described above.

上述各種實施例之元素及動作可被結合而提供其它實施例。此等及其它之改變可基於如上之詳細說明而對實施例為之。 The elements and actions of the various embodiments described above can be combined to provide other embodiments. These and other changes can be made to the embodiment based on the detailed description above.

1,2,3,4,5,6‧‧‧材料 1,2,3,4,5,6‧‧‧ materials

1220‧‧‧量子點 1220‧‧‧ Quantum dots

1221‧‧‧殼 1221‧‧‧Shell

Claims (27)

一種光學敏感性裝置，包含：一基材；及至少一像素，該至少一像素包含一實質上垂直的堆疊物，其包括：一第一導體，其側面地相鄰一第一絕緣物；一第一界面材料；一光敏性層，該光敏性層包括一交聯分子且其中該交聯分子中至少一官能基結合至該第一界面材料，該光敏性層包括一肖特基(Sehottky)接觸，其中電子將以高效率被提取且電洞將以低效率被注射；一第二界面材料；及一實質上透明之傳導層。 An optically sensitive device, comprising: a substrate; and at least one pixel, the at least one pixel comprising a substantially vertical stack including: a first conductor laterally adjacent to a first insulator; one A first interface material; a photosensitive layer, the photosensitive layer includes a cross-linked molecule and wherein at least one functional group in the cross-linked molecule is bonded to the first interface material, the photosensitive layer includes a Schottky (Sehottky) Contact, where electrons will be extracted with high efficiency and holes will be injected with low efficiency; a second interface material; and a substantially transparent conductive layer. 如請求項1之光學敏感性裝置，其中該基材係一矽積體化電路。 The optical sensitive device according to claim 1, wherein the substrate is a silicon integrated circuit. 如請求項1之光學敏感性裝置，其中該第一導體包括一金屬。 The optically sensitive device of claim 1, wherein the first conductor includes a metal. 如請求項1之光學敏感性裝置，其中該第一導體包括選自於一材料列表之一材料，該材料列表包括：TiN、TiO2、TixNy、Al、Au、Pt、Ni、Pd、ITO、Cu、Ru、TiSi、WSi2、Ga、In、Sn、Pb、Bi、Mg、Ca、Zn、Mo、Ti、Va、La、Cr、Mn、Fe、Co、Zr、Nb、Ag、Hf、Ta、W、Ir，及其等之組合。 The optically sensitive device of claim 1, wherein the first conductor includes a material selected from a material list including: TiN, TiO 2 , Ti x N y , Al, Au, Pt, Ni, Pd , ITO, Cu, Ru, TiSi, WSi 2 , Ga, In, Sn, Pb, Bi, Mg, Ca, Zn, Mo, Ti, Va, La, Cr, Mn, Fe, Co, Zr, Nb, Ag, Hf, Ta, W, Ir, and their combinations. 如請求項1之光學敏感性裝置，其中該第一導體包括TiN，及其中該第一導體係以TiOxNy終結。 The optically sensitive device of claim 1, wherein the first conductor includes TiN, and wherein the first conductive system is terminated with TiO x N y . 如請求項1之光學敏感性裝置，其中該第一界面材料包括至少選自於一材料列表之一材料，該材料列表包括：該導體之一純淨表面、TiO2、 TiOxNy、Al2O3、Au2O3、PtO、PtO2、Ni2O3、WO3、PdO、富氧之ITO；TiN、TiO2、TixNy、Al、Au、Pt、Ni、Pd、ITO、Cu、Ru、TiSi、WSi2、Ga、In、Sn、Pb、Bi、Mg、Ca、Zn、Mo、Ti、Va、La、Cr、Mn、Fe、Co、Zr、Nb、Ag、Hf、Ta、W、Ir之氧化物、氮化物或氧氮化物，及其等之組合。 The optical sensitive device according to claim 1, wherein the first interface material includes at least one material selected from a material list including: a pure surface of the conductor, TiO 2 , TiO x N y , Al 2 O 3 , Au 2 O 3 , PtO, PtO 2 , Ni 2 O 3 , WO 3 , PdO, oxygen-rich ITO; TiN, TiO 2 , Ti x N y , Al, Au, Pt, Ni, Pd, ITO, Cu, Ru, TiSi, WSi 2 , Ga, In, Sn, Pb, Bi, Mg, Ca, Zn, Mo, Ti, Va, La, Cr, Mn, Fe, Co, Zr, Nb, Ag, Hf, Ta , W, Ir oxides, nitrides or oxynitrides, and combinations thereof. 如請求項6之光學敏感性裝置，其中，一個氧化物厚度係於小於5nm之範圍內。 The optically sensitive device according to claim 6, wherein one oxide thickness is within a range of less than 5 nm. 如請求項6之光學敏感性裝置，其中一總氧化物厚度係於2至20nm之範圍內。 As in the optically sensitive device of claim 6, a total oxide thickness is in the range of 2 to 20 nm. 如請求項1之光學敏感性裝置，其中該第一界面材料包括一n-型金屬氧化物。 The optically sensitive device of claim 1, wherein the first interface material includes an n-type metal oxide. 如請求項1之光學敏感性裝置，其中該第一界面材料包括吸附之有機物。 The optically sensitive device of claim 1, wherein the first interface material includes adsorbed organic matter. 如請求項1之光學敏感性裝置，其中一異質接面係於該第一界面材料及該光敏性層之間形成。 The optically sensitive device of claim 1, wherein a heterojunction is formed between the first interface material and the photosensitive layer. 如請求項1之光學敏感性裝置，其中該第一界面材料包括一黏著層。 The optically sensitive device of claim 1, wherein the first interface material includes an adhesive layer. 如請求項1之光學敏感性裝置，其中該第一界面材料包括一經摻雜之導性氧化物。 The optically sensitive device of claim 1, wherein the first interface material includes a doped conductive oxide. 如請求項1之光學敏感性裝置，其中該光敏性層包括至少一量子點。 The optically sensitive device according to claim 1, wherein the photosensitive layer includes at least one quantum dot. 如請求項1之光學敏感性裝置，其中該第二界面材料提供底下材料之鈍化。 The optically sensitive device of claim 1, wherein the second interface material provides passivation of the underlying material. 如請求項1之光學敏感性裝置，其中該第二界面材料最小化物種於該第一導體、該第一界面材料與該光敏性層之間的移動。 The optically sensitive device of claim 1, wherein the second interface material minimizes the movement of species between the first conductor, the first interface material, and the photosensitive layer. 如請求項1之光學敏感性裝置，其中該第二界面材料最小化物種於該第一導體、該第一界面材料及該光敏性層中至少一者與材料堆疊物之外側之間的移動。 The optically sensitive device of claim 1, wherein the second interface material minimizes the movement of species between at least one of the first conductor, the first interface material, and the photosensitive layer and the outer side of the material stack. 如請求項1之光學敏感性裝置，其中該第二界面材料促進與疊置層之物理性黏著，該疊置層係諸如封裝層。 The optically sensitive device of claim 1, wherein the second interface material promotes physical adhesion with an overlay layer, such as an encapsulation layer. 如請求項1之光學敏感性裝置，其中該第二界面材料係與至少選自於一材料列表之一材料被封裝，該材料列表包括：電漿加強化學蒸氣沈積(PECVD)之SiO2、SiN，及SiOCN，其提供一實質上光學透明性膜。 The optically sensitive device according to claim 1, wherein the second interface material is encapsulated with at least one material selected from a material list including: SiO 2 and SiN of plasma enhanced chemical vapor deposition (PECVD) , And SiOCN, which provide a substantially optically transparent film. 如請求項1之光學敏感性裝置，其中該光敏性層包括至少選自於一材料列表之一材料，該材料列表包括：矽、單結晶矽、多結晶矽、奈米結晶矽、非結晶矽，及氫化之非結晶矽。 The optically sensitive device according to claim 1, wherein the photosensitive layer includes at least one material selected from a material list including: silicon, monocrystalline silicon, polycrystalline silicon, nanocrystalline silicon, amorphous silicon , And hydrogenated amorphous silicon. 如請求項1之光學敏感性裝置，其中該光敏性層包括至少選自於一材料列表之一材料，該材料列表包括：矽、鎵、砷、碳、PbS、PbSe、PbTe、Bi2S3、In2S3、銅-銦-鎵-硒化物、銅-銦-鎵-硫化物、SnS、SnSe，及SnTe。 The optically sensitive device according to claim 1, wherein the photosensitive layer includes at least one material selected from a material list including: silicon, gallium, arsenic, carbon, PbS, PbSe, PbTe, Bi 2 S 3 , In 2 S 3 , copper-indium-gallium-selenide, copper-indium-gallium-sulfide, SnS, SnSe, and SnTe. 如請求項1之光學敏感性裝置，其中於操作偏壓時，有效率地自該光敏性層之導電帶擷取該電子；以及於此相同偏壓，係以遠較低之功效使該電洞注射於該光敏性層之價電帶內。 The optically sensitive device according to claim 1, wherein the electrons are efficiently extracted from the conductive band of the photosensitive layer when the bias voltage is operated; and the same bias voltage makes the hole with much lower efficiency It is injected into the valence band of the photosensitive layer. 如請求項1之光學敏感性裝置，其中該第一界面材料係使一種電荷載體流動，同時阻絕另一種(諸如，電子)之流動，該電荷載體係諸如電洞。 The optically sensitive device of claim 1, wherein the first interface material causes one charge carrier to flow while blocking the flow of another (such as electrons), and the charge carrier is such as a hole. 如請求項1之光學敏感性裝置，其中該第一界面材料之一側固定於底下層；且另一側固定於該光敏性層。 The optically sensitive device of claim 1, wherein one side of the first interface material is fixed to the underlying layer; and the other side is fixed to the photosensitive layer. 如請求項24之光學敏感性裝置，其中該第一界面材料係於構成該像素之 材料間提供受控制之電子通訊。 The optically sensitive device according to claim 24, wherein the first interface material is composed of the pixels Provide controlled electronic communication between materials. 如請求項24之光學敏感性裝置，其中該第一界面材料係於構成該像素之材料間提供黏著。 The optical sensitive device of claim 24, wherein the first interface material provides adhesion between the materials constituting the pixel. 如請求項1之光學敏感性裝置，其中該第一界面材料提供該光敏性層與該第一導體之強烈鍵結。 The optically sensitive device of claim 1, wherein the first interface material provides strong bonding of the photosensitive layer and the first conductor.
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