TWI610427B - 用於影像感測器之感光性電容畫素 - Google Patents

用於影像感測器之感光性電容畫素 Download PDF

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TWI610427B
TWI610427B TW106116443A TW106116443A TWI610427B TW I610427 B TWI610427 B TW I610427B TW 106116443 A TW106116443 A TW 106116443A TW 106116443 A TW106116443 A TW 106116443A TW I610427 B TWI610427 B TW I610427B
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photosensitive
layer
cavity
transistor
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楊武璋
劉家穎
熊志偉
艾群詠
H 戴戴森
麥西堤多明尼克
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豪威科技股份有限公司
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Abstract

本發明揭示一種影像感測器畫素及影像感測器及一種製造影像感測器畫素及影像感測器之方法。該影像畫素包含一感光性電容器及一電晶體網路。該感光性電容器包含一電極、一導電層、一介電層及一感光性半導體材料。該導電層經安置於該電極周圍，且該介電層形成於該導電層與該電極之間。該感光性半導體材料係用於回應於影像光產生一影像信號且經安置於該介電層與該電極之間。該電晶體網路經耦合以從該感光性電容器之該電極讀出該影像信號。

Description

用於影像感測器之感光性電容畫素
本發明大體上係指影像感測，且特定言之係指作為一影像感測器內之一畫素或若干畫素之一感光性電容器。
一影像感測器係將光(呈一光學影像之形式)轉換為電子信號之一電子裝置。現代影像感測器一般為半導體電荷耦合裝置(「CCD」)或使用互補金屬氧化物半導體(「CMOS」)技術製造之主動畫素感測器。 在許多現代電子裝置中CMOS影像感測器已變得普遍存在。蜂巢式電話、膝上型電腦及相機皆可利用CMOS影像感測器作為影像/光偵測之一主要方法。裝置製造者正努力減小成本及提高影像感測器之效能以滿足零售及商業需求。現有CMOS影像感測器製造與標準CMOS製造程序不同，其為製造影像感測器添加額外之步驟、時間及成本。
本文中描述一感測器畫素及包含一感光性電容器之一影像感測器之實施例。在本發明中亦描述製造且操作包含一感光性電容器之一畫素之方法。在下列描述中，提出數種特定細節以提供對該等實施例之通透理解。然而，熟習相關技術者將認識到，可在無需使用特定細節中之一或多者或使用其他方法、組件、材料等等的情況下實踐本文描述之技術。在其他例項中，未詳細展示或描述熟知之結構、材料或操作以避免使特定態樣模糊。 貫穿此說明書，對「一項實施例」或「一實施例」之參考意謂，結合該實施例描述之一特定特徵、結構或特性包含於本發明之至少一項實施例中。因此，貫穿此說明書，各種位置中出現之短語「在一項實施例中」或「在一實施例中」並不必要皆係指代相同實施例。此外，特定特徵、結構或特性可在一或多個實施例中以任何適當方式組合。 圖1為示意性繪示根據本發明之一實施例之一成像系統100之一個實例之一方塊圖，成像系統100包含感光性電容器畫素之一畫素陣列102。成像系統100包含一畫素陣列102、控制電路108、讀出電路104及功能邏輯106。如所描繪之實例中展示，成像系統100包含耦合至控制電路108之畫素陣列102及讀出電路104。讀出電路104經耦合至功能邏輯106。控制電路108耦合至畫素陣列102以控制畫素陣列102之操作特性，以便擷取藉由由畫素陣列102接收之影像光所產生之影像。舉例而言，控制電路108可產生用於控制影像獲取之一快門信號或複數個快門信號。 在一個實例中，畫素陣列102係成像感測器或畫素110 (例如，畫素P1、P2……Pn)之一二維(2D)陣列。在一個實例中，各畫素110包含一感光性電容器，其耦合至電晶體以促進讀出。如繪示，各畫素110經配置成一列(例如，列R1至Ry)及一行(例如，行C1至Cx)以獲取一人、位置、物件等等之影像資料，該等影像資料可接著用於呈現該人、位置、物件等等之一影像。 在一個實例中，在各畫素110已獲取其影像資料或影像電荷之後，影像資料藉由讀出電路104透過讀出行112讀出且接著轉移至功能邏輯106。在各種實例中，讀出電路104可包含放大電路、類比數位轉換(ADC)電路或其他。功能邏輯106可僅儲存影像資料或甚至藉由應用後影像效應(例如，剪裁、旋轉、移除紅眼、調整亮度、調整對比度或其他)來操縱影像資料。在一個實例中，讀出電路104可沿著讀出行線一次讀出一列影像資料(已繪示)或可使用各種其他技術讀出影像資料(未繪示)，諸如一串列讀出或同時完全並行讀出所有畫素。 圖2繪示根據本發明之一實施例之包含於一畫素210中之一感光性電容器230之一實例之一橫截面。畫素210為畫素110之一個實例。畫素210包含一感光性電容器230，感光性電容器230包含電極235、導電層233、介電層232及感光性半導體材料231。電極235用作感光性電容器230之一個導體或「板」，且導電層233用作感光性電容器230之第二導體或「板」。在一項實施例中，導電層233經塑形為如同一管。介電層232使導電層233與感光性半導體材料231隔離，感光性半導體材料231安置於電極235與介電層232之間。在一項實施例中，感光性半導體材料231包含低溫多晶矽。在一項實施例中，感光性半導體材料231包含非晶多晶矽。非晶多晶矽一般阻斷大於650 nm之波長。使用非晶多晶矽作為感光性半導體材料231可能容許消除畫素410上方之一紅外濾波器以拒絕非可見光譜上之光。導電層233可為一金屬，諸如氮化鈦(「TiN」)或氮化鉭(「TaN」)。 在操作中，感光性半導體材料231沿電極235沿著其延伸之一軸接收影像光205。影像光205可在遇到感光性半導體材料231之前傳播通過鈍化層243。影像光205亦可在遇到感光性半導體材料231之前通過未知之額外光學器件(例如，透鏡)及濾波器(例如，彩色濾光器)。感光性半導體材料231回應於接收影像光205產生呈光電子形式之一影像信號。該等光電子經由電極235 (且經由所繪示之實施例中之金屬連接件236)流動至儲存節點221。在一曝光持續時間(亦稱為一「積分週期」)之後，由電荷儲存節點221中之影像信號產生之影像電荷可經轉移至浮動汲極223且最終藉由讀出電路讀出。轉移電晶體641包含閘極227、電荷儲存節點221及浮動擴散223。為將影像電荷從電荷儲存節點221轉移至浮動擴散223，藉由將一電壓施加至閘極227啟動轉移電晶體641。一般言之，一負電壓將啟動一P型電晶體而一正電壓(超過臨限電壓)將啟動一N型電晶體。 在圖2中，沿著半導體基板280之一前側281安置轉移電晶體641。前側281與半導體基板280之一背側282相對。半導體基板280可為P摻雜矽，且儲存節點221及浮動擴散223可為N摻雜。圖2展示畫素210為前側照明畫素，且熟習此項技術者可將包含於一畫素陣列210中之一影像感測器視為一前側照明影像感測器，此係因為影像光205將在遇到背側282之前遇到基板280之前側281。相比之下，背側照明影像感測器通常薄化半導體基板之背側，使得儲存節點221 (用作一光電二極體)從半導體基板之經薄化背側接收影像光。具有習知光電二極體畫素之背側照明影像感測器通常提供比具有習知光電二極體畫素之前側照明影像感測器更佳之光學效率，此係因為一影像光不必行進通過吸收一部分影像光之一互連層(用於控制光電二極體之讀出)。 在圖2中，影像光205不必通過一互連層行進至一光電二極體。實情係影像光205遇到感光性電容器230之感光性半導體材料231，而不行進通過包含金屬層251、252及層間介電質290之一互連層。在所繪示之實施例中，電極235沿著一軸延伸且感光性半導體材料231經同軸安置於電極235周圍。在一項實施例中，電極235為圓柱形的，然而在其他實施例中其可經不同地塑形。在所繪示之實施例中，感光性半導體材料231經塑形為集中於電極沿其延伸之軸周圍之一倒置截錐。在所繪示之實施例中，倒置截錐之較寬端經定位以接收影像光205。較寬端與最靠近電荷儲存節點221之倒置截錐之一較窄端相對。 在一項實施例中，電極235由一高度摻雜(N+)之低溫多晶矽製成。在另一實施例中，電極235為金屬。在一項實施例中，介電層232為一高K介電質。在一項實施例中，介電層232為具有一固定負電荷之一帶負電荷材料。一負電荷層可感應介電層232與感光性半導體材料231之一介面處之一空乏區，此將防止光生電子過濾至介電層中。替代地，光生電子將更可能地朝向電極235流動且最終至電荷儲存節點221中。當然，介電層232亦用作導電層233與感光性半導體材料231之間的一非導電緩衝層。在一項實施例中，針對一負電荷層使用鉿鋁氧化物。 圖3A到3I展示根據本發明之一實施例之用於製造感光性電容器畫素210之一實例程序。應理解，所揭示以製造一個畫素之技術可用來在一半導體基板上製造一感光性電容器畫素陣列。 圖3A展示可為P摻雜矽之一半導體基板280。支撐各畫素之一電晶體網路形成於基板280中，儘管圖3A中並未展示所有電晶體。下文將結合圖6及圖7A論述電晶體網路且其等可取決於所實施之特定實施例而不同。電晶體641包含儲存節點221、閘極227及浮動擴散223。可使用習知方法沿著基板280之前側281形成儲存節點221、閘極227及浮動擴散223以形成CMOS電晶體(例如，擴散或植入)。亦可沿著基板280之前側281形成電晶體網路中之其他電晶體(圖3A中未展示)。 在所繪示之實施例中，儲存節點221包含P型釘紮層262，其可減小基板280與形成於圖3B中之層間介電質290之間的一介面處之暗電流。一接觸層261形成於儲存節點221中。與儲存節點221之N摻雜相比，接觸層261可為N+摻雜。 圖3B展示實例製造程序中之下一階段。在圖3B中，一高K介電層263形成於電荷儲存節點221上方且一互連層形成於半導體基板280之前側281上。互連層促進控制畫素電晶體網路以讀出感光性電容器。互連層包含金屬層251及252，以及層間介電質290。形成一接觸元件236以連接至接觸層261。接觸元件236可經形成為第一金屬層251之形成部分。在圖3B中，接觸元件236包含向下延伸至接觸層261之變黑之矩形。在接觸元件236形成之後，層間介電質290形成於接觸元件236上方。在層間介電質290形成於金屬層上方之後，一腔293形成於接觸元件236上方之層間介電質290中。 圖3C展示實例製造程序中之另一階段。在圖3C中，一導電層233經沈積於腔293中、腔293之側壁上以及層間介電質290上。在一些實施例中，在導電層233之前形成一薄緩衝介電層(未展示)，使得導電層233形成於薄緩衝介電層上。在圖3D中，將導電層233之一底部部分從腔293之一底板移除。舉例而言，可藉由一圖案化蝕刻移除導電層233之底部部分。在圖3E中，一介電層232形成於腔293內之導電層233上方。 在圖3F中，在腔內且在介電層232上方形成一感光性半導體材料231。在一項實施例中，感光性半導體材料231為低溫多晶矽。當多晶矽形成時，一沈積之一第一部分可包含比沈積之一隨後部分高之一摻雜濃度(在一個實例中為P摻雜)。此導致具有一梯度之低溫多晶矽沿著沿介電層232之感光性半導體材料231之外部部分具有一增加之摻雜濃度。導電層233可為反射的以將所接收之影像光205重新引導至感光性半導體材料231中。 在圖3G中，一電極腔237形成於接觸元件236上方。在圖3G中，電極腔237通過層間介電質290、介電質232以及感光性半導體材料231延伸至接觸元件236。 在圖3H中，電極腔237經充填有一導電材料以形成電極235。在其他實施例中，腔237可僅經局部充填以形成電極235。在所繪示之程序中，腔237界定電極235之形狀。腔237及電極235可為圓柱形。電極235可為金屬或N+多晶矽。在電極235形成於電極腔237中之後，一頂部介電層243形成於導電層233、感光性半導體材料231及介電層232上方。 圖3I展示製造程序中之下一階段。在圖3I中，一接合墊層253及遮光元件241形成於頂部介電層243上方。可從相同金屬層圖案化接合墊層253及遮光元件241。可透過頂部介電層243形成一導電通孔247以將一電信號(例如，一偏壓電壓)提供至導電層233。 圖5展示在一畫素501中使用低溫多晶矽及一透明電極之一現有方法之一示意模型。在畫素501中，模型化為一二極體之一儲存節點(SN)耦合至一轉移電晶體TX以讀出光電二極體。具有一透明導電電極之多晶矽形成亦耦合至轉移電晶體之一肖特基(Schottky)二極體。當影像光遇到多晶矽時，藉由多晶矽產生之光電子影響儲存節點內之影像電荷，可接著藉由轉移電晶體將影像電荷轉移至一浮動擴散。 與圖5相比，圖6繪示根據本發明之一實施例之包含感光性電容器230之一畫素601之一示意性模型。畫素601包含耦合至轉移電晶體641之感光性電容器230。轉移電晶體641包含電荷儲存節點221及浮動擴散223。電極235/236耦合至電荷儲存節點221。電極235/236為感光性電容器230之一個「板」，且導電層233為感光性電容器230之另一「板」。當感光性電容器230接收影像光205時，在感光性半導體材料231中產生呈光電子形式之一影像信號。藉由感光性半導體材料231產生之影像信號將修改電極235/236及對應電荷儲存節點221上之電位。轉移電晶體641包含於經耦合以從電極235/236讀出影像電荷之一電晶體網路中。在圖6中，電晶體網路包含轉移電晶體(TX T1) 641、一重設電晶體(RST T2) 642、一源極隨耦器電晶體(SF T3) 643以及一列選擇電晶體(SEL T4) 644。轉移電晶體網路可藉由將影像電荷轉移至浮動擴散223而讀出影像信號。電晶體643放大影像信號且當啟動電晶體644時，可將經放大之信號讀出至讀出行上。可使用一偏壓電壓657偏壓導電層233。當重設電晶體642被啟用時重設電晶體642可重設浮動擴散223。導電層233上之偏壓電壓657可為供給電極235/236一較高電位之一負電壓，使得當藉由影像光205產生光電子時其等將朝向電極235流動。 重設電晶體T2 642在一重設信號RST之控制下在一重設電壓VRST與浮動擴散FD 223之間耦合以重設畫素601 (例如，使FD放電或充電至一預設定電壓)。重設電壓VRST經固定至根據畫素601之特定實施方案之一預設定電壓。浮動擴散FD 223經耦合以控制SF電晶體T3 643之閘極。SF電晶體T3在電源軌VDD與列選擇電晶體T4 644之間耦合。SF電晶體T3 643作為將一高阻抗連接提供至浮動擴散FD 223之一源極隨耦器而操作。在一項實施例中，藉由控制電路108產生TX信號、RST信號及SEL信號。 圖4繪示根據本發明之一實施例之耦合至包含於一畫素410中之一電晶體之一閘極427之一感光性電容器230之一個實例。畫素410為畫素110之一個實例。圖4類似於圖3I中繪示之畫素，除電極235/236耦合至包含汲極421、源極423及閘極427之源極隨耦器電晶體743之閘極427外。當影像光205在感光性半導體材料231中產生一影像信號時，其修改閘極427上之電位。可與圖3I中繪示之畫素類似地製造圖4中繪示之畫素。畫素410與畫素210之不同之處在於，電極235及觸點236耦合至一閘極而非耦合至一電荷儲存節點。 圖7A繪示根據本發明之一實施例之一畫素701之一示意性模型，畫素701包含耦合至畫素410之電晶體743之閘極427之一感光性電容器230。當閘極427上之電位藉由影像信號修改時，在源極423中產生一放大之影像信號。讀出影像信號之電晶體網路包含源極隨耦器電晶體SF 743及經耦合以將放大之影像信號轉移至所繪示之讀出行之一列選擇電晶體SEL 744。重設電晶體742視情況包含於電晶體網路中且在一曝光週期之後耦合至重設電極235/236及閘極427。 圖7B展示感光性電容器C1 230及電容器C2 748之一示意性模型，電容器C2 748為電晶體743之閘極電容。在感光性半導體材料231中產生電子之影像光205用作兩個串聯之電容器之間的一電源。若電容器C2小於C1，則在跨C2 748之一較大電壓中反映C1 230上之一小電壓變化。藉由以下給出串聯電容器之總電容：
Figure TWI610427BD00001
其中CT為串聯之C1及C2之總電容。藉由以下給出跨C1 230之電壓：
Figure TWI610427BD00002
其中V1為跨C1 230之電壓且VB為偏壓電壓757。藉由以下給出跨電晶體743之閘極之電壓：
Figure TWI610427BD00003
其中V2為跨C2 748之電壓。源極隨耦器電晶體中之閘極電容一般為小的，且因此C2 748之電容可經設計以在C2 748與C1 230之間分離偏壓電壓757。若源極隨耦器743為N型，則偏壓電壓757將為一正電壓。可藉由耦合至接合墊253之一通孔將偏壓電壓757施加至導電層233。 圖7C繪示根據本發明之一實施例之畫素701之操作一方法之一實例時序圖。在時間零處，偏壓電壓757為低(例如，在零與-1.0 V之間)，列選擇電晶體SEL 744為低(未啟用)，且節點747 (電晶體743之閘極427)為低。在時間t1處，啟用列選擇電晶體SEL 744，其將一基線信號781讀出至讀出行。在時間t2處，停用列選擇電晶體SEL 744，且導電層233經偏壓至一正偏壓電壓(例如，3伏) ，其反映於節點747上。在時間t2與t3之間(畫素701之積分週期)，節點747上之電壓降低，此係因為電子藉由影響感光性半導體材料231之影像光205產生。在時間t2與t3之間高強度影像光205將增加節點747上之電壓斜率，而在時間t2與t3之間低強度影像光205將減小節點747上之電壓斜率。在t3處，啟用列選擇電晶體SEL 744，其將影像信號782讀出至讀出行。在時間t4處，偏壓電壓757經驅動為低，且停用列選擇電晶體SEL 744。可從影像信號782減去基線信號781以產生一雜訊校正信號。若重設電晶體742包含於畫素701中之電晶體網路中，在時間t4之後其就將經脈衝激發以重設節點747。 使用所揭示之包含感光性電容器之畫素之影像感測器可比習知方法與標準邏輯及動態隨機存取記憶體(「DRAM」)製造更加相容。特定言之，所揭示之畫素無需用於習知CMOS影像感測器之深植入及特殊隔離程序。另外，由於感光性元件(感光性電容器230)在製造結束時形成，故其避免當前用以在習知背側照明CMOS影像感測器中形成畫素之晶圓處理及薄化。此外，可使用兩個畫素實施圖4中之實施例及圖7A中之模型，其中習知方法需要一電晶體網路中之三個或四個畫素以讀出各畫素。減少電晶體數目可增大用於畫素中之感光性材料之面積，藉此增加影像感測器之效能。 可使用電腦軟體及硬體實施上文解釋之操作畫素及影像感測器之方法。所描述之技術可構成在一有形或非暫時性機器(例如，電腦)可讀儲存媒體內體現之機器可執行指令，該等指令在藉由一機器執行時將使機器執行所描述之操作。另外，程序可在硬體內體現，諸如一特定應用積體電路(「ASIC」)或其他硬體。 一有形非暫時性機器可讀儲存媒體包含提供(例如，儲存)呈可藉由一機器(例如，一電腦、網路裝置、個人數位助理、製造工具、具有一或多個處理器之一組之任何裝置等等)存取之一形式之資訊之任何機構。舉例而言，一機器可讀儲存媒體包含可記錄/不可記錄媒體(例如，唯讀記憶體(ROM)、隨機存取記憶體(RAM)、磁碟儲存媒體、光學儲存媒體、快閃記憶體裝置等等)。 本發明之所繪示之實施例之以上描述(包含摘要中所描述之內容)並不意在為窮盡性的或將本發明限於所揭示之具體形式。雖然出於繪示之目的，本文中描述本發明之特定實施例及實例，但熟習此項技術者應認識到，在本發明之範圍內，各種等效修改為可能的。 鑒於以上實施方式，可對本發明做出此等修改。在隨附申請專利範圍中使用之術語不應被解釋為將本發明限於本說明書中揭示之特定實施例。實情係，本發明之範疇將完全地由隨附申請專利範圍判定，申請專利範圍應根據申請專利範圍解釋之所建立原則予以解釋。
100‧‧‧成像系統
102‧‧‧畫素陣列
104‧‧‧讀出電路
106‧‧‧功能邏輯
108‧‧‧控制電路
110‧‧‧畫素
112‧‧‧讀出行
205‧‧‧影像光
210‧‧‧畫素
221‧‧‧儲存節點
223‧‧‧浮動擴散
227‧‧‧閘極
230‧‧‧感光性電容器
231‧‧‧感光性半導體材料
232‧‧‧介電層
233‧‧‧導電層
235‧‧‧電極
236‧‧‧接觸元件/電極
237‧‧‧電極腔
241‧‧‧遮光元件
243‧‧‧鈍化層/頂部介電層
251‧‧‧金屬層
252‧‧‧金屬層
253‧‧‧接合墊層
261‧‧‧接觸層
262‧‧‧P型釘紮層
263‧‧‧高K介電層
280‧‧‧半導體基板
281‧‧‧前側
282‧‧‧背側
290‧‧‧層間介電質
293‧‧‧腔
410‧‧‧畫素
421‧‧‧汲極
423‧‧‧源極
427‧‧‧閘極
501‧‧‧畫素
601‧‧‧畫素
641‧‧‧轉移電晶體
642‧‧‧重設電晶體
643‧‧‧源極隨耦器電晶體
644‧‧‧列選擇電晶體
657‧‧‧偏壓電壓
701‧‧‧畫素
742‧‧‧重設電晶體
743‧‧‧源極隨耦器電晶體
744‧‧‧列選擇電晶體
747‧‧‧節點
748‧‧‧電容器
757‧‧‧偏壓電壓
781‧‧‧基線信號
782‧‧‧影像信號
C1‧‧‧行
C2‧‧‧行
C3‧‧‧行
C4‧‧‧行
C5‧‧‧行
Cx‧‧‧行
P1‧‧‧畫素
P2‧‧‧畫素
P3‧‧‧畫素
Pn‧‧‧畫素
R1‧‧‧列
R2‧‧‧列
R3‧‧‧列
R4‧‧‧列
R5‧‧‧列
Ry‧‧‧列
t1‧‧‧時間
t2‧‧‧時間
t3‧‧‧時間
y4‧‧‧時間
參考以下圖描述本發明之非限制性及非窮盡實施例，其中除非另有指定，否則貫穿各種視圖相似參考數字係指相似零件。 圖1為示意性繪示根據本發明之一實施例之一成像系統之一個實例之一方塊圖，該成像系統包含一畫素陣列，該畫素陣列包含感光性電容器畫素。 圖2繪示根據本發明之一實施例之包含於一畫素中之一感光性電容器之一個實例。 圖3A到3I展示根據本發明之一實施例之用於製造感光性電容器畫素之一實例程序。 圖4繪示根據本發明之一實施例之耦合至包含於一畫素中之一電晶體之一閘極之一感光性電容器之一個實例。 圖5展示在一畫素中使用低溫多晶矽及一透明電極之一現有方法之一示意模型。 圖6繪示根據本發明之一實施例之包含一感光性電容器之一畫素之一示意模型。 圖7A至圖7B繪示根據本發明之一實施例之包含耦合至畫素之一電晶體之一閘極之一感光性電容器之一畫素之示意模型。 圖7C繪示根據本發明之一實施例之用於操作圖7A中繪示之畫素之一實例時序圖。
205‧‧‧影像光
210‧‧‧畫素
221‧‧‧儲存節點
223‧‧‧浮動擴散
227‧‧‧閘極
230‧‧‧感光性電容器
231‧‧‧感光性半導體材料
232‧‧‧介電層
233‧‧‧導電層
235‧‧‧電極
236‧‧‧接觸元件/電極
241‧‧‧遮光元件
243‧‧‧鈍化層/頂部介電層
251‧‧‧金屬層
252‧‧‧金屬層
253‧‧‧接合墊層
261‧‧‧接觸層
262‧‧‧P型釘紮層
263‧‧‧高K介電層
280‧‧‧半導體基板
281‧‧‧前側
282‧‧‧背側
290‧‧‧層間介電質
641‧‧‧轉移電晶體

Claims (10)

  1. 一種製造一影像感測器的一像素陣列，該方法包含： 在一半導體基板層中沿該半導體基板的一前側形成一電晶體網路； 在該像素陣列中針對每一像素形成一接觸元件，其中每一接觸元件電耦接至該電晶體網路內的一電晶體； 在該半導體基板的該前側上(upon)形成一互連層(interconnect layer)，其中該互連層用於輔助(facilitating)控制該電晶體網路，及其中該互連層包含覆蓋該接觸元件的一介電層； 在該互連層中形成一腔(cavity)，其中該腔係形成於該接觸元件上(over)； 沿該腔的腔壁(cavity walls)形成一導電層； 在該腔內的該導電層上(over)形成一介電層； 沈積一感光性(photosensitive)半導體材料於該腔內及在該介電層上(over)； 在該接觸元件上形成一電極腔，其中該電極腔延伸至該接觸元件； 以一導電材料至少部分地填充該電極腔以形成一電極，其中該電極、該導電層及該感光性半導體材料形成感光性電容器，該感光性電容器經組態以回應於影像光而改變(vary)由該接觸元件所接收的一影像信號。
  2. 如請求項1的方法，其中該導電層對該影像光為反射的。
  3. 如請求項1的方法，其中該接觸元件耦接至一轉移電晶體的一電荷儲存節點，其中當該轉移電荷經啟動(activated)時，該轉移電晶體經耦接以將由該感光性電容器所產生的影像電荷轉移至該半導體基板內的一浮動擴散(floating diffusion)。
  4. 如請求項1的方法，其中該接觸元件耦接至一源極隨耦器電晶體(source follower transistor)的一控制終端，該源極隨耦器電晶體產生一放大影像信號以回應於由該感光性電容器所產生的一影像電荷。
  5. 如請求項1的方法，其進一步包含： 在沈積該導電性層於該等腔壁上之前，在該等腔壁之上(on)形成一緩衝介電層。
  6. 如請求項1的方法，其進一步包含： 在形成該介電層之前移除沈積於該腔之一底板(floor)上的該導電層之一底部部分(bottom portion)。
  7. 如請求項1的方法，其中該感光性半導體材料包含非晶矽。
  8. 如請求項1的方法，其中沈積該感光性半導體材料於該腔內包含在該沈積的一起點(start)比該沈積的一終點(end)摻雜更多的該感光性半導體材料。
  9. 如請求項1的方法，其進一步包含： 形成一頂部(top)介電層於該導電性材料、該感光性半導體材料及該介電層上(over)；及 穿過該頂部介電層形成一導電通孔(via)至該導電層，以提供一電信號至該導電層。
  10. 如請求項1的方法，其中形成該接觸元件包含在該介電層內形成一金屬接觸層。
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