TWI606519B - 溝槽式功率半導體元件及其製造方法 - Google Patents
溝槽式功率半導體元件及其製造方法 Download PDFInfo
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- TWI606519B TWI606519B TW105129317A TW105129317A TWI606519B TW I606519 B TWI606519 B TW I606519B TW 105129317 A TW105129317 A TW 105129317A TW 105129317 A TW105129317 A TW 105129317A TW I606519 B TWI606519 B TW I606519B
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- 239000004065 semiconductor Substances 0.000 title claims description 104
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000010410 layer Substances 0.000 claims description 161
- 239000012535 impurity Substances 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 20
- 239000002344 surface layer Substances 0.000 claims description 12
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims 1
- 229910001936 tantalum oxide Inorganic materials 0.000 claims 1
- 238000005530 etching Methods 0.000 description 15
- 230000005669 field effect Effects 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 8
- 238000011065 in-situ storage Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- -1 phosphorus ion Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 206010062717 Increased upper airway secretion Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 208000026435 phlegm Diseases 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
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Description
本發明涉及一種功率半導體元件及其製造方法,特別是涉及一種溝槽式功率電晶體及其製造方法。
現有的功率金氧半場效電晶體(Power Metal Oxide Semiconductor Field Transistor,Power MOSFET)多採取垂直結構的設計,以提升元件密度。功率型金氧半場效電晶體的工作損失可分成切換損失(switching loss)及導通損失(conducting loss)兩大類,其中閘極/汲極的電容值(Cgd)是影響切換損失的重要參數。閘極/汲極電容值太高會造成切換損失增加,進而限制功率型金氧半場效電晶體的切換速度,不利於應用高頻電路中。
本發明提供一種溝槽式功率半導體元件及其製造方法,是藉由一具有PN接面(PN junction)的閘極來降低閘極/汲極電容值。
為了解決上述的技術問題,本發明所採用的其中一技術方案是,提供一種溝槽式功率半導體元件的製造方法,其包括:形成磊晶層於基材_上;形成一基體區於所述磊晶層內;形成一溝槽於磊晶層內。隨後,形成初始閘極結構於溝槽中,其中初始閘極結構包括一覆蓋溝槽的閘絕緣層、一覆蓋閘絕緣層下半部的疊層、
一從溝槽上半部延伸至下半部的第一重摻雜半導體結構以及位於疊層上的兩個第二重摻雜半導體結構,且兩個第二重摻雜半導體結構設在閘絕緣層與第一重摻雜半導體結構之間。第一重摻雜半導體結構與第二重摻雜半導體結構分別具有第一導電型雜質及第二導電型雜質。接著,執行摻雜製程,同步地以一外加第二導電型雜質植入在所述基體區內形成一第一表層摻雜區以及在第一重摻雜半導體結構的頂部形成一第二表層摻雜區。隨後,執行一熱擴散製程,以使所述第一表層摻雜區形成一源極區,且使所述溝槽內形成一閘極,其中所述閘極包括一上摻雜區以及一下摻雜區,所述上摻雜區與所述下摻雜區之間形成一PN接面。
為了解決上述的技術問題,本發明所採用的另外一技術方案是,提供一種溝槽式功率半導體元件,其包括基材、磊晶層以及閘極結構。磊晶層位於基材上,並具有一溝槽。閘極結構位於溝槽內,並包括閘絕緣層、疊層以及閘極。閘絕緣層覆蓋溝槽的內壁面。疊層覆蓋閘絕緣層的下半部。閘極位於溝槽內,並通過閘絕緣層與疊層和磊晶層隔離。閘極包括一位於疊層上的上摻雜區及一被疊層圍繞的下摻雜區,上摻雜區與下摻雜區之間形成一PN接面,所述上摻雜區內的雜質濃度是由所述上摻雜區的外圍朝所述上摻雜區的內部遞減。
綜上所述,本發明之溝槽式功率半導體元件及其製造方法可在閘極中形成PN接面。由於PN接面在逆向偏壓下可產生接面電容(junction capacitance,Cj),且接面電容是和閘極/汲極之間的寄生電容(Cp)串聯,因此可降低閘極/汲極的等效電容(Cgd)。另外,在溝槽式功率半導體元件的製造方法中,執行源極摻雜製程時會同步對溝槽內的結構進行摻雜,隨後再執行熱擴散製程來同步形成源極區以及具有PN接面的閘極。如此,可以避免多次的熱擴散製程導致閘極的上摻雜區與下摻雜區內的導電型雜質相互擴散,而無法使閘極具有PN接面以及影響元件特性。
為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與附圖,然而所提供的附圖僅提供參考與說明用,並非用來對本發明加以限制。
1‧‧‧溝槽式功率半導體元件
10‧‧‧基材
11‧‧‧磊晶層
112‧‧‧溝槽
112a‧‧‧內壁面
111‧‧‧基體區
113‧‧‧源極區
110‧‧‧漂移區
120‧‧‧閘絕緣層
120s‧‧‧內表面
121‧‧‧疊層
122’‧‧‧第一初始介電層
123’‧‧‧第二初始介電層
122‧‧‧第一介電層
123‧‧‧第二介電層
125’、125”‧‧‧第一重摻雜半導體結構
S1‧‧‧第一側面
S2‧‧‧第二側面
h‧‧‧凹槽
126’‧‧‧第二導電型半導體材料
126”‧‧‧第二重摻雜半導體結構
12’‧‧‧初始閘極結構
12‧‧‧閘極結構
A1‧‧‧第一表層摻雜區
A2‧‧‧第二表層摻雜區
A21‧‧‧第一區域
A22‧‧‧第二區域
124‧‧‧閘極
126‧‧‧上摻雜區
125‧‧‧下摻雜區
127‧‧‧PN接面
C1‧‧‧第一電容
C2‧‧‧第二電容
C3‧‧‧第三電容
Cj‧‧‧接面電容
S100~S105‧‧‧流程步驟
圖1繪示本發明一實施例的溝槽式功率半導體元件製造方法的流程圖。
圖2A至圖2J分別繪示本發明一實施例的溝槽式功率半導體元件在各步驟的局部剖面示意圖。
圖3顯示本發明實施例的溝槽式功率半導體元件的局部剖面示意圖。
請參照圖1,顯示本發明一實施例的溝槽式功率半導體元件製造方法的流程圖。另外,請一併參照圖2A至圖2J,分別繪示本發明一實施例的溝槽式功率半導體元件在各步驟的局部剖面示意圖。
在步驟S100中,形成一磊晶層(epitaxial layer)11於基材10上。請配合參照圖2A。圖2A中繪示基材10,並且於基材10上已形成一磊晶層(epitaxial layer)11,其中基材10例如為矽基板(silicon substrate),其具有高摻雜濃度的第一重摻雜區以作為溝槽式功率金氧半場效電晶體的汲極(drain),磊晶層11則為低摻雜濃度。
基材10具有高濃度的第一型導電性雜質,而形成第一重摻雜區。第一重摻雜區是用來作為溝槽式功率金氧半場效電晶體的汲極(drain),且可分布於基材10的局部區域或是分布於整個基材10中。在本實施例的第一重摻雜區是分布於整個基材10內,但僅用於舉例而非用以限制本發明。前述的第一導電型雜質可以是N型或P型導電性雜質。假設基材10為矽基材,N型導電性雜質為五
價元素離子,例如磷離子或砷離子,而P型導電性雜質為三價元素離子,例如硼離子、鋁離子或鎵離子。
若溝槽式功率金氧半場效電晶體為N型,基材10摻雜N型導電性雜質。另一方面,若為P型溝槽式功率金氧半場效電晶體,則基材10摻雜P型導電性雜質。本發明實施例中,是以N型溝槽式功率金氧半場效電晶體為例說明。
磊晶層11形成於基材10上方,並具有低濃度的第一型導電性雜質。也就是說,以NMOS電晶體為例,基材10為高濃度的N型摻雜(N+),而磊晶層11則為低濃度的N型摻雜(N-)。反之,以PMOS電晶體為例,基材10為高濃度的P型摻雜(P+ doping),而磊晶層11則為低濃度的P型摻雜(P- doping)。
接著,進行步驟S101,形成一基體區於所述磊晶層內。如圖2A所示,基體區111形成在磊晶層11內且位於遠離基材10的一側。此外,由圖2A中可看出,磊晶層11中的其他區域形成溝槽式半導體元件的漂移區110。
在本實施例中,先進行基體摻雜製程以及基體熱擴散製程以在磊晶層11內形成基體區111,可以避免形成基體區的熱擴散製程影響閘極結構中的摻雜結構。
接著,在步驟S102,形成溝槽於磊晶層中。請參照圖2B,本發明實施例的溝槽112為深溝槽(deep trench)。也就是說,溝槽112由磊晶層11的表面向下延伸超過基體區111,也就是延伸至漂移區110中,並且溝槽112的底端靠近基材10。
詳細而言,在形成溝槽112的步驟中,是先利用光罩(未圖示)定義出閘極結構的位置,再以乾蝕刻或溼蝕刻的方式在磊晶層11內製作出溝槽112。
接著,在步驟S103中,形成初始閘極結構於溝槽內。請參照圖2C至圖2H,顯示形成本發明實施例中的初始閘極結構的詳細流程。
請先參照圖2C,依序在溝槽112的內壁面112a上形成閘絕緣層120、一第一初始介電層122’以及一第二初始介電層123’。詳細而言,閘絕緣層120、第一初始介電層122’以及第二初始介電層123’覆蓋磊晶層11的整個表面以及溝槽112的內壁面112a。
另外,構成第一初始介電層122’的材料不同於構成第二初始介電層123’的材料以及構成閘絕緣層120的材料。舉例而言,構成閘絕緣層120與第二初始介電層123’的材料可以是氧化物,如:氧化矽,而構成第一初始介電層122’的材料可以是氮化物,如:氮化矽。具體而言,只要第二初始介電層123’與第一初始介電層122’之間具有高蝕刻選擇比,而第一初始介電層122’與閘絕緣層120之間也具有高蝕刻選擇比,以在後續製程中可執行選擇性蝕刻,本發明實施例中並沒有限定閘絕緣層120、第一初始介電層122’以及第二初始介電層123’的材料。
前述的蝕刻選擇比是指在相同的蝕刻環境下,對於兩種不同的材料(如:第一初始介電層122’與第二初始介電層123’,或者閘絕緣層120與第一初始介電層122’)之間的蝕刻比例。由於第二初始介電層123’與第一初始介電層122’具有高蝕刻選擇比,因而在通過蝕刻製程中去除第二初始介電層123’時,不會一併將第一初始介電層122’移除。相似地,第一初始介電層122’與閘絕緣層120具有高蝕刻選擇比,在通過蝕刻製程中去除第一初始介電層122’時,不會將閘絕緣層120去除。
接著,請參照圖2D,形成第一重摻雜半導體結構125’於溝槽112內,第一重摻雜半導體結構125’由溝槽112的上半部延伸至下半部。
在一實施例中,是先形成第一導電型半導體材料於第二初始介電層123’上,並填入溝槽112中。第一導電型半導體材料可以是含導電性雜質的多晶矽(doped poly-Si)。形成第一導電型半導體材料的方式,可以是在內摻雜化學氣相沉積製程(in-situ doping
CVD process)。在另一實施例中,也可以先沉積無雜質(本質)多晶矽後,再以通過離子佈植製程將雜質植入多晶矽中。隨後,再執行熱驅入製程後完成第一導電型半導體材料。
接著,回蝕(etch back)去除位於磊晶層11上方的第一導電型半導體材料,而留下位於溝槽112內的第一導電型半導體材料,以形成第一重摻雜半導體結構125’。第一重摻雜半導體結構125’具有第一側面S1以及和第一側面S1相對的第二側面S2。
第一重摻雜半導體結構125’內具有第一導電型雜質,可以是N型雜質或P型雜質。詳細而言,當預定製備的溝槽式功率半導體元件是N型金氧半場效電晶體時,第一重摻雜半導體結構125’具有是P型雜質,而形成P型半導體結構。當溝槽式功率半導體元件是P型金氧半場效電晶體時,第一重摻雜半導體結構具有N型雜質,而形成N型半導體結構。
請繼續參照圖2E,去除位於溝槽112的上半部的第二初始介電層123’。詳細而言,位於磊晶層11上方的第二初始介電層123’以及位於溝槽112的上半部的第二初始介電層123’都會被移除,而形成位於溝槽112的下半部的第二介電層123。
在一實施例中,可以通過濕蝕刻去除部分第二初始介電層123’。須說明的是,在執行蝕刻製程時,第二初始介電層123’和第一重摻雜半導體結構125’具有高蝕刻選擇比,因此在去除位於溝槽112的上半部的第二初始介電層123’時,可以通過第一重摻雜半導體結構125’作為遮罩。
另外,第二初始介電層123’與第一初始介電層122’之間也具有高蝕刻選擇比。因此,在蝕刻位於溝槽112的上半部的第二初始介電層123’時,第一初始介電層122’不會被去除,而可以保護閘絕緣層120。
請繼續參照圖2F。接著,去除位於溝槽112的上半部的第一初始介電層122’,以在溝槽112的下半部形成疊層121。
詳細而言,位於磊晶層11上方的第一初始介電層122’以及位於溝槽112的上半部的第一初始介電層122’都會被去除,而在溝槽112的下半部形成第一介電層122。
相似地,在通過蝕刻製程去除部分第一初始介電層122’時,是通過第一重摻雜半導體結構125’以及第二介電層123作為遮罩。另外,由於第一初始介電層122’與閘絕緣層120之間具有高蝕刻選擇比,因此在去除部分第一初始介電層122’時,閘絕緣層120並不會被一併去除。
整體而言,在去除部分的第一初始介電層122’與第二初始介電層123’之後,會在溝槽112的下半部形成疊層121,其中疊層121是覆蓋閘絕緣層120的內表面120s的下半部,並包括上述的第一介電層122與第二介電層123。在本實施例中,疊層121的頂端會低於基體區111的下方邊緣,也就是低於基體區111的最低點所在的水平面。
另外,如圖2F所示,在去除部分的第一初始介電層122’與第二初始介電層123’之後,會使閘絕緣層120的內表面120s的上半部、第一重摻雜半導體結構125’的部分第一側面S1及部分第二側面S2暴露出來。換言之,兩個凹槽h為去除第二初始介電層123’上半部與第一初始介電層122’上半部而形成。兩個凹槽h會分別位於閘絕緣層120與第一側面S1之間,以及形成在閘絕緣層120與第二側面S2之間。
接著,請參照圖2G,全面地形成第二導電型半導體材料126’覆蓋第一重摻雜半導體結構125’以及閘絕緣層120,並於填入於兩個凹槽h內。
第二導電型半導體材料126’具有第二導電型雜質,可以是N型雜質或P型雜質,且第二導電型半導體材料126’可以是摻雜的多晶矽(doped poly-Si)。當溝槽式功率半導體元件是NMOS電晶體時,第二導電型半導體材料126’是摻雜N型雜質,而當溝槽式功
率半導體元件是PMOS電晶體時,第二導電型半導體材料126’是摻雜P型雜質。也就是說,第二導電型半導體材料126’的導電型,和基體區111的導電型以及第一重摻雜半導體結構125’的導電相反。在一實施中,可以通過在內摻雜化學氣相沉積製程(in-situ doping CVD process)來形成第二導電型半導體材料126’。
請參照圖2H,接著,回蝕去除位於磊晶層11上方的第二導電型半導體材料126’,以分別形成兩個第二重摻雜半導體結構126”於兩個凹槽h內。在經過上述步驟之後,在溝槽112內可形成初始閘極結構12’。
接著,請再參照圖1,在步驟S104,執行一摻雜製程,同步地以一外加第二導電型雜質植入在基體區內形成一第一表層摻雜區以及在第一重摻雜半導體結構的頂部形成一第二表層摻雜區。
詳細而言,請配合參照圖2I,在本實施例中,是在不使用任何遮罩的情況下,對基體區111以及初始閘極結構12’進行離子佈植,將第二導電型雜質摻雜(implant)到基體區111以及初始閘極結構12’中,以同步地在基體區111的表層形成第一表層摻雜區A1以及在第一重摻雜半導體結構125”與第二重摻雜半導體結構126”的頂部形成第二表層摻雜區A2。
第二表層摻雜區A2包括位於第一重摻雜半導體結構125”的第一區域A21,以及位於兩個第二重摻雜半導體結構126”頂部的第二區域A22。
須說明的是,第一重摻雜半導體結構125”內已經具有第一導電型雜質,在通過摻雜製程植入第二導電型雜質之後,由於所植入的第二導電型雜質濃度遠大於第一重摻雜半導體結構125”中的第一導電型雜質的濃度,因此,第一區域A21的導電性接近於第二導電型,也就是和第二重摻雜半導體結構126”的導電型相同。
接著,請參照圖1,在步驟S105中,執行一熱擴散製程,以使第一表層摻雜區形成一源極區,且在溝槽內形成一閘極。
請參照圖2J。閘極124包括一上摻雜區126以及一下摻雜區125,上摻雜區126與下摻雜區125之間形成一PN接面127,且上摻雜區126是通過第二表層摻雜區A2以及第二重摻雜半導體結構126”內的第二導電型雜質擴散而形成。
須說明的是,在執行熱擴散製程時,需控制加熱的溫度以及時間,來避免第二導電型雜質擴散到第一重摻雜半導體結構125”的整個下半部,導致無法在閘極124中形成PN接面127,也影響溝槽式功率半導體元件1的電性。在一實施例中,是通過快速熱製程(rapid thermal process)使第二導電型雜質擴散。
也就是說,第一重摻雜半導體結構125”的下半部會形成前述的下摻雜區125。據此,在經過熱擴散製程之後,可以同步地在基體區111內形成源極區113以及在溝槽112內形成閘極124的上摻雜區126和下摻雜區125。
要說明的是,雖然在執行熱擴散製程之前,第一表層摻雜區A1和第二表層摻雜區A2具有大致相同的深度。但是在執行熱擴散製程中,第一表層摻雜區A1內的第二型導電雜質的擴散速度會小於第二表層摻雜區A2內的第二型導電雜質的擴散速度。也就是說,上摻雜區126與下摻雜區125之間所形成的PN接面127所在位置會低於基體區111的最低點所在的水平面。另外,在一實施例中,PN接面127所在位置會低於疊層121的頂端。
請參照圖2J及圖3,其中圖3顯示本發明實施例的溝槽式功率半導體元件的局部剖面示意圖。
溝槽式功率半導體元件1包括基材10、磊晶層11以及閘極結構12,其中閘極結構12位於磊晶層11的溝槽112內,並具有閘絕緣層120、疊層121以及閘極124,其中閘極124可通過閘絕緣層120以及疊層121以和磊晶層11隔離。
如前所述,疊層121是覆蓋閘絕緣層120的下半部,並包括第一介電層122及第二介電層123。既然第一介電層122與第二介
電層123分別是通過蝕刻第一初始介電層122’與第二初始介電層123’而形成,第二介電層123與第一介電層122之間也會具有高蝕刻選擇比。在一實施例中,構成第一介電層122及第二介電層123的材料可分別是氮化矽及氧化矽。
閘極124包括被疊層121圍繞的下摻雜區125以及位於疊層121和下摻雜區125上方的上摻雜區126,且上摻雜區126與下摻雜區125之間形成一PN接面127。由於上摻雜區126是通過第二表層摻雜區A2以及第二重摻雜半導體結構126”內的第二導電型雜質擴散而形成,因此上摻雜區126內的雜質濃度是由上摻雜區126的外圍朝上摻雜區的內部遞減。
另外,溝槽式功率半導體元件1還具有基體區111以及源極區113。基體區111位於磊晶層11內並和閘極結構12的上半部相鄰,且源極區113位於基體區111上方,並和閘極結構12的上半部相鄰。基體區111的下方邊緣所在的水平面會高於疊層121的頂端。換言之,疊層121的頂端是低於基體區111的下方邊緣。
本發明實施例中,由於溝槽112為深溝槽,因此閘極結構12也會從磊晶層11的表面延伸到漂移區110內,如此,有助於增加溝槽功率半導體元件1的崩潰電壓,然而卻會增加閘極與汲極之間的寄生電容(Cp)。
如圖3所示,閘極124和汲極之間的寄生電容Cp是由第一電容C1、第二電容C2及第三電容C3並聯而形成,亦即Cp=C1+C2+C3。
過高的寄生電容Cp會降低溝槽式功率半導體元件1的切換速度。因此,在本發明實施例中,在閘極124中形成PN接面127。由於PN接面127在逆向偏壓下可產生接面電容(junction capacitance,Cj),且接面電容Cj是和寄生電容Cp串聯,使閘極/汲極等效電容(Cgd)、寄生電容Cp及接面電容Cj滿足下列關係式:Cgd=(Cp*Cj)/(Cp+Cj)。由於閘極/汲極等效電容Cgd會比原本
的寄生電容Cp更小,因而可使溝槽式功率半導體元件1的切換損失降低。
另外,為了在溝槽式功率半導體元件1處於導通狀態(ON)時,可在閘極124的PN接面127產生接面電容(Cj),上摻雜區126會和源極區113具有基本相同的導電型,而和基體區具有相反的導電型。以NMOS電晶體為例,源極區113與上摻雜區126皆為N型摻雜區,而基體區111與下摻雜區125皆為P型摻雜區。
當對閘極124的上摻雜區126施加正偏壓時,基體區111的負電荷會累積至溝槽112側邊而形成源極與汲極之間的載子通道,使溝槽式功率半導體元件1處於導通狀態。
然而,在閘極124的PN接面127則由於逆向偏壓而產生空乏區,可形成接面電容(Cj),從而降低閘極/汲極等效電容(Cgd)。反之,以PMOS電晶體為例,源極區113與上摻雜區126皆為P型摻雜,而基體區111與下摻雜區125皆為N型摻雜。
綜上所述,本發明的有益效果在於,本發明之溝槽式功率半導體元件及其製造方法可在閘極中形成PN接面。由於PN接面在逆向偏壓下可產生接面電容(junction capacitance,Cj),且接面電容是和閘極/汲極之間的寄生電容(Cp)串聯,因此可降低閘極/汲極的等效電容(Cgd)。
另外,在溝槽式功率半導體元件的製造方法中,基體區的基體熱擴散製程可在形成初始閘極結構的步驟之前,且執行源極摻雜製程時會同步對溝槽內的結構進行摻雜,隨後再執行熱擴散製程來同步形成源極區以及具有PN接面的閘極。如此,可以避免多次的熱擴散製程導致閘極的上摻雜區與下摻雜區內的導電型雜質相互擴散,而無法使閘極具有PN接面以及影響元件特性。
以上所公開的內容僅為本發明的優選可行實施例,並非因此侷限本發明的申請專利範圍,故凡運用本發明說明書及附圖內容所做的等效技術變化,均包含於本發明的申請專利範圍內。
S100~S105‧‧‧流程步驟
Claims (13)
- 一種溝槽式功率半導體元件的製造方法,其包括:形成一磊晶層於一基材上;形成一基體區於所述磊晶層內;形成一溝槽於所述磊晶層中;形成一初始閘極結構於所述溝槽內,其中所述初始閘極結構包括一覆蓋所述溝槽的閘絕緣層、一覆蓋所述閘絕緣層下半部的疊層、一從所述溝槽的上半部延伸至下半部的第一重摻雜半導體結構以及兩個位於所述疊層上的第二重摻雜半導體結構,所述兩個第二重摻雜半導體結構設於所述閘絕緣層與所述第一重摻雜半導體結構之間,所述第一重摻雜半導體結構與所述第二重摻雜半導體結構分別具有第一導電型雜質及第二導電型雜質;執行一摻雜製程,同步地以一外加第二導電型雜質植入在所述基體區內形成一第一表層摻雜區以及在所述第一重摻雜半導體結構的頂部形成一第二表層摻雜區;以及執行一熱擴散製程,以使所述第一表層摻雜區形成一源極區,且在所述溝槽內形成一閘極;其中,所述閘極包括一上摻雜區以及一下摻雜區,所述上摻雜區與所述下摻雜區之間形成一PN接面。
- 如請求項1所述的溝槽式功率半導體元件的製造方法,其中,形成所述初始閘極結構的步驟是在形成所述基體區的步驟之後。
- 如請求項1所述的溝槽式功率半導體元件的製造方法,其中,所述疊層包括一第一介電層與一第二介電層,所述第一介電層 夾設於所述第二介電層與所述閘絕緣層之間,且構成所述第一介電層的材料不同於構成所述第二介電層以及所述閘絕緣層的材料。
- 如請求項1所述的溝槽式功率半導體元件的製造方法,其中,形成所述初始閘極結構的步驟包括:依序在所述溝槽內形成所述閘絕緣層、一第一初始介電層以及一第二初始介電層;形成所述第一重摻雜半導體結構於溝槽內;去除位於所述溝槽上半部的所述第二初始介電層;去除位於所述溝槽上半部的所述第一初始介電層,以在所述溝槽下半部形成所述疊層;以及分別形成兩個所述第二重摻雜半導體結構於兩個凹槽內,其中兩個所述凹槽為去除所述第二初始介電層上半部與第一初始介電層上半部而形成。
- 如請求項1所述的溝槽式功率半導體元件的製造方法,其中,所述上摻雜區的第二導電型雜質的濃度是由所述上摻雜區的外圍朝所述上摻雜區的內部遞減。
- 如請求項1所述的溝槽式功率半導體元件的製造方法,其中,所述PN接面所在的位置低於所述基體區的最低點。
- 如請求項1所述的溝槽式功率半導體元件的製造方法,其中所述PN接面所在的位置低於所述疊層的頂部。
- 一種溝槽式功率半導體元件,其包括:一基材;一磊晶層,其位於所述基材上,並具有一溝槽;以及 一閘極結構,其位於所述溝槽內,其中所述閘極結構包括:一閘絕緣層,其覆蓋所述溝槽;一疊層,其覆蓋所述閘絕緣層的下半部;一閘極,其位於所述溝槽內,所述閘極以所述閘絕緣層及所述疊層與所述磊晶層隔離,其中所述閘極包括一被所述疊層圍繞的下摻雜區以及一位於所述疊層及所述下摻雜區上方的上摻雜區,所述上摻雜區與所述下摻雜區之間形成一PN接面,所述下摻雜區內具有第一導電型雜質,所述上摻雜區內具有第二導電型雜質,且所述上摻雜區內的所述第二導電型雜質的雜質濃度是由所述上摻雜區的外圍朝所述上摻雜區的內部遞減。
- 如請求項8所述的溝槽式功率半導體元件,還包括:一基體區,其位於所述磊晶層內並和所述閘極結構的上半部相鄰;以及一源極區,其位於磊晶層內並和所述閘極結構的上半部相鄰,其中所述源極區位於所述基體區的上方,且所述PN接面所在的位置低於所述基體區的最低點。
- 如請求項9所述的溝槽式功率半導體元件,其中,所述疊層的頂端低於所述基體區的下方邊緣。
- 如請求項8所述的溝槽式功率半導體元件,其中,所述疊層包括一第一介電層以及一夾設於所述第一介電層與所述下摻雜區之間的第二介電層,且構成所述第一介電層的材料不同於構成所述第二介電層以及所述閘絕緣層的材料。
- 如請求項11所述的溝槽式功率半導體元件,其中所述第一介 電層與所述第二介電層分別為一氮化矽與一氧化矽。
- 如請求項11所述的溝槽式功率半導體元件,其中所述第一介電層與所述第二介電層具有高蝕刻選擇比。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060014349A1 (en) * | 2003-03-05 | 2006-01-19 | Williams Richard K | Planarized and silicided trench contact |
US20130069145A1 (en) * | 2011-09-16 | 2013-03-21 | Kabushiki Kaisha Toshiba | Power semiconductor device |
TWM480763U (zh) * | 2014-03-20 | 2014-06-21 | Super Group Semiconductor Co Ltd | 溝槽式功率金氧半場效電晶體 |
TW201543686A (zh) * | 2014-05-09 | 2015-11-16 | Sinopower Semiconductor Inc | 溝槽式功率電晶體元件、晶圓結構及其製作方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB0028031D0 (en) * | 2000-11-17 | 2001-01-03 | Koninkl Philips Electronics Nv | Trench-gate field-effect transistors and their manufacture |
US6387758B1 (en) * | 2001-03-26 | 2002-05-14 | Advanced Micro Devices, Inc. | Method of making vertical field effect transistor having channel length determined by the thickness of a layer of dummy material |
GB0405325D0 (en) * | 2004-03-10 | 2004-04-21 | Koninkl Philips Electronics Nv | Trench-gate transistors and their manufacture |
US8497549B2 (en) | 2007-08-21 | 2013-07-30 | Fairchild Semiconductor Corporation | Method and structure for shielded gate trench FET |
US7833862B2 (en) * | 2008-03-03 | 2010-11-16 | Infineon Technologies Austria Ag | Semiconductor device and method for forming same |
CN101807546B (zh) | 2009-02-13 | 2013-04-17 | 尼克森微电子股份有限公司 | 沟道式金属氧化物半导体元件及其制作方法 |
JP5627494B2 (ja) * | 2011-02-09 | 2014-11-19 | 株式会社東芝 | 半導体装置およびその製造方法 |
TWI463650B (zh) | 2012-07-11 | 2014-12-01 | Anpec Electronics Corp | 功率半導體元件及其製作方法 |
TWI520337B (zh) | 2012-12-19 | 2016-02-01 | 財團法人工業技術研究院 | 階梯溝渠式金氧半場效電晶體及其製造方法 |
CN104934471B (zh) | 2014-03-20 | 2019-02-15 | 帅群微电子股份有限公司 | 沟槽式功率金氧半场效晶体管与其制造方法 |
DE102014113189B4 (de) * | 2014-09-12 | 2023-04-20 | Infineon Technologies Austria Ag | Halbleitervorrichtungen mit Feldelektrodenstrukturen, Gatestrukturen und Hilfsdiodenstrukturen |
JP2016167519A (ja) * | 2015-03-09 | 2016-09-15 | 株式会社東芝 | 半導体装置 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060014349A1 (en) * | 2003-03-05 | 2006-01-19 | Williams Richard K | Planarized and silicided trench contact |
US20130069145A1 (en) * | 2011-09-16 | 2013-03-21 | Kabushiki Kaisha Toshiba | Power semiconductor device |
TWM480763U (zh) * | 2014-03-20 | 2014-06-21 | Super Group Semiconductor Co Ltd | 溝槽式功率金氧半場效電晶體 |
TW201543686A (zh) * | 2014-05-09 | 2015-11-16 | Sinopower Semiconductor Inc | 溝槽式功率電晶體元件、晶圓結構及其製作方法 |
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