TWI605552B - 半導體元件、半導體基底及其形成方法 - Google Patents

半導體元件、半導體基底及其形成方法 Download PDF

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TWI605552B
TWI605552B TW105140582A TW105140582A TWI605552B TW I605552 B TWI605552 B TW I605552B TW 105140582 A TW105140582 A TW 105140582A TW 105140582 A TW105140582 A TW 105140582A TW I605552 B TWI605552 B TW I605552B
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Taiwan
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layer
compound semiconductor
iii
semiconductor layer
region
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TW105140582A
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TW201822305A (zh
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薛芳昌
林恆光
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新唐科技股份有限公司
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Priority to TW105140582A priority Critical patent/TWI605552B/zh
Priority to CN201710201928.XA priority patent/CN108198855B/zh
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Priority to US15/834,079 priority patent/US10276454B2/en
Publication of TW201822305A publication Critical patent/TW201822305A/zh

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Description

半導體元件、半導體基底及其形成方法
本發明是有關於一種半導體元件、半導體基底及其形成方法。
近年來，以III-V族化合物半導體為基礎的高電子遷移率電晶體(high electron mobility transistor；HEMT)因為其低阻值、高崩潰電壓以及快速開關切換頻率等特性，在高功率電子元件領域獲得相當大的關注。具體來說，將III-V族化合物半導體磊晶成長在矽基底的技術被廣泛地研究。然而，III-V族化合物半導體元件至今仍無法與矽元件有效地整合在一起，使其應用層面受限。
有鑒於此，本發明提供一種半導體元件、半導體基底及其形成方法，可抑制形成於此半導體基底上的元件之間的干擾。
本發明的半導體基底包括第一含矽層、單晶態III-V族化合物半導體層以及非晶態III-V族化合物半導體層。第一含矽層具 有第一區以及第二區。單晶態III-V族化合物半導體層配置於第一區的第一含矽層上。非晶態III-V族化合物半導體層配置於第二區的第一含矽層上。
在本發明的一實施例中，上述的半導體基底中，單晶態III-V族化合物半導體層與非晶態III-V族化合物半導體層接觸。
在本發明的一實施例中，上述的半導體基底中，單晶態III-V族化合物半導體層與非晶態III-V族化合物半導體層的組成相同。
在本發明的一實施例中，上述的半導體基底中，單晶態III-V族化合物半導體層與非晶態III-V族化合物半導體層各自包括第一氮化鎵層、氮化鋁鎵層以及第二氮化鎵層。第一氮化鎵層配置於第一含矽層上。氮化鋁鎵層配置於第一氮化鎵層上。第二氮化鎵層配置於氮化鋁鎵層上。
在本發明的一實施例中，上述的半導體基底中，單晶態III-V族化合物半導體層更延伸至非晶態III-V族化合物半導體層與第一含矽層之間，且單晶態III-V族化合物半導體層於第一區的厚度大於單晶態III-V族化合物半導體層於第二區的厚度。
在本發明的一實施例中，上述的半導體基底更包括絕緣層與第二含矽層。絕緣層配置於非晶態III-V族化合物半導體層上。第二含矽層配置於絕緣層上。
在本發明的一實施例中，上述的半導體基底中，第一含矽層具有<111>晶面，而第二含矽層具有<100>晶面。
本發明的半導體元件包括第一含矽層、單晶態III-V族化合物半導體層、非晶態III-V族化合物半導體層、第一元件以及第 二元件。第一含矽層具有第一區以及第二區。單晶態III-V族化合物半導體層配置於第一區的第一含矽層上。非晶態III-V族化合物半導體層配置於第二區的第一含矽層上。第一元件配置於單晶態III-V族化合物半導體層上。第二元件配置於非晶態III-V族化合物半導體層上。
在本發明的一實施例中，上述的半導體元件中，單晶態III-V族化合物半導體層與非晶態III-V族化合物半導體層的組成相同且彼此接觸。
在本發明的一實施例中，上述的半導體元件中，第一元件包括閘極、二塊狀物、源極以及汲極。二塊狀物位於閘極兩側。源極與汲極分別穿過該些塊狀物，其中該些塊狀物的材料包括三元化合物或四元化合物。
在本發明的一實施例中，上述的半導體元件更包括絕緣層以及第二含矽層。絕緣層配置於非晶態III-V族化合物半導體層上。第二含矽層配置於絕緣層上，其中第二元件配置於第二含矽層上。
在本發明的一實施例中，上述的半導體元件中，第一含矽層具有<111>晶面，而第二含矽層具有<100>晶面。
在本發明的一實施例中，上述的半導體元件中，單晶態III-V族化合物半導體層更延伸至非晶態III-V族化合物半導體層與第一含矽層之間，且單晶態III-V族化合物半導體層於第一區的厚度大於單晶態III-V族化合物半導體層於第二區的厚度，使得非晶態III-V族化合物半導體層的底部低於第一元件在運作時於單晶態III-V族化合物半導體層產生的二維電子氣的區域。
本發明的半導體的形成方法包括下列步驟。提供第一含矽層，第一含矽層具有第一區以及第二區。於第一區以及第二區的第一含矽層上形成單晶態III-V族化合物半導體層。進行處理步驟，使得第二區的單晶態III-V族化合物半導體層至少部分轉化為非晶態III-V族化合物半導體層。
在本發明的一實施例中，上述的半導體基底的形成方法中，處理步驟包括進行植入製程。
在本發明的一實施例中，上述的半導體基底的形成方法中，植入製程所使用的植入源包括氮、氬、碳、氟或其組合。
在本發明的一實施例中，上述的半導體基底的形成方法中，植入製程的能量為1KeV至600KeV，劑量為1012cm-3至1016cm-3。
在本發明的一實施例中，上述的半導體基底的形成方法中，處理步驟使第二區的單晶態III-V族化合物半導體層完全轉化為非晶態III-V族化合物半導體層。
在本發明的一實施例中，上述的半導體基底的形成方法更包括下列步驟。於非晶態III-V族化合物半導體層上形成絕緣層。於絕緣層上形成一第二含矽層。
在本發明的一實施例中，上述的半導體基底的形成方法中，第一含矽層的晶面與第二含矽層的晶面不同。
基於上述，藉由本發明的方法，可簡單地將III-V族化合物半導體元件與矽元件有效地整合在一起，將形成於不同區上的元件有效地隔離。因此，可抑制位於半導體基底的不同區的元件之間的干擾。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧第一區
20‧‧‧第二區
100‧‧‧第一含矽層
102、102b、102b1‧‧‧單晶態III-V族化合物半導體層
102a、102a1‧‧‧非晶態III-V族化合物半導體層
104、104b、104b1‧‧‧單晶態第一氮化鎵層
104a、104a1‧‧‧非晶態第一氮化鎵層
106、106b‧‧‧單晶態氮化鋁鎵層
106a‧‧‧非晶態氮化鋁鎵層
108、108b‧‧‧單晶態第二氮化鎵層
108a‧‧‧非晶態第二氮化鎵層
110、110a‧‧‧罩幕層
112‧‧‧絕緣層
114‧‧‧第二含矽層
116、124‧‧‧保護層
118‧‧‧半導體基底
120、122、320、322、420、422‧‧‧塊狀物
144、344、444、670‧‧‧第一元件
146、546、672‧‧‧第二元件
156、356、456、556、656‧‧‧半導體元件
158、358、458‧‧‧二維電子氣
324、326、424、426‧‧‧III-V族化合物半導體層
548、550‧‧‧元件
D1、D2、D3‧‧‧汲極
G1、G2、G3‧‧‧閘極
I‧‧‧植入製程
S1、S2、S3‧‧‧源極
圖1A至圖1C是依照本發明一實施例所繪示的一種半導體基底的形成方法的剖面示意圖。
圖1D至圖1F是依照本發明一實施例所繪示的一種半導體元件的形成方法的剖面示意圖。
圖2至圖6是依照本發明多個實施例所繪示的半導體元件的剖面示意圖。
圖1A至圖1C是依照本發明一實施例所繪示的一種半導體基底的形成方法的剖面示意圖。
請參照圖1A，半導體基底的形成方法包括下列步驟。首先，提供第一含矽層100，其具有第一區10以及第二區20。在一實施例中，第一含矽層100可為具有<111>晶面的單晶矽層。
接著，於第一區10以及第二區20的第一含矽層100上形成單晶態III-V族化合物半導體層102。形成單晶態III-V族化合物半導體層102的方法包括進行磊晶成長(epitaxial growth)製程，且單晶態III-V族化合物半導體層102可包括多數層。在一實施例中，單晶態III-V族化合物半導體層102可包括單晶態第一氮化鎵層104、單晶態氮化鋁鎵層106以及單晶態第二氮化鎵層 108。單晶態第一氮化鎵層104可配置於第一含矽層100上。單晶態氮化鋁鎵層106可配置於單晶態第一氮化鎵層104上。單晶態第二氮化鎵層108可配置於單晶態氮化鋁鎵層106上。
之後，在第一含矽層100上形成罩幕層110。在一實施例中，罩幕層110覆蓋第一區10的單晶態III-V族化合物半導體層102，而裸露出第二區20的單晶態III-V族化合物半導體層102的頂面。在一實施例中，罩幕層110的材料包括(例如但不限於)氧化矽。
接著，請參照圖1B，進行處理步驟，使得第二區20的單晶態III-V族化合物半導體層102至少部分地轉化為非晶態III-V族化合物半導體層。在一實施例中，於上述處理步驟之後，第二區20的單晶態III-V族化合物半導體層102完全地轉化為非晶態III-V族化合物半導體層102a，留下第一區10的單晶態III-V族化合物半導體層102b。非晶態III-V族化合物半導體層102a包括非晶態第一氮化鎵層104a、非晶態氮化鋁鎵層106a以及非晶態第二氮化鎵層108a。單晶態III-V族化合物半導體層102b包括單晶態第一氮化鎵層104b、單晶態氮化鋁鎵層106b以及單晶態第二氮化鎵層108b。
本發明的處理步驟用於非晶化第二區20的至少部分膜層，故可視為非晶化步驟。在一實施例中，上述處理步驟包括進行植入製程I，其所使用的植入源可包括氮、氬、碳、氟或其組合。舉例來說，植入製程I的能量可為1KeV至600KeV，且其劑量可為1012cm-3至1016cm-3，但本發明並不以此為限。在一實施例中，第一區10的單晶態III-V族化合物半導體層102b與第二區 20的非晶態III-V族化合物半導體層102a的組成實質上相同。
本發明的處理步驟將第二區20的單晶態III-V族化合物半導體層轉化為非晶態III-V族化合物半導體層102a，進而顯著地提高其電阻值。在一實施例中，第二區20的非晶態III-V族化合物半導體層102a可視為絕緣體。
之後，請參照圖1C，可於非晶態III-V族化合物半導體層102a上形成絕緣層112。在一實施例中，絕緣層112的材料包括(例如但不限於)氧化矽。接著，可於絕緣層112上形成第二含矽層114，其中第一含矽層100的晶面可與第二含矽層114的晶面不同。在一實施例中，第一含矽層100可為具有<111>晶面的單晶矽層，而第二含矽層114可為具有<100>晶面的單晶矽層。以此方式，在第二區20上可形成絕緣體上矽(silicon on insulator)的結構。接著，可在第二含矽層上114形成保護層116，以覆蓋第二含矽層114。保護層116的材料可包括(例如但不限於)氧化矽。至此，完成本發明的半導體基底118的製作。
以下，將參照圖1C說明本發明的半導體基底118的結構。請參照圖1C，半導體基底118包括第一含矽層100、單晶態III-V族化合物半導體層102b以及非晶態III-V族化合物半導體層102a。第一含矽層100具有第一區10以及第二區20。單晶態III-V族化合物半導體層102b配置於第一區10的第一含矽層100上。另外，非晶態III-V族化合物半導體層102a配置於第二區20的第一含矽層100上。
在一實施例中，單晶態III-V族化合物半導體層102b可與非晶態III-V族化合物半導體層102a接觸。單晶態III-V族化合 物半導體層102b與非晶態III-V族化合物半導體層102a的組成可實質上相同，僅晶態不同。單晶態III-V族化合物半導體層102b可包括依序配置於第一區10的第一含矽層100上的單晶態第一氮化鎵層104b、單晶態氮化鋁鎵層106b以及單晶態第二氮化鎵層108b。相似地，非晶態III-V族化合物半導體層102a可包括依序配置於第二區20的第一含矽層100上的非晶態第一氮化鎵層104a、非晶態氮化鋁鎵層106a以及非晶態第二氮化鎵層108a。
半導體基底118可更包括絕緣層112與第二含矽層114，其中絕緣層112配置於非晶態III-V族化合物半導體層102a上，且第二含矽層114配置於絕緣層112上。第一含矽層100例如具有<111>晶面，且第二含矽層114例如具有<100>晶面。另外，半導體基底118可更包括保護層116，其覆蓋第二含矽層114。
特別要說明的是，由於半導體基底118的第二區20的非晶態III-V族化合物半導體層102a的電阻值相當高，所以在後續製程中形成於第二區20上的元件可與形成於第一區10上的元件有效地隔離。因此，可抑制第一區10上的元件與第二區20上的元件之間的干擾。
此外，本發明的半導體基底118中，第一區10的單晶態III-V族化合物半導體層102b與第二區20的非晶態III-V族化合物半導體層102a形成為直接接觸，因此，在後續製程中形成於第一區10上的元件可緊鄰於形成於第二區20上的元件，兩者之間的間距可大幅降至微米等級。如此一來，可將不同的元件形成於半導體基底118上，以形成系統晶片(system on chip)，且可抑制不同的元件之間的干擾。
圖1D至圖1F是依照本發明一實施例所繪示的一種半導體元件的形成方法的剖面示意圖。
首先，提供如圖1C所示的半導體基底118。接著，請參照圖1D至圖1F，於單晶態III-V族化合物半導體層102b上形成第一元件144。在一實施例中，第一元件144可為HEMT元件。如圖1D所示，於單晶態III-V族化合物半導體層102b上形成兩個塊狀物120與122。形成兩個塊狀物120與122的方法包括先將罩幕層110圖案化，以形成罩幕層110a。接著，分別於罩幕層110a的兩側形成塊狀物120及122。具體來說，塊狀物120可形成於絕緣層112與罩幕層110a之間，且罩幕層110a可形成於塊狀物102與塊狀物122之間。
在一實施例中，塊狀物120與122中的每一者可包括三元化合物或四元化合物。三元化合物可包括(但不限於)銦、鋁、及氮。四元化合物可包括(但不限於)銦、鋁、鎵以及氮。上述三元化合物或四元化合物可為單層或多層結構。在一實施例中，三元化合物可包括InAlN，或由InAlN與AlN所組成。在一實施例中，四元化合物可由InAlGaN所組成。
此外，塊狀物120與122的形成方法包括進行選擇性磊晶再成長(selectively epitaxial regrowth)，其僅會在裸露出的單晶態III-V族化合物半導體層102b上磊晶成長，且其製程溫度大約在800℃至1200℃之間。由於第二含矽層114可被保護層116所覆蓋，所以在形成塊狀物120與122時可避免第二含矽層114受到高溫破壞。
接著，可在第一區10與第二區20上形成保護層124。具 體來說，保護層124可覆蓋塊狀物120與122、罩幕層110a、非晶態III-V族化合物半導體層102a以及保護層116。保護層124的材料可包括(但不限於)氧化矽(SiO2)、氮化矽(Si3N4)、氧化鋁(Al2O3)或其組合。
之後，請參照圖1F，形成閘極G1、汲極D1以及源極S1。在一實施例中，先形成汲極D1以及源極S1，再形成閘極G1。具體地說，汲極D1/源極S1形成為穿過保護層124、塊狀物120/122，並延伸至單晶態III-V族化合物半導體層102b的單晶態第二氮化鎵層108b以及單晶態氮化鋁鎵層106b中。形成源極S1/汲極D1的方法包括先於塊狀物122/120中分別形成金屬插塞，再進行高溫擴散製程，使金屬插塞的金屬向下擴散至第二氮化鎵層108b以及單晶態氮化鋁鎵層106b中。源極S1/汲極D1的材料包括(例如但不限於)鋁鈦合金，或其他可與單晶態III-V族化合物半導體層102b形成歐姆接觸(ohmic contact)的材料。
接著，閘極G1形成為穿過保護層124、罩幕層110a。形成閘極G1的方法包括先於保護層124、罩幕層110a中形成開口，再填入閘極金屬於開口中。閘極金屬的材料包括(例如但不限於)氮化鈦、鎳或其他可與單晶態III-V族化合物半導體層102b形成蕭基接觸(schottky contact)的材料。在一實施例中，閘極G1除了可為如圖1F所示的結構之外，也可為金屬在絕緣體上(metal-on-insulator,MIS)結構。
之後，於非晶態III-V族化合物半導體層102a上形成第二元件146。在一實施例中，第二元件146包括金氧半導體元件。第二元件146包括閘極G2以及位於閘極G2兩側的汲極D2與源 極S2。閘極G2、汲極D2與源極S2形成為穿過保護層124與116，並與第二含矽層114中的摻雜區(未繪示)電性連接。至此，完成本發明的半導體元件156的製作。
以下，將參照圖1F說明本發明的半導體元件156的結構。請參照圖1F，半導體元件156包括半導體基底118、第一元件144以及第二元件146。第一元件144配置於單晶態III-V族化合物半導體層102b上，且第二元件146配置於非晶態III-V族化合物半導體層102a上。
第一元件144可包括閘極G1、塊狀物120與塊狀物122、汲極D1與源極S1。塊狀物120與塊狀物122位於閘極G1的兩側，且汲極D1與源極S1分別穿過塊狀物120與塊狀物122。在一實施例中，塊狀物120與塊狀物122的材料包括氮化鋁銦(InAlN)。第二元件146可包括閘極G2、汲極D2與源極S2。
特別要說明的是，第一元件144在運作時，可形成二維電子氣158，其位於第一氮化鎵層104b中鄰近於氮化鋁鎵層106b的區域。二維電子氣158可提高第一元件144的操作速度。另外，由於第二元件146下方的非晶態III-V族化合物半導體層102a的電阻值相當高，故上述的二維電子氣158並不會延伸至第二元件146的下方。因此，第二元件146在運作時，可避免受到第一元件144的干擾。
基於上述，由於半導體基底118的第二區20的非晶態III-V族化合物半導體層102a的電阻值相當高，所以形成於第二區20上的第二元件146可與形成於第一區10上的第一元件144有效地隔離。因此，可抑制第一元件144與第二元件146之間的干擾。
在上述實施例中，圖1B的處理步驟將第二區20的單晶態III-V族化合物半導體層102完全地轉化為非晶態III-V族化合物半導體層102a，其用於說明，並不用於限定本發明。在另一實施例中(請參照圖2)，圖1B的處理步驟僅將第二區20的單晶態III-V族化合物半導體層102部分地轉化為非晶態III-V族化合物半導體層102a1，留下第一區10的單晶態III-V族化合物半導體層102b1。更具體地說，第二區20的單晶態第二氮化鎵層108與單晶態氮化鋁鎵層106均完全轉化為非晶態第二氮化鎵層108a以及非晶態氮化鋁鎵層106a，而第二區20的單晶態第一氮化鎵層104僅部分轉化為非晶態第一氮化鎵層104a1。
第一區10的單晶態III-V族化合物半導體層102b1包括單晶態第一氮化鎵層104b1、單晶態氮化鋁鎵層106b以及單晶態第二氮化鎵層108b，且單晶態III-V族化合物半導體層102b1可更延伸至第二區20的非晶態III-V族化合物半導體層102a1與第一含矽層100之間。
另外，單晶態III-V族化合物半導體層102b1於第一區10的厚度大於單晶態III-V族化合物半導體層102b1於第二區20的厚度，使得第二區20的非晶態III-V族化合物半導體層102a1的底部低於第一元件144在運作時於單晶態III-V族化合物半導體層102b1產生的二維電子氣158的區域。
據此，第一元件144所形成的二維電子氣158亦並不會延伸至第二元件146的下方。因此，第二元件146在運作時，不會受到第一元件144的干擾。
圖3至圖6是依照本發明所繪示多個實施例的半導體元 件的剖面示意圖。圖3至圖6的半導體元件與圖1F的半導體元件類似，差異處將詳細說明如下，相同處則不再贅述。
圖3的半導體元件356與圖1F所示的半導體元件156相似，其差異處在於：圖3的塊狀物320與322為多層結構，而圖1F的塊狀物120與122為單層結構。
更具體地說，圖3的第一元件344的塊狀物320與322中的每一者均包括兩個III-V族化合物半導體層324與位於III-V族化合物半導體層324之間的III-V族化合物半導體層326。在一實施例中，III-V族化合物半導體層324的材料包括氮化鋁銦，且III-V族化合物半導體層326的材料包括氮化鋁(AlN)。
圖4的半導體元件456與圖1F所示的半導體元件156相似，其差異處在於：圖4的塊狀物420與422為超晶格(superlattice)結構，而圖1F的塊狀物120與122為單層結構。
更具體地說，圖4的第一元件444的塊狀物420與422中的每一者均包括交互堆疊的多層III-V族化合物半導體層424與多層III-V族化合物半導體層426，以形成超晶格結構。
在一實施例中，塊狀物420與422的最底層為III-V族化合物半導體層424。在另一實施例中，塊狀物420與422的最底層為III-V族化合物半導體層426。此外，本發明並不對III-V族化合物半導體層424的數量與III-V族化合物半導體層426的數量作限制。在一實施例中，III-V族化合物半導體層424的材料包括氮化鋁銦，且III-V族化合物半導體層426的材料包括氮化鋁。
與圖1F所示的第一元件144相比，圖3的第一元件344與圖4的第一元件444在運作時可產生濃度更高的二維電子氣 358、458。因此，可進一步第提高第一元件344、444的操作速度。
在圖4所示的實施例中，III-V族化合物半導體層424的能隙(bandgap)可與III-V族化合物半導體層426的能隙相異。另外，每一III-V族化合物半導體層424與每一III-V族化合物半導體層426的厚度僅為數奈米。據此，可在第一元件444中形成多重量子井(multiple quantum wells)，而進一步提高二維電子氣458的濃度。換言之，可進一步地提高第一元件444的操作速度。
圖5的半導體元件556與圖1F所示的半導體元件156相似，其差異處在於：圖5的半導體元件556中的第二元件546可包括彼此相鄰的元件548與元件550。元件548可包括閘極G2、汲極D2與源極S2。元件550可包括閘極G3、汲極D3與源極S3。在一實施例中，元件548與元件550構成互補式金屬氧化物半導體(CMOS)元件。
圖6的半導體元件656與圖IF所示的半導體元件156相似，其差異處在於：圖6的半導體元件656中的第一元件670與第二元件672不限於上述的元件，所屬領域中具有通常知識者可依據其需求選用適當的元件作為第一元件670與第二元件672。
在一實施例中，第一元件670為III-V族化合物半導體元件，例如HEMT元件；而第二元件672為矽元件，例如金氧半元件、二極體元件、微波元件、高功率元件、高壓元件或其組合。
綜上所述，藉由本發明的方法，可簡單地將III-V族化合物半導體元件與矽元件有效地整合在一起，將形成於不同區上的元件有效地隔離。因此，可抑制位於半導體基底的不同區的元件之間的干擾。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧第一區
20‧‧‧第二區
100‧‧‧第一含矽層
102a‧‧‧非晶態III-V族化合物半導體層
102b‧‧‧單晶態III-V族化合物半導體層
104a‧‧‧非晶態第一氮化鎵層
104b‧‧‧單晶態第一氮化鎵層
106a‧‧‧非晶態氮化鋁鎵層
106b‧‧‧單晶態氮化鋁鎵層
108a‧‧‧非晶態第二氮化鎵層
108b‧‧‧單晶態第二氮化鎵層
110‧‧‧罩幕層
112‧‧‧絕緣層
114‧‧‧第二含矽層
116‧‧‧保護層
118‧‧‧半導體基底

Claims (10)

  1. 一種半導體基底，包括：一第一含矽層，具有一第一區以及一第二區；以及一單晶態III-V族化合物半導體層，配置於該第一區的該第一含矽層上；以及一非晶態III-V族化合物半導體層，配置於該第二區的該第一含矽層上。
  2. 如申請專利範圍第1項所述的半導體基底，其中該單晶態III-V族化合物半導體層與該非晶態III-V族化合物半導體層各自包括：一第一氮化鎵層，配置於該第一含矽層上；一氮化鋁鎵層，配置於該第一氮化鎵層上；以及一第二氮化鎵層，配置於該氮化鋁鎵層上。
  3. 如申請專利範圍第1項所述的半導體基底，其中該單晶態III-V族化合物半導體層更延伸至該非晶態III-V族化合物半導體層與該第一含矽層之間，且該單晶態III-V族化合物半導體層於該第一區的厚度大於該單晶態III-V族化合物半導體層於該第二區的厚度。
  4. 一種半導體元件，包括：一第一含矽層，具有一第一區以及一第二區；以及一單晶態III-V族化合物半導體層，配置於該第一區的該第一含矽層上；一非晶態III-V族化合物半導體層，配置於該第二區的該第一含矽層上； 一第一元件，配置於該單晶態III-V族化合物半導體層上；以及一第二元件，配置於該非晶態III-V族化合物半導體層上。
  5. 如申請專利範圍第4項所述的半導體元件，其中該單晶態III-V族化合物半導體層與該非晶態III-V族化合物半導體層的組成相同且彼此接觸。
  6. 如申請專利範圍第4項所述的半導體元件，其中該第一元件包括：一閘極：二塊狀物，位於該閘極兩側；以及一源極與一汲極，分別穿過該些塊狀物，其中該些塊狀物的材料包括三元化合物或四元化合物。
  7. 如申請專利範圍第4項所述的半導體元件，更包括：一絕緣層，配置於該非晶態III-V族化合物半導體層上；以及一第二含矽層，配置於該絕緣層上，其中該第二元件配置於該第二含矽層上。
  8. 如申請專利範圍第4項所述的半導體元件，其中該單晶態III-V族化合物半導體層更延伸至該非晶態III-V族化合物半導體層與該第一含矽層之間，且該單晶態III-V族化合物半導體層於該第一區的厚度大於該單晶態III-V族化合物半導體層於該第二區的厚度，使得該非晶態III-V族化合物半導體層的底部低於該第一元件在運作時於該單晶態III-V族化合物半導體層產生的二維電子氣的區域。
  9. 一種半導體基底的形成方法，包括： 提供一第一含矽層，該第一含矽層具有一第一區以及一第二區；於該第一區以及該第二區的該第一含矽層上形成一單晶態III-V族化合物半導體層；以及進行一處理步驟，使得該第二區的該單晶態III-V族化合物半導體層至少部分轉化為一非晶態III-V族化合物半導體層，其中該非晶態III-V族化合物半導體層持續為非晶態狀態。
  10. 如申請專利範圍第9項所述的半導體基底的形成方法，其中該處理步驟包括進行一植入製程。
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