TWI597631B - Touch display device - Google Patents
Touch display device Download PDFInfo
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- TWI597631B TWI597631B TW105103703A TW105103703A TWI597631B TW I597631 B TWI597631 B TW I597631B TW 105103703 A TW105103703 A TW 105103703A TW 105103703 A TW105103703 A TW 105103703A TW I597631 B TWI597631 B TW I597631B
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- display device
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- 239000000758 substrate Substances 0.000 claims description 93
- 239000004065 semiconductor Substances 0.000 claims description 30
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 6
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- 229910002367 SrTiO Inorganic materials 0.000 description 1
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- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/136286—Wiring, e.g. gate line, drain line
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- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
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- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04112—Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material
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Description
本揭露實施例係有關於觸控顯示裝置，且特別係有關於一種觸控訊號線位於陣列基板上之觸控顯示裝置。 The disclosure relates to a touch display device, and more particularly to a touch display device in which a touch signal line is located on an array substrate.
隨著科技不斷的進步，使得各種資訊設備不斷地推陳出新，例如手機、平板電腦、超輕薄筆電、及衛星導航等。除了一般以鍵盤或滑鼠的輸入或操控之外，利用觸控式技術來操控資訊設備是一種相當直覺且受歡迎的操控方式。其中，觸控顯示裝置具有人性化及直覺化的輸入操作介面，使得任何年齡層的使用者都可直接以手指或觸控筆選取或操控資訊設備。 With the continuous advancement of technology, various information devices are constantly being introduced, such as mobile phones, tablet computers, ultra-thin notebooks, and satellite navigation. In addition to the keyboard or mouse input or manipulation, the use of touch technology to manipulate information devices is a fairly intuitive and popular way to manipulate. Among them, the touch display device has a user-friendly and intuitive input operation interface, so that users of any age can directly select or manipulate the information device with a finger or a stylus.
然而，目前的觸控顯示裝置並非各方面皆令人滿意。舉例而言，觸控顯示裝置之儲存電容係指裝置之畫素電極與共同電極之間的電容。當觸控顯示裝置之解析度增加時，若此儲存電容太小，則易有畫面品質不良之風險。 However, current touch display devices are not satisfactory in all aspects. For example, the storage capacitance of the touch display device refers to the capacitance between the pixel electrode of the device and the common electrode. When the resolution of the touch display device increases, if the storage capacitor is too small, there is a risk of poor picture quality.
因此，業界仍須一種可更進一步提升觸控顯示裝置之儲存電容，以降低畫面品質不良之風險的觸控顯示裝置。 Therefore, the industry still needs a touch display device that can further improve the storage capacitance of the touch display device to reduce the risk of poor picture quality.
本揭露提供一種觸控顯示裝置，包括：第一基板；電晶體，設於第一基板上；第一絕緣層，設於電晶體上；第一電 極，設於第一絕緣層上；第二絕緣層，設於第一電極上；導電層，設於第二絕緣層上，導電層包括觸控訊號線；第三絕緣層，設於導電層上；及第二電極，設於第三絕緣層上，其中第一電極與第二電極的其中之一與觸控訊號線電性連接，其中第一電極與第二電極的另一者與電晶體電性連接，且與導電層至少部分重疊。 The present disclosure provides a touch display device including: a first substrate; a transistor disposed on the first substrate; a first insulating layer disposed on the transistor; The first insulating layer is disposed on the first insulating layer; the second insulating layer is disposed on the first electrode; the conductive layer is disposed on the second insulating layer, the conductive layer comprises a touch signal line; and the third insulating layer is disposed on the conductive layer And the second electrode is disposed on the third insulating layer, wherein one of the first electrode and the second electrode is electrically connected to the touch signal line, wherein the other of the first electrode and the second electrode is electrically connected The crystal is electrically connected and at least partially overlaps the conductive layer.
為讓本揭露之特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下。 In order to make the features and advantages of the present disclosure more comprehensible, the preferred embodiments are described below, and are described in detail below with reference to the accompanying drawings.
100‧‧‧顯示裝置 100‧‧‧ display device
102‧‧‧陣列基板 102‧‧‧Array substrate
104‧‧‧閘極線 104‧‧‧ gate line
106‧‧‧資料線 106‧‧‧Information line
108‧‧‧次畫素 108‧‧‧ pixels
110‧‧‧電晶體 110‧‧‧Optoelectronics
112‧‧‧源極電極 112‧‧‧Source electrode
114‧‧‧汲極電極 114‧‧‧汲electrode
116‧‧‧半導體層 116‧‧‧Semiconductor layer
116S1‧‧‧第一側 116S1‧‧‧ first side
116S2‧‧‧第二側 116S2‧‧‧ second side
118‧‧‧閘極電極 118‧‧‧gate electrode
120‧‧‧導電層 120‧‧‧ Conductive layer
120E‧‧‧邊緣 120E‧‧‧ edge
120E1‧‧‧邊緣 120E1‧‧‧ edge
120E2‧‧‧邊緣 120E2‧‧‧ edge
120E3‧‧‧邊緣 120E3‧‧‧ edge
120E4‧‧‧邊緣 120E4‧‧‧ edge
120A‧‧‧第一部分 120A‧‧‧Part 1
120B‧‧‧第二部分 120B‧‧‧Part II
122‧‧‧畫素電極 122‧‧‧pixel electrodes
124‧‧‧第一基板 124‧‧‧First substrate
126‧‧‧閘極介電層 126‧‧ ‧ gate dielectric layer
128‧‧‧第一絕緣層 128‧‧‧First insulation
128A1‧‧‧開口 128A1‧‧‧ openings
128A2‧‧‧開口 128A2‧‧‧ openings
128A3‧‧‧開口 128A3‧‧‧ openings
130‧‧‧平坦層 130‧‧‧flat layer
130A1‧‧‧開口 130A1‧‧‧ openings
130A2‧‧‧開口 130A2‧‧‧ openings
130A3‧‧‧開口 130A3‧‧‧ openings
130A4‧‧‧開口 130A4‧‧‧ openings
130S1‧‧‧第三側 130S1‧‧‧ third side
130S2‧‧‧第四側 130S2‧‧‧ fourth side
132‧‧‧共同電極 132‧‧‧Common electrode
134‧‧‧第二絕緣層 134‧‧‧Second insulation
134S‧‧‧上表面 134S‧‧‧ upper surface
134A1‧‧‧開口 134A1‧‧‧ openings
134A2‧‧‧開口 134A2‧‧‧ openings
134A3‧‧‧開口 134A3‧‧‧ openings
136‧‧‧驅動元件 136‧‧‧Drive components
138‧‧‧第三絕緣層 138‧‧‧ Third insulation layer
138A1‧‧‧開口 138A1‧‧‧ openings
138A2‧‧‧開口 138A2‧‧‧ openings
138A3‧‧‧開口 138A3‧‧‧ openings
138A4‧‧‧開口 138A4‧‧‧ openings
140‧‧‧第二基板 140‧‧‧second substrate
142‧‧‧顯示介質 142‧‧‧Display media
144‧‧‧基板 144‧‧‧Substrate
146‧‧‧遮光層 146‧‧‧Lighting layer
146E1‧‧‧邊緣 146E1‧‧‧ edge
146E2‧‧‧邊緣 146E2‧‧‧ edge
148‧‧‧彩色濾光層 148‧‧‧Color filter layer
150‧‧‧保護層 150‧‧‧protection layer
300‧‧‧顯示裝置 300‧‧‧ display device
400‧‧‧顯示裝置 400‧‧‧ display device
500‧‧‧顯示裝置 500‧‧‧ display device
600‧‧‧顯示裝置 600‧‧‧ display device
D1‧‧‧第一距離 D1‧‧‧First distance
D2‧‧‧第二距離 D2‧‧‧Second distance
D3‧‧‧第三距離 D3‧‧‧ third distance
D4‧‧‧第四距離 D4‧‧‧ fourth distance
1B-1B’‧‧‧線段 1B-1B’‧‧‧ segment
1C-1C’‧‧‧線段 1C-1C’‧‧‧ segment
1D-1D’‧‧‧線段 1D-1D’‧‧‧ segments
3B-3B’‧‧‧線段 3B-3B’‧‧‧ Segment
3C-3C’‧‧‧線段 3C-3C’‧‧‧ segment
3D-3D’‧‧‧線段 3D-3D’‧‧‧ segments
4B-4B’‧‧‧線段 4B-4B’‧‧‧ Segment
4C-4C’‧‧‧線段 4C-4C’‧‧‧ Segment
5B-5B’‧‧‧線段 5B-5B’‧‧‧ Segment
6B-6B’‧‧‧線段 6B-6B’‧‧‧ Segment
6C-6C’‧‧‧線段 6C-6C’‧‧‧ segment
A1‧‧‧方向 A1‧‧ Direction
A2‧‧‧方向 A2‧‧‧ direction
第1A圖係本揭露一些實施例之顯示裝置之上視圖。 Figure 1A is a top plan view of a display device in accordance with some embodiments.
第1B圖係沿著第1A圖之線段1B-1B’所繪製之剖面圖。 Fig. 1B is a cross-sectional view taken along line 1B-1B' of Fig. 1A.
第1C圖係沿著第1A圖之線段1C-1C’所繪製之剖面圖。 Fig. 1C is a cross-sectional view taken along line 1C-1C' of Fig. 1A.
第1D圖係沿著第1A圖之線段1D-1D’所繪製之剖面圖。 The 1D image is a cross-sectional view taken along the line segment 1D-1D' of Fig. 1A.
第2圖係本揭露一些實施例之顯示裝置之上視圖。 Figure 2 is a top plan view of a display device of some embodiments.
第3A圖係本揭露一些實施例之顯示裝置之上視圖。 Figure 3A is a top plan view of a display device of some embodiments.
第3B圖係沿著第3A圖之線段3B-3B’所繪製之剖面圖。 Fig. 3B is a cross-sectional view taken along line 3B-3B' of Fig. 3A.
第3C圖係沿著第3A圖之線段3C-3C’所繪製之剖面圖。 Fig. 3C is a cross-sectional view taken along line 3C-3C' of Fig. 3A.
第3D圖係沿著第3A圖之線段3D-3D’所繪製之剖面圖。 The 3D image is a cross-sectional view taken along line 3D-3D' of Fig. 3A.
第4A圖係本揭露一些實施例之顯示裝置之上視圖。 Figure 4A is a top plan view of a display device in accordance with some embodiments.
第4B圖係沿著第4A圖之線段4B-4B’所繪製之剖面圖。 Fig. 4B is a cross-sectional view taken along line 4B-4B' of Fig. 4A.
第4C圖係沿著第4A圖之線段4C-4C’所繪製之剖面圖。 Fig. 4C is a cross-sectional view taken along line 4C-4C' of Fig. 4A.
第5A圖係本揭露一些實施例之顯示裝置之上視圖。 Figure 5A is a top plan view of a display device in accordance with some embodiments.
第5B圖係沿著第5A圖之線段5B-5B’所繪製之剖面圖。 Fig. 5B is a cross-sectional view taken along line 5B-5B' of Fig. 5A.
第6A圖係本揭露一些實施例之顯示裝置之上視圖。 Figure 6A is a top plan view of a display device in accordance with some embodiments.
第6B圖係沿著第6A圖之線段6B-6B’所繪製之剖面圖。 Fig. 6B is a cross-sectional view taken along line 6B-6B' of Fig. 6A.
第6C圖係沿著第6A圖之線段6C-6C’所繪製之剖面圖。 Fig. 6C is a cross-sectional view taken along line 6C-6C' of Fig. 6A.
以下針對本揭露之顯示裝置作詳細說明。應了解的是，以下之敘述提供許多不同的實施例或例子，用以實施本揭露之不同樣態。以下所述特定的元件及排列方式僅為簡單清楚描述本揭露。當然，這些僅用以舉例而非本揭露之限定。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本揭露，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸之情形。或者，亦可能間隔有一或更多其它材料層之情形，在此情形中，第一材料層與第二材料層之間可能不直接接觸。 The display device of the present disclosure will be described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the various aspects of the disclosure. The specific elements and arrangements described below are merely illustrative of the disclosure. Of course, these are only used as examples and not as a limitation of the disclosure. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the disclosure, and are not intended to be a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.
必需了解的是，圖式之元件或裝置可以此技術人士所熟知之各種形式存在。此外，當某層在其它層或基板「上」時，有可能是指「直接」在其它層或基板上，或指某層在其它層或基板上，或指其它層或基板之間夾設其它層。 It must be understood that the elements or devices of the drawings may be in various forms well known to those skilled in the art. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.
此外，實施例中可能使用相對性的用語，例如「較低」或「底部」及「較高」或「頂部」，以描述圖式的一個元件對於另一元件的相對關係。能理解的是，如果將圖式的裝置翻轉使 其上下顛倒，則所敘述在「較低」側的元件將會成為在「較高」側的元件。 In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawing to another. It can be understood that if the device of the schema is flipped When it is turned upside down, the component described on the "lower" side will become the component on the "higher" side.
在此，「約」、「大約」、「大抵」之用語通常表示在一給定值或範圍的20%之內，較佳是10%之內，且更佳是5%之內，或3%之內，或2%之內，或1%之內，或0.5%之內。在此給定的數量為大約的數量，亦即在沒有特定說明「約」、「大約」、「大抵」的情況下，仍可隱含「約」、「大約」、「大抵」之含義。 Here, the terms "about", "about" and "major" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, in the absence of specific descriptions of "about", "about" and "major", the meanings of "about", "about" and "major" may still be implied.
能理解的是，雖然在此可使用用語「第一」、「第二」、「第三」等來敘述各種元件、組成成分、區域、層、及/或部分，這些元件、組成成分、區域、層、及/或部分不應被這些用語限定，且這些用語僅是用來區別不同的元件、組成成分、區域、層、及/或部分。因此，以下討論的一第一元件、組成成分、區域、層、及/或部分可在不偏離本揭露之教示的情況下被稱為一第二元件、組成成分、區域、層、及/或部分。 It will be understood that the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or portions, such elements, components, and regions. The layers, and/or portions are not to be limited by the terms, and the terms are used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or portion discussed below may be referred to as a second element, component, region, layer, and/or without departing from the teachings of the disclosure. section.
除非另外定義，在此使用的全部用語(包括技術及科學用語)具有與此篇揭露所屬之一般技藝者所通常理解的相同涵義。能理解的是這些用語，例如在通常使用的字典中定義的用語，應被解讀成具有一與相關技術及本揭露的背景或上下文一致的意思，而不應以一理想化或過度正式的方式解讀，除非在此特別定義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning It will be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context or context of the present disclosure, and should not be in an idealized or overly formal manner. Interpretation, unless specifically defined herein.
本揭露實施例可配合圖式一併理解，本揭露之圖式亦被視為揭露說明之一部分。需了解的是，本揭露之圖式並未以實際裝置及元件之比例繪示。在圖式中可能誇大實施例的形狀與厚度以便清楚表現出本揭露之特徵。此外，圖式中之結構及裝置 係以示意之方式繪示，以便清楚表現出本揭露之特徵。 The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not shown in the form of actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly illustrate the features of the present disclosure. In addition, the structure and device in the drawings It is illustrated in a schematic manner to clearly illustrate the features of the present disclosure.
在本揭露中，相對性的用語例如「下」、「上」、「水平」、「垂直」、「之下」、「之上」、「頂部」、「底部」等等應被理解為該段以及相關圖式中所繪示的方位。此相對性的用語僅是為了方便說明之用，其並不代表其所敘述之裝置需以特定方位來製造或運作。而關於接合、連接之用語例如「連接」、「互連」等，除非特別定義，否則可指兩個結構係直接接觸，或者亦可指兩個結構並非直接接觸，其中有其它結構設於此兩個結構之間。且此關於接合、連接之用語亦可包括兩個結構都可移動，或者兩個結構都固定之情況。 In this disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "lower", "above", "top", "bottom", etc. shall be understood as The orientation shown in the paragraph and related schemas. This relative term is used for convenience of description only, and does not mean that the device described therein is to be manufactured or operated in a particular orientation. Terms such as "joining" and "interconnecting", etc., unless otherwise defined, may mean that two structures are in direct contact, or that two structures are not in direct contact, and other structures are provided here. Between the two structures. The term "joining and joining" may also include the case where both structures are movable or both structures are fixed.
應注意的是，在後文中「基板」一詞可包括透明基板上已形成的元件與覆蓋在基板上的各種膜層，其上方可以已形成任何所需的電晶體元件，不過此處為了簡化圖式，僅以平整的基板表示之。此外，「基板表面」係包括透明基板上最上方且暴露之膜層，例如一絕緣層及/或金屬線。 It should be noted that the term "substrate" may hereinafter include the formed elements on the transparent substrate and the various film layers overlying the substrate, and any desired transistor elements may have been formed thereon, but here to simplify The figure is shown only on a flat substrate. In addition, the "substrate surface" includes the uppermost and exposed film layer on the transparent substrate, such as an insulating layer and/or metal lines.
顯示裝置之儲存電容係指裝置之畫素電極與共同電極之間的電容。當顯示裝置之解析度越高時，其畫素的尺寸越小。此時若儲存電容太小，則於畫素進入電荷保持(holding)狀態時，會因為電晶體之微小漏電流而造成畫素電壓(或液晶夾壓)的改變，導致畫面亮度產生變化，形成畫面閃爍。此外，儲存電容過小也會導致畫素的電容耦合效應過大，易有畫面品質不良之風險，也會產生畫面閃爍。 The storage capacitance of the display device refers to the capacitance between the pixel electrode of the device and the common electrode. When the resolution of the display device is higher, the size of the pixel is smaller. At this time, if the storage capacitor is too small, when the pixel enters the charge holding state, the pixel voltage (or liquid crystal pinch) changes due to the tiny leakage current of the transistor, resulting in a change in the brightness of the screen. The picture flashes. In addition, if the storage capacitor is too small, the capacitive coupling effect of the pixel will be too large, and the risk of poor picture quality may occur, and the screen flicker may also occur.
因此，由於顯示裝置之觸控訊號線係與共同電極電性連接，故此觸控訊號線亦可視為共同電極之延伸。因此，本揭 露實施例藉由將此觸控訊號線與畫素電極重疊，可提升顯示裝置之儲存電容，降低畫面品質不良之風險。 Therefore, since the touch signal line of the display device is electrically connected to the common electrode, the touch signal line can also be regarded as an extension of the common electrode. Therefore, this disclosure In the embodiment, by overlapping the touch signal line and the pixel electrode, the storage capacitance of the display device can be increased, and the risk of poor picture quality can be reduced.
首先，參見第1A圖，該圖係本揭露一些實施例之顯示裝置100之陣列基板102的上視圖。如第1A圖所示，陣列基板102包括沿第一方向A1延伸之掃描線(閘極線)104，以及與此掃描線104交會之資料線106。易言之，此閘極線104係沿著方向A1延伸，而大抵垂直或正交(orthogonal)此掃描線(閘極線)延伸方向A1之方向係為方向A2。此外，陣列基板102更包括對應每一個次畫素108設置之電晶體110。 First, referring to FIG. 1A, there is shown a top view of an array substrate 102 of a display device 100 of some embodiments. As shown in FIG. 1A, the array substrate 102 includes scan lines (gate lines) 104 extending in the first direction A1, and data lines 106 intersecting the scan lines 104. In other words, the gate line 104 extends along the direction A1, and the direction perpendicular to or orthogonal to the direction of extension A1 of the scan line (gate line) is the direction A2. In addition, the array substrate 102 further includes a transistor 110 disposed corresponding to each of the sub-pixels 108.
上述顯示裝置100可為觸控液晶顯示器，例如為薄膜電晶體液晶顯示器。或者，此液晶顯示器可為扭轉向列(Twisted Nematic,TN)型液晶顯示器、超扭轉向列(Super Twisted Nematic,STN)型液晶顯示器、雙層超扭轉向列(Double layer Super Twisted Nematic,DSTN)型液晶顯示器、垂直配向(Vertical Alignment,VA)型液晶顯示器、水平電場效應(In-Plane Switching,IPS)型液晶顯示器、膽固醇(Cholesteric)型液晶顯示器、藍相(Blue Phase)型液晶顯示器、邊際電場效應(FFS)型液晶顯示器、或其它任何適合之液晶顯示器。 The display device 100 can be a touch liquid crystal display, such as a thin film transistor liquid crystal display. Alternatively, the liquid crystal display can be a Twisted Nematic (TN) type liquid crystal display, a Super Twisted Nematic (STN) type liquid crystal display, or a Double Layer Super Twisted Nematic (DSTN). Liquid crystal display, Vertical Alignment (VA) type liquid crystal display, In-Plane Switching (IPS) type liquid crystal display, Cholesteric type liquid crystal display, Blue Phase type liquid crystal display, margin An electric field effect (FFS) type liquid crystal display, or any other suitable liquid crystal display.
上述陣列基板102可包括電晶體基板。上述資料線106係透過電晶體110提供訊號至次畫素108，而此掃描線(閘極線)104係透過電晶體110提供掃描脈衝訊號至次畫素108，並配合上述訊號一同控制次畫素108。 The above array substrate 102 may include a transistor substrate. The data line 106 provides a signal to the sub-pixel 108 through the transistor 110. The scan line (gate line) 104 provides a scan pulse signal to the sub-pixel 108 through the transistor 110, and controls the sub-picture together with the signal. Prime 108.
上述電晶體110包括源極電極112、汲極電極114、設於源極電極112與汲極電極114之間的半導體層116、以及閘極電極 118。此閘極電極118可自掃描線104延第二方向A2延伸而出，而此源極電極112則可為資料線106之一部分。 The transistor 110 includes a source electrode 112, a drain electrode 114, a semiconductor layer 116 disposed between the source electrode 112 and the drain electrode 114, and a gate electrode 118. The gate electrode 118 can extend from the scan line 104 in the second direction A2, and the source electrode 112 can be a portion of the data line 106.
此外，陣列基板102更包括一導電層120。在一些實施例中，導電層為一觸控訊號線120，此觸控訊號線120大抵與上述資料線106重疊設置，且與顯示裝置100之共同電極(未繪示於第1A圖，可參見後續第1B-1D圖)電性連接。此外，陣列基板102更包括畫素電極122，此畫素電極122可電性連接電晶體110之汲極電極114。 In addition, the array substrate 102 further includes a conductive layer 120. In some embodiments, the conductive layer is a touch signal line 120. The touch signal line 120 is disposed substantially opposite to the data line 106 and is common to the display device 100 (not shown in FIG. 1A. Subsequent 1B-1D diagram) electrical connection. In addition, the array substrate 102 further includes a pixel electrode 122. The pixel electrode 122 can be electrically connected to the gate electrode 114 of the transistor 110.
需注意的是，為清楚描述本揭露實施例，上述第1A圖中並未繪示後續之共同電極。 It should be noted that in order to clearly describe the disclosed embodiment, the subsequent common electrode is not shown in FIG. 1A.
此外，如第1A圖所示，觸控訊號線120係與畫素電極122至少部分重疊。由於顯示裝置之觸控訊號線120係與共同電極電性連接，故此觸控訊號線120亦可視為共同電極之延伸。因此，本揭露實施例藉由將此觸控訊號線120與畫素電極122至少部分重疊，可提升顯示裝置100中畫素電極122與共同電極之間的儲存電容，故可降低畫面品質不良之風險。 In addition, as shown in FIG. 1A, the touch signal line 120 is at least partially overlapped with the pixel electrode 122. Since the touch signal line 120 of the display device is electrically connected to the common electrode, the touch signal line 120 can also be regarded as an extension of the common electrode. Therefore, in the embodiment of the present disclosure, by at least partially overlapping the touch signal line 120 and the pixel electrode 122, the storage capacitance between the pixel electrode 122 and the common electrode in the display device 100 can be improved, thereby reducing the image quality. risk.
第1B-1D圖係本揭露實施例之顯示裝置100之剖面圖，第1B圖係沿著如第1A圖之線段1B-1B’所繪製之剖面圖，第1C圖係沿著第1A圖之線段1C-1C’所繪製之剖面圖，第1D圖係沿著第1A圖之線段1D-1D’所繪製之剖面圖。如第1C圖所示，陣列基板102可包括一第一基板124，此第一基板124可包括透明基板，例如為玻璃基板、陶瓷基板、塑膠基板或其它任何適合之基板。電晶體110係設於第一基板124上。電晶體110例如可為薄膜電晶體，且可包括設於此第一基板124上之閘極電極118，以及設於閘極電極118 及第一基板124上之閘極介電層126。 1B-1D is a cross-sectional view of the display device 100 of the embodiment, and FIG. 1B is a cross-sectional view taken along line 1B-1B' of FIG. 1A, and FIG. 1C is along the first FIG. A cross-sectional view drawn by line segment 1C-1C', and a 1D image is a cross-sectional view taken along line 1D-1D' of Fig. 1A. As shown in FIG. 1C, the array substrate 102 can include a first substrate 124, which can include a transparent substrate, such as a glass substrate, a ceramic substrate, a plastic substrate, or any other suitable substrate. The transistor 110 is disposed on the first substrate 124. The transistor 110 can be, for example, a thin film transistor, and can include a gate electrode 118 disposed on the first substrate 124 and a gate electrode 118 And a gate dielectric layer 126 on the first substrate 124.
此閘極電極118可為非晶矽、複晶矽、一或多種金屬、金屬氮化物、導電金屬氧化物、或上述之組合。上述金屬可包括但不限於鉬(molybdenum)、鎢(tungsten)、鈦(titanium)、鉭(tantalum)、鉑(platinum)或鉿(hafnium)。上述金屬氮化物可包括但不限於氮化鉬(molybdenum nitride)、氮化鎢(tungsten nitride)、氮化鈦(titanium nitride)以及氮化鉭(tantalum nitride)。上述導電金屬氧化物可包括但不限於釕金屬氧化物(ruthenium oxide)以及銦錫金屬氧化物(indium tin oxide)。此閘極電極118可藉由前述之化學氣相沉積法(CVD)、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沈積方式形成，例如，在一實施例中，可用低壓化學氣相沈積法(LPCVD)在525~650℃之間沈積而製得非晶矽導電材料層或複晶矽導電材料層，其厚度範圍可為約1000Å至約10000Å。 The gate electrode 118 can be an amorphous germanium, a germanium germanium, one or more metals, a metal nitride, a conductive metal oxide, or a combination thereof. The above metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum or hafnium. The above metal nitrides may include, but are not limited to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride. The above conductive metal oxide may include, but is not limited to, ruthenium oxide and indium tin oxide. The gate electrode 118 can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method, for example, in an embodiment. The amorphous germanium conductive material layer or the polycrystalline germanium conductive material layer may be deposited by low pressure chemical vapor deposition (LPCVD) at a temperature between 525 and 650 ° C, and may have a thickness ranging from about 1000 Å to about 10000 Å.
此閘極介電層126可為氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)介電材料、或其它任何適合之介電材料、或上述之組合。此高介電常數(high-k)介電材料之材料可為金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬的氮氧化物、金屬鋁酸鹽、鋯矽酸鹽、鋯鋁酸鹽。例如，此高介電常數(high-k)介電材料可為LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfO2、HfO3、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO3(BST)、Al2O3、其它適當材料之其它高介電常數介電材料、或 上述組合。此閘極介電層126可藉由化學氣相沉積法(CVD)或旋轉塗佈法形成，此化學氣相沉積法例如可為低壓化學氣相沉積法(low pressure chemical vapor deposition，LPCVD)、低溫化學氣相沉積法(low temperature chemical vapor deposition，LTCVD)、快速升溫化學氣相沉積法(rapid thermal chemical vapor deposition，RTCVD)、電漿輔助化學氣相沉積法(plasma enhanced chemical vapor deposition，PECVD)、原子層化學氣相沉積法之原子層沉積法(atomic layer deposition，ALD)或其它常用的方法。 The gate dielectric layer 126 can be tantalum oxide, tantalum nitride, hafnium oxynitride, a high-k dielectric material, or any other suitable dielectric material, or a combination thereof. The material of the high-k dielectric material may be a metal oxide, a metal nitride, a metal halide, a transition metal oxide, a transition metal nitride, a transition metal telluride, a metal oxynitride, Metal aluminate, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfO. 2 , HfO 3 , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO 3 (BST), Al 2 O 3 , other high dielectric constants of other suitable materials Dielectric material, or a combination of the above. The gate dielectric layer 126 can be formed by chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD). Low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD) Atomic layer deposition (ALD) or other commonly used methods of atomic layer chemical vapor deposition.
電晶體110更包括設於閘極介電層126上之半導體層116，此半導體層116與閘極電極118重疊，且上述源極電極112與汲極電極114係分別設於半導體層116之兩側，且分別與半導體層116兩側部分重疊。 The transistor 110 further includes a semiconductor layer 116 disposed on the gate dielectric layer 126. The semiconductor layer 116 overlaps the gate electrode 118, and the source electrode 112 and the drain electrode 114 are respectively disposed on the semiconductor layer 116. The sides are partially overlapped with both sides of the semiconductor layer 116, respectively.
此半導體層116可包括元素半導體，包括矽、錯(germanium)；化合物半導體，包括氮化鎵(gallium nitride，GaN)、碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)；合金半導體，包括矽鍺合金(SiGe)、磷砷鎵合金(GaAsP)、砷鋁銦合金(AlInAs)、砷鋁鎵合金(AlGaAs)、砷銦鎵合金(GaInAs)、磷銦鎵合金(GaInP)及/或磷砷銦鎵合金(GaInAsP)或上述材料之組合。 The semiconductor layer 116 may include an elemental semiconductor including germanium, germanium; a compound semiconductor including gallium nitride (GaN), silicon carbide, gallium arsenide, gallium phosphide ( Gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors including bismuth alloy (SiGe), phosphorus gallium arsenide (GaAsP), arsenic Aluminum indium alloy (AlInAs), arsenic aluminum gallium alloy (AlGaAs), arsenic gallium alloy (GaInAs), indium gallium alloy (GaInP) and/or phosphorus indium gallium alloy (GaInAsP) or a combination thereof.
上述源極電極112與汲極電極114之材料可包括銅、鋁、鉬、鎢、金、鉻、鎳、鉑、鈦、銥、銠、上述之合金、上述 之組合或其它導電性佳的金屬材料，例如可為鉬鋁鉬(Mo/Al/Mo)或鈦鋁鈦(Ti/Al/Ti)之三層結構。於其它實施例中，上述源極電極112與汲極電極114之材料可為一非金屬材料，只要使用之材料具有導電性即可。此源極電極112與汲極電極114之材料可藉由前述之化學氣相沉積法(CVD)、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沉積方式形成。在一些實施例中，上述源極電極112與汲極電極114之材料可相同，且可藉由同一道沈積步驟形成。然而，在其它實施例中，上述源極電極112與汲極電極114亦可藉由不同之沈積步驟形成，且其材料可彼此不同。 The material of the source electrode 112 and the drain electrode 114 may include copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, tantalum, niobium, the above alloy, the above The combination or other highly conductive metal material may be, for example, a three-layer structure of molybdenum aluminum molybdenum (Mo/Al/Mo) or titanium aluminum titanium (Ti/Al/Ti). In other embodiments, the material of the source electrode 112 and the drain electrode 114 may be a non-metal material as long as the material used has conductivity. The material of the source electrode 112 and the drain electrode 114 can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method. . In some embodiments, the material of the source electrode 112 and the drain electrode 114 may be the same and may be formed by the same deposition step. However, in other embodiments, the source electrode 112 and the drain electrode 114 may be formed by different deposition steps, and the materials thereof may be different from each other.
繼續參見第1B圖，陣列基板102更包括覆蓋電晶體110與閘極介電層126且設於第一基板124上之第一絕緣層128。易言之，此第一絕緣層128設於電晶體110上。此第一絕緣層128可為氮化矽、二氧化矽、或氮氧化矽。第一絕緣層128可藉由化學氣相沉積法(CVD)或旋轉塗佈法形成，此化學氣相沉積法例如可為低壓化學氣相沉積法(low pressure chemical vapor deposition，LPCVD)、低溫化學氣相沉積法(low temperature chemical vapor deposition，LTCVD)、快速升溫化學氣相沉積法(rapid thermal chemical vapor deposition，RTCVD)、電漿輔助化學氣相沉積法(plasma enhanced chemical vapor deposition，PECVD)、原子層化學氣相沉積法之原子層沉積法(atomic layer deposition，ALD)或其它常用的方法。 Continuing to refer to FIG. 1B , the array substrate 102 further includes a first insulating layer 128 covering the transistor 110 and the gate dielectric layer 126 and disposed on the first substrate 124 . In other words, the first insulating layer 128 is disposed on the transistor 110. The first insulating layer 128 may be tantalum nitride, hafnium oxide, or hafnium oxynitride. The first insulating layer 128 can be formed by chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD), low temperature chemistry. Low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), atom Atomic layer deposition (ALD) or other commonly used methods of layer chemical vapor deposition.
接著，此第一絕緣層128上可選擇性設有平坦層130，此平坦層130亦可為絕緣層。此平坦層130之材質可為有機之絕緣材料(光感性樹脂)或無機之絕緣材料(氮化矽、氧化矽、 氮氧化矽、碳化矽、氧化鋁、或上述材質之組合)。此外，此平坦層130係設於第一絕緣層128與後續之第二絕緣層之間。在本揭露一些實施例中，可藉由兩次蝕刻步驟分別蝕刻上述平坦層130與第一絕緣層128，以形成平坦層130中的開口130A1與第一絕緣層128中的開口128A1。 Then, the first insulating layer 128 is selectively provided with a flat layer 130, and the flat layer 130 may also be an insulating layer. The material of the flat layer 130 may be an organic insulating material (photosensitive resin) or an inorganic insulating material (tantalum nitride, tantalum oxide, Niobium oxynitride, niobium carbide, alumina, or a combination of the above materials). In addition, the planarization layer 130 is disposed between the first insulating layer 128 and the subsequent second insulating layer. In some embodiments of the present disclosure, the planarization layer 130 and the first insulating layer 128 may be separately etched by two etching steps to form the opening 130A1 in the planarization layer 130 and the opening 128A1 in the first insulating layer 128.
參見第1B-1D圖，陣列基板102更包括設於平坦層130上(或第一絕緣層128上)之共同電極132。此共同電極132可包括透明導電材料，例如為銦錫氧化物(ITO)、氧化錫(SnO)、氧化銦鋅(IZO)、氧化銦鎵鋅(IGZO)、氧化銦錫鋅(ITZO)、氧化銻錫(ATO)、氧化銻鋅(AZO)、上述之組合或其它任何適合之透明導電氧化物材料。 Referring to FIGS. 1B-1D, the array substrate 102 further includes a common electrode 132 disposed on the planarization layer 130 (or on the first insulating layer 128). The common electrode 132 may include a transparent conductive material such as indium tin oxide (ITO), tin oxide (SnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), oxidation. Anthraquinone (ATO), bismuth oxide (AZO), combinations of the foregoing, or any other suitable transparent conductive oxide material.
繼續參見第1B-1D圖，顯示裝置100更包括設於平坦層130上(或第一絕緣層128上)且覆蓋共同電極132之第二絕緣層134。易言之，此第二絕緣層134設於共同電極132上。此第二絕緣層134可為氮化矽、二氧化矽、或氮氧化矽。而上述平坦層130係設於第一絕緣層128與第二絕緣層134之間。參見第1D圖，此第二絕緣層134具有開口134A1，此開口134A1由第二絕緣層134之上表面134S向下延伸至共同電極132。 Continuing to refer to FIGS. 1B-1D, the display device 100 further includes a second insulating layer 134 disposed on the planarization layer 130 (or on the first insulating layer 128) and covering the common electrode 132. In other words, the second insulating layer 134 is disposed on the common electrode 132. The second insulating layer 134 may be tantalum nitride, hafnium oxide, or hafnium oxynitride. The flat layer 130 is disposed between the first insulating layer 128 and the second insulating layer 134. Referring to FIG. 1D, the second insulating layer 134 has an opening 134A1 extending downward from the upper surface 134S of the second insulating layer 134 to the common electrode 132.
接著，導電層係設於第二絕緣層134上。在此實施例中，導電層可包括觸控訊號線120，此觸控訊號線120係透過上述開口134A1電性連接共同電極132。 Next, the conductive layer is disposed on the second insulating layer 134. In this embodiment, the conductive layer may include a touch signal line 120. The touch signal line 120 is electrically connected to the common electrode 132 through the opening 134A1.
上述觸控訊號線120之材料可包括銅、鋁、鉬、鎢、金、鉻、鎳、鉑、鈦、銥、銠、上述之合金、上述之組合或其它導電性佳的金屬材料，例如可為鉬鋁鉬(Mo/Al/Mo)或鈦鋁鈦 (Ti/Al/Ti)之三層結構。於其它實施例中，上述觸控訊號線120之材料可為一非金屬材料，只要使用之材料具有導電性即可。此觸控訊號線120之材料可藉由前述之化學氣相沉積法(CVD)、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沉積方式形成。 The material of the touch signal line 120 may include copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, tantalum, niobium, the above alloy, the above combination or other conductive metal materials, for example, Molybdenum aluminum molybdenum (Mo/Al/Mo) or titanium aluminum titanium Three-layer structure of (Ti/Al/Ti). In other embodiments, the material of the touch signal line 120 may be a non-metal material as long as the material used is electrically conductive. The material of the touch signal line 120 can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method.
此外，由於共同電極132電性連接觸控訊號線120，故此共同電極132不但是作為顯示裝置的共同電極，亦是作為觸控時的感測電極，其觸控的驅動方式可為自電容驅動方式(self-capacitive type)。 In addition, since the common electrode 132 is electrically connected to the touch signal line 120, the common electrode 132 is not only a common electrode of the display device, but also a sensing electrode for touch control, and the driving method of the touch can be self-capacitance driving. Self-capacitive type.
詳細而言，參見第2圖，該圖係本揭露一些實施例之顯示裝置100之陣列基板102之上視圖。如第2圖所示，共同電極132透過開口134A1電性連接觸控訊號線120，更透過觸控訊號線120電性連接至驅動元件136。此驅動元件136可單純為一觸控驅動元件136，亦可為整合顯示與觸控之驅動元件136。 In detail, referring to FIG. 2, there is shown a top view of the array substrate 102 of the display device 100 of some embodiments. As shown in FIG. 2 , the common electrode 132 is electrically connected to the touch signal line 120 through the opening 134A1 , and is electrically connected to the driving element 136 through the touch signal line 120 . The driving component 136 can be simply a touch driving component 136 or a driving component 136 that integrates display and touch.
繼續參見第1B-1D圖，顯示裝置100更包括設於第二絕緣層134上且覆蓋觸控訊號線120之第三絕緣層138。易言之，此第三絕緣層138設於觸控訊號線120上。此第三絕緣層138可為氮化矽、二氧化矽、或氮氧化矽。 Continuing to refer to FIG. 1B-1D , the display device 100 further includes a third insulating layer 138 disposed on the second insulating layer 134 and covering the touch signal line 120 . In other words, the third insulating layer 138 is disposed on the touch signal line 120. The third insulating layer 138 may be tantalum nitride, hafnium oxide, or hafnium oxynitride.
繼續參見第1B-1D圖，顯示裝置100更包括設於第三絕緣層138上且電性連接電晶體110之畫素電極122。此畫素電極122之材料可包括透明導電材料，例如為銦錫氧化物(ITO)、氧化錫(SnO)、氧化銦鋅(IZO)、氧化銦鎵鋅(IGZO)、氧化銦錫鋅(ITZO)、氧化銻錫(ATO)、氧化銻鋅(AZO)、上述之組合或其它任何適合之透明導電氧化物材料。 Continuing to refer to FIG. 1B-1D, the display device 100 further includes a pixel electrode 122 disposed on the third insulating layer 138 and electrically connected to the transistor 110. The material of the pixel electrode 122 may include a transparent conductive material such as indium tin oxide (ITO), tin oxide (SnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO). ), antimony tin oxide (ATO), antimony zinc oxide (AZO), combinations of the foregoing or any other suitable transparent conductive oxide material.
此外，如第1C圖所示，陣列基板102更包括位於第二絕緣層134中的開口134A2，與位於第三絕緣層138中的開口138A1。此畫素電極122係透過開口138A1、134A2與128A1電性連接電晶體110之汲極電極114。 In addition, as shown in FIG. 1C, the array substrate 102 further includes an opening 134A2 in the second insulating layer 134 and an opening 138A1 in the third insulating layer 138. The pixel electrode 122 is electrically connected to the drain electrode 114 of the transistor 110 through the openings 138A1, 134A2 and 128A1.
此外，如第1D圖所示，共同電極132與觸控訊號線120電性連接，而如第1A、1C-1D圖所示，畫素電極122與電晶體110電性連接，且與導電層120(例如，觸控訊號線120)至少部分重疊。 In addition, as shown in FIG. 1D, the common electrode 132 is electrically connected to the touch signal line 120, and as shown in FIGS. 1A and 1C-1D, the pixel electrode 122 is electrically connected to the transistor 110, and is electrically connected to the conductive layer. 120 (eg, touch signal lines 120) at least partially overlap.
此外，參見第1D圖，相較於畫素電極122與共同電極132之間有兩層絕緣層(亦即第二絕緣層134與第三絕緣層138)，畫素電極122與觸控訊號線120之間僅有一層絕緣層(亦即第三絕緣層138)，故畫素電極122與觸控訊號線120之間的距離小於畫素電極122與共同電極132之間的距離。由於較小的距離可產生較大的儲存電容，故相較於畫素電極122與共同電極132，相距較近的畫素電極122與觸控訊號線120可大幅提升裝置之儲存電容，故可降低畫面品質不良之風險。例如，在本揭露一些實施例中，將畫素電極122與觸控訊號線120(亦可稱作導電層120)至少部分重疊可使儲存電容由90fF大幅提升至143fF。 In addition, referring to FIG. 1D, there are two insulating layers (ie, the second insulating layer 134 and the third insulating layer 138) between the pixel electrode 122 and the common electrode 132, the pixel electrode 122 and the touch signal line. There is only one insulating layer between 120 (ie, the third insulating layer 138), so the distance between the pixel electrode 122 and the touch signal line 120 is smaller than the distance between the pixel electrode 122 and the common electrode 132. Since the smaller distance can generate a larger storage capacitance, the pixel electrodes 122 and the touch signal line 120 which are closer to each other than the pixel electrode 122 and the common electrode 132 can greatly increase the storage capacitance of the device. Reduce the risk of poor picture quality. For example, in some embodiments of the present disclosure, at least partially overlapping the pixel electrode 122 with the touch signal line 120 (also referred to as the conductive layer 120) can substantially increase the storage capacitance from 90 fF to 143 fF.
應注意的是，除上述第1A-1D圖所示之實施例以外，本揭露之畫素電極與共同電極亦可以其它配置方式，如第3A-3D圖之實施例所示。本揭露之範圍並不以第1A-1D圖所示之實施例為限。此部分將於後文詳細說明。 It should be noted that the pixel electrode and the common electrode of the present disclosure may be arranged in other configurations than the embodiment shown in the above FIGS. 1A-1D, as shown in the embodiment of FIGS. 3A-3D. The scope of the disclosure is not limited to the embodiments shown in Figures 1A-1D. This section will be explained in detail later.
應注意的是，後文中與前文相同或相似的元件或膜層將以相同或相似之標號表示，其材料、製造方法與功能皆與前文所述相同或相似，故此部分在後文中將不再贅述。 It should be noted that elements or layers that are the same or similar to those in the foregoing will be denoted by the same or similar reference numerals, and the materials, manufacturing methods and functions thereof are the same or similar to those described above, and therefore will not be described later. Narration.
第3A圖係本揭露一些實施例之顯示裝置300之陣列基板102之上視圖。第3B圖係沿著第3A圖之線段3B-3B’所繪製之剖面圖。第3C圖係沿著第3A圖之線段3C-3C’所繪製之剖面圖。第3D圖係沿著第3A圖之線段3D-3D’所繪製之剖面圖。如第3B-3D圖所示，顯示裝置300之畫素電極122係設於平坦層130上(或第一絕緣層128上)，此畫素電極122延伸入開口130A1與128A1中並電性連接電晶體110之汲極電極114。 FIG. 3A is a top plan view of the array substrate 102 of the display device 300 of some embodiments. Fig. 3B is a cross-sectional view taken along line 3B-3B' of Fig. 3A. Fig. 3C is a cross-sectional view taken along line 3C-3C' of Fig. 3A. The 3D image is a cross-sectional view taken along line 3D-3D' of Fig. 3A. As shown in FIG. 3B-3D, the pixel electrode 122 of the display device 300 is disposed on the flat layer 130 (or the first insulating layer 128). The pixel electrode 122 extends into the openings 130A1 and 128A1 and is electrically connected. The drain electrode 114 of the transistor 110.
繼續參見第3B-3D圖，顯示裝置300更包括設於平坦層130上(或第一絕緣層128上)且覆蓋畫素電極122之第二絕緣層134。而上述平坦層130係設於第一絕緣層128與第二絕緣層134之間。 Continuing to refer to FIGS. 3B-3D, display device 300 further includes a second insulating layer 134 disposed on planar layer 130 (or on first insulating layer 128) and covering pixel electrode 122. The flat layer 130 is disposed between the first insulating layer 128 and the second insulating layer 134.
繼續參見第3B-3D圖，觸控訊號線120(或導電層120)係設於此第二絕緣層134上。接著，顯示裝置300更包括設於第二絕緣層134上且覆蓋觸控訊號線120之第三絕緣層138。此第三絕緣層138具有露出觸控訊號線120之開口138A2，如第3D圖所示。 Continuing to refer to FIGS. 3B-3D, touch signal line 120 (or conductive layer 120) is disposed on second insulating layer 134. The display device 300 further includes a third insulating layer 138 disposed on the second insulating layer 134 and covering the touch signal line 120. The third insulating layer 138 has an opening 138A2 exposing the touch signal line 120, as shown in FIG. 3D.
顯示裝置300更包括設於第三絕緣層138上且電性連接觸控訊號線120之共同電極132。詳細而言，共同電極132係設於第三絕緣層138上，並透過上述開口138A2電性連接觸控訊號線120。此外，此共同電極132不但是作為顯示裝置的共同電極，亦是作為觸控時的感測電極。 The display device 300 further includes a common electrode 132 disposed on the third insulating layer 138 and electrically connected to the touch signal line 120. In detail, the common electrode 132 is disposed on the third insulating layer 138 and electrically connected to the touch signal line 120 through the opening 138A2. In addition, the common electrode 132 serves not only as a common electrode of the display device but also as a sensing electrode at the time of touch.
第3A-3D圖所示之實施例與前述第1A-1D圖之實施例之差別在於共同電極132係設於畫素電極122之上。此外，與前述第1A-1D圖之實施例相同之部分為，共同電極132與觸控訊號線120電性連接，而畫素電極122與電晶體110電性連接，且與觸控訊 號線120至少部分重疊，如第3A-3D圖所示。 The embodiment shown in FIGS. 3A-3D differs from the embodiment of the first 1A-1D in that the common electrode 132 is disposed above the pixel electrode 122. In addition, the same part as the embodiment of the first embodiment 1A-1D is that the common electrode 132 is electrically connected to the touch signal line 120, and the pixel electrode 122 is electrically connected to the transistor 110, and the touch signal is connected. The lines 120 overlap at least partially, as shown in Figures 3A-3D.
第4A圖係本揭露一些實施例之顯示裝置400之陣列基板102之上視圖。第4B圖係沿著第4A圖之線段4B-4B’所繪製之剖面圖。第4C圖係沿著第4A圖之線段4C-4C’所繪製之剖面圖。如第4A圖所示，在本揭露一些實施例中，觸控訊號線120可與電晶體110至少部分重疊。例如，觸控訊號線120可與電晶體110中的半導體層116至少部分重疊。 FIG. 4A is a top plan view of the array substrate 102 of the display device 400 of some embodiments. Fig. 4B is a cross-sectional view taken along line 4B-4B' of Fig. 4A. Fig. 4C is a cross-sectional view taken along line 4C-4C' of Fig. 4A. As shown in FIG. 4A, in some embodiments of the present disclosure, the touch signal line 120 may at least partially overlap the transistor 110. For example, the touch signal line 120 can at least partially overlap the semiconductor layer 116 in the transistor 110.
在傳統之顯示裝置中，係以相對第一基板設置之另一基板上的遮光層(例如後續第二基板140之遮光層146)遮蔽電晶體之半導體層。然而，為了確保此遮光層可遮蔽電晶體之半導體層，於決定此遮光層之面積時，必須考慮第一基板與此另一基板對組時的誤差，故導致此遮光層之面積較大。 In a conventional display device, a semiconductor layer of a transistor is shielded by a light shielding layer on another substrate disposed opposite to the first substrate (for example, a light shielding layer 146 of the subsequent second substrate 140). However, in order to ensure that the light shielding layer can shield the semiconductor layer of the transistor, when determining the area of the light shielding layer, it is necessary to consider the error when the first substrate is paired with the other substrate, so that the area of the light shielding layer is large.
相較之下，在本揭露一些實施例中，電晶體之半導體層係以觸控訊號線(亦即導電層)遮蔽，而非以另一基板上的遮光層遮蔽。由於決定此觸控訊號線之面積時，僅需考慮觸控訊號線之光罩與半導體層之光罩的對位誤差(小於第一基板與此另一基板對組時的誤差，例如可為第一基板與此另一基板對組時的誤差的0.5倍)，而不需考慮第一基板與此另一基板對組時的誤差，故此觸控訊號線(亦即導電層)之面積可較小。而由於另一基板上的遮光層不需遮蔽半導體層，故此遮光層之面積亦可較小，故可提升顯示裝置的開口率以及穿透率。 In contrast, in some embodiments of the present disclosure, the semiconductor layer of the transistor is shielded by a touch signal line (ie, a conductive layer) instead of being shielded by a light shielding layer on the other substrate. When determining the area of the touch signal line, it is only necessary to consider the alignment error of the photomask of the touch signal line and the photomask of the semiconductor layer (less than the error between the first substrate and the other substrate pair, for example, The error of the first substrate and the other substrate is 0.5 times), and the error of the touch signal line (ie, the conductive layer) can be determined without considering the error between the first substrate and the other substrate. Smaller. Since the light shielding layer on the other substrate does not need to shield the semiconductor layer, the area of the light shielding layer can be small, so that the aperture ratio and the transmittance of the display device can be improved.
在本揭露一些實施例中，觸控訊號線120(或導電層120)可覆蓋整個半導體層116。 In some embodiments of the present disclosure, the touch signal line 120 (or the conductive layer 120) may cover the entire semiconductor layer 116.
此外，如第4B圖所示，平坦層130具有開口130A2， 此開口130A2具有傾斜的側壁，且畫素電極122透過開口130A2與第一絕緣層128之開口128A2電性連接電晶體110。而如第4A-4B圖所示，在本揭露一些實施例中，導電層120(例如觸控訊號線120)可與平坦層130之第一開口130A2至少部分重疊。例如，觸控訊號線120可覆蓋平坦層130之第一開口130A2。 Further, as shown in FIG. 4B, the flat layer 130 has an opening 130A2, The opening 130A2 has a slanted sidewall, and the pixel electrode 122 is electrically connected to the transistor 110 through the opening 130A2 and the opening 128A2 of the first insulating layer 128. As shown in FIG. 4A-4B, in some embodiments of the present disclosure, the conductive layer 120 (eg, the touch signal line 120) may at least partially overlap the first opening 130A2 of the planar layer 130. For example, the touch signal line 120 may cover the first opening 130A2 of the flat layer 130.
上述平坦層130之開口130A2處會因膜層表面之不平整而導致漏光，故在傳統之顯示裝置中，係以相對第一基板設置之另一基板上的遮光層(例如後續第二基板140之遮光層146)遮蔽平坦層之開口處。然而，為了確保此遮光層可遮蔽平坦層之開口處，於決定此遮光層之面積時，必須考慮第一基板與此另一基板對組時的誤差，故導致此遮光層之面積較大。 The opening 130A2 of the flat layer 130 may cause light leakage due to unevenness of the surface of the film layer. Therefore, in the conventional display device, the light shielding layer on the other substrate disposed opposite to the first substrate (for example, the subsequent second substrate 140) The light shielding layer 146) shields the opening of the flat layer. However, in order to ensure that the light shielding layer can cover the opening of the flat layer, when determining the area of the light shielding layer, it is necessary to consider the error when the first substrate is paired with the other substrate, so that the area of the light shielding layer is large.
相較之下，在本揭露一些實施例中，平坦層之開口係以觸控訊號線(亦即導電層)遮蔽，而非以另一基板上的遮光層遮蔽。由於決定此觸控訊號線之面積時，僅需考慮觸控訊號線之光罩與平坦層之開口之光罩的對位誤差(小於第一基板與此另一基板對組時的誤差，例如可為第一基板與此另一基板對組時的誤差的0.5倍)，而不需考慮第一基板與此另一基板對組時的誤差，故此觸控訊號線(亦即導電層)之面積可較小。而由於另一基板上的遮光層不需遮蔽平坦層之開口，故此遮光層之面積亦可較小，故可提升顯示裝置的開口率以及穿透率。 In contrast, in some embodiments of the present disclosure, the opening of the flat layer is shielded by a touch signal line (ie, a conductive layer) instead of being shielded by a light shielding layer on the other substrate. When determining the area of the touch signal line, it is only necessary to consider the alignment error of the photomask of the touch signal line and the opening of the flat layer (less than the error between the first substrate and the other substrate pair, for example The error of the first substrate and the other substrate may be 0.5 times, regardless of the error when the first substrate and the other substrate are paired, so the touch signal line (ie, the conductive layer) The area can be smaller. Since the light shielding layer on the other substrate does not need to cover the opening of the flat layer, the area of the light shielding layer can be small, so that the aperture ratio and the transmittance of the display device can be improved.
在本揭露一些實施例中，觸控訊號線120(亦即導電層120)可覆蓋整個平坦層130之開口130A2。 In some embodiments of the present disclosure, the touch signal line 120 (ie, the conductive layer 120) may cover the opening 130A2 of the entire flat layer 130.
繼續參見第4A圖，半導體層116具有第一側116S1與第二側116S2，且第一側116S1與第二側116S2互為相反側。第一 側116S1與觸控訊號線120(亦即導電層120)之邊緣120E(例如邊緣120E1)之最短距離為第一距離D1，第二側116S2與觸控訊號線120(亦即導電層120)之邊緣120E(例如邊緣120E2)之最短距離為第二距離D2。 Continuing to refer to FIG. 4A, the semiconductor layer 116 has a first side 116S1 and a second side 116S2, and the first side 116S1 and the second side 116S2 are opposite sides of each other. the first The shortest distance between the side 116S1 and the edge 120E of the touch signal line 120 (ie, the conductive layer 120) (for example, the edge 120E1) is the first distance D1, and the second side 116S2 and the touch signal line 120 (ie, the conductive layer 120) The shortest distance of the edge 120E (e.g., edge 120E2) is the second distance D2.
此外，開口130A2具有第三側130S1與第四側130S2，且第三側130S1與第四側130S2互為相反側。第三側130S1與觸控訊號線120(亦即導電層120)之邊緣120E(例如邊緣120E3)之最短距離為第三距離D3，第四側130S2與觸控訊號線120(亦即導電層120)之邊緣120E(例如邊緣120E4)之最短距離為第四距離D4。此第三距離D3可大於第一距離D1與第二距離D2，第四距離D4可大於第一距離D1與第二距離D2。 Further, the opening 130A2 has a third side 130S1 and a fourth side 130S2, and the third side 130S1 and the fourth side 130S2 are opposite sides of each other. The shortest distance between the third side 130S1 and the edge 120E of the touch signal line 120 (ie, the conductive layer 120) (eg, the edge 120E3) is the third distance D3, and the fourth side 130S2 and the touch signal line 120 (ie, the conductive layer 120) The shortest distance of the edge 120E (eg, edge 120E4) is the fourth distance D4. The third distance D3 may be greater than the first distance D1 and the second distance D2, and the fourth distance D4 may be greater than the first distance D1 and the second distance D2.
此外，上述半導體層116之第一側116S1與第二側116S2為半導體層116沿閘極線延伸方向A1延伸之側邊。上述開口130A2之第三側130S1與第四側130S2為開口130A2沿閘極線延伸方向A1延伸之側邊。且上述最短距離係指沿A2方向上之最短距離。易言之，上述第一、第二、第三、第四距離為沿相同方向延伸的距離。 In addition, the first side 116S1 and the second side 116S2 of the semiconductor layer 116 are sides of the semiconductor layer 116 extending in the direction in which the gate line extends. The third side 130S1 and the fourth side 130S2 of the opening 130A2 are sides on which the opening 130A2 extends in the direction in which the gate line extends. And the shortest distance described above refers to the shortest distance in the A2 direction. In other words, the first, second, third, and fourth distances are distances extending in the same direction.
第4A圖係以第4B圖之開口130A2之底部邊緣為準繪製其開口130A2之側邊。依據一些實施例，事實上，開口130A2之側邊可為第4B圖所示之傾斜側邊，亦即，開口130A2係由底部往頂部而擴大。因此，開口130A2之頂部會略大於第4A圖所繪之側邊，故觸控訊號線120(亦即導電層120)需較大之面積以遮蔽開口130A2，亦即需較大之第三距離D3與第四距離D4。 Figure 4A depicts the side of the opening 130A2 with the bottom edge of the opening 130A2 of Figure 4B as the standard. According to some embodiments, in fact, the side of the opening 130A2 may be the inclined side shown in FIG. 4B, that is, the opening 130A2 is enlarged from the bottom to the top. Therefore, the top of the opening 130A2 is slightly larger than the side of the drawing shown in FIG. 4A. Therefore, the touch signal line 120 (ie, the conductive layer 120) needs a larger area to cover the opening 130A2, that is, a larger third distance is required. D3 and the fourth distance D4.
然而，由於第4A圖之半導體層116之側邊即為第4B 圖之半導體層116之側邊，通常並無上述傾斜側邊之問題，故觸控訊號線120(亦即導電層120)可不需較大之面積即可遮蔽半導體層116。因此，依據一些實施例，第三距離D3可大於第一距離D1與第二距離D2，且第四距離D4可大於第一距離D1與第二距離D2。 However, since the side of the semiconductor layer 116 of FIG. 4A is the 4B The side of the semiconductor layer 116 of the figure generally does not have the problem of the inclined side, so that the touch signal line 120 (ie, the conductive layer 120) can shield the semiconductor layer 116 without a large area. Therefore, according to some embodiments, the third distance D3 may be greater than the first distance D1 and the second distance D2, and the fourth distance D4 may be greater than the first distance D1 and the second distance D2.
依據一些實施例，第四距離D4可大於或等於第三距離D3。例如，在本揭露一些實施例中，如第4A圖所示，第四距離D4大於第三距離D3。然而，應注意的是，除上述第4A圖所示之實施例以外，本揭露之第四距離D4亦可等於第三距離D3。 According to some embodiments, the fourth distance D4 may be greater than or equal to the third distance D3. For example, in some embodiments of the present disclosure, as shown in FIG. 4A, the fourth distance D4 is greater than the third distance D3. However, it should be noted that the fourth distance D4 of the present disclosure may be equal to the third distance D3, in addition to the embodiment shown in FIG. 4A above.
此外，如第4C圖所示，共同電極132係透過開口138A3電性連接觸控訊號線120(亦即導電層120)，此開口138A3係位於第二絕緣層134及/或第三絕緣層138中。例如，在此實施例中，此開口138A3係位於第三絕緣層138中。此外，如第4B圖所示，畫素電極122電性連接電晶體110。 In addition, as shown in FIG. 4C, the common electrode 132 is electrically connected to the touch signal line 120 (ie, the conductive layer 120) through the opening 138A3. The opening 138A3 is located in the second insulating layer 134 and/or the third insulating layer 138. in. For example, in this embodiment, the opening 138A3 is located in the third insulating layer 138. Further, as shown in FIG. 4B, the pixel electrode 122 is electrically connected to the transistor 110.
此外，在本揭露一些實施例中，如第4A圖所示，第二開口138A3不與第一開口130A2重疊。 Moreover, in some embodiments of the present disclosure, as shown in FIG. 4A, the second opening 138A3 does not overlap the first opening 130A2.
繼續參見第4B-4C圖，顯示裝置300更包括相對陣列基板102設置之第二基板140以及設於陣列基板102與第二基板140之間的顯示介質142。 Continuing to refer to FIG. 4B-4C , the display device 300 further includes a second substrate 140 disposed opposite the array substrate 102 and a display medium 142 disposed between the array substrate 102 and the second substrate 140 .
在一些實施例中，第二基板140為彩色濾光層基板。詳細而言，作為彩色濾光層基板之第二基板140可包括一基板144、設於此基板144上之遮光層146、設於此遮光層146上之彩色濾光層148、以及覆蓋遮光層146與彩色濾光層148之保護層150。 In some embodiments, the second substrate 140 is a color filter layer substrate. In detail, the second substrate 140 as a color filter layer substrate may include a substrate 144, a light shielding layer 146 disposed on the substrate 144, a color filter layer 148 disposed on the light shielding layer 146, and a light shielding layer. 146 and protective layer 150 of color filter layer 148.
上述基板144可包括透明基板，例如可為玻璃基板、陶瓷基板、塑膠基板或其它任何適合之透明基板，上述遮光層146 可包括黑色光阻、黑色印刷油墨、黑色樹脂。而上述彩色濾光層148可包括紅色濾光層、綠色濾光層、藍色濾光層、或其它任何適合之彩色濾光層。 The substrate 144 may include a transparent substrate, such as a glass substrate, a ceramic substrate, a plastic substrate, or any other suitable transparent substrate, and the light shielding layer 146. It can include black photoresist, black printing ink, and black resin. The color filter layer 148 may include a red filter layer, a green filter layer, a blue filter layer, or any other suitable color filter layer.
在本揭露一些實施例中，顯示介質142可為液晶材料，此液晶材料可包括向列型液晶(nematic)、層列型液晶(smectic)、膽固醇液晶(cholesteric)、藍相液晶(Blue phase)或其它任何適合之液晶材料。 In some embodiments of the present disclosure, the display medium 142 may be a liquid crystal material, which may include nematic, smectic, cholesteric, blue phase. Or any other suitable liquid crystal material.
此外，在本揭露一些實施例中，參見第4A圖，遮光層146之邊緣可與觸控訊號線120(亦即導電層120)之邊緣對齊。例如，在本揭露一些實施例中，遮光層146之邊緣146E1可對齊導電層120之邊緣120E3，而遮光層146之邊緣146E2可對齊導電層120之邊緣120E4。 In addition, in some embodiments of the present disclosure, referring to FIG. 4A, the edge of the light shielding layer 146 may be aligned with the edge of the touch signal line 120 (ie, the conductive layer 120). For example, in some embodiments of the present disclosure, the edge 146E1 of the light shielding layer 146 may be aligned with the edge 120E3 of the conductive layer 120, and the edge 146E2 of the light shielding layer 146 may be aligned with the edge 120E4 of the conductive layer 120.
應注意的是，雖然第4A-4C圖所示之實施例之開口第二138A3不與第一開口130A2重疊，然而在其它實施例中，本揭露之開口138A3亦可與開口130A2重疊，如第5A-5B圖之實施例所示。本揭露之範圍並不以第4A-4C圖所示之實施例為限。此部分將於後文詳細說明。 It should be noted that although the opening second 138A3 of the embodiment shown in FIG. 4A-4C does not overlap with the first opening 130A2, in other embodiments, the opening 138A3 of the present disclosure may overlap with the opening 130A2, as in the first The embodiment of Figure 5A-5B is shown. The scope of the disclosure is not limited to the embodiments shown in Figures 4A-4C. This section will be explained in detail later.
第5A圖係本揭露一些實施例之顯示裝置500之陣列基板102之上視圖。第5B圖係沿著第5A圖之線段5B-5B’所繪製之剖面圖。第5A-5B圖所示之實施例與前述第4A-4C圖之實施例之差別在於第三絕緣層138之第二開口138A4與平坦層130之第一開口130A3至少部分重疊。共同電極132透過第二開口138A4電性連接觸控訊號線120，而畫素電極122透過第一開口130A3電性連接電晶體110。 FIG. 5A is a top plan view of the array substrate 102 of the display device 500 of some embodiments. Fig. 5B is a cross-sectional view taken along line 5B-5B' of Fig. 5A. The embodiment shown in FIGS. 5A-5B differs from the embodiment of the aforementioned 4A-4C in that the second opening 138A4 of the third insulating layer 138 at least partially overlaps the first opening 130A3 of the planar layer 130. The common electrode 132 is electrically connected to the touch signal line 120 through the second opening 138A4, and the pixel electrode 122 is electrically connected to the transistor 110 through the first opening 130A3.
應注意的是，除上述第4A-5B圖所示之實施例以外，本揭露之畫素電極與共同電極亦可以其它配置方式，如第6A-6C圖之實施例所示。本揭露之範圍並不以第4A-5B圖所示之實施例為限。此部分將於後文詳細說明。 It should be noted that the pixel electrode and the common electrode of the present disclosure may be arranged in other configurations than the embodiment shown in the above-mentioned 4A-5B, as shown in the embodiment of FIGS. 6A-6C. The scope of the disclosure is not limited to the embodiment shown in Figures 4A-5B. This section will be explained in detail later.
第6A圖係本揭露一些實施例之顯示裝置600之陣列基板102之上視圖。第6B圖係沿著第6A圖之線段6B-6B’所繪製之剖面圖。第6C圖係沿著第6A圖之線段6C-6C’所繪製之剖面圖。第6A-6C圖所示之實施例與前述第4A-5B圖之實施例之差別在於畫素電極122係設於共同電極132之上。且導電層120包括一第一部分120A與一第二部分120B。第一部分120A為觸控訊號線，第二部分120B為一導電遮蔽層。 FIG. 6A is a top plan view of the array substrate 102 of the display device 600 of some embodiments. Fig. 6B is a cross-sectional view taken along line 6B-6B' of Fig. 6A. Fig. 6C is a cross-sectional view taken along line 6C-6C' of Fig. 6A. The difference between the embodiment shown in FIGS. 6A-6C and the embodiment of the above-mentioned 4A-5B is that the pixel electrode 122 is disposed on the common electrode 132. The conductive layer 120 includes a first portion 120A and a second portion 120B. The first portion 120A is a touch signal line, and the second portion 120B is a conductive shielding layer.
詳細而言，參見第6A圖，導電層120之觸控訊號線120A與導電遮蔽層120B彼此電性絕緣，且觸控訊號線120A係覆蓋半導體層116，而導電遮蔽層120B覆蓋第一開口130A4。 In detail, referring to FIG. 6A, the touch signal line 120A of the conductive layer 120 and the conductive shielding layer 120B are electrically insulated from each other, and the touch signal line 120A covers the semiconductor layer 116, and the conductive shielding layer 120B covers the first opening 130A4. .
如第6B圖所示，導電層120之導電遮蔽層120B電性連接畫素電極122，且畫素電極122透過此導電遮蔽層120B及第一絕緣層128之開口128A3電性連接電晶體110。 As shown in FIG. 6B, the conductive shielding layer 120B of the conductive layer 120 is electrically connected to the pixel electrode 122, and the pixel electrode 122 is electrically connected to the transistor 110 through the conductive shielding layer 120B and the opening 128A3 of the first insulating layer 128.
而如第6C圖所示，導電層120之觸控訊號線120A透過第二絕緣層134之第二開口134A3電性連接共同電極132，且此第二開口134A3位於第二絕緣層134中。 As shown in FIG. 6C , the touch signal line 120A of the conductive layer 120 is electrically connected to the common electrode 132 through the second opening 134A3 of the second insulating layer 134 , and the second opening 134A3 is located in the second insulating layer 134 .
綜上所述，本揭露實施例藉由將觸控訊號線與畫素電極至少部分重疊，可提升顯示裝置之儲存電容，降低畫面品質不良之風險。此外，在本揭露一些實施例中，電晶體之半導體層及平坦層之開口係以觸控訊號線(亦即導電層)遮蔽，而非以另 一基板上的遮光層遮蔽，故可縮小遮光層之面積，並可提升顯示裝置的開口率以及穿透率。 In summary, the present disclosure can improve the storage capacitance of the display device and reduce the risk of poor picture quality by at least partially overlapping the touch signal line and the pixel electrode. In addition, in some embodiments of the disclosure, the openings of the semiconductor layer and the flat layer of the transistor are shielded by touch signal lines (ie, conductive layers) instead of another The light shielding layer on one substrate is shielded, so that the area of the light shielding layer can be reduced, and the aperture ratio and the transmittance of the display device can be improved.
此外，應注意的是，熟習本技術領域之人士均深知，本揭露所述之汲極與源極可互換，因其定義係與本身所連接的電壓位準有關。 In addition, it should be noted that those skilled in the art are well aware that the drains and sources described herein are interchangeable because their definition is related to the voltage level to which they are connected.
值得注意的是，以上所述之元件尺寸、元件參數、以及元件形狀皆非為本揭露之限制條件。此技術領域中具有通常知識者可以根據不同需要調整這些設定值。另外，本揭露之顯示裝置及其製造方法並不僅限於第1A-6C圖所圖示之狀態。本揭露可以僅包括第1A-6C圖之任何一或複數個實施例之任何一或複數項特徵。換言之，並非所有圖示之特徵均須同時實施於本揭露之顯示裝置及其製造方法中。 It should be noted that the component sizes, component parameters, and component shapes described above are not limitations of the disclosure. Those of ordinary skill in the art can adjust these settings according to different needs. Further, the display device and the method of manufacturing the same according to the present disclosure are not limited to the state illustrated in FIGS. 1A-6C. The disclosure may include only any one or more of the features of any one or a plurality of embodiments of Figures 1A-6C. In other words, not all illustrated features must be simultaneously implemented in the display device of the present disclosure and its method of manufacture.
雖然本揭露的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。此外，本揭露之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本揭露使用。因此，本揭露之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本揭露之保護範圍也包括各個申請專利範圍及實施例的組合。 Although the embodiments of the present disclosure and its advantages are disclosed above, it should be understood that those skilled in the art can make changes, substitutions, and refinements without departing from the spirit and scope of the disclosure. In addition, the scope of the disclosure is not limited to the processes, machines, manufactures, compositions, devices, methods, and steps in the specific embodiments described in the specification, and those of ordinary skill in the art may disclose the disclosure It is understood that the processes, machines, manufactures, compositions, devices, methods, and procedures that are presently or in the future may be used in accordance with the present disclosure as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of protection of the present disclosure includes the above-described processes, machines, manufacturing, material compositions, devices, methods, and procedures. In addition, each patent application scope constitutes an individual embodiment, and the scope of protection of the disclosure also includes a combination of the scope of the patent application and the embodiments.
100‧‧‧顯示裝置 100‧‧‧ display device
102‧‧‧陣列基板 102‧‧‧Array substrate
104‧‧‧閘極線 104‧‧‧ gate line
106‧‧‧資料線 106‧‧‧Information line
108‧‧‧次畫素 108‧‧‧ pixels
110‧‧‧電晶體 110‧‧‧Optoelectronics
112‧‧‧源極電極 112‧‧‧Source electrode
114‧‧‧汲極電極 114‧‧‧汲electrode
116‧‧‧半導體層 116‧‧‧Semiconductor layer
118‧‧‧閘極電極 118‧‧‧gate electrode
120‧‧‧導電層 120‧‧‧ Conductive layer
122‧‧‧畫素電極 122‧‧‧pixel electrodes
128A1‧‧‧開口 128A1‧‧‧ openings
130A1‧‧‧開口 130A1‧‧‧ openings
134A1‧‧‧開口 134A1‧‧‧ openings
1B-1B’‧‧‧線段 1B-1B’‧‧‧ segment
1C-1C’‧‧‧線段 1C-1C’‧‧‧ segment
1D-1D’‧‧‧線段 1D-1D’‧‧‧ segments
A1‧‧‧方向 A1‧‧ Direction
A2‧‧‧方向 A2‧‧‧ direction
Claims (14)
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