TWI594443B - Shottcky diode structure and method for forming the same - Google Patents
Shottcky diode structure and method for forming the same Download PDFInfo
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本發明是關於一種蕭特基二極體結構及蕭特基二極體結構之形成方法。The present invention relates to a Schottky diode structure and a method of forming a Schottky diode structure.
蕭特基二極體（Schottky Diode）是利用金屬與半導體基板接觸而形成蕭基接觸（Schottky Contact），由於金屬中沒有少數載子，故蕭特基二極體的特性是其電流係由多數載子（即電子）移動所產生。多數載流子由半導體穿過接面而注入金屬的傳導帶，由於此過程不涉及多數載子與少數載子的結合（隨機反應而且需要時間較長），因此蕭特基二極體停止導通的速度會比P-N接面二極體速度要快，再加上蕭特基二極體的導通電壓降較低，這些特性使得蕭特基二極體可快速地切換於導通與不導通之間而不會造成過長的時間延遲，因而被廣泛地應用於電子裝置中。Schottky Diode is a Schottky Contact that uses a metal to contact a semiconductor substrate. Since there are no minority carriers in the metal, the characteristics of the Schottky diode are the majority of its current system. Produced by the movement of carriers (ie electrons). Most carriers are injected into the conduction band of the metal by the semiconductor passing through the junction. Since the process does not involve the combination of the majority carrier and the minority carrier (random reaction and takes a long time), the Schottky diode stops conducting. The speed will be faster than the PN junction diode, and the low turn-on voltage drop of the Schottky diode. These characteristics allow the Schottky diode to quickly switch between conduction and non-conduction. It does not cause excessive time delays and is therefore widely used in electronic devices.
若欲進一步提升蕭特基二極體的性能，由於蕭特基二極體的切換速度與其蕭基接觸的能障（barrier）有關，習知的蕭特基二極體係藉由提高半導體基板之摻雜濃度來降低蕭基接觸的能障，以提升其切換速度。然而，現今之半導體材料摻雜技術所能達成的摻雜濃度已難以再進一步提升，因此，如何降低蕭基接觸之能障高度係為當前所需面臨的重要課題。In order to further enhance the performance of the Schottky diode, the Schottky diode system is improved by the semiconductor substrate because the switching speed of the Schottky diode is related to the barrier of the Xiaoji contact. The doping concentration reduces the energy barrier of the Xiaoji contact to increase its switching speed. However, the doping concentration that can be achieved by the current semiconductor material doping technology is difficult to further increase. Therefore, how to reduce the barrier height of the Xiaoji contact is an important issue that is currently required.
有鑑於此，本發明提出一種蕭特基二極體結構及蕭特基二極體結構之形成方法。In view of this, the present invention proposes a Schottky diode structure and a method of forming a Schottky diode structure.
在一實施例中，蕭特基二極體結構包含半導體基板、磊晶層、第一金屬矽化物層、第二金屬矽化物層、第一金屬層及第二金屬層。半導體基板與磊晶層具有相同之導電型。半導體基板包含一上表面及一下表面，磊晶層覆蓋上表面且形成有複數凸部與複數凹部，各凸部之頂面與上表面之間具有一第一垂直距離，各凹部之底面與上表面之間具有一第二垂直距離，第一垂直距離係在0.1 μm至50 μm之範圍間，第二垂直距離係在0.099 μm至49.99 μm之範圍間。第一金屬矽化物層及第二金屬矽化物層分別形成於磊晶層及半導體基板之下表面。第一金屬層及第二金屬層分別接觸第一金屬矽化物層及第二金屬矽化物層。In one embodiment, the Schottky diode structure includes a semiconductor substrate, an epitaxial layer, a first metal germanide layer, a second metal germanide layer, a first metal layer, and a second metal layer. The semiconductor substrate and the epitaxial layer have the same conductivity type. The semiconductor substrate comprises an upper surface and a lower surface. The epitaxial layer covers the upper surface and is formed with a plurality of convex portions and a plurality of concave portions. The top surface and the upper surface of each convex portion have a first vertical distance, and the bottom surface and the upper portion of each concave portion There is a second vertical distance between the surfaces, the first vertical distance being in the range of 0.1 μm to 50 μm and the second vertical distance being in the range of 0.099 μm to 49.99 μm. The first metal telluride layer and the second metal telluride layer are respectively formed on the epitaxial layer and the lower surface of the semiconductor substrate. The first metal layer and the second metal layer respectively contact the first metal telluride layer and the second metal germanide layer.
在一實施例中，前述之半導體基板之下表面亦形成有複數凸部與複數凹部。In one embodiment, the lower surface of the semiconductor substrate is also formed with a plurality of convex portions and a plurality of concave portions.
在一實施例中，前述之形成於下表面之凸部之頂面與上表面之間具有一第三垂直距離，形成於下表面之複數凹部與上表面之間具有一第四垂直距離，第四垂直距離與第三垂直距離的比值係在0.99至0.99999之範圍間。In an embodiment, the top surface of the convex portion formed on the lower surface has a third vertical distance between the top surface and the upper surface, and the plurality of concave portions formed on the lower surface and the upper surface have a fourth vertical distance. The ratio of the four vertical distances to the third vertical distance is in the range of 0.99 to 0.99999.
在一實施例中，前述之半導體基板之材質包含矽、氮化鎵或碳化矽。In one embodiment, the material of the semiconductor substrate comprises germanium, gallium nitride or tantalum carbide.
在一實施例中，前述之第二垂直距離與第一垂直距離的比值係在0.99至0.9998之範圍間。In one embodiment, the ratio of the aforementioned second vertical distance to the first vertical distance is between 0.99 and 0.9998.
在一實施例中，前述之第三垂直距離係在1 μm至1000 μm之範圍間，第四垂直距離係在0.99 μm至999.99 μm之範圍間。In one embodiment, the aforementioned third vertical distance is in the range of 1 μm to 1000 μm, and the fourth vertical distance is in the range of 0.99 μm to 999.99 μm.
在一實施例中，位於前述磊晶層之相鄰之兩凸部之間距、位於磊晶層之相鄰之兩凹部之間距、位於前述半導體基板之下表面之相鄰之兩凸部之間距以及位於下表面之相鄰之兩凹部之間距係在0.01 μm至20 μm之範圍間。In one embodiment, the distance between two adjacent convex portions of the epitaxial layer, the distance between two adjacent concave portions located in the epitaxial layer, and the distance between two adjacent convex portions on the lower surface of the semiconductor substrate And the distance between two adjacent recesses on the lower surface is in the range of 0.01 μm to 20 μm.
在一實施例中，蕭特基二極體結構的形成方法包含形成一磊晶層於一半導體基板之一上表面；蝕刻磊晶層以形成複數凸部及複數凹部，各凸部之頂面與上表面之間具有一第一垂直距離，各凹部與上表面之間具有一第二垂直距離，第一垂直距離係在0.1 μm至50 μm之範圍間，第二垂直距離係在0.099 μm至49.99 μm之範圍間；形成一第一金屬矽化物層於磊晶層；形成第一金屬層接觸第一金屬矽化物層；形成一第二金屬矽化物層於半導體基板之下表面；及形成一第二金屬層接觸第二金屬矽化物層。In one embodiment, the method for forming a Schottky diode structure includes forming an epitaxial layer on an upper surface of a semiconductor substrate; etching the epitaxial layer to form a plurality of protrusions and a plurality of recesses, and top surfaces of the protrusions Having a first vertical distance from the upper surface, each recess having a second vertical distance from the upper surface, the first vertical distance being between 0.1 μm and 50 μm, and the second vertical distance being between 0.099 μm and Between the range of 49.99 μm; forming a first metal telluride layer on the epitaxial layer; forming a first metal layer contacting the first metal telluride layer; forming a second metal germanide layer on the lower surface of the semiconductor substrate; and forming a The second metal layer contacts the second metal telluride layer.
在一實施例中，於形成第二金屬層於半導體基板之下表面之前，蝕刻半導體基板之下表面以在下表面形成複數凸部及複數凹部。In one embodiment, before forming the second metal layer on the lower surface of the semiconductor substrate, the lower surface of the semiconductor substrate is etched to form a plurality of protrusions and a plurality of recesses on the lower surface.
在一實施例中，前述之形成於下表面之凸部之頂面與上表面之間具有一第三垂直距離，形成於下表面之複數凹部與上表面之間具有一第四垂直距離，於蝕刻半導體基板之下表面之步驟中，進行濕蝕刻製程及乾蝕刻製程使第三垂直距離係在1 μm至1000 μm之範圍間，且使該第四垂直距離係在0.99 μm至999.99 μm之範圍間。In one embodiment, the top surface formed on the lower surface has a third vertical distance between the top surface and the upper surface, and the plurality of recesses formed on the lower surface have a fourth vertical distance from the upper surface. In the step of etching the lower surface of the semiconductor substrate, the wet etching process and the dry etching process are performed so that the third vertical distance is in the range of 1 μm to 1000 μm, and the fourth vertical distance is in the range of 0.99 μm to 999.99 μm. between.
綜上所述，根據本發明之蕭特基二極體結構之一實施例，磊晶層具有凸部及凹部使得蕭基接觸係為非平坦而提升金屬矽化物層與金屬層之間的接觸面積，如此一來便降低蕭基接觸之接觸電阻進而提升蕭特基二極體之性能。再者，藉由蝕刻製程而非藉由光罩來形成凹部及凸部可降低製程之生產成本。In summary, according to an embodiment of the Schottky diode structure of the present invention, the epitaxial layer has convex portions and concave portions such that the Schottky contact system is non-flat and enhances contact between the metal telluride layer and the metal layer. The area, in this way, reduces the contact resistance of the Shoji contact and thus the performance of the Schottky diode. Moreover, the manufacturing cost of the process can be reduced by forming the recesses and protrusions by the etching process instead of by the reticle.
圖1為根據本發明之蕭特基二極體結構之一實施例之剖面示意圖。請參照圖1，蕭特基二極體包含半導體基板11、磊晶層12、兩金屬矽化物層（為方便描述，分別稱之為第一金屬矽化物層15及第二金屬矽化物層16）及兩金屬層（為方便描述，分別稱之為第一金屬層13及第二金屬層14）。其中，第一金屬矽化物層15及第二金屬矽化物層16分別形成於磊晶層12及半導體基板11。第一金屬層13覆蓋磊晶層12，磊晶層12覆蓋半導體基板11，半導體基板11覆蓋第二金屬層14。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view showing an embodiment of a Schottky diode structure in accordance with the present invention. Referring to FIG. 1 , the Schottky diode includes a semiconductor substrate 11 , an epitaxial layer 12 , and two metal telluride layers (referred to as a first metal telluride layer 15 and a second metal germanide layer 16 respectively for convenience of description). And two metal layers (referred to as first metal layer 13 and second metal layer 14 for convenience of description). The first metal telluride layer 15 and the second metal germanide layer 16 are formed on the epitaxial layer 12 and the semiconductor substrate 11, respectively. The first metal layer 13 covers the epitaxial layer 12, the epitaxial layer 12 covers the semiconductor substrate 11, and the semiconductor substrate 11 covers the second metal layer 14.
半導體基板11包含上表面111及下表面112，磊晶層12覆蓋半導體基板11之上表面111。第一金屬矽化物層15位於磊晶層12之表面，第一金屬層13覆蓋磊晶層12而接觸第一金屬矽化物層15，以形成蕭基接觸（schottky contact）。如圖1所示，第一金屬矽化物層15與第一金屬層13之間的蕭基接觸係為非平坦的，詳言之，磊晶層12形成有複數凸部121與複數凹部122，第一金屬矽化物層15則具有相應之凹凸狀，各凸部121之頂面1211接觸第一金屬層13，各凸部121之側面1212亦接觸第一金屬層13，各凹部122接觸第一金屬層13。相較於平坦之蕭基接觸，磊晶層12中的第一金屬矽化物層15於半導體基板11之水平方向及垂直方向接觸第一金屬層13而增加第一金屬矽化物層15與第一金屬層13之間的蕭基接觸之面積，進而提升蕭基二極體之性能。The semiconductor substrate 11 includes an upper surface 111 and a lower surface 112, and the epitaxial layer 12 covers the upper surface 111 of the semiconductor substrate 11. The first metal telluride layer 15 is on the surface of the epitaxial layer 12, and the first metal layer 13 covers the epitaxial layer 12 to contact the first metal telluride layer 15 to form a Schottky contact. As shown in FIG. 1 , the Schottky contact between the first metal telluride layer 15 and the first metal layer 13 is non-flat. In detail, the epitaxial layer 12 is formed with a plurality of convex portions 121 and a plurality of concave portions 122. The first metal telluride layer 15 has a corresponding concavo-convex shape, and the top surface 1211 of each convex portion 121 contacts the first metal layer 13. The side surface 1212 of each convex portion 121 also contacts the first metal layer 13, and each concave portion 122 contacts the first portion. Metal layer 13. The first metal telluride layer 15 in the epitaxial layer 12 contacts the first metal layer 13 in the horizontal direction and the vertical direction of the semiconductor substrate 11 to increase the first metal germanide layer 15 and the first layer, compared to the flat Schottky contact. The area of the base contact between the metal layers 13 further enhances the performance of the Schottky diode.
如圖1所示，各凸部121的頂面1211與半導體基板11之上表面111之間具有第一垂直距離d1，各凹部122之底面1221與半導體基板11之上表面111之間具有一第二垂直距離d2。於此，第一垂直距離d1與第二垂直距離d2之差值（即， ）係表示各凹部122的深度，若此深度愈深，表示各側面1212的表面積愈大而增加第一金屬矽化物層15與第一金屬層13之間的接觸面積。然而，過深之凹部122致使第二垂直距離d2變得過小，如此可能導致蕭特基二極體的其他不良效應。基此，第一垂直距離d1係在0.1 μm至50 μm之範圍間，而第二垂直距離d2係在0.099 μm至49.99 μm之範圍間，即第二垂直距離d2與第一垂直距離d1的比值較佳地係在0.99至0.9998之範圍間（即， ），也就是說，各凹部122的深度係在0.001 μm至0.01 μm之範圍間，即第一垂直距離d1的0.02%至1%之範圍間（即， ）。在前述之實施態樣中，當第一垂直距離d1為0.1 μm時，蕭特基二極體之崩潰電壓可達20 V；當第一垂直距離d1為50 μm時，蕭特基二極體之崩潰電壓可達10 kV。基此，蕭特基二極體可具有符合產品需求之崩潰電壓並同時具有較佳之性能。 As shown in FIG. 1 , the top surface 1211 of each convex portion 121 has a first vertical distance d1 from the upper surface 111 of the semiconductor substrate 11 , and the bottom surface 1221 of each concave portion 122 and the upper surface 111 of the semiconductor substrate 11 have a first Two vertical distances d2. Here, the difference between the first vertical distance d1 and the second vertical distance d2 (ie, The depth of each recess 122 is indicated. If the depth is deeper, the larger the surface area of each side surface 1212 is, the larger the contact area between the first metal telluride layer 15 and the first metal layer 13 is. However, the too deep recess 122 causes the second vertical distance d2 to become too small, which may result in other undesirable effects of the Schottky diode. Accordingly, the first vertical distance d1 is in the range of 0.1 μm to 50 μm, and the second vertical distance d2 is in the range of 0.099 μm to 49.99 μm, that is, the ratio of the second vertical distance d2 to the first vertical distance d1. Preferably between 0.99 and 0.9998 (ie, That is, the depth of each recess 122 is in the range of 0.001 μm to 0.01 μm, that is, between 0.02% and 1% of the first vertical distance d1 (ie, ). In the foregoing embodiment, when the first vertical distance d1 is 0.1 μm, the breakdown voltage of the Schottky diode can reach 20 V; when the first vertical distance d1 is 50 μm, the Schottky diode The breakdown voltage can reach 10 kV. Based on this, the Schottky diode can have a breakdown voltage that meets the needs of the product and at the same time has better performance.
如圖1所示，第二金屬矽化物層16係位於半導體基板11之下表面112，第二金屬層14接觸第二金屬矽化物層16而形成歐姆接觸。在一些實施態樣中，第二金屬矽化物層16與第二金屬層14之間的歐姆接觸亦為非平坦的。詳言之，半導體基板11之下表面112亦形成有複數凸部113與複數凹部114，使第二金屬矽化物層16具有相應之凹凸狀，各凸部113之頂面1131接觸第二金屬層14，各凹部114之底面1141接觸第二金屬層14，且各凸部113之側面1132亦接觸第二金屬層14，也就是說，第二金屬矽化物層16於其水平方向及垂直方向之兩維度方向接觸第二金屬層14使第二金屬矽化物層16與第二金屬層14之間的接觸面積增加，進而降低第二金屬矽化物層16與第二金屬層14之間的接觸電阻而提升蕭特基二極體之性能。As shown in FIG. 1, the second metal telluride layer 16 is located on the lower surface 112 of the semiconductor substrate 11, and the second metal layer 14 contacts the second metal telluride layer 16 to form an ohmic contact. In some implementations, the ohmic contact between the second metal telluride layer 16 and the second metal layer 14 is also non-planar. In detail, the lower surface 112 of the semiconductor substrate 11 is also formed with a plurality of convex portions 113 and a plurality of concave portions 114, so that the second metal telluride layer 16 has corresponding concave and convex shapes, and the top surface 1131 of each convex portion 113 contacts the second metal layer. 14. The bottom surface 1141 of each recess 114 contacts the second metal layer 14, and the side surface 1132 of each convex portion 113 also contacts the second metal layer 14, that is, the second metal telluride layer 16 is horizontally and vertically. Contacting the second metal layer 14 in the two-dimensional direction increases the contact area between the second metal telluride layer 16 and the second metal layer 14, thereby reducing the contact resistance between the second metal telluride layer 16 and the second metal layer 14. And improve the performance of the Schottky diode.
再者，如圖1所示，各凸部113的頂面1131與半導體基板11之上表面111之間具有第三垂直距離d3，各凹部114之底面1141與半導體基板11之上表面111之間具有一第四垂直距離d4。於此，第三垂直距離d3與第四垂直距離d4之差值（即， ）係表示各凹部114的深度，若此深度愈深，表示各側面1132的表面積愈大而增加第二金屬矽化物層16與第二金屬層14之間的接觸面積。而第四垂直距離d4與第三垂直距離d3的比值較佳地係在0.99至0.99999之範圍間（即， ），也就是說，各凹部114的深度係在第三垂直距離d3的0.001%至1%之範圍間（即， ）。在一些實施例中，第三垂直距離d3係可在1 μm至1000 μm之範圍間，而第二垂直距離d2係可在0.99 μm至999.99 μm之範圍間。於此，各凹部114的深度係為0.01μm。 Moreover, as shown in FIG. 1, the top surface 1131 of each convex portion 113 and the upper surface 111 of the semiconductor substrate 11 have a third vertical distance d3, and between the bottom surface 1141 of each concave portion 114 and the upper surface 111 of the semiconductor substrate 11. There is a fourth vertical distance d4. Here, the difference between the third vertical distance d3 and the fourth vertical distance d4 (ie, The depth of each recess 114 is indicated. If the depth is deeper, the larger the surface area of each side surface 1132 is, the larger the contact area between the second metal telluride layer 16 and the second metal layer 14 is. And the ratio of the fourth vertical distance d4 to the third vertical distance d3 is preferably between 0.99 and 0.99999 (ie, ), that is, the depth of each recess 114 is between 0.001% and 1% of the third vertical distance d3 (ie, ). In some embodiments, the third vertical distance d3 may be in the range of 1 μm to 1000 μm, and the second vertical distance d2 may be in the range of 0.99 μm to 999.99 μm. Here, the depth of each concave portion 114 is 0.01 μm.
在一些實施態樣中，相鄰之兩凹部122之間的間距、相鄰之兩凹部114之間的間距、相鄰之兩凸部121之間的間距以及相鄰之兩凸部113之間的間距係位於0.01 μm至20 μm之範圍間。In some embodiments, the spacing between the adjacent two recesses 122, the spacing between the adjacent two recesses 114, the spacing between the adjacent two convex portions 121, and between the adjacent two convex portions 113 The spacing is between 0.01 μm and 20 μm.
在本實施例中，磊晶層12為同質磊晶（homoepitaxial），也就是說，磊晶層12與半導體基板11具有相同的導電型，舉例來說，以半導體基板11包含矽且導電型為N型為例，半導體基板11之材質可包含具重摻雜之N型矽，而磊晶層12之材質可包含具輕摻雜之N型矽。在另一些實施態樣中，半導體基板11及磊晶層12之材質亦可包含氮化鎵（GaN）或碳化矽（SiC）。第一金屬層13及第二金屬層14之材質可以選自Ti、Ni、Ag、Al等任何可導電之金屬以及前述項目之組合。兩金屬矽化物層15、16之材質可包含鈦（Titanium）、鎳（nickel）及鉑（Platinum）。In the present embodiment, the epitaxial layer 12 is homoepitaxial, that is, the epitaxial layer 12 has the same conductivity type as the semiconductor substrate 11, for example, the semiconductor substrate 11 includes germanium and the conductive type is For example, the N-type material may include a heavily doped N-type germanium, and the epitaxial layer 12 may comprise a lightly doped N-type germanium. In other embodiments, the material of the semiconductor substrate 11 and the epitaxial layer 12 may also include gallium nitride (GaN) or tantalum carbide (SiC). The material of the first metal layer 13 and the second metal layer 14 may be selected from any electrically conductive metal such as Ti, Ni, Ag, Al, and the like. The material of the two metal telluride layers 15, 16 may comprise titanium (Titanium), nickel (nickel) and platinum (Platinum).
在本實施例中，如圖1所示，凸部113、121及凹部114、122為圓柱體使蕭基接觸及歐姆接觸均呈波浪狀，但本發明不以此為限，在另一些實施態樣中，請參照圖2至圖4，如圖2所示，凸部113、121及凹部114、122之形狀亦可為方柱體。如圖3及圖4所示，凸部113、121及凹部114、122之形狀亦可為錐體。In this embodiment, as shown in FIG. 1 , the convex portions 113 and 121 and the concave portions 114 and 122 are cylindrical, so that both the Schottky contact and the ohmic contact are wave-shaped, but the invention is not limited thereto, and is implemented in other embodiments. In the aspect, please refer to FIG. 2 to FIG. 4 . As shown in FIG. 2 , the shapes of the convex portions 113 and 121 and the concave portions 114 and 122 may also be a square cylinder. As shown in FIGS. 3 and 4, the convex portions 113 and 121 and the concave portions 114 and 122 may have a shape of a cone.
圖5至圖12為圖1之蕭特基二極體之形成方法之一實施例之分解步驟圖。首先，如圖5及圖6所示，於半導體基板11之上表面111形成磊晶層12，磊晶層12及半導體基板11之厚度分別為第一垂直距離d1及第三垂直距離d3。接著，如圖7所示，對磊晶層12進行蝕刻（etching）製程，以在磊晶層12之表面形成複數凸部121及凹部122而形成一非平坦之表面。並且，控制蝕刻製程進行的時間，使得第一垂直距離d1係在0.1 μm至50 μm之範圍間，而第二垂直距離d2係在0.099 μm至49.99 μm之範圍間。在一些實施態樣中，於蝕刻磊晶層12之步驟中，以等向性蝕刻（isotropic etching）之濕蝕刻（wet etching）製程來形成複數凸部121及凹部122，倘若各凹部122的深度未達第一垂直距離d1的0.02%至1%之範圍間，例如，各凹部122的深度僅為第一垂直距離d1的0.005%，此時可進一步對各凹部122進行乾蝕刻（dry etching），以增加凹部122之深度。5 to 12 are exploded views of an embodiment of the method for forming a Schottky diode of FIG. 1. First, as shown in FIGS. 5 and 6, an epitaxial layer 12 is formed on the upper surface 111 of the semiconductor substrate 11, and the thicknesses of the epitaxial layer 12 and the semiconductor substrate 11 are a first vertical distance d1 and a third vertical distance d3, respectively. Next, as shown in FIG. 7, the epitaxial layer 12 is subjected to an etching process to form a plurality of convex portions 121 and concave portions 122 on the surface of the epitaxial layer 12 to form an uneven surface. Also, the etching process is controlled such that the first vertical distance d1 is in the range of 0.1 μm to 50 μm, and the second vertical distance d2 is in the range of 0.099 μm to 49.99 μm. In some embodiments, in the step of etching the epitaxial layer 12, the plurality of convex portions 121 and the recesses 122 are formed by an isotropic etching wet etching process, provided that the depth of each of the concave portions 122 is deep. Between 0.02% and 1% of the first vertical distance d1, for example, the depth of each recess 122 is only 0.005% of the first vertical distance d1. At this time, each recess 122 may be further dry-etched. To increase the depth of the recess 122.
接著，以擴散（Diffusion）方法或以離子佈植（ion implantation）的方式在磊晶層12之表面摻雜金屬，例如鈦、鎳及鉑，以在磊晶層12之表面區域形成第一金屬矽化物層15，如圖8所示。接著，如圖9所示，進行沉積製程以在磊晶層12上形成第一金屬層13。第一金屬層13形成後，第一金屬層13填充於各凹部122中而接觸各凸部121及各凹部122之表面，即凸部121之頂面1211、凸部121之側面1212及凹部122之底面1221。Then, a metal such as titanium, nickel, and platinum is doped on the surface of the epitaxial layer 12 by a diffusion method or ion implantation to form a first metal in a surface region of the epitaxial layer 12. The telluride layer 15 is as shown in FIG. Next, as shown in FIG. 9, a deposition process is performed to form the first metal layer 13 on the epitaxial layer 12. After the first metal layer 13 is formed, the first metal layer 13 is filled in each of the concave portions 122 to contact the surfaces of the convex portions 121 and the concave portions 122, that is, the top surface 1211 of the convex portion 121, the side surface 1212 of the convex portion 121, and the concave portion 122. The bottom surface 1221.
在一些實施態樣中，在形成第二金屬層14之前，如圖10所示，對半導體基板11的另一表面即下表面112進行蝕刻製程，以在下表面112形成複數凸部113及複數凹部114而形成另一非平坦之表面。並且，控制蝕刻的時間，使得第三垂直距離d3與第四垂直距離d4的比值係在0.99至0.99999之範圍間。同理，亦可藉由濕蝕刻製程及乾蝕刻製程使得第三垂直距離d3與第四垂直距離d4的比值係在0.99至0.99999之範圍間，而濕蝕刻製程及乾蝕刻製程已詳述於前，於此不再贅述。In some embodiments, before forming the second metal layer 14, as shown in FIG. 10, the other surface of the semiconductor substrate 11, that is, the lower surface 112 is etched to form a plurality of convex portions 113 and a plurality of concave portions on the lower surface 112. 114 forms another non-flat surface. Also, the etching time is controlled such that the ratio of the third vertical distance d3 to the fourth vertical distance d4 is in the range of 0.99 to 0.99999. Similarly, the ratio of the third vertical distance d3 to the fourth vertical distance d4 may be in the range of 0.99 to 0.99999 by the wet etching process and the dry etching process, and the wet etching process and the dry etching process are detailed in the front. This will not be repeated here.
接著，如圖11所示，以擴散方法或以離子佈植的方式在半導體基板11之下表面112摻雜金屬，以在下表面112形成第二金屬矽化物層16。Next, as shown in FIG. 11, the lower surface 112 of the semiconductor substrate 11 is doped with a metal by diffusion or ion implantation to form a second metal germanide layer 16 on the lower surface 112.
最後，在形成複數凸部113及複數凹部114之後，如圖12所示，在半導體基板11之下表面112上進行沉積製程以形成第二金屬層14。第二金屬層14填充於各凹部114中而接觸各凸部113及各凹部114之表面，即凸部113之頂面1131、凸部113之側面1132及凹部114之底面1141。Finally, after forming the plurality of convex portions 113 and the plurality of concave portions 114, as shown in FIG. 12, a deposition process is performed on the lower surface 112 of the semiconductor substrate 11 to form the second metal layer 14. The second metal layer 14 is filled in each of the concave portions 114 to contact the surfaces of the convex portions 113 and the concave portions 114, that is, the top surface 1131 of the convex portion 113, the side surface 1132 of the convex portion 113, and the bottom surface 1141 of the concave portion 114.
在一些實施態樣中，可藉由沉積製程之化學氣相沉積法（chemical vapor deposition；CVD）或物理氣象沉積法（physical vapor deposition；PVD）來形成第一金屬層13及第二金屬層14。再者，在一些實施態樣中，為了增加第一金屬矽化物層15與第一金屬層13之間的接觸面積，以及第二金屬矽化物層16與第二金屬層14之間的接觸面積，可進一步以利用蝕刻技術或物理加工技術使各凸部121及凹部122之各表面為一彎曲面，如圖1所示，相較於圖2至圖4中之凸部113、121及凹部114、122，圖1中之凸部113之頂面1131、凸部113之側面1132、凸部121之頂面1211、凸部121之側面1212、凹部114之底面1141以及凹部122之底面1221均為一彎曲面而使第一金屬矽化物層15與第一金屬層13之間以及第二金屬矽化物層16與第二金屬層14之間具有較大的接觸面積。In some embodiments, the first metal layer 13 and the second metal layer 14 may be formed by a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) of a deposition process. . Moreover, in some embodiments, in order to increase the contact area between the first metal telluride layer 15 and the first metal layer 13, and the contact area between the second metal telluride layer 16 and the second metal layer 14 Further, each surface of each of the convex portion 121 and the concave portion 122 may be a curved surface by using an etching technique or a physical processing technique, as shown in FIG. 1 , compared with the convex portions 113, 121 and the concave portion in FIGS. 2 to 4 . 114, 122, the top surface 1131 of the convex portion 113 in FIG. 1, the side surface 1132 of the convex portion 113, the top surface 1211 of the convex portion 121, the side surface 1212 of the convex portion 121, the bottom surface 1141 of the concave portion 114, and the bottom surface 1221 of the concave portion 122 are both A curved surface has a large contact area between the first metal telluride layer 15 and the first metal layer 13 and between the second metal telluride layer 16 and the second metal layer 14.
綜上所述，根據本發明之一蕭特基二極體之實施例，磊晶層具有凸部及凹部使得蕭基接觸係為非平坦而提升金屬矽化物層與金屬層之間的接觸面積，如此一來便降低蕭基接觸之接觸電阻進而提升蕭特基二極體之性能。再者，藉由蝕刻製程而非藉由光罩來形成凹部及凸部可降低製程之生產成本。In summary, according to an embodiment of the Schottky diode of the present invention, the epitaxial layer has convex portions and concave portions such that the Schottky contact system is non-flat and the contact area between the metal telluride layer and the metal layer is increased. In this way, the contact resistance of the Xiaoji contact is lowered to improve the performance of the Schottky diode. Moreover, the manufacturing cost of the process can be reduced by forming the recesses and protrusions by the etching process instead of by the reticle.
雖然本發明已以實施例揭露如上然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之專利申請範圍所界定者為準。The present invention has been disclosed in the above embodiments, and it is not intended to limit the present invention. Any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended patent application.
11‧‧‧半導體基板
111‧‧‧上表面
112‧‧‧下表面
113‧‧‧凸部
1131‧‧‧頂面
1132‧‧‧側面
114‧‧‧凹部
1141‧‧‧底面
12‧‧‧磊晶層
121‧‧‧凸部
1211‧‧‧頂面
1212‧‧‧側面
122‧‧‧凹部
1221‧‧‧底面
13‧‧‧第一金屬層
14‧‧‧第二金屬層
15‧‧‧第一金屬矽化物層
16‧‧‧第二金屬矽化物層
d1‧‧‧第一垂直距離
d2‧‧‧第二垂直距離
d3‧‧‧第三垂直距離
d4‧‧‧第四垂直距離11‧‧‧Semiconductor substrate
111‧‧‧Upper surface
112‧‧‧ lower surface
113‧‧‧ convex
1131‧‧‧ top surface
1132‧‧‧ side
114‧‧‧ recess
1141‧‧‧ bottom
12‧‧‧ epitaxial layer
121‧‧‧ convex
1211‧‧‧ top surface
1212‧‧‧ side
122‧‧‧ recess
1221‧‧‧ bottom
13‧‧‧First metal layer
14‧‧‧Second metal layer
15‧‧‧First metal telluride layer
16‧‧‧Second metal telluride layer
D1‧‧‧first vertical distance
D2‧‧‧second vertical distance
D3‧‧‧ third vertical distance
D4‧‧‧ fourth vertical distance
[圖1] 為根據本發明之蕭特基二極體結構之第一實施例之剖面示意圖。 [圖2] 為根據本發明之蕭特基二極體結構之第二實施例之剖面示意圖。 [圖3] 為根據本發明之蕭特基二極體結構之第三實施例之剖面示意圖。 [圖4] 為根據本發明之蕭特基二極體結構之第四實施例之剖面示意圖。 [圖5] 為根據本發明之蕭特基二極體結構之形成方法之一實施例之步驟分解圖（一）。 [圖6] 為根據本發明之蕭特基二極體結構之形成方法之一實施例之步驟分解圖（二）。 [圖7] 為根據本發明之蕭特基二極體結構之形成方法之一實施例之步驟分解圖（三）。 [圖8] 為根據本發明之蕭特基二極體結構之形成方法之一實施例之步驟分解圖（四）。 [圖9] 為根據本發明之蕭特基二極體結構之形成方法之一實施例之步驟分解圖（五）。 [圖10] 為根據本發明之蕭特基二極體結構之形成方法之一實施例之步驟分解圖（六）。 [圖11] 為根據本發明之蕭特基二極體結構之形成方法之一實施例之步驟分解圖（七）。 [圖12] 為根據本發明之蕭特基二極體結構之形成方法之一實施例之步驟分解圖（八）。Fig. 1 is a schematic cross-sectional view showing a first embodiment of a Schottky diode structure according to the present invention. Fig. 2 is a schematic cross-sectional view showing a second embodiment of the Schottky diode structure according to the present invention. Fig. 3 is a schematic cross-sectional view showing a third embodiment of the Schottky diode structure according to the present invention. Fig. 4 is a schematic cross-sectional view showing a fourth embodiment of the Schottky diode structure according to the present invention. Fig. 5 is an exploded perspective view (I) of an embodiment of a method for forming a Schottky diode structure according to the present invention. Fig. 6 is an exploded perspective view (2) of an embodiment of a method for forming a Schottky diode structure according to the present invention. Fig. 7 is an exploded perspective view (III) of an embodiment of a method for forming a Schottky diode structure according to the present invention. Fig. 8 is an exploded perspective view (4) of an embodiment of a method for forming a Schottky diode structure according to the present invention. Fig. 9 is an exploded perspective view (5) of an embodiment of a method for forming a Schottky diode structure according to the present invention. Fig. 10 is an exploded perspective view (6) of an embodiment of a method for forming a Schottky diode structure according to the present invention. [Fig. 11] Fig. 11 is an exploded view (7) of an embodiment of a method for forming a Schottky diode structure according to the present invention. Fig. 12 is an exploded perspective view (8) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
11‧‧‧半導體基板 11‧‧‧Semiconductor substrate
111‧‧‧上表面 111‧‧‧Upper surface
112‧‧‧下表面 112‧‧‧ lower surface
113‧‧‧凸部 113‧‧‧ convex
1131‧‧‧頂面 1131‧‧‧ top surface
1132‧‧‧側面 1132‧‧‧ side
114‧‧‧凹部 114‧‧‧ recess
1141‧‧‧底面 1141‧‧‧ bottom
12‧‧‧磊晶層 12‧‧‧ epitaxial layer
121‧‧‧凸部 121‧‧‧ convex
1211‧‧‧頂面 1211‧‧‧ top surface
1212‧‧‧側面 1212‧‧‧ side
122‧‧‧凹部 122‧‧‧ recess
1221‧‧‧底面 1221‧‧‧ bottom
13‧‧‧第一金屬層 13‧‧‧First metal layer
14‧‧‧第二金屬層 14‧‧‧Second metal layer
15‧‧‧第一金屬矽化物層 15‧‧‧First metal telluride layer
16‧‧‧第二金屬矽化物層 16‧‧‧Second metal telluride layer
d1‧‧‧第一垂直距離 D1‧‧‧first vertical distance
d2‧‧‧第二垂直距離 D2‧‧‧second vertical distance
d3‧‧‧第三垂直距離 D3‧‧‧ third vertical distance
d4‧‧‧第四垂直距離 D4‧‧‧ fourth vertical distance
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| TW201614733A (en) * | 2014-10-03 | 2016-04-16 | Brillliant Engineering Tech Co Ltd | Trench Schottky diode and manufacturing method thereof |
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| WO2001091187A1 (en) * | 2000-05-22 | 2001-11-29 | Abb Ab | A semiconductor device |
| TW201605058A (en) * | 2014-07-25 | 2016-02-01 | Pan Jit Internat Inc | Trench Schottky diode |
| TW201614733A (en) * | 2014-10-03 | 2016-04-16 | Brillliant Engineering Tech Co Ltd | Trench Schottky diode and manufacturing method thereof |
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