TWI589116B - A system and method of driving a power transistor - Google Patents
A system and method of driving a power transistor Download PDFInfo
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- TWI589116B TWI589116B TW105130500A TW105130500A TWI589116B TW I589116 B TWI589116 B TW I589116B TW 105130500 A TW105130500 A TW 105130500A TW 105130500 A TW105130500 A TW 105130500A TW I589116 B TWI589116 B TW I589116B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Description
本發明涉及電路領域，更具體地涉及驅動功率電晶體的系統和方法。 The present invention relates to the field of circuits, and more particularly to systems and methods for driving power transistors.
近年來，隨著電子產業和積體電路的快速發展，各國對電子產品能耗的要求越來越高。在小功率電源轉換器領域，雙極型功率電晶體(Bipolar Power Transistor，本文簡稱為功率電晶體)以良好的開關特性和低廉的價格等優勢得以廣泛使用。為了滿足能耗標準，期望降低用於功率電晶體的驅動電路的損耗，提高該驅動電路的效率。 In recent years, with the rapid development of the electronics industry and integrated circuits, countries are increasingly demanding energy consumption for electronic products. In the field of low-power power converters, Bipolar Power Transistor (referred to as power transistor) is widely used with good switching characteristics and low price. In order to meet the energy consumption standard, it is desirable to reduce the loss of the driving circuit for the power transistor and improve the efficiency of the driving circuit.
在現有的用於功率電晶體的驅動電路中，不管輸入電壓高低，都採用固定的驅動電流來驅動功率電晶體。這樣，很容易出現以下情況：當輸入電壓低時，由於導通時間長，功率電晶體的輸入電荷過多，功率電晶體很容易進入深度飽和的工作狀態，從而導致功率電晶體的關斷速度慢，關斷損耗上升；當輸入電壓高時，由於導通時間短，功率電晶體的輸入電荷不足，功率電晶體未進入飽和的工作狀態，從而導致功率電晶體的導通損耗上升。在上述兩種情況下，用於功率電晶體的驅動電路的能耗都比較高。 In the existing driving circuit for a power transistor, a fixed driving current is used to drive the power transistor regardless of the input voltage level. In this way, it is easy to occur that when the input voltage is low, the input electric charge of the power transistor is excessive due to the long conduction time, and the power transistor can easily enter the deep saturated working state, thereby causing the power transistor to turn off slowly. The turn-off loss rises; when the input voltage is high, the input capacitance of the power transistor is insufficient due to the short on-time, and the power transistor does not enter a saturated operating state, thereby causing the conduction loss of the power transistor to rise. In both cases, the power consumption of the drive circuit for the power transistor is relatively high.
鑒於以上所述的問題，本發明提供了一種新穎的驅動功率電晶體的系統和方法。 In view of the problems described above, the present invention provides a novel system and method for driving a power transistor.
根據本公開的一個方面，提供了一種驅動功率電晶體的系統，包括：比例轉換電路，被配置為基於第一控制信號，利用第一轉換比例或第二轉換比例對表徵流過功率電晶體的電流的第一表徵信號進行轉 換，生成第二表徵信號；以及開關驅動電路，被配置為基於第二控制信號、第三控制信號、以及第二表徵信號，生成控制功率電晶體的導通與截止的驅動信號，其中比例轉換電路在第一控制信號處於高位準時利用第一轉換比例對第一表徵信號進行轉換，並且在第一控制信號處於低位準時利用第二轉換比例對第一表徵信號進行轉換，開關驅動電路在第二控制信號處於高位準且第三控制信號處於低位準的第一時段內將第一預定信號作為驅動信號，在第二控制信號處於高位準且第三控制信號處於低位準的第二時段內將第二表徵信號作為驅動信號，並且在第二控制信號和第三控制信號均處於高位準時將第二預定信號作為驅動信號。 According to an aspect of the present disclosure, a system for driving a power transistor is provided, comprising: a ratio conversion circuit configured to characterize a flow through a power transistor using a first conversion ratio or a second conversion ratio pair based on a first control signal The first characterization signal of the current is turned And generating a second characterization signal; and a switch driving circuit configured to generate a driving signal for controlling conduction and deactivation of the power transistor based on the second control signal, the third control signal, and the second characterization signal, wherein the proportional conversion circuit Converting the first characterization signal with the first conversion ratio when the first control signal is at a high level, and converting the first characterization signal with the second conversion ratio when the first control signal is at a low level, the switch driving circuit is in the second control The first predetermined signal is used as the driving signal in the first period in which the signal is at the high level and the third control signal is in the low level, and the second is in the second period in which the second control signal is at the high level and the third control signal is in the low level The characterization signal is used as a drive signal, and the second predetermined signal is used as a drive signal when both the second control signal and the third control signal are at a high level.
根據本公開的另一方面，提供了一種驅動功率電晶體的方法，包括：基於第一控制信號，利用第一轉換比例或第二轉換比例對表徵流過功率電晶體的電流的第一表徵信號進行轉換，生成第二表徵信號；以及基於第二控制信號、第三控制信號、以及第二表徵信號，生成控制功率電晶體的導通與截止的驅動信號，其中在第一控制信號處於高位準時利用第一轉換比例對第一表徵信號進行轉換，並且在第一控制信號處於低位準時利用第二轉換比例對第一表徵信號進行轉換，在第二控制信號處於高位準且第三控制信號處於低位準的第一時段內將第一預定信號作為驅動信號，在第二控制信號處於高位準且第三控制信號處於低位準的第二時段內將第二表徵信號作為驅動信號，並且在第二控制信號和第三控制信號均處於高位準時將第二預定信號作為驅動信號。 In accordance with another aspect of the present disclosure, a method of driving a power transistor is provided, comprising: utilizing a first conversion ratio or a second conversion ratio pair to characterize a first characterization signal of a current flowing through a power transistor based on a first control signal Performing a conversion to generate a second characterization signal; and generating a driving signal for controlling the on and off of the power transistor based on the second control signal, the third control signal, and the second characterization signal, wherein the first control signal is utilized when the first control signal is at a high level The first conversion ratio converts the first characterization signal, and converts the first characterization signal with the second conversion ratio when the first control signal is at a low level, the second control signal is at a high level and the third control signal is at a low level The first predetermined signal is used as the driving signal in the first period, the second characterization signal is used as the driving signal in the second period in which the second control signal is at the high level, and the second control signal is in the low level, and in the second control signal The second predetermined signal is used as the driving signal when both the third control signal and the third control signal are at a high level.
根據本申請實施例的基於導通時間控制驅動功率電晶體的系統和方法提供了一種以較低功率損耗來驅動功率電晶體的途徑。取決於實施例，還可以獲得一個或多個益處。參考下面的詳細描述和附圖可以全面地理解本發明的這些益處以及各個另外的目的、特徵和優點。 A system and method for controlling a power transistor based on on-time control in accordance with embodiments of the present application provides a way to drive a power transistor at a lower power loss. One or more benefits may also be obtained depending on the embodiment. These and other additional objects, features and advantages of the present invention will be fully understood from the description and appended claims.
100‧‧‧系統 100‧‧‧ system
101‧‧‧脈波生成電路 101‧‧‧ Pulse wave generation circuit
102‧‧‧開關驅動電路 102‧‧‧Switch drive circuit
103‧‧‧偏置電流電路 103‧‧‧ Bias current circuit
104‧‧‧K1/K2比例轉換電路 104‧‧‧K1/K2 ratio conversion circuit
105‧‧‧固定導通時間生成電路 105‧‧‧Fixed on-time generation circuit
106‧‧‧一次繞組電感 106‧‧‧One winding inductance
107‧‧‧功率電晶體 107‧‧‧Power transistor
108‧‧‧取樣電阻 108‧‧‧Sampling resistor
200‧‧‧流程圖 200‧‧‧flow chart
300、400‧‧‧時序圖 300, 400‧‧‧ Timing Chart
201、202、203‧‧‧步驟 201, 202, 203‧ ‧ steps
t0、t1、t2、t3、t4‧‧‧時間 t 0 , t 1 , t 2 , t 3 , t 4 ‧‧‧ time
301、302、303、304、401、402、403、404‧‧‧波形 301, 302, 303, 304, 401, 402, 403, 404‧‧‧ waveforms
PWM‧‧‧脈波開關信號 PWM‧‧‧ Pulse Switch Signal
PWM_PRE‧‧‧預關斷信號 PWM_PRE‧‧‧ pre-shutdown signal
PWM_ON‧‧‧PWM導通時間 PWM_ON‧‧‧PWM on time
TON_TH‧‧‧固定導通時間 T ON_TH ‧‧‧Fixed on time
Re‧‧‧偏置電阻 Re‧‧‧ bias resistor
VIN‧‧‧輸入電壓 V IN ‧‧‧ input voltage
VCS‧‧‧電壓信號 V CS ‧‧‧ voltage signal
IB‧‧‧偏置電流信號 I B ‧‧‧bias current signal
ICS‧‧‧電流信號 I CS ‧‧‧current signal
Ipusle‧‧‧脈波驅動電流 I pusle ‧‧‧pulse drive current
IBASE‧‧‧基極驅動電流信號 I BASE ‧‧‧base drive current signal
下面，將結合附圖對本實用新型的示例性實施例的特徵、優點和技術 效果進行描述，附圖中相似的附圖標記表示相似的元件，其中：第1圖是示出了根據本公開的實施例的、基於導通時間控制驅動功率電晶體的系統的框圖。 In the following, features, advantages and techniques of an exemplary embodiment of the present invention will be described with reference to the drawings. The effect is described in the drawings, like reference numerals designate like elements, in which: FIG. 1 is a block diagram showing a system for controlling a power transistor based on on-time control, in accordance with an embodiment of the present disclosure.
第2圖是示出了根據本公開的實施例的、基於導通時間控制驅動功率電晶體的方法的流程圖。 2 is a flow chart showing a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure.
第3圖是示出了根據本公開的實施例的、示出基於導通時間控制驅動功率電晶體的方法中各信號與功率電晶體的基極電流的時序關係的簡化時序圖。 3 is a simplified timing diagram showing a timing relationship of respective signals and a base current of a power transistor in a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure.
第4圖是示出了根據本公開的實施例的、示出基於導通時間控制驅動功率電晶體的方法中各信號與功率電晶體的基極電流的另一時序關係的簡化時序圖。 4 is a simplified timing diagram showing another timing relationship of respective signals with a base current of a power transistor in a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure.
下面將詳細描述本發明的各個方面的特徵和示例性實施例。在下面的詳細描述中，提出了許多具體細節，以便提供對本發明的全面理解。但是，對於本領域技術人員來說很明顯的是，本發明可以在不需要這些具體細節中的一些細節的情況下實施。下面對實施例的描述僅僅是為了通過示出本發明的示例來提供對本發明的更好的理解。本發明決不限於下面所提出的任何具體配置和演算法，而是在不脫離本發明的精神的前提下覆蓋了元素、部件和演算法的任何修改、替換和改進。在附圖和下面的描述中，沒有示出公知的結構和技術，以便避免對本發明造成不必要的模糊。 Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth However, it will be apparent to those skilled in the art that the present invention may be practiced without some of the details. The following description of the embodiments is merely provided to provide a better understanding of the invention. The present invention is in no way limited to any specific configurations and algorithms presented below, but without departing from the spirit and scope of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary obscuring the invention.
第1圖是示出根據本發明實施例的驅動功率電晶體的系統的框圖。如第1圖所示，驅動功率電晶體的系統100包括開關驅動電路102、取樣電壓K1/K2比例轉換電路104，並且還可選的包括脈波生成電路101、偏置電流電路103、固定導通時間生成電路105。此外，系統還可以包括變壓器的一次繞組電感106、功率電晶體107、以及取樣電阻108。 FIG. 1 is a block diagram showing a system for driving a power transistor according to an embodiment of the present invention. As shown in FIG. 1, the system 100 for driving a power transistor includes a switch driving circuit 102, a sampling voltage K1/K2 ratio conversion circuit 104, and optionally includes a pulse wave generating circuit 101, a bias current circuit 103, and a fixed conduction. Time generation circuit 105. In addition, the system can also include a primary winding inductance 106 of the transformer, a power transistor 107, and a sampling resistor 108.
在一個示例中，功率電晶體107是雙極結型電晶體。在 另一示例中，功率電晶體107是場效應電晶體(例如，金屬氧化物半導體場效應電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET))。在又另一示例中，功率電晶體107是絕緣閘雙極性電晶體(Insulated Gate Bipolar Transistor,IGBT)。在各種示例中，偏置電路往往有若干元件，其中偏置電阻Re的電阻值可以由本領域技術人員根據需要設置。 In one example, power transistor 107 is a bipolar junction transistor. in In another example, the power transistor 107 is a field effect transistor (eg, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)). In yet another example, the power transistor 107 is an insulated gate bipolar transistor (IGBT). In various examples, the biasing circuit tends to have several components, wherein the resistance value of the biasing resistor Re can be set as desired by those skilled in the art.
如第1圖所示，脈波生成電路101與開關驅動電路102、偏置電流電路103、K1/K2比例轉換電路104、以及功率電晶體107的基極相耦接。開關驅動電路102與脈波生成電路101、偏置電流電路103、K1/K2比例轉換電路104相耦接。偏置電流電路103與脈波生成電路101、開關驅動電路102相耦接。K1/K2比例轉換電路104與脈波生成電路101、開關驅動電路102、固定導通時間生成電路105、以及取樣電阻108相耦接。一次繞組電感106的一端相耦接與功率電晶體107的集極相耦接，另一端接開關電源的輸入電壓VIN。功率電晶體107的基極與脈波生成電路101相耦接，集極與一次繞組電感106的一端相耦接，並且發射極與取樣電阻108的一端相耦接。取樣電阻108的一端與功率電晶體107的發射極相耦接，另一端接地。 As shown in Fig. 1, the pulse wave generating circuit 101 is coupled to the switch drive circuit 102, the bias current circuit 103, the K1/K2 ratio conversion circuit 104, and the base of the power transistor 107. The switch drive circuit 102 is coupled to the pulse wave generating circuit 101, the bias current circuit 103, and the K1/K2 ratio conversion circuit 104. The bias current circuit 103 is coupled to the pulse wave generating circuit 101 and the switch driving circuit 102. The K1/K2 ratio conversion circuit 104 is coupled to the pulse wave generation circuit 101, the switch drive circuit 102, the fixed on-time generation circuit 105, and the sampling resistor 108. One end of the primary winding inductor 106 is coupled to the collector of the power transistor 107, and the other end is coupled to the input voltage V IN of the switching power supply. The base of the power transistor 107 is coupled to the pulse wave generating circuit 101, the collector is coupled to one end of the primary winding inductor 106, and the emitter is coupled to one end of the sampling resistor 108. One end of the sampling resistor 108 is coupled to the emitter of the power transistor 107, and the other end is grounded.
根據一些實施例，開關驅動電路102接收來自脈波生成電路101的脈寬調變(Pulse Width Modulation,PWM)信號/預關斷信號(PWM_PRE)、來自偏置電流電路103的偏置電流信號IB、以及來自K1/K2比例轉換電路104的電流信號ICS。開關驅動電路102可以基於所接收的脈波開關信號PWM/PWM_PRE、偏置電流信號IB和斜坡電流信號ICS來生成基極驅動電流信號IBASE，以控制功率電晶體107的導通和截止。 According to some embodiments, the switch drive circuit 102 receives a Pulse Width Modulation (PWM) signal/pre-shutdown signal (PWM_PRE) from the pulse wave generation circuit 101, and a bias current signal I from the bias current circuit 103. B , and the current signal I CS from the K1/K2 ratio conversion circuit 104. The switch drive circuit 102 can generate a base drive current signal I BASE based on the received pulse switching signal PWM/PWM_PRE, the bias current signal I B , and the ramp current signal I CS to control the turn-on and turn-off of the power transistor 107.
取樣電阻106上對開關電源進行取樣，所得的電壓信號VCS被輸入K1/K2比例轉換電路104。隨後K1/K2比例轉換電路104按不同K1/K2比例將電壓信號VCS轉換成斜坡電流信號ICS。具體地，如果脈波開關信號PWM的導通時間PWM_ON小於固定導通時間TON_TH(例 如，導通時間閾值)，則K1/K2比例轉換電路104將VCS按K1比例轉換成ICS，並且如果脈波開關信號PWM的導通時間PWM_ON大於固定導通時間TON_TH，則K1/K2比例轉換電路104首先將VCS以較大的K1比例轉換，隨後再進一步以較小的K2比例轉換成ICS，其中K1比例在大小上相較K2比例更大；並且其中固定導通時間TON_TH是可以根據實際情況預定義的閾值時間。 The switching power supply is sampled on the sampling resistor 106, and the resulting voltage signal V CS is input to the K1/K2 ratio conversion circuit 104. The K1/K2 ratio conversion circuit 104 then converts the voltage signal V CS into a ramp current signal I CS at a different K1/K2 ratio. Specifically, if the on-time PWM_ON of the pulse wave switching signal PWM is less than the fixed on-time T ON_TH (eg, the on-time threshold), the K1/K2 ratio conversion circuit 104 converts V CS into I CS in a K1 ratio, and if the pulse wave The on-time PWM_ON of the switching signal PWM is greater than the fixed on-time T ON_TH , and the K1/K2 ratio conversion circuit 104 first converts V CS by a larger K1 ratio, and then further converts to I CS with a smaller K2 ratio, where K1 The ratio is larger in magnitude than the K2 ratio; and wherein the fixed on-time T ON_TH is a threshold time that can be predefined according to actual conditions.
從而，當系統輸入電壓VIN高時，由於PWM導通時間PWM_ON比固定導通時間TON_TH短，使得VCS能採用大的K1比例轉換成ICS，較大ICS能確保基極輸入電荷足夠使功率電晶體107進入飽和的工作狀態，減少功率電晶體導通損耗。而當系統輸入電壓VIN低時，由於PWM導通時間PWM_ON遠比固定導通時間TON_TH長，使得VCS首先以較大的K1比例轉換，隨後再進一步以較小的K2比例轉換成ICS，這樣轉換產生的較小ICS能保證基極輸入電荷不過剩，減少功率電晶體107的驅動損耗。 Therefore, when the system input voltage V IN is high, since the PWM on-time PWM_ON is shorter than the fixed on-time T ON_TH , V CS can be converted to I CS by using a large K1 ratio, and the larger I CS can ensure that the base input charge is sufficient. Power transistor 107 enters a saturated operating state, reducing power transistor conduction losses. When the system input voltage V IN is low, since the PWM on-time PWM_ON is much longer than the fixed on-time T ON_TH , V CS is first converted with a larger K1 ratio, and then further converted to I CS with a smaller K2 ratio. The smaller I CS produced by this conversion ensures that the base input charge is not left, reducing the drive loss of the power transistor 107.
第2圖是示出了根據本公開的實施例的、基於導通時間控制驅動功率電晶體的方法的流程圖。該圖僅作為示例，其不應該不適當地限制申請專利範圍。本領域的普通技術人員應該理解很多變化、替代和修改。 2 is a flow chart showing a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure. This figure is only an example and should not unduly limit the scope of patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art.
方法開始於步驟201，接收脈寬調變PWM信號以及來自功率電晶體的發射極的取樣電壓信號VCS；並且隨後在步驟202，將電壓信號VCS轉換成電流信號ICS。其中如果PWM的導通時間PWM_ON小於導通時間閾值，則將電壓信號VCS按K1比例轉換成電流信號ICS，並且如果PWM_ON大於導通時間閾值，則首先將電壓信號VCS按K1比例轉換、隨後再進一步以K2比例轉換成電流信號ICS，其中K1比例在大小上相較K2比例更大。 The method begins in step 201 by receiving a pulse width modulated PWM signal and a sampled voltage signal V CS from the emitter of the power transistor; and then at step 202, converting the voltage signal V CS to a current signal I CS . Wherein if the PWM on-time PWM_ON less than the on-time threshold, the voltage signal V CS conversion press K1 proportional to current signal I CS, and if PWM_ON than the turn on time threshold value, the first voltage signal V CS press K1 scale conversion, followed by Further converted to a current signal I CS in a K2 ratio, wherein the K1 ratio is larger in magnitude than the K2 ratio.
方法隨後前進到步驟203，接收PWM信號、偏置電流信號IB、以及電流信號ICS，並且至少部分地基於電流信號ICS來生成基極驅 動電流信號IBASE以驅動功率電晶體。 The method then proceeds to step 203 to receive the PWM signal, the bias current signal I B , and the current signal I CS , and generate a base drive current signal I BASE based at least in part on the current signal I CS to drive the power transistor.
第3圖是示出了根據本公開的實施例的、示出基於導通時間控制驅動功率電晶體的方法中各信號與功率電晶體的基極電流的時序關係的簡化時序圖300。該圖僅作為示例，其不應該不適當地限制申請專利範圍。本領域的普通技術人員應該理解很多變化、替代和修改。如第3圖所示，波形301代表固定導通時間TON_TH，波形302代表隨時間變化的PWM信號，波形303代表隨時間變化的PWM_PRE信號，並且波形304代表隨時間變化的基極驅動電流信號IBASE。 3 is a simplified timing diagram 300 showing a timing relationship of respective signals to a base current of a power transistor in a method of driving a power transistor based on on-time control, in accordance with an embodiment of the present disclosure. This figure is only an example and should not unduly limit the scope of patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. As shown in FIG. 3, waveform 301 represents a fixed on-time T ON_TH , waveform 302 represents a PWM signal that changes with time, waveform 303 represents a PWM_PRE signal that changes with time, and waveform 304 represents a base drive current signal I that changes with time. BASE .
第3圖示出了當系統輸入電壓VIN高時的信號時序。其中對於PWM信號相關聯的導通時間段和關斷時間段，導通時間段PWN_ON在時間t0處開始並且在時間t3處結束。例如，t0 t1 t2 t3 t4。其中，根據功率二極體的基極電流和發射極電流之間的關係，可以將由取樣電阻(例如，取樣電阻108)所取樣的電壓VCS與基極驅動電流信號IBASE的關係表示如下：VCS=(1+β)×IBASE×R (公式1) Figure 3 shows the signal timing when the system input voltage V IN is high. Wherein for the on-time period and the off-time period associated with the PWM signal, the on-time period PWN_ON starts at time t 0 and ends at time t 3 . For example, t 0 t 1 t 2 t 3 t 4 . Wherein, according to the relationship between the base current and the emitter current of the power diode, the relationship between the voltage V CS sampled by the sampling resistor (for example, the sampling resistor 108) and the base driving current signal I BASE can be expressed as follows: V CS = (1 + β) × I BASE × R (Equation 1)
其中，β代表功率電晶體(例如，功率電晶體107)的靜態電流放大係數，R代表感測電阻的電阻值。 Where β represents the quiescent current amplification factor of the power transistor (eg, power transistor 107) and R represents the resistance value of the sense resistor.
根據一個實施例，在t0處，PWM信號從邏輯低位準改變到邏輯高位準，作為響應，基極驅動電流信號IBASE突變為固定時間寬度的脈波驅動電流Ipusle，例如，Ipusle的高位準持續時間可以為t0~t1。由於PWM導通時間PWN_ON(例如，t0~t3期間)比固定導通時間TON_TH(例如，t0~t4期間)短，將VCS按K1比例轉換成ICS。例如，電流信號ICS被配置為按如下的公式確定：ICS=VCS×K1 (公式2) According to one embodiment, at t 0 , the PWM signal changes from a logic low level to a logic high level, and in response, the base drive current signal I BASE is abruptly changed to a fixed time width pulse drive current I pusle , eg, I pusle The high level duration can be t 0 ~ t 1 . Since the PWM on-time PWN_ON (for example, during t 0 to t 3 ) is shorter than the fixed on-time T ON — TH (for example, during t 0 to t 4 ), V CS is converted to I CS in a K1 ratio. For example, the current signal I CS is configured to be determined as follows: I CS =V CS ×K1 (Equation 2)
其中，VCS代表對開關電源系統進行取樣的取樣電阻(例如，取樣電阻108)所獲得的取樣電壓，K1為PWN_ON短於TON_TH時VCS與ICS的轉換比例，K1為相對較大的比例以確保使得功率電晶體進入 飽和狀態的足夠ICS，從而降低導通損耗。如第3圖所示，根據公式1-公式2，在t1~t2時間段期間，至少部分地基於電流信號ICS的基極驅動電流信號IBASE線性增加。 Wherein, V CS represents a sampling voltage obtained by sampling a sampling resistor (for example, sampling resistor 108) for sampling the switching power supply system, and K1 is a conversion ratio of V CS to I CS when PWN_ON is shorter than T ON_TH , and K1 is relatively large. The ratio is to ensure sufficient I CS to bring the power transistor into saturation, thereby reducing conduction losses. As shown in FIG. 3, according to Equation 1 - Equation 2, the base drive current signal I BASE is at least partially linearly increased based on the current signal I CS during the period t 1 ~ t 2 .
在一個實施例中，當預關斷信號PWM_PRE(例如，在t2處)從邏輯低位準改變到邏輯高位準，首先降低基極驅動電流信號IBASE(例如，如t2~t3時間段所示)，然後當PWM信號與預關斷信號PWM_PRE同時(例如，在t3處)從邏輯低位準改變到邏輯高位準，將基極驅動電流信號IBASE降低為關斷功率電晶體，這種對基極驅動電流信號IBASE的分級降低有利於減少關斷損耗。 In one embodiment, when the pre-turn-off signal PWM_PRE (e.g., at t 2) changes from a logic low level to a logic high level, to first reduce the base drive current signal I BASE (e.g., such as t 2 ~ t 3 period Shown), then when the PWM signal changes from the logic low level to the logic high level simultaneously with the pre-shutdown signal PWM_PRE (eg, at t 3 ), the base drive current signal I BASE is lowered to turn off the power transistor, which A step-down of the base drive current signal I BASE is beneficial to reduce turn-off losses.
第4圖是示出了根據本公開的實施例的、示出基於導通時間控制驅動功率電晶體的方法中各信號與功率電晶體的基極電流的另一時序關係的簡化時序圖。該圖僅作為示例，其不應該不適當地限制申請專利範圍。本領域的普通技術人員應該理解很多變化、替代和修改。如第4圖所示，波形401代表固定導通時間TON_TH，波形402代表隨時間變化的PWM信號，波形403代表隨時間變化的PWM_PRE信號，並且波形404代表隨時間變化的基極驅動電流信號IBASE。 4 is a simplified timing diagram showing another timing relationship of respective signals with a base current of a power transistor in a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure. This figure is only an example and should not unduly limit the scope of patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. As shown in FIG. 4, waveform 401 represents a fixed on-time T ON_TH , waveform 402 represents a PWM signal that changes with time, waveform 403 represents a PWM_PRE signal that changes with time, and waveform 404 represents a base drive current signal I that changes with time. BASE .
第4圖示出了當系統輸入電壓VIN低時的信號時序。其中對於PWM信號相關聯的導通時間段和關斷時間段，導通時間段PWN_ON在時間t0處開始並且在時間t4處結束。例如，t0 t1 t2 t3 t4。類似於第3圖，由取樣電阻(例如，取樣電阻108)所取樣的電壓VCS與基極驅動電流信號IBASE的關係如公式1所示。 Figure 4 shows the signal timing when the system input voltage V IN is low. Wherein for the on-time period and the off-time period associated with the PWM signal, the on-time period PWN_ON starts at time t 0 and ends at time t 4 . For example, t 0 t 1 t 2 t 3 t 4 . Similar to FIG. 3, the relationship between the voltage V CS sampled by the sampling resistor (for example, the sampling resistor 108) and the base drive current signal I BASE is as shown in Equation 1.
根據一個實施例，在t0處，PWM信號從邏輯低位準改變到邏輯高位準，作為響應，基極驅動電流信號IBASE突變為固定時間寬度的脈波驅動電流Ipusle，例如，Ipusle的高位準持續時間可以為t0~t1。由於PWM導通時間PWN_ON(例如，t0~t4期間)遠長於固定導通時間TON_TH(例如，t0~t2期間)，使得VCS首先以較大的K1比例轉換，隨後再進一步以較小的K2比例轉換成ICS，這樣轉換產生的較小ICS能保證基極輸入電荷 不過剩，減少功率電晶體的驅動損耗。電流信號ICS被配置為按如下的公式確定：ICS’=VCS×K1 ICS=ICS’×K2 (公式3) According to one embodiment, at t 0 , the PWM signal changes from a logic low level to a logic high level, and in response, the base drive current signal I BASE is abruptly changed to a fixed time width pulse drive current I pusle , eg, I pusle The high level duration can be t 0 ~ t 1 . Since the PWM on-time PWN_ON (for example, during t 0 to t 4 ) is much longer than the fixed on-time T ON — TH (for example, during t 0 to t 2 ), V CS is first converted with a larger K1 ratio, and then further The small K2 ratio is converted to I CS , so that the smaller I CS generated by the conversion can ensure that the base input charge is not left, reducing the driving loss of the power transistor. The current signal I CS is configured to be determined as follows: I CS '=V CS ×K1 I CS =I CS '×K2 (Equation 3)
其中，VCS代表對開關電源系統進行取樣的取樣電阻(例如，取樣電阻108)所獲得的取樣電壓，K1為PWN_ON短於TON_TH時VCS與ICS的轉換比例，K2為PWN_ON長於TON_TH時VCS與ICS的轉換比例，其中K2為相對較小的比例。根據公式1-公式2，在t1~t2時間段期間，至少部分地基於電流信號ICS的基極驅動電流信號IBASE線性增加。隨後在t2處(閾值信號TON_TH在該處從邏輯高位準改變到邏輯低位準)，中間信號ICS’突降預定大小，並隨即以基於K2的較小速率線性增長，如公式3所示。 Wherein, V CS represents a sampling voltage obtained by sampling a sampling resistor (for example, sampling resistor 108) for sampling the switching power supply system, K1 is a conversion ratio of V CS to I CS when PWN_ON is shorter than T ON_TH , and K2 is PWN_ON longer than T ON_TH The ratio of V CS to I CS , where K2 is a relatively small ratio. According to Equation 1 - Equation 2, during the period t 1 ~ t 2 , the base drive current signal I BASE is at least partially linearly increased based on the current signal I CS . Then at t 2 (where the threshold signal T ON_TH changes from a logic high level to a logic low level), the intermediate signal I CS 'bumps down by a predetermined magnitude and then linearly grows at a smaller rate based on K2, as in Equation 3. Show.
在一個實施例中，當預關斷信號PWM_PRE(例如，在t3處)從邏輯低位準改變到邏輯高位準，首先降低基極驅動電流信號IBASE(例如，如t3~t4時間段所示)。然後當PWM信號與預關斷信號PWM_PRE同時(例如，在t4處)從邏輯低位準改變到邏輯高位準，將基極驅動電流信號IBASE降低為關斷功率電晶體，這種對基極驅動電流信號IBASE的分級降低有利於減少關斷損耗。 In one embodiment, when the pre-turn-off signal PWM_PRE (e.g., at t 3) changes from a logic low level to a logic high level, to first reduce the base drive current signal I BASE (e.g., such as t 3 ~ t 4 time period Shown). Then, when the PWM signal and the pre-shutdown signal PWM_PRE are simultaneously changed (for example, at t 4 ) from the logic low level to the logic high level, the base driving current signal I BASE is lowered to the off power transistor, the pair of bases The step-down of the drive current signal I BASE is beneficial to reduce the turn-off loss.
本發明可以以其他的具體形式實現，而不脫離其精神和本質特徵。例如，特定實施例中所描述的演算法可以被修改，而系統體系結構並不脫離本發明的基本精神。因此，當前的實施例在所有方面都被看作是示例性的而非限定性的，本發明的範圍由所附申請專利範圍而非上述描述定義，並且，落入申請專利範圍的含義和等同物的範圍內的全部改變從而都被包括在本發明的範圍之中。 The invention may be embodied in other specific forms without departing from the spirit and essential characteristics. For example, the algorithms described in the specific embodiments can be modified, and the system architecture does not depart from the basic spirit of the invention. The present embodiments are to be considered in all respects as illustrative and not limiting, and the scope of the invention All changes in the scope of the invention are thus included in the scope of the invention.
本發明各個實施例中的一些或所有元件單獨地和/或與至少另一元件相組合地是利用一個或多個軟體元件、一個或多個硬體元件和/或軟體與硬體元件的一種或多種組合來實現的。在另一示例中，本發明各 個實施例中的一些或所有元件單獨地和/或與至少另一元件相組合地在一個或多個電路中實現，例如在一個或多個類比電路和/或一個或多個數位電路中實現。在又一示例中，本發明的各個實施例和/或示例可以相組合。 Some or all of the elements of various embodiments of the invention, alone and/or in combination with at least one other element, utilize one or more of the software elements, one or more hardware elements, and/or one of the soft and hard elements. Or a variety of combinations to achieve. In another example, each of the inventions Some or all of the elements in one embodiment are implemented in one or more circuits, alone or in combination with at least one other element, such as in one or more analog circuits and/or one or more digital circuits. . In yet another example, various embodiments and/or examples of the invention may be combined.
雖然已描述了本發明的具體實施例，然而本領域技術人員將明白，還存在於所述實施例等同的其它實施例。因此，將明白，本發明不受所示具體實施例的限制，而是僅由申請專利範圍來限定。 Although specific embodiments of the invention have been described, it will be apparent to those skilled in the art Therefore, it is to be understood that the invention is not limited by
100‧‧‧系統 100‧‧‧ system
101‧‧‧脈波生成電路 101‧‧‧ Pulse wave generation circuit
102‧‧‧開關驅動電路 102‧‧‧Switch drive circuit
103‧‧‧偏置電流電路 103‧‧‧ Bias current circuit
104‧‧‧K1/K2比例轉換電路 104‧‧‧K1/K2 ratio conversion circuit
105‧‧‧固定導通時間生成電路 105‧‧‧Fixed on-time generation circuit
106‧‧‧一次繞組電感 106‧‧‧One winding inductance
107‧‧‧功率電晶體 107‧‧‧Power transistor
108‧‧‧取樣電阻 108‧‧‧Sampling resistor
PWM‧‧‧脈波開關信號 PWM‧‧‧ Pulse Switch Signal
PWM_PRE‧‧‧預關斷信號 PWM_PRE‧‧‧ pre-shutdown signal
TON_TH‧‧‧固定導通時間 T ON_TH ‧‧‧Fixed on time
VIN‧‧‧輸入電壓 V IN ‧‧‧ input voltage
VCS‧‧‧電壓信號 V CS ‧‧‧ voltage signal
IB‧‧‧偏置電流信號 I B ‧‧‧bias current signal
ICS‧‧‧電流信號 I CS ‧‧‧current signal
IBASE‧‧‧基極驅動電流信號 I BASE ‧‧‧base drive current signal
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| CN110138221B (en) * | 2018-02-08 | 2020-12-25 | 比亚迪股份有限公司 | Power supply and switching power supply circuit thereof |
| CN110138220B (en) * | 2018-02-08 | 2022-05-20 | 比亚迪半导体股份有限公司 | Power supply and switching power supply circuit thereof |
| CN108880296B (en) * | 2018-06-12 | 2021-01-05 | 昂宝电子（上海）有限公司 | Power supply conversion system |
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| US7151406B2 (en) * | 2005-03-15 | 2006-12-19 | Texas Instruments Incorporated | Compensation of nonlinearity introduced by dead time in switching output stage |
| US7495423B1 (en) * | 2006-04-03 | 2009-02-24 | National Semiconductor Corporation | Apparatus and method for loop adjustment for a DC/DC switching regulator |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201810947A (en) | 2018-03-16 |
| CN106130319B (en) | 2019-04-16 |
| CN106130319A (en) | 2016-11-16 |
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