TWI588908B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI588908B
TWI588908B TW104140485A TW104140485A TWI588908B TW I588908 B TWI588908 B TW I588908B TW 104140485 A TW104140485 A TW 104140485A TW 104140485 A TW104140485 A TW 104140485A TW I588908 B TWI588908 B TW I588908B
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layer
fin structure
oxide
gate
channel
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TW201642354A (zh
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陳昭雄
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台灣積體電路製造股份有限公司
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Description

半導體裝置及其製造方法
本發明是關於半導體積體電路，特別是有關於具鰭式結構的半導體裝置及其製造方法。
當半導體工業已進展至奈米科技製程世代以追求更高的裝置密度、更高的效能和更低的成本，來自生產和設計的考驗造就了三維(3D)設計的發展，例如鰭式場效電晶體(Fin field effect transistor，FinFET)。FinFET裝置典型上包含具有高深寬比(aspect ratio)的半導體鰭(fins)，且形成半導體裝置的通道(channel)和源/汲極(source/drain，S/D)區域於其中。形成閘極(gate)於鰭式結構上和沿著鰭式結構的邊緣(例如：環繞)，利用增加通道和源/汲極區域表面積的優勢，以產生更快、更穩定和更良好控制的半導體電晶體裝置。一些裝置中，FinFET的源/汲極部分之應變材料係利用，例如矽鍺(SiGe)、磷化矽(SiP)或碳化矽(SiC)，以增加載子移動性。再者，氧化物結構上的通道係用以改善載子移動性和維持筆直的鰭式輪廓。
根據本揭示的一個觀點，在半導體裝置的製造方法中，形成鰭式結構包含井層、井層上之氧化物層和氧化物層上之通道層。形成隔離絕緣層使得鰭式結構的通道層從隔離絕 緣層突出，且至少一部份或整體的氧化物層嵌入隔離絕緣層內。形成閘極結構於鰭式結構的一部分和隔離絕緣層上。藉由蝕刻鰭式結構未被閘極結構覆蓋之一部分形成凹陷部，使得氧化層被移除和暴露出井層在二個閘極結構60之間的表面。形成磊晶層於凹陷部內暴露的井層和通道層上。將形成在暴露的井層上的磊晶層改質為改質層，使改質層對鹼性溶液的蝕刻選擇性較未改質的磊晶層增加。
根據本揭示的另一觀點，在半導體裝置的製造方法中，在基底上形成鰭式結構，此鰭式結構包含井層、井層上之氧化物層和氧化物層上之通道層。形成隔離絕緣層使得鰭式結構的通道層從隔離絕緣層突出，且至少一部份或整體的氧化物層嵌入隔離絕緣層內。形成第一閘極結構和第二閘極結構於鰭式結構的一部分和隔離絕緣層上。藉由蝕刻鰭式結構在第一閘極結構和第二閘極結構之間的一部分以形成凹陷部，使得氧化層被移除和暴露出井層在第一閘極結構和第二閘極結構之間的表面。形成磊晶層於凹陷部內暴露的井層和通道層上。將形成在暴露的井層上的磊晶層改質為改質層，使改質層對鹼性溶液的蝕刻選擇性增加。
根據本揭示的另一觀點，半導體裝置包含FinFET裝置。此FinFET裝置包含鰭式結構沿第一方向延伸且從隔離絕緣層突出。鰭式結構和隔離絕緣層設置於基底上。鰭式結構包含井層、井層上之氧化物層和氧化物層上之通道層。此FinFET裝置也包含閘極堆疊。閘極堆疊包含閘極電極層和閘極介電層，覆蓋一部分鰭式結構，且沿垂直於第一方向的第二方向延 伸。此FinFET裝置更包含源極和汲極，源極和汲極各自包含在鰭式結構內形成的凹陷部分內和上的應力源層((stressor layer)，或稱應變層(strain layer))。應力源層施加應力於閘極堆疊下的鰭式結構之通道層。再者，此FinFET裝置包含設置於井層和應力源層之間的改質層。改質層對鹼性溶液的耐蝕刻性(etching resistivity)較井層和通道層之至少一者高。
10‧‧‧基底
15‧‧‧井區
20‧‧‧第一磊晶層
25‧‧‧氧化物層
30‧‧‧第二磊晶層
40‧‧‧鰭式結構
42‧‧‧通道層
44‧‧‧井層
50‧‧‧隔離絕緣層
60‧‧‧閘極結構
100‧‧‧遮罩層
105‧‧‧遮罩圖案
110‧‧‧硬遮罩之頂層
112‧‧‧硬遮罩之底層
114‧‧‧閘極電極層
115‧‧‧閘極介電層
120‧‧‧側壁絕緣層
130‧‧‧凹陷部
140‧‧‧半導體磊晶層
145‧‧‧底部區域
150‧‧‧P型雜質
160‧‧‧應力源層
170‧‧‧層間介電層
175‧‧‧閘極電極空位
180‧‧‧金屬閘極結構
藉由以下的詳述配合所附圖式，可以更加理解本揭示的觀點。這裡強調的是，根據工業上的標準慣例，許多特徵部件(feature)僅為了闡述目的，並沒有按照比例繪製。事實上，為了能清楚地討論，許多特徵部件的尺寸可能被任意地增加或減少。
第1到19圖是根據本揭示的一實施例，顯示製造具有鰭式(fin)結構的半導體場效電晶體(field effect transistor，FET)裝置範例的製程，其中第9到16圖是根據本揭示的一實施例，顯示二個閘極結構60之間沿第8圖線X1-X1的部分區域剖面示意圖。
可理解的是以下揭示提供很多不同的實施例或範例，用於實施本發明之不同特徵。組件和配置的具體實施例或範例描述如下，以簡化本揭示。當然，這些僅僅是範例，並非用以限定本揭示。舉例而言，元件的尺寸並未限制於揭示的範圍或數值，但可取決於製程狀態及/或所需的裝置特性。再者，敘述中若提及第一特徵部件形成在第二特徵部件之上，可能包 含第一和第二特徵部件直接接觸的實施例，也可能包含額外的特徵部件形成在第一和第二特徵部件之間，使得它們不直接接觸的實施例。為了簡化和清楚，各種的特徵部件可被任意地繪示成不同的尺寸。
再者，空間上相關的措辭，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」和其他類似的字詞，可用於此，以簡化描述一元件或特徵與其他元件或特徵之間，如圖所示之關係的陳述。此空間上相關的措辭意欲包含使用中的裝置或操作除圖式描繪之方向外的不同方向。儀器可以其他方向定位(旋轉90度或其他定位方向)，且在此使用的空間相關描述符號可同樣依此解讀。此外，措辭「由……製成」可具有「包括」或「由……構成」的涵義。
第1到19圖顯示製造具有鰭式結構的半導體場效電晶體(fin field effect transistor，FinFET)裝置範例的製程。可理解的是，在第1到18圖的操作之前、中、後可提供額外的操作，且一些以下敘述的操作可為了方法的其他實施例被取代或刪除，操作的順序可互相交換。
如第1圖所示，植入雜質離子(摻質)於矽基底10內，以形成井區15，實施此離子植入以防止衝穿效應(punch-through effect)。
舉例而言，基底10為雜質濃度在約1.12x1015cm-3到約1.68x1015cm-3範圍內的P型矽基底。在其他實施例中，基底10為雜質濃度在約0.905x1015cm-3到約2.34x1015cm-3範圍內的N型矽基底。在一些實施例中，基底10為矽基底且有(100)的 上表面。
或者，基底10可包括另一元素半導體，例如鍺(Ge)；或包括化合物半導體，包含IV-IV族化合物半導體，例如SiC和SiGe，III-V族化合物半導體，例如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或前述之組合。在一實施例中，基底10為矽於絕緣體上(silicon-on insulator，SOI)的矽層基底。當使用SOI基底時，鰭式結構可從SOI基底的矽層或絕緣層突出，後者的情形中，SOI基底的矽層係用於形成鰭式結構。非晶形的基底，例如非晶形Si或非晶形SiC，或者絕緣材料，例如氧化矽，也可用作基底10。基底10可包含已適當摻入雜質(例如P型或N型的導電性)的各種區域。
舉例而言，對於N型FinFET摻雜物用硼(例如BF2)，對於P型FinFET摻雜物用磷。
如第2圖所示，磊晶地成長第一磊晶層20於基底10的表面上，且磊晶地成長第二磊晶層30於第一磊晶層20上。再者，形成遮罩層100於第二磊晶層30上。
舉例而言，第一磊晶層20可為鍺(Ge)或Si(1-x)Gex，其中x在約0.1到約0.9的範圍內。在此實施例中，Si(1-x)Gex係用作第一磊晶層20。在本揭示中，Si(1-x)Gex可簡化稱為矽鍺(SiGe)。一些實施例中，第一磊晶層20為矽鍺，且厚度在約10奈米到約100奈米的範圍內。在某些實施例中，第一磊晶層20為矽鍺，且厚度在約1奈米到約20奈米的範圍內，或一些其他的實施例中，在約2奈米到約10奈米的範圍內。
舉例而言，第二磊晶層30可為矽(Si)或Si(1-y)Gey，其中y小於x。在此實施例中第二磊晶層30為矽。一些實施例中，第二磊晶層30為矽，且厚度在約20奈米到約70奈米的範圍內。在某些實施例中，第二磊晶層30為矽，且厚度在約30奈米到約50奈米的範圍內。
舉例而言，一些實施例中，遮罩層100可包含氧化物墊層(例如氧化矽)和氮化矽(SiN)遮罩層。一些實施例中，氧化物墊層的厚度在約2奈米到約15奈米的範圍內，且氮化矽遮罩層的厚度在約10奈米到約50奈米的範圍內。在此實施例中，遮罩層為氮化矽。
藉由圖案化的操作，將遮罩層100圖案化為遮罩圖案105。一些實施例中，每一個遮罩圖案105的寬度在約5奈米到約40奈米的範圍內，或其他實施例中，在約10奈米到約30奈米的範圍內。
如第3圖所示，使用遮罩圖案105為蝕刻遮罩，藉由乾式蝕刻法及/或溼式蝕刻法蝕刻出溝槽，將矽的第二磊晶層30、矽鍺的第一磊晶層20和矽的基底10圖案化為鰭式結構40。
如第3圖所示，三個鰭式結構40係設置為與彼此相鄰。然而，鰭式結構40的數量並未限制為三，數量可為一、二、四、五或更多。此外，一或多個虛設鰭式結構可設置在相鄰於鰭式結構40的兩面，以在圖案化製程中改善圖案的精確度(fidelity)。一些實施例中，鰭式結構40的寬度在約5奈米到約40奈米的範圍內，某些實施例中，可在約7奈米到約15奈米的 範圍內。一些實施例中，鰭式結構40的高度在約100奈米到約300奈米的範圍內，其他實施例中，可在約50奈米到約100奈米的範圍內。一些實施例中，鰭式結構40之間的間隔(space)在約5奈米到約80奈米的範圍內，其他實施例中，可在約7奈米到15奈米的範圍內。然而，在本發明所屬技術領域中具有通常知識者將理解本揭示所有提及之尺寸和數值僅為範例，可因應不同積體電路的尺寸等級而改變。
如第4圖所示，將鰭式結構40內矽鍺的第一磊晶層20氧化，以形成矽鍺的氧化物層25。因為矽鍺(特別是鍺)較矽氧化快，可選擇性地形成矽鍺的氧化物層25。然而，也可將矽的第二磊晶層30之側壁和矽的基底10之側壁輕微氧化以形成氧化矽。藉由在含氧氣(O2)和氫氣(H2)或水蒸氣(H2O)的氣體中退火或加熱，可使矽鍺層氧化。此實施例中，在約大氣壓下於約400℃到約600℃的溫度範圍內實施使用水蒸氣的溼式氧化。一些實施例中，矽鍺的氧化物層25厚度在約5奈米到約25奈米的範圍內，或其他實施例中，在約10奈米到約20奈米的範圍內。若第一磊晶層20為鍺，氧化物層25為氧化鍺。
如第5圖所示，舉例而言，藉由溼式蝕刻移除一部分矽鍺的氧化物層25。溼式蝕刻的蝕刻劑可為稀釋的氫氟酸(HF)。藉由調整蝕刻狀況(例如：蝕刻時間)，移除形成於矽的第二磊晶層30之側壁和矽的基底10之側壁上的氧化矽，也輕微地蝕刻矽鍺的氧化物層25。
接著，形成隔離絕緣層50。隔離絕緣層50包含一或多層由低壓化學氣相沉積(low-pressure chemical vapor deposition，LPCVD)、電漿化學氣相沉積(plasma-CVD)或流動式化學氣相沉積(flowable CVD)形成的絕緣材料，例如氧化矽、氮氧化矽或氮化矽。在流動式化學氣相沉積中，沉積流動式的介電材料，而非氧化矽。流動式的介電材料，一如其名，在沉積時能「流動」以填入高深寬比的間隙或空間。一般而言，添加各種化學物質於含矽的前驅物(precursor)內，以使沉積膜流動。一些實施例中，加入氮氫鍵。流動式介電材料的範例，特別是流動式的氧化矽前驅物，包含矽酸鹽(silicate)、矽氧烷(siloxane)、甲基矽倍半氧烷(methyl silsesquioxane，MSQ)、氫矽倍半氧烷(hydrogen silsesquioxane，HSQ)、MSQ/HSQ之組合、全氫矽氮烷(perhydrosilazane，TCPS)、全氫聚矽氮烷(perhydropolysilazane，PSZ)、四乙氧基矽烷(tetraethoxysilane，TEOS)或矽烷基胺類(silyl-amine)(例如：三甲矽烷基胺(trisilylamine，TSA))。這些流動式的氧化矽材料係形成於多項操作的製程。在沉積流動式的膜之後，將其固化，然後退火以移除不需要的元素，形成氧化矽。當不需要的元素已移除，流動式的膜會收縮且緻密化。一些實施例中，實施多項退火製程，不只一次固化和退火流動式的膜。流動式的膜可摻雜硼及/或磷。一些實施例中，可藉由一或多層旋塗式玻璃(spin-on-glass，SOG)、SiO、SiON、SiOCN及/或摻氟矽玻璃(fluoride-doped silicate glass，FSG)形成隔離絕緣層50。
再者，舉例而言，藉由化學機械研磨(chemical mechanical polishing，CMP)方法或其他平坦化方法，例如回蝕(etch-back)製程，以移除遮罩圖案105和隔離絕緣層50的頂部。 平坦化後的結構如第6圖所示。
形成隔離絕緣層50之後，可實施熱處理製程，例如退火製程，以改善隔離絕緣層50的品質，此熱處理製程可在平坦化操作前或後實施。
如第7圖所示，舉例而言，藉由回蝕製程減少隔離絕緣層50的厚度，以便暴露一部分鰭式結構40。鰭式結構40暴露的部分成為FinFET的通道層42，且嵌入隔離絕緣層50的部分成為FinFET的井層44。回蝕製程可藉由乾式蝕刻或溼式蝕刻實施。藉由調整蝕刻時間，可獲得所需的剩餘隔離絕緣層50之厚度。
如第7圖所示，矽鍺的氧化物層25並未從隔離絕緣層50暴露出，且通道層42的底部嵌入隔離絕緣層50內。然而，一些實施例中，矽鍺的氧化物層25和整個通道層42可從隔離絕緣層50暴露出。
如第8圖所示，閘極結構60形成於鰭式結構40的部分通道層42上。第9圖顯示二個閘極結構60之間沿線X1-X1的部分區域剖面示意圖，閘極介電層115如第9圖所示和閘極電極層114形成於隔離絕緣層50和通道層42上，然後實施圖案化操作以獲得包含閘極電極層114和閘極介電層115的閘極結構60。在此實施例中，閘極電極層114為多晶矽。一些實施例中，藉由使用包含頂層110和底層112的硬遮罩，將多晶矽層圖案化成為閘極電極層114，其中硬遮罩之頂層110為氧化矽，且硬遮罩之底層112為氮化矽。其他實施例中，硬遮罩之頂層110可為氮化矽，且硬遮罩之底層112可為氧化矽。閘極介電層115可為氧化 矽，藉由CVD、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(Atomic layer deposition，ALD)、電子束蒸鍍(e-beam evaporation)或其他合適的製程形成。
在一實施例中，使用後閘極(gate-last)技術(閘極置換技術)。在後閘極技術中，前述操作形成的閘極電極層114和閘極介電層115分別為虛設閘極電極層和虛設閘極介電層，最終被移除。
或者，其他實施例可使用前閘極(gate-first)技術。這種情況下，將閘極電極層114和閘極介電層115用作FinFET的閘極電極層和閘極介電層。一些實施例中，閘極介電層115可包含一或多層氧化矽、氮化矽、氮氧化矽或高介電常數(high-k)之介電材料。高介電常數之介電材料包括金屬氧化物。用作高介電常數之介電材料的金屬氧化物的範例包含Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu這些金屬的氧化物及/或前述之混合物。一些實施例中，閘極介電層115的厚度在約1奈米到約5奈米的範圍內。一些實施例中，閘極介電層115可包含二氧化矽製的界面層。一些實施例中，閘極介電層115可包括單一或多層結構。
再者，閘極電極層114可為均勻或不均勻摻雜的多晶矽。一些其他的實施例中，閘極電極層114可包含金屬，例如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、其他功函數相容於基底材料的導電材料或前述之組合。使用合適的製程，例如ALD、CVD、PVD、電鍍或前述之組合形成閘 極電極層114。一些實施例中，閘極電極層114的寬度在約30奈米到約60奈米的範圍內。
再者，如第8圖所示，側壁絕緣層120係由氧化矽、氮化矽及/或氮氧化矽製成。側壁絕緣層120形成於閘極結構60的主要側壁上和通道層42未被閘極結構60覆蓋的主要側壁上。在此實施例中，側壁絕緣層120的材料為氮化矽。
為了形成側壁絕緣層120，藉由CVD和回蝕操作的實施，形成一層氮化矽於閘極結構60和通道層42的整體結構上。
第9圖顯示沿著第8圖的線X1-X1切入閘極結構60下的一個通道層42的剖面圖。第9到15圖中，閘極結構60的頂部未繪示。雖然，第8圖顯示一個閘極結構60，而第9圖繪示二個閘極結構60。然而，單一鰭式結構的閘極結構數量並未限制於一或二個，數量可為三、四、五或更多。
如第10圖所示，蝕刻未被閘極結構60覆蓋的通道層42部分以形成凹陷部130。直到暴露矽鍺的氧化物層25，凹陷部130才形成。一些實施例中，藉由在3到20mTorr的氣壓下使用包含CH4、CF4、CH2F2、CHF3、O2、HBr、Cl2、NF3、N2及/或He氣體的電漿蝕刻，對通道層42實施凹陷蝕刻，此凹陷蝕刻為非等向性的蝕刻。
如第11圖所示，部分矽鍺的氧化物層25的蝕刻係藉由例如使用CF4及/或CH2F2氣體的乾式蝕刻及/或溼式蝕刻進行，此蝕刻為等向性的蝕刻。在蝕刻矽鍺的氧化物層25的期間，部分矽的通道層42也被蝕刻。
如第12圖所示，藉由例如使用CF4及/或CH2F2氣體的乾式蝕刻及/或溼式蝕刻，對矽鍺的氧化物層25實施額外的蝕刻，使井層44之表面暴露。
如第13圖所示，形成半導體磊晶層140於凹陷部130內的通道層42和井層44上。半導體磊晶層140與通道層42的材料相同。在此實施例中，通道層42和半導體磊晶層140係由矽製成。當基底10為(100)面之矽，井層44的上表面也為(100)面，且形成於井層42上的半導體磊晶層140的上表面也為(100)面。一些實施例中，半導體磊晶層140的厚度在約3奈米到約20奈米的範圍內，且在其他實施例中，可在約5奈米到約10奈米的範圍內。
形成半導體磊晶層140後，將凹陷部130的底部區域145改質，使得改質的底部區域145對鹼性溶液(例如氫氧化四甲銨(tetramethylammonium，TMAH)或氫氧化鉀(KOH))的蝕刻選擇性較未改質的矽層增加。一些實施例中，改質的底部區域145大抵上未被鹼性溶液蝕刻。舉例而言，當矽層高度摻雜P型摻雜物時，P++矽層被鹼性溶液蝕刻的蝕刻速率會降低。
如第14圖所示，對凹陷部130底部的半導體磊晶層140，離子植入P型雜質150。一些實施例中，此P型雜質為硼或BF2。藉由硼的植入，凹陷部130的底部成為改質的底部區域145。
一些實施例中，硼植入的劑量在約1x1015離子/cm2到約1x1016離子/cm2的範圍內，且其他實施例中，可在2x1015離子/cm2到約5x1016離子/cm2的範圍內。值得注意的是，約 1x1015離子/cm2到約1x1016離子/cm2的劑量範圍係對應約0.5x1020原子/cm3到約0.5x1021原子/cm3的植入層範圍。一些實施例中，加速能量在約100keV到約200keV的範圍內，且可為約120keV到約150keV的範圍。離子植入之後，實施退火於約1000℃到約1200℃的溫度範圍內，以驅使雜質進入，且再結晶被植入的矽區域。藉由高度植入硼於(100)面矽層內，對於TMAH的耐蝕刻性成為井層44及/或通道層42(未改質的矽層)對於TMAH耐蝕刻性的一點到些許倍。一些實施例中，改質的底部區域145之深度在約3奈米到約20奈米的範圍，且其他實施例中，可在約5奈米到約10奈米的範圍內。
如第15圖所示，以鹼性溶液(例如TMAH)對矽的半導體磊晶層140和通道層42實施溼式蝕刻。因為底部區域145係植入硼，底部區域145並未如矽的半導體磊晶層140側邊區域般蝕刻得多。藉由TMAH溼式蝕刻，橫向蝕刻矽的半導體磊晶層140側邊區域和通道層42，且顯露對應(111)面的表面。
若未將底部區域改質，藉由TMAH的蝕刻將進行至垂直方向，並且也會蝕刻部分的井層44。相較之下，若將底部區域改質，可能防止對井層44不必要的垂直蝕刻，同時精確地控制對矽的半導體磊晶層140和通道層42的橫向蝕刻。舉例而言，一些實施例中，通道層42橫向蝕刻停止的表面可能位於側壁絕緣層120下，且可能位於閘極電極層114下。
在某些實施例中，通道層42可由Ge或Si(1-x)Gex製成，其中x在約0.1到約0.9的範圍內，在此情況中，半導體磊晶層140包含Ge或Si(1-x)Gex。
如第16和17圖所示，在蝕刻矽的半導體磊晶層140和通道層42至所需的量之後，形成應力源層160於凹陷部130內。一些實施例中，應力源層160包含單層或多層，其中對於P型FET包含矽鍺，對於N型FET包含SiP、SiC或SiCP。應變材料係磊晶地形成於凹陷部內。應力源層160成為源極和汲極的一部分。第16圖顯示在應力源層160形成後，半導體FET裝置的範例示意圖。
如第18圖所示，形成應力源層160(源極/汲極)後，形成層間介電層170於第16和17圖的結構上。移除多晶矽的閘極電極層114以形成閘極電極空位175。層間介電層170的絕緣材料可包含一或多層氧化矽、氮化矽、氮氧化矽(SiON)、SiOCN、摻氟矽玻璃(FSG)或低介電常數之介電材料。層間介電層170係由CVD形成。
如第19圖所示，形成金屬閘極結構180於閘極電極空位175內。金屬閘極結構180包含金屬閘極電極層和閘極介電層。金屬閘極電極層可包含單層或多層結構。在本實施例中，金屬閘極電極層包含金屬，例如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、其他功函數相容於基底材料的導電材料或前述之組合。金屬閘極電極層可使用合適的製程形成，例如ALD、CVD、PVD、電鍍或前述之組合。一些實施例中，金屬閘極電極層的寬度在約30奈米到約60奈米的範圍內。一些實施例中，閘極介電層可包含氮化矽、氮氧化矽或高介電常數之介電材料。高介電常數之介電材料包括金屬氧化物。用於高介電常數之介電材料的金屬氧化物之範例包含Li、 Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu這些金屬的氧化物及/或前述之混合物。一些實施例中，閘極介電層的厚度在約1奈米到約5奈米的範圍內。
可以理解的是，FinFET裝置可經過更多的CMOS製程以形成各種特徵部件，例如接觸(contacts)/導孔(vias)、互連金屬層、介電層、鈍化(passivation)層等。
在此陳述的各種實施例或範例提供與現存技術相比的一些優勢。在本揭示的一些實施例中，藉由雜質植入(例如硼)，將凹陷部底部的矽磊晶區域改質。藉由此改質的底部區域，可防止對井層之不必要的垂直蝕刻，同時也精確地控制對凹陷部內矽磊晶層和通道層的橫向蝕刻。
將理解的是，在此並未討論到所有的優勢，並非所有的實施例和範例都需要特別的優勢，且其他實施例或範例可能提供不同的優勢。
以上概述數個實施例為特徵，以便在本發明所屬技術領域中具有通常知識者可以更理解本揭示的觀點。在發明所屬技術領域中具有通常知識者應該理解他們能以本揭示為基礎，設計或修改其他製程和結構以達到與在此介紹的實施例相同之目的及/或優勢。在發明所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並無悖離本揭示的精神與範圍，且他們能在不違背本揭示之精神和範圍之下，做各式各樣的改變、取代和替換。
145‧‧‧改質的底部區域
160‧‧‧應力源層
170‧‧‧層間介電層
180‧‧‧金屬閘極結構

Claims (8)

  1. 一種半導體裝置的製造方法，包括：形成一鰭式結構，包含一井層、一該井層上之氧化物層和一該氧化物層上之通道層；形成一隔離絕緣層，使得該鰭式結構之該通道層從該隔離絕緣層突出，且至少一部分或整體的該氧化物層嵌入該隔離絕緣層內；在一部分該鰭式結構上和該隔離絕緣層上形成一閘極結構；藉由蝕刻該鰭式結構未被該閘極結構覆蓋之一部分，形成一凹陷部，以移除該氧化物層和暴露出該井層之一表面；在該暴露的井層上和該凹陷部內的該通道層上形成一磊晶層；以及將形成在該暴露的井層上的該磊晶層改質為一改質層，使得該改質層對一鹼性溶液的蝕刻選擇性較一未改質的磊晶層增加，其中藉由植入一P型雜質實施該磊晶層的改質，該P型雜質為硼，且硼的劑量在1x1015離子/cm2到1x1016離子/cm2的範圍內。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該氧化物層包含矽鍺氧化物。
  3. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該井層和該通道層由矽或矽化合物製成。
  4. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該鹼性溶液為氫氧化四甲銨(tetramethylammonium，TMAH) 或氫氧化鉀(KOH)，且使用氫氧化四甲銨或氫氧化鉀實施該磊晶層的蝕刻。
  5. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包括：蝕刻該通道層上的該磊晶層和該通道層；以及在該改質層和該蝕刻的通道層上形成一應力源層。
  6. 一種半導體裝置的製造方法，包括：在一基底上形成一鰭式結構，該鰭式結構包含一井層、該井層上之一氧化物層和該氧化物層上之一通道層；形成一隔離絕緣層，使得該鰭式結構之該通道層從該隔離絕緣層突出，且至少一部分或整體的該氧化物層嵌入該隔離絕緣層內；在一部分該鰭式結構上和該隔離絕緣層上形成一第一閘極結構和一第二閘極結構；藉由蝕刻該鰭式結構在該第一閘極結構和該第二閘極結構之間的一部分，形成一凹陷部，以移除該氧化物層和暴露出該井層在該第一閘極結構和該第二閘極結構之間的一表面；在該暴露的井層上和該凹陷部內的該通道層上形成一磊晶層；以及將形成在該暴露的井層上的該磊晶層改質為一改質層，使得該改質層對一鹼性溶液的蝕刻選擇性較一未改質的磊晶層增加，其中藉由植入硼實施該磊晶層的改質，且硼的劑量在1x1015離子/cm2到1x1016離子/cm2的範圍內。
  7. 一種半導體裝置，包括：一鰭式場效電晶體裝置，包含：一鰭式結構，沿著一第一方向延伸，且從一隔離絕緣層突出，該鰭式結構和該隔離絕緣層設置於一基底上，該鰭式結構包含一井層、該井層上之一氧化物層和該氧化物層上之一通道層；一閘極堆疊，包含一閘極電極層和一閘極介電層，覆蓋一部分該鰭式結構，且沿著垂直於該第一方向的一第二方向延伸；一源極和一汲極，各自包含在該鰭式結構內形成的一凹陷部內和上的一應力源層，該應力源層施加一應力於該閘極堆疊下的該鰭式結構之一通道層；以及一改質層，在該井層和該應力源層之間，其中該改質層對一鹼性溶液的蝕刻選擇性較該井層和該通道層之至少一者高，且該改質層為摻雜硼的量從0.5x1020原子/cm3到0.5x1021原子/cm3的矽。
  8. 如申請專利範圍第7項所述之半導體裝置，其中該鰭式結構設置在該基底的(100)面上。
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