TWI587262B - Gate driving circuit and operating method thereof - Google Patents
Gate driving circuit and operating method thereof Download PDFInfo
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- TWI587262B TWI587262B TW104139026A TW104139026A TWI587262B TW I587262 B TWI587262 B TW I587262B TW 104139026 A TW104139026 A TW 104139026A TW 104139026 A TW104139026 A TW 104139026A TW I587262 B TWI587262 B TW I587262B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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Description
本發明係與液晶顯示面板之驅動電路有關，特別是關於一種應用於液晶顯示面板之閘極驅動電路及其運作方法。 The invention relates to a driving circuit of a liquid crystal display panel, in particular to a gate driving circuit applied to a liquid crystal display panel and a method for operating the same.
一般而言，由於液晶顯示面板上的電晶體開關會有寄生電容且液晶顯示面板上每個像素(Pixel)的儲存電容值亦不盡相同，導致閘極驅動電路輸出至液晶顯示面板上的閘極線(Gate Lines)之閘極輸出電壓訊號在由較高的第一閘極驅動電壓(VGH)轉為較低的第二閘極驅動電壓(VGL)時會對儲存電容所要儲存的電壓有一耦合效應，即使對共同電壓(VCOM)進行調整後，液晶顯示面板所顯示之畫面仍會有閃爍(Flicker)之現象發生。 In general, since the transistor switch on the liquid crystal display panel has parasitic capacitance and the storage capacitor value of each pixel (Pixel) on the liquid crystal display panel is also different, the gate driving circuit outputs a gate to the liquid crystal display panel. The gate output voltage signal of the Gate Lines has a voltage to be stored in the storage capacitor when the higher first gate drive voltage (VGH) is converted to the lower second gate drive voltage (VGL). The coupling effect, even if the common voltage (VCOM) is adjusted, the screen displayed on the LCD panel will still have a flicker phenomenon.
為了改善上述的畫面閃爍現象，通常會透過對閘極驅動電路之閘極輸出電壓訊號之波形進行削角(Gate Pulse Shading)的方式來進行。請參照圖1至圖3，圖1係繪示先前技術之閘極驅動電路的示意圖；圖2係繪示圖1中之控制訊號S1~S3的時序圖；圖3係繪示開始進行波形削角時受到閘極驅動電路之外部寄生電容之影響而出現之電壓急降現象的示意圖。 In order to improve the above-described flickering phenomenon, it is usually performed by performing a Gate Pulse Shading on the waveform of the gate output voltage signal of the gate driving circuit. 1 to FIG. 3, FIG. 1 is a schematic diagram of a gate driving circuit of the prior art; FIG. 2 is a timing diagram of the control signals S1 to S3 of FIG. 1; FIG. 3 is a schematic diagram of starting a waveform cutting. Schematic diagram of the voltage drop phenomenon caused by the external parasitic capacitance of the gate drive circuit at the corner.
如圖1所示，於傳統的閘極驅動電路1中，偏壓接腳PB分別 耦接外部電阻RE及外部電容CP，當閘極驅動電路1尚未對閘極輸出電壓訊號進行削角(圖2中之T1期間)時，外部電容CP上的電荷為零；當閘極驅動電路1開始對閘極輸出電壓訊號進行削角(圖2中之T2期間)時，外部電容CP上的電荷會先與閘極驅動電路1的內部電容CG上的電荷以及閘極驅動電路1的外部負荷電容CLOAD上的電荷彼此中和，並使得偏壓接腳PB的電壓VBIAS與第一接點N1的電壓VGHP達到一穩態點，這將導致當時間進入T2時，閘極輸出電壓訊號會因為前述的電荷中和現象而先快速下降，當偏壓接腳PB的電壓VBIAS與第一接點N1的電壓VGHP達到穩態點後才會出現削角的波形。此一電壓急降現象在外部電容CP愈大的情況下愈為明顯，亦即閘極輸出電壓訊號的削角波形會受到閘極驅動電路之外部寄生電容之大小的影響而改變，亟待克服。 As shown in FIG. 1, in the conventional gate driving circuit 1, the bias pins PB are respectively The external resistor RE and the external capacitor CP are coupled. When the gate driving circuit 1 has not chamfered the gate output voltage signal (during T1 in FIG. 2), the charge on the external capacitor CP is zero; when the gate driving circuit 1 When the gate output voltage signal is chamfered (during T2 in FIG. 2), the charge on the external capacitor CP is first charged with the charge on the internal capacitance CG of the gate drive circuit 1 and the outside of the gate drive circuit 1. The charges on the load capacitor CLOAD are neutralized with each other, and the voltage VBIAS of the bias pin PB and the voltage VGHP of the first contact N1 reach a steady state point, which causes the gate output voltage signal to be generated when the time enters T2. Because of the aforementioned charge neutralization phenomenon, the waveform of chamfering occurs only when the voltage VBIAS of the bias pin PB and the voltage VGHP of the first contact N1 reach a steady state point. This voltage drop phenomenon becomes more and more obvious when the external capacitance CP is larger, that is, the chamfering waveform of the gate output voltage signal is changed by the magnitude of the external parasitic capacitance of the gate driving circuit, which needs to be overcome.
因此，本發明提出一種閘極驅動電路及其運作方法，以解決先前技術所遭遇到之上述問題。 Accordingly, the present invention provides a gate drive circuit and a method of operating the same to solve the above problems encountered in the prior art.
根據本發明之一較佳具體實施例為一種閘極驅動電路。於此實施例中，閘極驅動電路應用於液晶顯示面板。閘極驅動電路包含偏壓接腳、第一電晶體、第二電晶體、第三電晶體、第四電晶體及第五電晶體。偏壓接腳分別耦接外部電阻及外部電容。第一電晶體耦接於第一閘極驅動電壓與第一接點之間，其中第一接點耦接閘極驅動電路之輸出端。第二電晶體分別耦接第二接點與第三接點，其中第二接點耦接第一接點且第三接點耦接偏壓接腳。第三電晶體相對於第二電晶體設置並分別耦接第二接點與第三接點。第四電晶體相對於第二電晶體設置並亦分 別耦接第二接點與第三接點。第五電晶體相對於第二電晶體設置並亦分別耦接第二接點與第三接點。第一電晶體、第三電晶體、第四電晶體及第五電晶體均為P型電晶體且第二電晶體為N型電晶體；第三電晶體、第四電晶體及第五電晶體彼此並聯；於閘極驅動電路之預充電期間內，第一電晶體係維持於開啟狀態下且第二電晶體係維持於關閉狀態下，第三電晶體、第四電晶體及第五電晶體係依序分別由關閉狀態轉變為開啟狀態。 A preferred embodiment of the invention is a gate drive circuit. In this embodiment, the gate driving circuit is applied to a liquid crystal display panel. The gate driving circuit includes a bias pin, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The bias pins are respectively coupled to an external resistor and an external capacitor. The first transistor is coupled between the first gate driving voltage and the first contact, wherein the first contact is coupled to the output of the gate driving circuit. The second transistor is coupled to the second contact and the third contact, wherein the second contact is coupled to the first contact and the third contact is coupled to the bias pin. The third transistor is disposed relative to the second transistor and coupled to the second contact and the third contact, respectively. The fourth transistor is disposed relative to the second transistor and is also divided Do not couple the second contact and the third contact. The fifth transistor is disposed relative to the second transistor and is also coupled to the second contact and the third contact, respectively. The first transistor, the third transistor, the fourth transistor, and the fifth transistor are all P-type transistors and the second transistor is an N-type transistor; the third transistor, the fourth transistor, and the fifth transistor Parallel to each other; during the pre-charging period of the gate driving circuit, the first electro-crystalline system is maintained in an on state and the second electro-crystalline system is maintained in a closed state, the third transistor, the fourth transistor, and the fifth transistor The system is sequentially changed from a closed state to an open state.
於一實施例中，當閘極驅動電路結束預充電期間並進入波形削角期間內，第一電晶體由開啟狀態轉變為關閉狀態且第二電晶體由關閉狀態轉變為開啟狀態，第三電晶體、第四電晶體及第五電晶體均維持於開啟狀態下。 In an embodiment, when the gate driving circuit ends the precharge period and enters the waveform chamfering period, the first transistor changes from the on state to the off state and the second transistor changes from the off state to the on state, the third The crystal, the fourth transistor, and the fifth transistor are all maintained in an open state.
於一實施例中，當閘極驅動電路進入預充電期間之前，閘極驅動電路係正常運作且第一電晶體係維持於開啟狀態下，第二電晶體、第三電晶體、第四電晶體及第五電晶體均維持於關閉狀態下。 In one embodiment, before the gate driving circuit enters the precharge period, the gate driving circuit is normally operated and the first transistor system is maintained in an on state, the second transistor, the third transistor, and the fourth transistor. And the fifth transistor is maintained in a closed state.
於一實施例中，當閘極驅動電路結束波形削角期間並進入一非重疊期間內，第一電晶體維持於關閉狀態下，第二電晶體由開啟狀態轉變為關閉狀態，第三電晶體、第四電晶體及第五電晶體均由開啟狀態轉變為關閉狀態。 In one embodiment, when the gate driving circuit ends the waveform chamfering period and enters a non-overlapping period, the first transistor is maintained in the off state, and the second transistor is turned from the on state to the off state, the third transistor The fourth transistor and the fifth transistor are all changed from an on state to a off state.
於一實施例中，當閘極驅動電路結束非重疊期間後，閘極驅動電路係正常運作且第一電晶體由關閉狀態轉變為開啟狀態，第二電晶體、第三電晶體、第四電晶體及第五電晶體均維持於關閉狀態下。 In one embodiment, after the gate driving circuit ends the non-overlapping period, the gate driving circuit operates normally and the first transistor changes from the off state to the on state, the second transistor, the third transistor, and the fourth battery. Both the crystal and the fifth transistor are maintained in a closed state.
於一實施例中，閘極驅動電路進一步包含內部電容，其一 端耦接至第一接點與第二接點之間且其另一端耦接第二閘極驅動電壓，其中第二閘極驅動電壓係低於第一閘極驅動電壓。 In an embodiment, the gate driving circuit further includes an internal capacitor, one of which The terminal is coupled between the first contact and the second contact and the other end of the second gate driving voltage is coupled to the second gate driving voltage, wherein the second gate driving voltage is lower than the first gate driving voltage.
根據本發明之另一較佳具體實施例亦為一種閘極驅動電路。於此實施例中，閘極驅動電路應用於液晶顯示面板。閘極驅動電路包含偏壓接腳、第一電晶體~第四電晶體。偏壓接腳分別耦接外部電阻及外部電容。第一電晶體耦接於第一閘極驅動電壓與第一接點之間，其中第一接點耦接閘極驅動電路之輸出端。第二電晶體分別耦接第二接點與第三接點，其中第二接點耦接第一接點且第三接點耦接偏壓接腳。第三電晶體相對於第二電晶體設置並分別耦接第二接點與第三接點。第四電晶體耦接於第一閘極驅動電壓與偏壓接腳之間。第一電晶體、第三電晶體及第四電晶體均為P型電晶體且第二電晶體為N型電晶體；於閘極驅動電路之預充電期間內，第一電晶體係維持於開啟狀態下且第二電晶體及第三電晶體均維持於關閉狀態下，第四電晶體係由關閉狀態轉變為開啟狀態。 Another preferred embodiment of the present invention is also a gate drive circuit. In this embodiment, the gate driving circuit is applied to a liquid crystal display panel. The gate driving circuit includes a bias pin, a first transistor to a fourth transistor. The bias pins are respectively coupled to an external resistor and an external capacitor. The first transistor is coupled between the first gate driving voltage and the first contact, wherein the first contact is coupled to the output of the gate driving circuit. The second transistor is coupled to the second contact and the third contact, wherein the second contact is coupled to the first contact and the third contact is coupled to the bias pin. The third transistor is disposed relative to the second transistor and coupled to the second contact and the third contact, respectively. The fourth transistor is coupled between the first gate driving voltage and the bias pin. The first transistor, the third transistor and the fourth transistor are all P-type transistors and the second transistor is an N-type transistor; during the pre-charging period of the gate driving circuit, the first electro-crystalline system is maintained on In the state, the second transistor and the third transistor are both maintained in the off state, and the fourth transistor system is changed from the off state to the on state.
根據本發明之另一較佳具體實施例為一種閘極驅動電路運作方法。於此實施例中，閘極驅動電路運作方法用以運作應用於液晶顯示面板之閘極驅動電路。閘極驅動電路包含偏壓接腳、第一電晶體、第二電晶體、第三電晶體、第四電晶體及第五電晶體。偏壓接腳分別耦接外部電阻及外部電容。第一電晶體耦接於第一閘極驅動電壓與第一接點之間。第一接點耦接閘極驅動電路之輸出端，第二電晶體分別耦接第二接點與第三接點，第二接點耦接第一接點且第三接點耦接偏壓接腳，第一電晶體、第三電晶體、第四電晶體及第五電晶體均為P型電晶體且第二 電晶體為N型電晶體。閘極驅動電路運作方法包含下列步驟：將第三電晶體、第四電晶體及第五電晶體彼此並聯且均相對於第二電晶體設置並分別耦接第二接點與第三接點；以及於閘極驅動電路之預充電期間內，維持第一電晶體於開啟狀態下且維持第二電晶體於關閉狀態下，並將第三電晶體、第四電晶體及第五電晶體依序分別由關閉狀態轉變為開啟狀態。 Another preferred embodiment of the present invention is a method of operating a gate drive circuit. In this embodiment, the gate driving circuit operates to operate the gate driving circuit applied to the liquid crystal display panel. The gate driving circuit includes a bias pin, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The bias pins are respectively coupled to an external resistor and an external capacitor. The first transistor is coupled between the first gate driving voltage and the first contact. The first contact is coupled to the output end of the gate driving circuit, the second transistor is coupled to the second contact and the third contact, the second contact is coupled to the first contact, and the third contact is coupled to the bias a pin, the first transistor, the third transistor, the fourth transistor, and the fifth transistor are both P-type transistors and second The transistor is an N-type transistor. The operation method of the gate driving circuit includes the following steps: connecting the third transistor, the fourth transistor, and the fifth transistor to each other in parallel and both disposed opposite to the second transistor and respectively coupled to the second contact and the third contact; And maintaining the first transistor in an on state and maintaining the second transistor in a closed state during the precharge period of the gate driving circuit, and sequentially ordering the third transistor, the fourth transistor, and the fifth transistor Change from off state to on state respectively.
根據本發明之另一較佳具體實施例亦為一種閘極驅動電路運作方法。於此實施例中，閘極驅動電路運作方法用以運作應用於液晶顯示面板之閘極驅動電路。閘極驅動電路包含偏壓接腳、第一電晶體、第二電晶體、第三電晶體及第四電晶體。偏壓接腳分別耦接外部電阻及外部電容。第一電晶體耦接於第一閘極驅動電壓與第一接點之間。第一接點耦接閘極驅動電路之輸出端。第二電晶體分別耦接第二接點與第三接點。第二接點耦接第一接點且第三接點耦接偏壓接腳。第一電晶體、第三電晶體及第四電晶體均為P型電晶體且第二電晶體為N型電晶體。閘極驅動電路運作方法包含下列步驟：將第三電晶體相對於第二電晶體設置並分別耦接第二接點與第三接點；將第四電晶體耦接於第一閘極驅動電壓與偏壓接腳之間；以及於閘極驅動電路之預充電期間內，維持第一電晶體於開啟狀態下且分別維持第二電晶體及第三電晶體於關閉狀態下，並將第四電晶體由關閉狀態轉變為開啟狀態。 Another preferred embodiment of the present invention is also a method of operating a gate driving circuit. In this embodiment, the gate driving circuit operates to operate the gate driving circuit applied to the liquid crystal display panel. The gate driving circuit includes a bias pin, a first transistor, a second transistor, a third transistor, and a fourth transistor. The bias pins are respectively coupled to an external resistor and an external capacitor. The first transistor is coupled between the first gate driving voltage and the first contact. The first contact is coupled to the output end of the gate drive circuit. The second transistor is coupled to the second contact and the third contact, respectively. The second contact is coupled to the first contact and the third contact is coupled to the bias pin. The first transistor, the third transistor, and the fourth transistor are all P-type transistors and the second transistor is an N-type transistor. The operation method of the gate driving circuit includes the following steps: the third transistor is disposed relative to the second transistor and coupled to the second contact and the third contact respectively; and the fourth transistor is coupled to the first gate driving voltage And the biasing pin; and during the pre-charging period of the gate driving circuit, maintaining the first transistor in an on state and respectively maintaining the second transistor and the third transistor in a closed state, and fourth The transistor changes from a closed state to an open state.
相較於先前技術，根據本發明之閘極驅動電路及其運作方法能夠有效避免先前技術中進行閘極輸出電壓訊號之波形削角時所產生之電壓急降(Voltage Drop)現象，使得根據本發明之閘極驅動電路及其運 作方法所得到之削角波形不會受到閘極驅動電路之外部寄生電容之大小的影響而改變。 Compared with the prior art, the gate driving circuit and the operating method thereof according to the present invention can effectively avoid the voltage drop phenomenon generated when the waveform of the gate output voltage signal is chamfered in the prior art, so that Invented gate drive circuit and its operation The chamfering waveform obtained by the method is not affected by the magnitude of the external parasitic capacitance of the gate driving circuit.
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。 The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.
S10~S19、S20~S29‧‧‧步驟 S10~S19, S20~S29‧‧‧ steps
1、4、7‧‧‧閘極驅動電路 1, 4, 7‧‧ ‧ gate drive circuit
M1~M7‧‧‧第一電晶體~第七電晶體 M1~M7‧‧‧first transistor~seventh transistor
S1~S5‧‧‧第一控制訊號~第五控制訊號 S1~S5‧‧‧First Control Signal~5th Control Signal
N1~N3‧‧‧第一接點~第三接點 N1~N3‧‧‧first contact~third contact
T0、T4‧‧‧正常運作期間 T0, T4‧‧‧ during normal operation
T1‧‧‧預充電期間 T1‧‧‧Precharge period
T2‧‧‧波形削角期間 T2‧‧‧ waveform chamfering period
T3‧‧‧非重疊期間 T3‧‧‧ non-overlapping period
VGH‧‧‧第一閘極驅動電壓 VGH‧‧‧first gate drive voltage
VGL‧‧‧第二閘極驅動電壓 VGL‧‧‧second gate drive voltage
VSS‧‧‧公共接地端電壓 VSS‧‧‧Common ground terminal voltage
VGHP‧‧‧第一接點的電壓 VGHP‧‧‧ voltage of the first contact
VBIAS‧‧‧偏壓接腳的電壓 VBIAS‧‧‧ voltage of the bias pin
PB‧‧‧偏壓接腳 PB‧‧‧ bias pin
RE‧‧‧外部電阻 RE‧‧‧External resistance
CP‧‧‧外部電容 CP‧‧‧External capacitance
CG‧‧‧內部電容 CG‧‧‧Internal capacitance
RLOAD‧‧‧負荷電阻 RLOAD‧‧‧ load resistor
CLOAD‧‧‧負荷電容 CLOAD‧‧‧ load capacitance
OUTPUT‧‧‧輸出端 OUTPUT‧‧‧ output
△V‧‧‧電壓下降量 △V‧‧‧voltage drop
圖1係繪示先前技術之閘極驅動電路的示意圖。 1 is a schematic diagram showing a gate drive circuit of the prior art.
圖2係繪示圖1中之控制訊號S1~S3的時序圖。 FIG. 2 is a timing diagram of the control signals S1 S S3 in FIG. 1 .
圖3係繪示開始進行波形削角時受到閘極驅動電路之外部寄生電容之影響而出現之電壓急降現象的示意圖。 FIG. 3 is a schematic diagram showing a voltage drop phenomenon which is caused by the external parasitic capacitance of the gate driving circuit when the waveform is chamfered.
圖4係繪示根據本發明之一較佳具體實施例的閘極驅動電路的示意圖。 4 is a schematic diagram of a gate driving circuit in accordance with a preferred embodiment of the present invention.
圖5係繪示圖4中之控制訊號S1~S5的時序圖。 FIG. 5 is a timing diagram of the control signals S1 S S5 in FIG. 4 .
圖6係繪示削角波形不會受到閘極驅動電路之外部寄生電容之影響而改變的示意圖。 FIG. 6 is a schematic diagram showing that the chamfered waveform is not affected by the external parasitic capacitance of the gate driving circuit.
圖7繪示根據本發明之另一較佳具體實施例的閘極驅動電路的示意圖。 FIG. 7 is a schematic diagram of a gate driving circuit according to another preferred embodiment of the present invention.
圖8係繪示圖7中之控制訊號S1~S4的時序圖。 FIG. 8 is a timing diagram of the control signals S1 to S4 in FIG. 7.
圖9係繪示削角波形不會受到閘極驅動電路之外部寄生電容之影響而改變的示意圖。 FIG. 9 is a schematic diagram showing that the chamfered waveform is not changed by the external parasitic capacitance of the gate driving circuit.
圖10繪示根據本發明之另一較佳具體實施例的閘極驅動電路運作方法的示意圖。 FIG. 10 is a schematic diagram showing a method of operating a gate driving circuit according to another preferred embodiment of the present invention.
圖11繪示根據本發明之另一較佳具體實施例的閘極驅動電 路運作方法的示意圖。 FIG. 11 illustrates a gate driving power according to another preferred embodiment of the present invention. Schematic diagram of the way the road works.
根據本發明之一較佳具體實施例為一種閘極驅動電路。於此實施例中，閘極驅動電路應用於液晶顯示面板，用以產生閘極輸出電壓訊號至液晶顯示面板上的複數條閘極線。 A preferred embodiment of the invention is a gate drive circuit. In this embodiment, the gate driving circuit is applied to the liquid crystal display panel for generating a gate output voltage signal to a plurality of gate lines on the liquid crystal display panel.
請參照圖4，圖4係繪示根據此具體實施例中之閘極驅動電路的示意圖。如圖4所示，閘極驅動電路4包含偏壓接腳PB、第一電晶體M1、第二電晶體M2、第三電晶體M3、第四電晶體M4及第五電晶體M5。 Please refer to FIG. 4. FIG. 4 is a schematic diagram of a gate driving circuit according to this embodiment. As shown in FIG. 4, the gate driving circuit 4 includes a bias pin PB, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5.
偏壓接腳PB分別耦接外部電阻RE及外部電容CP。其中，外部電阻RE係耦接於偏壓接腳PB與公共接地端電壓VSS之間；外部電容CP亦係耦接於偏壓接腳PB與公共接地端電壓VSS之間。實際上，外部電容CP可以是一寄生電容，外部電阻RE可以是一可變電阻，但不以此為限。 The bias pin PB is coupled to the external resistor RE and the external capacitor CP, respectively. The external resistor RE is coupled between the bias pin PB and the common ground terminal voltage VSS; the external capacitor CP is also coupled between the bias pin PB and the common ground terminal voltage VSS. In fact, the external capacitor CP can be a parasitic capacitor, and the external resistor RE can be a variable resistor, but is not limited thereto.
第一電晶體M1耦接於第一閘極驅動電壓VGH與第一接點N1之間，其中第一接點N1耦接閘極驅動電路4之輸出端OUTPUT。第二電晶體M2分別耦接第二接點N2與第三接點N3，其中第二接點N2耦接第一接點N1且第三接點N3耦接偏壓接腳PB。 The first transistor M1 is coupled between the first gate driving voltage VGH and the first contact N1, wherein the first contact N1 is coupled to the output terminal OUTPUT of the gate driving circuit 4. The second transistor M2 is coupled to the second contact N2 and the third contact N3, wherein the second contact N2 is coupled to the first contact N1 and the third contact N3 is coupled to the bias pin PB.
第三電晶體M3、第四電晶體M4及第五電晶體M5彼此並聯，其中第三電晶體M3相對於第二電晶體M2設置並分別耦接第二接點N2與第三接點N3；第四電晶體M4相對於第二電晶體M2設置並亦分別耦接第二接點N2與第三接點N3；第五電晶體M5相對於第二電晶體M2設置並亦分別耦接第二接點N2與第三接點N3。 The third transistor M3, the fourth transistor M4, and the fifth transistor M5 are connected in parallel with each other, wherein the third transistor M3 is disposed relative to the second transistor M2 and coupled to the second contact N2 and the third contact N3, respectively; The fourth transistor M4 is disposed opposite to the second transistor M2 and is also coupled to the second node N2 and the third node N3 respectively; the fifth transistor M5 is disposed opposite to the second transistor M2 and is also coupled to the second transistor Contact N2 and third contact N3.
需說明的是，於此實施例中，第一電晶體M1、第三電晶 體M3、第四電晶體M4及第五電晶體M5均為P型電晶體且第二電晶體M2為N型電晶體，但不以此為限。第一電晶體M1、第二電晶體M2、第三電晶體M3、第四電晶體M4及第五電晶體M5之閘極分別受到第一控制訊號S1、第二控制訊號S2、第三控制訊號S3、第四控制訊號S4及第五控制訊號S5之控制而選擇性處於開啟或關閉之狀態。 It should be noted that, in this embodiment, the first transistor M1 and the third transistor are The body M3, the fourth transistor M4, and the fifth transistor M5 are all P-type transistors, and the second transistor M2 is an N-type transistor, but is not limited thereto. The gates of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are respectively received by the first control signal S1, the second control signal S2, and the third control signal The control of S3, the fourth control signal S4 and the fifth control signal S5 is selectively turned on or off.
實際上，如圖4所示，閘極驅動電路4還包含有內部電容CG。內部電容CG的一端耦接至第一接點N1與第二接點N2之間且內部電容CG的另一端耦接第二閘極驅動電壓VGL，其中第二閘極驅動電壓VGL係低於第一閘極驅動電壓VGH。 Actually, as shown in FIG. 4, the gate driving circuit 4 further includes an internal capacitance CG. One end of the internal capacitor CG is coupled between the first contact N1 and the second contact N2 and the other end of the internal capacitor CG is coupled to the second gate driving voltage VGL, wherein the second gate driving voltage VGL is lower than the first A gate drive voltage VGH.
此外，如圖4所示，閘極驅動電路4還包含有第六電晶體M6及第七電晶體M7，其中第六電晶體M6為P-type電晶體且第七電晶體M7為N-type電晶體。第六電晶體M6及第七電晶體M7係串接於第一接點N1與第二閘極驅動電壓VGL之間，並且第六電晶體M6及第七電晶體M7之閘極係受到第二閘極驅動電壓VGL的控制。閘極驅動電路4的輸出端OUTPUT係位於第六電晶體M6與第七電晶體M7之間，並且輸出端OUTPUT耦接外部的負荷電阻RLOAD。至於外部的負荷電容CLOAD則是耦接於負荷電阻RLOAD與公共接地端電壓VSS之間。 In addition, as shown in FIG. 4, the gate driving circuit 4 further includes a sixth transistor M6 and a seventh transistor M7, wherein the sixth transistor M6 is a P-type transistor and the seventh transistor M7 is an N-type. Transistor. The sixth transistor M6 and the seventh transistor M7 are connected in series between the first contact N1 and the second gate driving voltage VGL, and the gates of the sixth transistor M6 and the seventh transistor M7 are subjected to the second Control of the gate drive voltage VGL. The output terminal OUTPUT of the gate driving circuit 4 is located between the sixth transistor M6 and the seventh transistor M7, and the output terminal OUTPUT is coupled to the external load resistor RLOAD. The external load capacitor CLOAD is coupled between the load resistor RLOAD and the common ground terminal voltage VSS.
接著，請參照圖5，圖5係繪示圖4中之第一控制訊號S1、第二控制訊號S2、第三控制訊號S3、第四控制訊號S4及第五控制訊號S5的時序圖。 Next, please refer to FIG. 5. FIG. 5 is a timing diagram of the first control signal S1, the second control signal S2, the third control signal S3, the fourth control signal S4, and the fifth control signal S5 in FIG.
如圖5所示，於正常運作期間T0內，閘極驅動電路4係正常運作且第一電晶體M1係維持於開啟(ON)狀態下，而第二電晶體M2、第 三電晶體M3、第四電晶體M4及第五電晶體M5均維持於關閉(OFF)狀態下。 As shown in FIG. 5, during the normal operation period T0, the gate driving circuit 4 is normally operated and the first transistor M1 is maintained in an ON state, and the second transistor M2 is The three transistor M3, the fourth transistor M4, and the fifth transistor M5 are both maintained in an OFF state.
當閘極驅動電路4結束正常運作期間T0時隨即進入預充電期間T1。於預充電期間T1內，第一電晶體M1仍維持於開啟(ON)狀態下且第二電晶體M2仍維持於關閉(OFF)狀態下，至於第三電晶體M3、第四電晶體M4及第五電晶體M5則會依序分別由原本的關閉(OFF)狀態轉變為開啟(ON)狀態。 When the gate driving circuit 4 ends the normal operation period T0, it enters the precharge period T1. During the pre-charging period T1, the first transistor M1 is still maintained in the ON state and the second transistor M2 is still maintained in the OFF state, as for the third transistor M3 and the fourth transistor M4. The fifth transistor M5 is sequentially changed from the original OFF state to the ON state.
需特別說明的是，此實施例中之第三電晶體M3、第四電晶體M4及第五電晶體M5並非「同時」由原本的關閉(OFF)狀態轉變為開啟(ON)狀態，而是彼此相隔一時間差「依序」由原本的關閉(OFF)狀態轉變為開啟(ON)狀態，其主要作用在於：當剛進入預充電期間T1時，第三電晶體M3、第四電晶體M4及第五電晶體M5當中只有第三電晶體M3是開啟的，其餘兩個電晶體M4與M5則是關閉的，亦即開啟的P-type電晶體數量較少且阻抗增加產生限流，故能避免先前技術中所有P-type電晶體同時開啟導致閘極驅動電路4的內外電容上之電荷彼此中和所造成的電壓急降(Voltage Drop)現象。 It should be noted that the third transistor M3, the fourth transistor M4, and the fifth transistor M5 in this embodiment are not "simultaneously" changed from the original OFF state to the ON state, but A time difference "in order" from the original OFF state to the ON state, the main function of which is: when entering the precharge period T1, the third transistor M3, the fourth transistor M4 and Among the fifth transistor M5, only the third transistor M3 is turned on, and the other two transistors M4 and M5 are turned off, that is, the number of P-type transistors that are turned on is small and the impedance is increased to generate a current limit. The voltage drop phenomenon caused by the simultaneous opening of all P-type transistors in the prior art causing the charges on the internal and external capacitors of the gate driving circuit 4 to neutralize each other is avoided.
當閘極驅動電路4結束預充電期間T1時隨即進入波形削角期間T2。於波形削角期間T2內，第一電晶體M1會由原本的開啟(ON)狀態轉變為關閉(OFF)狀態且第二電晶體M2會由原本的關閉(OFF)狀態轉變為開啟(ON)狀態，至於第三電晶體M3、第四電晶體M4及第五電晶體M5則都會維持於原本的開啟(ON)狀態下。 When the gate driving circuit 4 ends the precharge period T1, it enters the waveform chamfering period T2. During the waveform chamfering period T2, the first transistor M1 will change from the original ON state to the OFF state and the second transistor M2 will transition from the original OFF state to the ON state. In the state, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are maintained in the original ON state.
當閘極驅動電路4結束波形削角期間T2時隨即進入非重 疊期間T3。於非重疊期間T3內，第一電晶體M1會維持於原本的關閉(OFF)狀態下，第二電晶體M2則會由原本的開啟(ON)狀態轉變為關閉(OFF)狀態，至於第三電晶體M3、第四電晶體M4及第五電晶體M5則都會由原本的開啟(ON)狀態轉變為關閉(OFF)狀態。 When the gate driving circuit 4 ends the waveform chamfering period T2, it enters the non-heavy Stacking period T3. During the non-overlapping period T3, the first transistor M1 is maintained in the original OFF state, and the second transistor M2 is changed from the original ON state to the OFF state. The transistor M3, the fourth transistor M4, and the fifth transistor M5 are all switched from the original ON state to the OFF state.
當閘極驅動電路4結束非重疊期間T3時隨即再次進入正常運作期間T4。於正常運作期間T4內，閘極驅動電路4正常運作且第一電晶體M1會由原本的關閉(OFF)狀態轉變為開啟(ON)狀態，至於第二電晶體M2、第三電晶體M3、第四電晶體M4及第五電晶體M5則都會維持於原本的關閉(OFF)狀態下。其餘可依上述類推，於此不另行贅述。 When the gate driving circuit 4 ends the non-overlapping period T3, it immediately enters the normal operation period T4. During the normal operation period T4, the gate driving circuit 4 operates normally and the first transistor M1 changes from the original OFF state to the ON state. As for the second transistor M2, the third transistor M3, The fourth transistor M4 and the fifth transistor M5 are maintained in the original OFF state. The rest can be analogized by the above, and will not be described here.
需說明的是，如圖6所示，在預充電期間T1內，閘極輸出電壓訊號之電壓等於第一閘極驅動電壓VGH；當預充電期間T1結束並進入波形削角期間T2時，閘極輸出電壓訊號之電壓即會從原本的第一閘極驅動電壓VGH開始隨時間增加而下降；當波形削角期間T2結束並進入非重疊期間T3時，閘極輸出電壓訊號之電壓已下降至(第一閘極驅動電壓VGH-電壓下降量△V)，其中電壓下降量△V小於(第一閘極驅動電壓VGH-第二閘極驅動電壓VGL)。接著，於非重疊期間T3內，閘極輸出電壓訊號之電壓會再由(第一閘極驅動電壓VGH-電壓下降量△V)繼續下降至第二閘極驅動電壓VGL為止。 It should be noted that, as shown in FIG. 6, during the pre-charging period T1, the voltage of the gate output voltage signal is equal to the first gate driving voltage VGH; when the pre-charging period T1 ends and enters the waveform chamfering period T2, the gate The voltage of the pole output voltage signal will decrease with time from the original first gate driving voltage VGH; when the waveform chamfering period T2 ends and enters the non-overlapping period T3, the voltage of the gate output voltage signal has dropped to (First Gate Driving Voltage VGH - Voltage Drop Amount ΔV), wherein the voltage drop amount ΔV is smaller than (first gate driving voltage VGH - second gate driving voltage VGL). Then, in the non-overlapping period T3, the voltage of the gate output voltage signal is further decreased (the first gate driving voltage VGH-voltage falling amount ΔV) to the second gate driving voltage VGL.
接下來，請參照圖7，於本發明之另一較佳具體實施例中，閘極驅動電路7包含偏壓接腳PB、第一電晶體M1、第二電晶體M2、第三電晶體M3及第四電晶體M4。 Next, referring to FIG. 7, in another preferred embodiment of the present invention, the gate driving circuit 7 includes a bias pin PB, a first transistor M1, a second transistor M2, and a third transistor M3. And a fourth transistor M4.
偏壓接腳PB分別耦接外部電阻RE及外部電容CP。其中， 外部電阻RE係耦接於偏壓接腳PB與公共接地端電壓VSS之間；外部電容CP亦係耦接於偏壓接腳PB與公共接地端電壓VSS之間。實際上，外部電容CP可以是一寄生電容，外部電阻RE可以是一可變電阻，但不以此為限。 The bias pin PB is coupled to the external resistor RE and the external capacitor CP, respectively. among them, The external resistor RE is coupled between the bias pin PB and the common ground terminal voltage VSS; the external capacitor CP is also coupled between the bias pin PB and the common ground terminal voltage VSS. In fact, the external capacitor CP can be a parasitic capacitor, and the external resistor RE can be a variable resistor, but is not limited thereto.
第一電晶體M1耦接於第一閘極驅動電壓VGH與第一接點N1之間，其中第一接點N1耦接閘極驅動電路4之輸出端OUTPUT。第二電晶體M2分別耦接第二接點N2與第三接點N3，其中第二接點N2耦接第一接點N1且第三接點N3耦接偏壓接腳PB。 The first transistor M1 is coupled between the first gate driving voltage VGH and the first contact N1, wherein the first contact N1 is coupled to the output terminal OUTPUT of the gate driving circuit 4. The second transistor M2 is coupled to the second contact N2 and the third contact N3, wherein the second contact N2 is coupled to the first contact N1 and the third contact N3 is coupled to the bias pin PB.
需特別說明的是，第三電晶體M3相對於第二電晶體M2設置並分別耦接第二接點N2與第三接點N3。第四電晶體M4耦接於第一閘極驅動電壓VGH與偏壓接腳PB之間。 It should be noted that the third transistor M3 is disposed relative to the second transistor M2 and coupled to the second node N2 and the third node N3, respectively. The fourth transistor M4 is coupled between the first gate driving voltage VGH and the bias pin PB.
於此實施例中，第一電晶體M1、第三電晶體M3及第四電晶體M4均為P型電晶體且第二電晶體M2為N型電晶體，但不以此為限。一第一電晶體M1、第二電晶體M2、第三電晶體M3及第四電晶體M4之閘極分別受到第一控制訊號S1、第二控制訊號S2、第三控制訊號S3及第四控制訊號S4之控制而選擇性處於開啟或關閉之狀態。 In this embodiment, the first transistor M1, the third transistor M3, and the fourth transistor M4 are all P-type transistors, and the second transistor M2 is an N-type transistor, but is not limited thereto. The gates of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are respectively received by the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control The signal S4 is controlled to be selectively turned on or off.
實際上，如圖7所示，閘極驅動電路7還包含有內部電容CG。內部電容CG的一端耦接至第一接點N1與第二接點N2之間且內部電容CG的另一端耦接第二閘極驅動電壓VGL，其中第二閘極驅動電壓VGL係低於第一閘極驅動電壓VGH。 Actually, as shown in FIG. 7, the gate driving circuit 7 further includes an internal capacitance CG. One end of the internal capacitor CG is coupled between the first contact N1 and the second contact N2 and the other end of the internal capacitor CG is coupled to the second gate driving voltage VGL, wherein the second gate driving voltage VGL is lower than the first A gate drive voltage VGH.
此外，如圖7所示，閘極驅動電路7還包含有第五電晶體M5及第六電晶體M6，其中第五電晶體M5為P-type電晶體且第六電晶體M6為N-type電晶體。第五電晶體M5及第六電晶體M6係串接於第一接點 N1與第二閘極驅動電壓VGL之間，並且第五電晶體M5及第六電晶體M6之閘極係受到第二閘極驅動電壓VGL的控制。閘極驅動電路7的輸出端OUTPUT係位於第五電晶體M5與第六電晶體M6之間，並且輸出端OUTPUT耦接外部的負荷電阻RLOAD。至於外部的負荷電容CLOAD則是耦接於負荷電阻RLOAD與公共接地端電壓VSS之間。 In addition, as shown in FIG. 7, the gate driving circuit 7 further includes a fifth transistor M5 and a sixth transistor M6, wherein the fifth transistor M5 is a P-type transistor and the sixth transistor M6 is an N-type. Transistor. The fifth transistor M5 and the sixth transistor M6 are connected in series to the first contact N1 is between the second gate driving voltage VGL, and the gates of the fifth transistor M5 and the sixth transistor M6 are controlled by the second gate driving voltage VGL. The output terminal OUTPUT of the gate driving circuit 7 is located between the fifth transistor M5 and the sixth transistor M6, and the output terminal OUTPUT is coupled to the external load resistor RLOAD. The external load capacitor CLOAD is coupled between the load resistor RLOAD and the common ground terminal voltage VSS.
接著，請參照圖8，圖8係繪示圖7中之第一控制訊號S1、第二控制訊號S2、第三控制訊號S3及第四控制訊號S4的時序圖。 Next, please refer to FIG. 8. FIG. 8 is a timing diagram of the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 in FIG.
如圖8所示，於正常運作期間T0內，閘極驅動電路7係正常運作且第一電晶體M1係維持於開啟(ON)狀態下，而第二電晶體M2、第三電晶體M3及第四電晶體M4均維持於關閉(OFF)狀態下。 As shown in FIG. 8, during the normal operation period T0, the gate driving circuit 7 is normally operated and the first transistor M1 is maintained in an ON state, and the second transistor M2 and the third transistor M3 are The fourth transistor M4 is maintained in the OFF state.
當閘極驅動電路7結束正常運作期間T0時隨即進入預充電期間T1。於預充電期間T1內，第一電晶體M1仍維持於開啟(ON)狀態下且第二電晶體M2及第三電晶體M3都仍維持於關閉(OFF)狀態下，至於第四電晶體M4則會依序分別由原本的關閉(OFF)狀態轉變為開啟(ON)狀態。 When the gate driving circuit 7 ends the normal operation period T0, it enters the precharge period T1. During the pre-charging period T1, the first transistor M1 is still maintained in the ON state and the second transistor M2 and the third transistor M3 are still maintained in the OFF state. As for the fourth transistor M4. It will be changed from the original OFF state to the ON state in sequence.
需特別說明的是，此實施例係透過將耦接於第一閘極驅動電壓VGH與偏壓接腳PB之間的第四電晶體M4由原本的關閉(OFF)狀態轉變為開啟(ON)狀態來對外部電容CP進行預充電，至於第二電晶體M2與第三電晶體M3則都維持於關閉(OFF)狀態下，使得外部電容CP上的電荷不可能與內部電容CG及外部負荷電容CLOAD上的電荷彼此中和，故能有效避免先前技術中之電壓急降現象發生。 It should be particularly noted that this embodiment converts the fourth transistor M4 coupled between the first gate driving voltage VGH and the bias pin PB from the original OFF state to the ON state. The state pre-charges the external capacitor CP, and the second transistor M2 and the third transistor M3 are both maintained in an OFF state, so that the charge on the external capacitor CP cannot be related to the internal capacitor CG and the external load capacitor. The charges on CLOAD are neutralized with each other, so that the voltage drop phenomenon in the prior art can be effectively avoided.
當閘極驅動電路7結束預充電期間T1時隨即進入波形削角期間T2。於波形削角期間T2內，第一電晶體M1及第四電晶體M4均會 由原本的開啟(ON)狀態轉變為關閉(OFF)狀態且第二電晶體M2及第三電晶體M3均會由原本的關閉(OFF)狀態轉變為開啟(ON)狀態。 When the gate driving circuit 7 ends the precharge period T1, it enters the waveform chamfering period T2. During the waveform chamfering period T2, both the first transistor M1 and the fourth transistor M4 will The original ON state is changed to the OFF state and both the second transistor M2 and the third transistor M3 are changed from the original OFF state to the ON state.
當閘極驅動電路7結束波形削角期間T2時隨即進入非重疊期間T3。於非重疊期間T3內，第一電晶體M1及第四電晶體M4均會維持於原本的關閉(OFF)狀態下，第二電晶體M2及第三電晶體M3則會由原本的開啟(ON)狀態轉變為關閉(OFF)狀態。 When the gate driving circuit 7 ends the waveform chamfering period T2, it enters the non-overlapping period T3. During the non-overlapping period T3, the first transistor M1 and the fourth transistor M4 are maintained in the original OFF state, and the second transistor M2 and the third transistor M3 are turned on (ON). The state changes to the OFF state.
當閘極驅動電路7結束非重疊期間T3時隨即再次進入正常運作期間T4。於正常運作期間T4內，閘極驅動電路7正常運作且第一電晶體M1會由原本的關閉(OFF)狀態轉變為開啟(ON)狀態，至於第二電晶體M2、第三電晶體M3及第四電晶體M4則都會維持於原本的關閉(OFF)狀態下。其餘可依上述類推，於此不另行贅述。 When the gate driving circuit 7 ends the non-overlapping period T3, it immediately enters the normal operation period T4. During the normal operation period T4, the gate driving circuit 7 operates normally and the first transistor M1 changes from the original OFF state to the ON state, as for the second transistor M2 and the third transistor M3. The fourth transistor M4 is maintained in the original OFF state. The rest can be analogized by the above, and will not be described here.
需說明的是，如圖9所示，在預充電期間T1內，閘極輸出電壓訊號之電壓等於第一閘極驅動電壓VGH；當預充電期間T1結束並進一入波形削角期間T2時，閘極輸出電壓訊號之電壓即會從原本的第一閘極驅動電壓VGH開始隨時間增加而下降；當波形削角期間T2結束並進入非重疊期間T3時，閘極輸出電壓訊號之電壓已下降至(第一閘極驅動電壓VGH-電壓下降量△V)，其中電壓下降量△V小於(第一閘極驅動電壓VGH-第二閘極驅動電壓VGL)。接著，於非重疊期間T3內，閘極輸出電壓訊號之電壓會再由(第一閘極驅動電壓VGH-電壓下降量△V)繼續下降至第二閘極驅動電壓VGL為止。 It should be noted that, as shown in FIG. 9, during the pre-charging period T1, the voltage of the gate output voltage signal is equal to the first gate driving voltage VGH; when the pre-charging period T1 ends and enters the waveform chamfering period T2, The voltage of the gate output voltage signal will decrease with time from the original first gate driving voltage VGH; when the waveform chamfering period T2 ends and enters the non-overlapping period T3, the voltage of the gate output voltage signal has decreased. To (first gate driving voltage VGH - voltage drop amount ΔV), wherein the voltage drop amount ΔV is smaller than (first gate driving voltage VGH - second gate driving voltage VGL). Then, in the non-overlapping period T3, the voltage of the gate output voltage signal is further decreased (the first gate driving voltage VGH-voltage falling amount ΔV) to the second gate driving voltage VGL.
根據本發明之另一較佳具體實施例為一種閘極驅動電路運作方法。於此實施例中，閘極驅動電路運作方法用以運作應用於液晶顯 示面板之閘極驅動電路。閘極驅動電路包含偏壓接腳、第一電晶體、第二電晶體、第三電晶體、第四電晶體及第五電晶體。其中，第一電晶體、第三電晶體、第四電晶體及第五電晶體均為P型電晶體且第二電晶體為N型電晶體。 Another preferred embodiment of the present invention is a method of operating a gate drive circuit. In this embodiment, the gate driving circuit operation method is applied to the liquid crystal display The gate drive circuit of the display panel. The gate driving circuit includes a bias pin, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor, the third transistor, the fourth transistor, and the fifth transistor are all P-type transistors and the second transistor is an N-type transistor.
偏壓接腳分別耦接外部電阻及外部電容。第一電晶體耦接於第一閘極驅動電壓與第一接點之間。第一接點耦接閘極驅動電路之輸出端。第二電晶體分別耦接第二接點與第三接點。第二接點耦接第一接點且第三接點耦接偏壓接腳。 The bias pins are respectively coupled to an external resistor and an external capacitor. The first transistor is coupled between the first gate driving voltage and the first contact. The first contact is coupled to the output end of the gate drive circuit. The second transistor is coupled to the second contact and the third contact, respectively. The second contact is coupled to the first contact and the third contact is coupled to the bias pin.
此外，閘極驅動電路可進一步包含內部電容。內部電容之一端耦接至第一接點與第二接點之間且其另一端耦接第二閘極驅動電壓，其中第二閘極驅動電壓係低於第一閘極驅動電壓。 Additionally, the gate drive circuit can further include an internal capacitor. One end of the internal capacitor is coupled between the first contact and the second contact and the other end of the second capacitor is coupled to the second gate drive voltage, wherein the second gate drive voltage is lower than the first gate drive voltage.
請參照圖10，圖10繪示根據此實施例中之閘極驅動電路運作方法的示意圖。如圖10所示，閘極驅動電路運作方法包含下列步驟：(S10)該方法將第三電晶體、第四電晶體及第五電晶體彼此並聯且均相對於第二電晶體設置並分別耦接第二接點與第三接點；(S12)於閘極驅動電路之正常運作期間內，閘極驅動電路係正常運作且該方法維持第一電晶體於開啟狀態下，並分別維持第二電晶體、第三電晶體、第四電晶體及第五電晶體於關閉狀態下；(S14)於閘極驅動電路之預充電期間內，該方法維持第一電晶體於開啟狀態下且維持第二電晶體於關閉狀態下，並將第三電晶體、第四電晶體及第五電晶體依序分別由關閉狀態轉變為開啟狀態；(S16)於閘極驅動電路之波形削角期間內，該方法將第一 電晶體由開啟狀態轉變為關閉狀態以及將第二電晶體由關閉狀態轉變為開啟狀態，並分別維持第三電晶體、第四電晶體及第五電晶體於開啟狀態下；(S18)於閘極驅動電路之非重疊期間內，該方法維持第一電晶體於關閉狀態下，並將第二電晶體由開啟狀態轉變為關閉狀態以及分別將第三電晶體、第四電晶體及第五電晶體由開啟狀態轉變為關閉狀態；(S19)當閘極驅動電路結束非重疊期間後，閘極驅動電路再次回到正常運作期間，該方法將第一電晶體由關閉狀態轉變為開啟狀態，並分別維持第二電晶體、第三電晶體、第四電晶體及第五電晶體於關閉狀態下。 Please refer to FIG. 10. FIG. 10 is a schematic diagram of a method for operating a gate driving circuit according to this embodiment. As shown in FIG. 10, the method for operating the gate driving circuit includes the following steps: (S10) The method connects the third transistor, the fourth transistor, and the fifth transistor in parallel with each other and are respectively coupled to and coupled to the second transistor. Connecting the second contact and the third contact; (S12) during the normal operation of the gate driving circuit, the gate driving circuit is normally operated and the method maintains the first transistor in an open state and maintains the second respectively The transistor, the third transistor, the fourth transistor, and the fifth transistor are in a closed state; (S14) during the pre-charging period of the gate driving circuit, the method maintains the first transistor in an on state and maintains the first The second transistor is in a closed state, and the third transistor, the fourth transistor, and the fifth transistor are sequentially changed from a closed state to an open state respectively; (S16) during a waveform chamfering period of the gate driving circuit, The method will be the first The transistor is changed from an on state to a off state and a second transistor is turned from an off state to an on state, and the third transistor, the fourth transistor, and the fifth transistor are respectively maintained in an on state; (S18) During the non-overlapping period of the pole drive circuit, the method maintains the first transistor in the off state, and changes the second transistor from the on state to the off state and respectively the third transistor, the fourth transistor, and the fifth transistor The crystal is changed from the on state to the off state; (S19) after the gate driving circuit ends the non-overlapping period, the gate driving circuit returns to the normal operation again, the method turns the first transistor from the off state to the on state, and The second transistor, the third transistor, the fourth transistor, and the fifth transistor are respectively maintained in a closed state.
根據本發明之另一較佳具體實施例亦為一種閘極驅動電路運作方法。於此實施例中，閘極驅動電路運作方法用以運作應用於液晶顯示面板之閘極驅動電路。閘極驅動電路包含偏壓接腳、第一電晶體、第二電晶體、第三電晶體及第四電晶體。偏壓接腳分別耦接外部電阻及外部電容。第一電晶體耦接於第一閘極驅動電壓與第一接點之間。第一接點耦接閘極驅動電路之輸出端。第二電晶體分別耦接第二接點與第三接點。第二接點耦接第一接點且第三接點耦接偏壓接腳。第一電晶體、第三電晶體及第四電晶體均為P型電晶體且第二電晶體為N型電晶體。 Another preferred embodiment of the present invention is also a method of operating a gate driving circuit. In this embodiment, the gate driving circuit operates to operate the gate driving circuit applied to the liquid crystal display panel. The gate driving circuit includes a bias pin, a first transistor, a second transistor, a third transistor, and a fourth transistor. The bias pins are respectively coupled to an external resistor and an external capacitor. The first transistor is coupled between the first gate driving voltage and the first contact. The first contact is coupled to the output end of the gate drive circuit. The second transistor is coupled to the second contact and the third contact, respectively. The second contact is coupled to the first contact and the third contact is coupled to the bias pin. The first transistor, the third transistor, and the fourth transistor are all P-type transistors and the second transistor is an N-type transistor.
請參照圖11，圖11繪示根據此實施例中之閘極驅動電路運作方法的示意圖。如圖11所示，閘極驅動電路運作方法包含下列步驟：(S20)將第三電晶體相對於第二電晶體設置並分別耦接第 二接點與第三接點並將第四電晶體耦接於第一閘極驅動電壓與偏壓接腳之間；(S22)於閘極驅動電路之正常運作期間，閘極驅動電路係正常運作且該方法維持第一電晶體於開啟狀態下，並分別維持第二電晶體、第三電晶體及第四電晶體於關閉狀態下；(S24)於閘極驅動電路之預充電期間內，該方法維持第一電晶體於開啟狀態下且分別維持第二電晶體及第三電晶體於關閉狀態下，並將第四電晶體由關閉狀態轉變為開啟狀態；(S26)於閘極驅動電路之波形削角期間內，該方法分別將第一電晶體及第四電晶體由開啟狀態轉變為關閉狀態並分別將第二電晶體及第三電晶體由關閉狀態轉變為開啟狀態；(S28)於閘極驅動電路之非重疊期間內，該方法分別維持第一電晶體及第四電晶體於關閉狀態下，並分別將第二電晶體及第三電晶體由開啟狀態轉變為關閉狀態；(S29)當閘極驅動電路結束非重疊期間後，閘極驅動電路再次回到正常運作期間，該方法將第一電晶體由關閉狀態轉變為開啟狀態，並分別維持第二電晶體、第三電晶體及第四電晶體於關閉狀態下。 Please refer to FIG. 11. FIG. 11 is a schematic diagram of a method for operating a gate driving circuit according to this embodiment. As shown in FIG. 11, the operation method of the gate driving circuit includes the following steps: (S20) disposing the third transistor relative to the second transistor and respectively coupling the first The second contact and the third contact couple the fourth transistor between the first gate driving voltage and the bias pin; (S22) during the normal operation of the gate driving circuit, the gate driving circuit is normal Operating and maintaining the first transistor in an on state, and maintaining the second transistor, the third transistor, and the fourth transistor in a closed state, respectively; (S24) during a precharge period of the gate driving circuit, The method maintains the first transistor in an on state and respectively maintains the second transistor and the third transistor in a closed state, and changes the fourth transistor from a closed state to an on state; (S26) to the gate driving circuit During the waveform chamfering period, the method respectively changes the first transistor and the fourth transistor from an on state to a off state and respectively changes the second transistor and the third transistor from a closed state to an on state; (S28) During the non-overlapping period of the gate driving circuit, the method respectively maintains the first transistor and the fourth transistor in a closed state, and respectively changes the second transistor and the third transistor from an on state to a off state; S29) When the gate After the non-overlapping period of the driving circuit ends, the gate driving circuit returns to the normal operation period again, the method turns the first transistor from the off state to the on state, and maintains the second transistor, the third transistor and the fourth electrode respectively. The crystal is in the off state.
相較於先前技術，根據本發明之閘極驅動電路及其運作方法能夠有效避免先前技術中進行波形削角時所產生之電壓急降(Voltage Drop)現象，使得根據本發明之閘極驅動電路及其運作方法所得到之削角波形不會受到閘極驅動電路之外部寄生電容之大小的影響而改變。 Compared with the prior art, the gate driving circuit and the operating method thereof according to the present invention can effectively avoid the voltage drop phenomenon generated when the waveform is chamfered in the prior art, so that the gate driving circuit according to the present invention The chamfering waveform obtained by its operation method is not affected by the magnitude of the external parasitic capacitance of the gate driving circuit.
由以上較佳具體實施例之詳述，係希望能更加清楚描述 本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。 It is intended to be more clearly described by the detailed description of the preferred embodiments above. The scope and spirit of the present invention is not limited by the preferred embodiments disclosed herein. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.
S10~S19‧‧‧步驟 S10~S19‧‧‧Steps
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|---|---|---|---|---|
| CN1355520A (en) * | 2000-11-28 | 2002-06-26 | 凌阳科技股份有限公司 | Programmable driver circuit |
| TW200620229A (en) * | 2004-12-09 | 2006-06-16 | Samsung Electronics Co Ltd | Output buffer of a source driver in a liquid crystal display having a high slew rate and a method of controlling the output buffer |
| TW200703202A (en) * | 2005-05-31 | 2007-01-16 | Samsung Electronics Co Ltd | Source driver controlling slew rate |
| TW200721083A (en) * | 2005-11-21 | 2007-06-01 | Samsung Electronics Co Ltd | Precharging circuits for a signal line of an liquid crystal display (LCD) in which the precharge voltage is based on the magnitude of a gray-scale voltage corresponding to image data and related LCD systems, drivers, and methods |
| US20120169709A1 (en) * | 2010-12-31 | 2012-07-05 | Seung Kyu Lee | Gate driving circuit and display device including the same |
-
2015
- 2015-11-24 TW TW104139026A patent/TWI587262B/en active
- 2015-12-29 CN CN201511004839.3A patent/CN106601196B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355520A (en) * | 2000-11-28 | 2002-06-26 | 凌阳科技股份有限公司 | Programmable driver circuit |
| TW200620229A (en) * | 2004-12-09 | 2006-06-16 | Samsung Electronics Co Ltd | Output buffer of a source driver in a liquid crystal display having a high slew rate and a method of controlling the output buffer |
| TW200703202A (en) * | 2005-05-31 | 2007-01-16 | Samsung Electronics Co Ltd | Source driver controlling slew rate |
| TW200721083A (en) * | 2005-11-21 | 2007-06-01 | Samsung Electronics Co Ltd | Precharging circuits for a signal line of an liquid crystal display (LCD) in which the precharge voltage is based on the magnitude of a gray-scale voltage corresponding to image data and related LCD systems, drivers, and methods |
| US20120169709A1 (en) * | 2010-12-31 | 2012-07-05 | Seung Kyu Lee | Gate driving circuit and display device including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106601196B (en) | 2019-05-21 |
| TW201715500A (en) | 2017-05-01 |
| CN106601196A (en) | 2017-04-26 |
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