TW201640470A - A single stage gate drive circuit with multiplex outputs - Google Patents
A single stage gate drive circuit with multiplex outputs Download PDFInfo
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Abstract
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本發明係關於一種單級閘極驅動電路，尤其是關於一種單級閘極驅動電路之多輸出設計。
The present invention relates to a single-stage gate drive circuit, and more particularly to a multi-output design of a single-stage gate drive circuit.
按，薄膜電晶體顯示器已成為現在顯示科技產品的主流，尤其應用於手機上有輕巧及方便攜帶等特點，而且非晶矽薄膜電晶體相對於多晶矽薄膜電晶體而言，使用非晶矽薄膜電晶體所製作的顯示器能夠降低生產成本，且能夠在低溫下製作在大面積的玻璃基板上，而提高生產速率。According to the film, the transistor display has become the mainstream of the current display technology products, especially for the light weight and convenient carrying of the mobile phone, and the amorphous germanium film transistor is compared with the polycrystalline germanium film transistor, and the amorphous germanium film is used. A display made of a crystal can reduce the production cost and can be fabricated on a large-area glass substrate at a low temperature to increase the production rate.
隨著系統整合式玻璃面板的概念陸續提出，近來許多產品將顯示器驅動電路中的閘極掃描電路整合在玻璃上，即為GOA（Gate-Driver-on-Array）電路，GOA電路具有諸多優勢，除了可以減少顯示器邊框的面積外，更能夠減少閘極掃描驅動電路IC的使用。With the concept of system-integrated glass panels, many products have recently integrated the gate scanning circuit in the display driver circuit on the glass, which is a GOA (Gate-Driver-on-Array) circuit. The GOA circuit has many advantages. In addition to reducing the area of the display bezel, the use of the gate scan drive circuit IC can be reduced.
鑒於顯示器窄邊框的需求，本發明提出降低單級閘極驅動電路面積需求的技術。
In view of the need for a narrow bezel of the display, the present invention proposes a technique for reducing the area requirement of a single-stage gate drive circuit.
本發明之目的之一，為提供一種單級閘極驅動電路，其可以提升掃描線充放電速度。One of the objects of the present invention is to provide a single-stage gate driving circuit which can increase the charging and discharging speed of a scanning line.
本發明之目的之一，為提供一單級閘極驅動電路，其利用多輸出設計達到佈局面積的減少。One of the objects of the present invention is to provide a single-stage gate drive circuit that utilizes a multiple output design to achieve a reduction in layout area.
為達以上目的，本發明提供一種單級閘極驅動電路，其具有多個掃描電路而為多輸出設計，其中一第一掃描電路包含一設定單元與一驅動單元，設定單元接收一起始訊號產生一控制訊號，驅動單元耦接設定單元並接收控制訊號及一第一時脈訊號，控制訊號及第一時脈訊號使驅動單元產生一第一掃描訊號。驅動單元依據第一時脈訊號驅動第一掃描訊號提升至一第一準位，驅動單元依據第一時脈訊號驅動第一掃描訊號降低至一第二準位，第一準位高於第二準位。一第二掃描電路耦接第一掃描電路，並接收第一掃描訊號及一第二時脈訊號，第二掃描電路依據第一掃描訊號及第二時脈訊號產生一第二掃描訊號。
To achieve the above objective, the present invention provides a single-stage gate driving circuit having a plurality of scanning circuits and a multi-output design, wherein a first scanning circuit includes a setting unit and a driving unit, and the setting unit receives an initial signal generation. a control signal, the driving unit is coupled to the setting unit and receives the control signal and a first clock signal, and the control signal and the first clock signal cause the driving unit to generate a first scanning signal. The driving unit drives the first scanning signal to a first level according to the first clock signal, and the driving unit drives the first scanning signal to decrease to a second level according to the first clock signal, and the first level is higher than the second level. Level. A second scanning circuit is coupled to the first scanning circuit and receives the first scanning signal and the second clock signal. The second scanning circuit generates a second scanning signal according to the first scanning signal and the second clock signal.
1‧‧‧第一單級閘極驅動電路
2‧‧‧第二單級閘極驅動電路
3‧‧‧第三單級閘極驅動電路
10‧‧‧設定單元
11‧‧‧驅動單元
12‧‧‧設定單元
13‧‧‧驅動單元
14‧‧‧控制單元
15‧‧‧抗雜訊單元
16‧‧‧保護單元
A‧‧‧控制訊號
B‧‧‧控制訊號
C‧‧‧控制訊號
CLK1‧‧‧第一時脈訊號
CLK2‧‧‧第二時脈訊號
CLK3‧‧‧第三時脈訊號
CLK4‧‧‧第四時脈訊號
D‧‧‧控制訊號
E‧‧‧控制訊號
F‧‧‧控制訊號
M1‧‧‧第一設定元件
M2‧‧‧第二設定元件
M3‧‧‧驅動元件
M4‧‧‧設定元件(在圖式中出現，但說明書中並未點出)
M5‧‧‧驅動元件
M6‧‧‧電晶體
M7‧‧‧電晶體
M8‧‧‧電晶體
M9‧‧‧第一電晶體
M10‧‧‧第二電晶體
M11‧‧‧第三電晶體
M12‧‧‧第四電晶體
M13‧‧‧電晶體
REF‧‧‧參考準位
S0‧‧‧起始訊號
S1‧‧‧第一掃描訊號
S2‧‧‧第二掃描訊號
S3‧‧‧第三掃描訊號
S4‧‧‧第四掃描訊號
S5‧‧‧第五掃描訊號
S6‧‧‧第六掃描訊號
S7‧‧‧第七掃描訊號
T1‧‧‧第一區間
T2‧‧‧第二區間
T3‧‧‧第三區間
T4‧‧‧第四區間
T5‧‧‧第五區間
T6‧‧‧第六區間
T7‧‧‧第七區間
T8‧‧‧第八區間
T9‧‧‧第九區間
T10‧‧‧第十區間
T11‧‧‧第十一區間
VDD‧‧‧第一電源
VSS‧‧‧第二電源1‧‧‧First single-stage gate drive circuit
2‧‧‧Second single-stage gate drive circuit
3‧‧‧ third single-stage gate drive circuit
10‧‧‧Setting unit
11‧‧‧Drive unit
12‧‧‧Setting unit
13‧‧‧Drive unit
14‧‧‧Control unit
15‧‧‧Anti-noise unit
16‧‧‧Protection unit
A‧‧‧ control signal
B‧‧‧Control signal
C‧‧‧Control signal
CLK1‧‧‧ first clock signal
CLK2‧‧‧ second clock signal
CLK3‧‧‧ third clock signal
CLK4‧‧‧ fourth clock signal
D‧‧‧Control signal
E‧‧‧Control signal
F‧‧‧Control signal
M1‧‧‧ first setting component
M2‧‧‧Second setting component
M3‧‧‧ drive components
M4‧‧‧Set component (appears in the drawing, but not in the manual)
M5‧‧‧ drive components
M6‧‧‧O crystal
M7‧‧‧O crystal
M8‧‧‧O crystal
M9‧‧‧First transistor
M10‧‧‧second transistor
M11‧‧‧ third transistor
M12‧‧‧4th transistor
M13‧‧‧O crystal
REF‧‧‧ reference level
S0‧‧‧ start signal
S1‧‧‧ first scan signal
S2‧‧‧ second scan signal
S3‧‧‧ third scan signal
S4‧‧‧ fourth scan signal
S5‧‧‧ fifth scan signal
S6‧‧‧ sixth scan signal
S7‧‧‧ seventh scan signal
T1‧‧‧ first interval
T2‧‧‧Second interval
T3‧‧‧ third interval
T4‧‧‧4th interval
T5‧‧‧ fifth interval
T6‧‧‧ sixth interval
T7‧‧‧ seventh interval
T8‧‧‧ eighth interval
T9‧‧‧9th interval
T10‧‧‧10th interval
T11‧‧‧11th interval
VDD‧‧‧first power supply
VSS‧‧‧second power supply
第一圖：其係為本發明之多級閘極驅動電路的串接之一實施例的圖示；
第二圖：其係為本發明之單級閘極驅動電路之多輸出設計之一實施例的電路圖；
第三圖：其係為本發明之單級閘極驅動電路之多輸出設計的時序圖；
第四圖：其係為本發明第二圖之下一級閘極驅動電路之多輸出設計的電路圖；
First: an illustration of one embodiment of a series connection of a multi-level gate drive circuit of the present invention;
Second: it is a circuit diagram of an embodiment of a multi-output design of a single-stage gate drive circuit of the present invention;
Third: it is a timing diagram of the multi-output design of the single-stage gate drive circuit of the present invention;
The fourth figure is a circuit diagram of the multi-output design of the first-level gate driving circuit under the second figure of the present invention;
為使 貴審查委員對本發明之特徵及所達成之功效有更進一步之瞭解與認識，謹佐以實施例及配合詳細之說明，說明如後：In order to give your reviewers a better understanding and understanding of the features and effects of the present invention, please refer to the examples and the detailed descriptions, as explained below:
請參閱第一圖，其係為本發明之多級閘極驅動電路的串接之一實施例的圖示。如圖所示為多級閘極驅動電路1、2、3串接，且每一級閘極驅動電路1、2、3皆分別輸出兩個掃描訊號S1~S6。本發明的第一閘級驅動電路1接收一起始訊號S0、一第一時脈訊號CLK1與一第二時脈訊號CLK2產生一第一掃描訊號S1與一第二掃描訊號S2，第一掃描訊號S1與第二掃描訊號S2透過複數掃描線控制複數像素，其中第二掃描訊號S2亦是一第二單級閘極驅動電路2的起始訊號，同理第二單級閘極驅動電路2輸出的掃描訊號S4亦是第三單級閘極驅動電路3的起始訊號。換言之，單級閘極驅動電路1若非第一級時，單級閘極驅動電路1同樣會接收前一級閘級驅動電路的掃描訊號作為起始訊號S0。Please refer to the first figure, which is an illustration of one embodiment of a series connection of a multi-level gate drive circuit of the present invention. As shown in the figure, the multi-level gate driving circuits 1, 2, and 3 are connected in series, and each of the gate driving circuits 1, 2, and 3 outputs two scanning signals S1 to S6, respectively. The first gate driving circuit 1 of the present invention receives a start signal S0, a first clock signal CLK1 and a second clock signal CLK2 to generate a first scan signal S1 and a second scan signal S2, the first scan signal S1 and the second scan signal S2 control the plurality of pixels through the plurality of scan lines, wherein the second scan signal S2 is also the start signal of the second single-stage gate drive circuit 2, and the output of the second single-stage gate drive circuit 2 is the same. The scan signal S4 is also the start signal of the third single-stage gate drive circuit 3. In other words, if the single-stage gate driving circuit 1 is not the first stage, the single-stage gate driving circuit 1 also receives the scanning signal of the previous stage gate driving circuit as the starting signal S0.
請參閱第二圖，其係為本發明之單級閘極驅動電路1之多輸出設計之一實施例的電路圖。如圖所示，第一單級閘極驅動電路1具有兩個掃描電路，一第一掃描電路包含一設定單元10與一驅動單元11，一第二掃描電路包含一設定單元12與一驅動單元13。設定單元10接收起始訊號S0與一第一電源VDD而產生一控制訊號A，驅動單元11耦接設定單元10並接收控制訊號A與第一時脈訊號CLK1，控制訊號A控制驅動單元11依據第一時脈訊號CLK1產生第一掃描訊號S1，換言之，控制訊號A與第一時脈訊號CLK1使驅動單元11產生第一掃描訊號S1。第二掃描電路的設定單元12耦接第一掃描電路的驅動單元11，並接收第一掃描訊號S1與第一電源VDD而產生一控制訊號B。驅動單元13耦接設定單元12，並接收控制訊號B與第二時脈訊號CLK2，控制訊號B控制驅動單元13依據第二時脈訊號CLK2產生第二掃描訊號S2，換言之，控制訊號B與第二時脈訊號CLK2使驅動單元13產生第二掃描訊號S2。如此本發明的第一單級閘極驅動電路1輸出第一掃描訊號S1與第二掃描訊號S2，而為一單級閘極驅動電路的多輸出設計。Please refer to the second figure, which is a circuit diagram of an embodiment of the multi-output design of the single-stage gate driving circuit 1 of the present invention. As shown in the figure, the first single-stage gate driving circuit 1 has two scanning circuits. A first scanning circuit includes a setting unit 10 and a driving unit 11. The second scanning circuit includes a setting unit 12 and a driving unit. 13. The setting unit 10 receives the start signal S0 and a first power source VDD to generate a control signal A. The driving unit 11 is coupled to the setting unit 10 and receives the control signal A and the first clock signal CLK1. The control signal A controls the driving unit 11 according to The first clock signal CLK1 generates the first scan signal S1. In other words, the control signal A and the first clock signal CLK1 cause the driving unit 11 to generate the first scan signal S1. The setting unit 12 of the second scanning circuit is coupled to the driving unit 11 of the first scanning circuit, and receives the first scanning signal S1 and the first power source VDD to generate a control signal B. The driving unit 13 is coupled to the setting unit 12 and receives the control signal B and the second clock signal CLK2. The control signal B controls the driving unit 13 to generate the second scanning signal S2 according to the second clock signal CLK2, in other words, the control signal B and the second The second clock signal CLK2 causes the drive unit 13 to generate the second scan signal S2. Thus, the first single-stage gate driving circuit 1 of the present invention outputs the first scanning signal S1 and the second scanning signal S2, and is designed as a multiple output of a single-stage gate driving circuit.
復參閱第一圖與第二圖，第一掃描電路的設定單元10包含一第一設定元件M1與一第二設定元件M2，第一設定元件M1具有一輸入端、一控制端及一輸出端，輸入端接收第一電源VDD，控制端接收起始訊號S0，輸出端耦接驅動單元11，第一設定元件M1依據起始訊號S0及第一電源VDD產生控制訊號A。第二設定元件M2具有一輸入端、一控制端及一輸出端，輸入端接收一第二電源VSS，控制端接收一第二單級閘極驅動電路2輸出的一第三掃描訊號S3，輸出端耦接驅動單元11，第二設定元件M2依據第三掃描訊號S3及第二電源VSS設定控制訊號A，換言之，第三掃描訊號S3將控制訊號A設定為第二電源VSS的準位。若第二電源VSS的準位為一地電位，則第三掃描訊號S3將控制訊號A設定為地電位，如此第三掃描訊號S3使控制訊號A放電而降低為地電位，所以驅動單元11不會產生第一掃描訊號S1。Referring to the first and second figures, the setting unit 10 of the first scanning circuit includes a first setting component M1 and a second setting component M2. The first setting component M1 has an input terminal, a control terminal and an output terminal. The input terminal receives the first power supply VDD, the control terminal receives the start signal S0, the output terminal is coupled to the driving unit 11, and the first setting component M1 generates the control signal A according to the start signal S0 and the first power source VDD. The second setting component M2 has an input terminal, a control terminal and an output terminal. The input terminal receives a second power source VSS, and the control terminal receives a third scan signal S3 outputted by the second single-stage gate driving circuit 2, and outputs The terminal is coupled to the driving unit 11, and the second setting component M2 sets the control signal A according to the third scanning signal S3 and the second power source VSS. In other words, the third scanning signal S3 sets the control signal A to the level of the second power source VSS. If the level of the second power source VSS is a ground potential, the third scan signal S3 sets the control signal A to the ground potential, so that the third scan signal S3 discharges the control signal A to the ground potential, so the driving unit 11 does not A first scan signal S1 is generated.
再者，第一掃描電路的驅動單元11包含一驅動元件M3與一電容器C1，驅動元件M3具有一輸入端、一控制端及一輸出端，輸入端接收第一時脈訊號CLK1，控制端耦接設定單元10，輸出端耦接第二掃描電路的設定單元12，驅動元件M3依據第一時脈訊號CLK1及控制訊號A而產生第一掃描訊號S1。如此，第一掃描電路之驅動單元11的輸出端輸出第一掃描訊號S1，第一掃描訊號S1耦接第二掃描電路之設定單元12，以使第二掃描電路產生第二掃描訊號S2。Furthermore, the driving unit 11 of the first scanning circuit comprises a driving component M3 and a capacitor C1. The driving component M3 has an input terminal, a control terminal and an output terminal. The input terminal receives the first clock signal CLK1, and the control terminal coupling The setting unit 10 is coupled to the setting unit 12 of the second scanning circuit, and the driving element M3 generates the first scanning signal S1 according to the first clock signal CLK1 and the control signal A. The first scanning signal S1 is coupled to the setting unit 12 of the second scanning circuit, so that the second scanning circuit generates the second scanning signal S2.
參閱第二圖，第一掃描電路還包含一電容器C1，電容器C1耦接於驅動元件M3的控制端與輸出端之間。因此，當控制訊號A未控制驅動元件M3導通時，電容器C1之一第一端的準位為控制訊號A的準位，當控制訊號A控制驅動元件M3導通時，電容器C1之一第二端的準位為第一時脈訊號CLK1的準位，而且電容器C1之第一端的準位改為控制訊號A的準位加上第一時脈訊號CLK1的準位。如此，當第一時脈訊號CLK1為一高準位時，電容器C1的第一端為控制訊號A的準位加上第一時脈訊號CLK1的準位；即電容器C1依據控制訊號A及第一時脈訊號CLK1提升第一掃描訊號S1的準位。Referring to the second figure, the first scanning circuit further includes a capacitor C1 coupled between the control terminal and the output terminal of the driving component M3. Therefore, when the control signal A does not control the driving element M3 to be turned on, the level of the first end of the capacitor C1 is the level of the control signal A, and when the control signal A controls the driving element M3 to be turned on, the second end of the capacitor C1 The level is the level of the first clock signal CLK1, and the level of the first end of the capacitor C1 is changed to the level of the control signal A plus the level of the first clock signal CLK1. Thus, when the first clock signal CLK1 is at a high level, the first end of the capacitor C1 is the level of the control signal A plus the level of the first clock signal CLK1; that is, the capacitor C1 is based on the control signal A and the The one-time signal CLK1 boosts the level of the first scanning signal S1.
承接上述，當第一時脈訊號CLK1為一低準位（例如：一地電位）時，電容器C1的第一端為控制訊號A的準位。換言之，驅動元件M3的控制端會依據第一時脈訊號CLK1提升準位或降低準位而產生第一掃描訊號S1，或者可以說本發明的單級閘極驅動電路1利用驅動單元11、13就可以完成掃描線的充電與放電工作，而大幅減少電路面積並提升對掃描線的充電速度。In the above, when the first clock signal CLK1 is at a low level (for example, a ground potential), the first end of the capacitor C1 is the level of the control signal A. In other words, the control terminal of the driving component M3 generates the first scanning signal S1 according to the first clock signal CLK1 raising the level or lowering the level, or it can be said that the single-stage gate driving circuit 1 of the present invention utilizes the driving units 11 and 13 The charging and discharging operations of the scanning line can be completed, and the circuit area is greatly reduced and the charging speed of the scanning line is increased.
此外，如第二圖所示，第一掃描電路的控制訊號A僅需要控制驅動元件M3而無須控制驅動元件M5，第二掃描電路的控制訊號B同樣僅需要控制驅動元件M5而無須控制其他驅動元件，所以本發明的單級閘極驅動電路1的輸出負載較低，以至於單級閘極驅動電路1的輸出能力較好。In addition, as shown in the second figure, the control signal A of the first scanning circuit only needs to control the driving component M3 without controlling the driving component M5, and the control signal B of the second scanning circuit only needs to control the driving component M5 without controlling other driving. Since the output load of the single-stage gate driving circuit 1 of the present invention is low, the output capability of the single-stage gate driving circuit 1 is good.
復參閱第二圖，本發明的單級閘極驅動電路1具有一抗雜訊電路，抗雜訊電路耦接第一掃描電路及第二掃描電路，並接收第一時脈訊號CLK1以降低第一掃描電路1的雜訊及第二掃描電路的雜訊，此處所指發生雜訊的地方為驅動元件M3、M5的控制端與輸出端的雜訊。抗雜訊電路包含一控制單元14、抗雜訊單元15與一保護單元16，控制單元14接收第一電源VDD、第一時脈訊號CLK1及控制訊號A。Referring to the second figure, the single-stage gate driving circuit 1 of the present invention has an anti-noise circuit, the anti-noise circuit is coupled to the first scanning circuit and the second scanning circuit, and receives the first clock signal CLK1 to reduce the first The noise of the scanning circuit 1 and the noise of the second scanning circuit, where the noise occurs, are the noise of the control terminal and the output terminal of the driving components M3 and M5. The anti-noise circuit comprises a control unit 14, an anti-noise unit 15 and a protection unit 16, and the control unit 14 receives the first power supply VDD, the first clock signal CLK1 and the control signal A.
承接上述，控制單元14包含複數電晶體M6~M8，第一電源VDD控制電晶體M7處於導通狀態，第一時脈訊號CLK1控制電晶體M6為導通或截止狀態，同樣的，控制訊號A控制電晶體M8為導通或截止狀態。其中，控制訊號A控制電晶體M8導通時，控制訊號C為參考準位REF，因此抗雜訊電路未啟用抗雜訊工作，換言之，控制訊號A控制抗雜訊電路未啟用抗雜訊工作。當控制訊號A控制電晶體M8截止時，若第一時脈訊號CLK1控制電晶體M6導通，則控制訊號C為第一電源VDD的準位，如此抗雜訊電路啟用抗雜訊工作，換言之，第一電源VDD及第一時脈訊號CLK1控制抗雜訊電路啟用抗雜訊工作。In the above, the control unit 14 includes a plurality of transistors M6-M8. The first power supply VDD controls the transistor M7 to be in an on state, and the first clock signal CLK1 controls the transistor M6 to be in an on or off state. Similarly, the control signal A controls the power. The crystal M8 is in an on or off state. Wherein, when the control signal A controls the transistor M8 to be turned on, the control signal C is the reference level REF, so the anti-noise operation is not enabled by the anti-noise circuit, in other words, the anti-noise operation is not enabled by the control signal A control anti-noise circuit. When the control signal A controls the transistor M8 to be turned off, if the first clock signal CLK1 controls the transistor M6 to be turned on, the control signal C is at the level of the first power source VDD, so that the anti-noise circuit enables anti-noise operation, in other words, The first power supply VDD and the first clock signal CLK1 control the anti-noise circuit to enable anti-noise operation.
參閱第二圖，抗雜訊單元15包含一第一電晶體M9、一第二電晶體M10、一第三電晶體M11與一第四電晶體M12，第一電晶體M9具有一輸入端、一控制端及一輸出端，輸入端耦接第一掃描電路之驅動單元11，控制端耦接控制單元14，輸出端耦接一參考準位REF，第一電晶體M9使第一掃描電路之驅動單元11之一控制端的準位穩定於參考準位REF。第二電晶體M10具有一輸入端、一控制端及一輸出端，輸入端耦接第一掃描電路之驅動單元11，控制端耦接控制單元14，輸出端耦接參考準位REF，第二電晶體M10使第一掃描電路之驅動單元11之輸出端的準位穩定於參考準位REF。Referring to the second figure, the anti-noise unit 15 includes a first transistor M9, a second transistor M10, a third transistor M11 and a fourth transistor M12. The first transistor M9 has an input end and a a control end and an output end, the input end is coupled to the driving unit 11 of the first scanning circuit, the control end is coupled to the control unit 14, the output end is coupled to a reference level REF, and the first transistor M9 drives the first scanning circuit The level of the control terminal of one of the units 11 is stabilized at the reference level REF. The second transistor M10 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 11 of the first scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to the reference level REF. The transistor M10 stabilizes the level of the output of the driving unit 11 of the first scanning circuit to the reference level REF.
承接上述，第三電晶體M11具有一輸入端、一控制端及一輸出端，輸入端耦接第二掃描電路之一驅動單元13，控制端耦接控制單元14，輸出端耦接參考準位REF，第三電晶體M11使第二掃描電路之驅動單元13之控制端的準位穩定於參考準位REF。第四電晶體M12具有一輸入端、一控制端及一輸出端，輸入端耦接第二掃描電路之驅動單元13，控制端耦接控制單元14，輸出端耦接參考準位REF，第四電晶體M12使第二掃描電路之驅動單元13之輸出端的準位穩定於參考準位REF。換言之，當控制訊號C控制驅動單元11、13的控制端與輸出端為參考準位REF時，可以使驅動單元11、13的控制端與輸出端的電位穩定而避免雜訊的影響，如此掃描線將不會受到訊號耦合的影響。The third transistor M11 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 13 of the second scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to the reference level. REF, the third transistor M11 stabilizes the level of the control terminal of the driving unit 13 of the second scanning circuit at the reference level REF. The fourth transistor M12 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 13 of the second scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to the reference level REF. The transistor M12 stabilizes the level of the output of the driving unit 13 of the second scanning circuit to the reference level REF. In other words, when the control signal C controls the control terminal and the output terminal of the driving unit 11, 13 to be the reference level REF, the potentials of the control terminal and the output terminal of the driving unit 11 and 13 can be stabilized to avoid the influence of noise, such a scanning line. Will not be affected by signal coupling.
參閱第二圖，保護單元16可以為一電晶體M13，電晶體M13具有一輸入端、一控制端及一輸出端，輸入端耦接第一電晶體M9、第二電晶體M10、第三電晶體M11與第四電晶體M12，控制端接收一第三時脈訊號CLK3，輸出端耦接參考準位REF。當第一時脈訊號CLK1與第二時脈訊號CLK2非為一參考準位時（例如：地電位），第一時脈訊號CLK1與第二時脈訊號CLK2對掃描線會有耦合雜訊，因此第三時脈訊號CLK3控制電晶體M13截止，使控制訊號C維持於高準位，讓第一掃描電路與第二掃描電路的輸出維持於參考準位REF，而降低耦合雜訊對掃描線的影響。Referring to the second figure, the protection unit 16 can be a transistor M13. The transistor M13 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the first transistor M9, the second transistor M10, and the third device. The crystal M11 and the fourth transistor M12, the control terminal receives a third clock signal CLK3, and the output terminal is coupled to the reference level REF. When the first clock signal CLK1 and the second clock signal CLK2 are not a reference level (for example, ground potential), the first clock signal CLK1 and the second clock signal CLK2 may have coupling noise to the scan line. Therefore, the third clock signal CLK3 controls the transistor M13 to be turned off, the control signal C is maintained at a high level, the output of the first scan circuit and the second scan circuit is maintained at the reference level REF, and the coupled noise is reduced to the scan line. Impact.
承接上述，反之，當第一時脈訊號CLK1與第二時脈訊號CLK2為一參考準位REF時，第一時脈訊號CLK1與第二時脈訊號CLK2對掃描線不會有耦合雜訊，因此第三時脈訊號CLK3控制電晶體M13放電，使控制訊號C改變為參考準位REF。換言之，本發明的保護單元16依據第三時脈訊號CLK3而週期性的將第一電晶體M9、第二電晶體M10、第三電晶體M11與第四電晶體M12的控制端維持於參考準位REF，以避免耦合雜訊。According to the above, when the first clock signal CLK1 and the second clock signal CLK2 are a reference level REF, the first clock signal CLK1 and the second clock signal CLK2 do not have coupling noise to the scan line. Therefore, the third clock signal CLK3 controls the discharge of the transistor M13 to change the control signal C to the reference level REF. In other words, the protection unit 16 of the present invention periodically maintains the control ends of the first transistor M9, the second transistor M10, the third transistor M11, and the fourth transistor M12 according to the third clock signal CLK3. Bit REF to avoid coupling noise.
基於上述，本發明的第一掃描電路與第二掃描電路共用一個抗雜訊電路，而減少抗雜訊電路的佈局面積。再者，本發明的抗雜訊電路會將驅動單元11、13的控制端與輸出端進行重置而維持於參考準位REF，如此單級閘極驅動電路1、2、3可以減少重置元件的設置，而亦可以縮減佈局面積。換言之，本發明的抗雜訊電路同時做到抗雜訊與重置的功能。故，本發明縮減閘極驅動電路之多處佈局面積而達到窄邊框的目的。Based on the above, the first scanning circuit and the second scanning circuit of the present invention share an anti-noise circuit to reduce the layout area of the anti-noise circuit. Furthermore, the anti-noise circuit of the present invention resets the control terminal and the output terminal of the driving units 11, 13 and maintains the reference level REF, so that the single-stage gate driving circuits 1, 2, 3 can reduce the reset. The component is set, and the layout area can also be reduced. In other words, the anti-noise circuit of the present invention simultaneously performs the functions of anti-noise and reset. Therefore, the present invention reduces the layout area of the gate driving circuit to achieve a narrow frame.
請參閱第三圖，其係為本發明之單級閘極驅動電路之多輸出設計的時序圖。此時序圖為本發明單級閘極驅動電路的時序圖，也就是說，第一圖的第一單級閘極驅動電路1、第二單級閘極驅動電路2及第三單級閘極驅動電路3的操作方式與時序皆可以參考第三圖。Please refer to the third figure, which is a timing diagram of the multi-output design of the single-stage gate driving circuit of the present invention. The timing diagram is a timing diagram of the single-stage gate driving circuit of the present invention, that is, the first single-stage gate driving circuit 1, the second single-stage gate driving circuit 2, and the third single-stage gate of the first figure. For the operation mode and timing of the driving circuit 3, reference may be made to the third figure.
於第一區間T1，起始訊號S0為高準位，第一設定元件M1與電晶體M8為導通狀態；如此，控制訊號A的準位被充電至第一電源VDD的準位，且因為第一時脈訊號CLK1與第二時脈訊號CLK2為參考準位REF，不會有耦合雜訊，所以控制訊號C經由電晶體M8放電而為參考準位REF；此時抗雜訊電路未啟用，且第一掃描訊號S1與第一時脈訊號CLK1同樣為參考準位REF。於第二區間T2，第一時脈訊號CLK1改變為高準位，且經由電容器C1的充電而將控制訊號A的準位提升為第一電源VDD的準位加上第一時脈訊號CLK1的準位，此時第一掃描訊號S1亦可以提升至高準位，第一掃描訊號S1並將掃描線充電至高準位；再者，第一掃描訊號S1會控制第二掃描電路的電晶體M5導通，因此控制訊號B的準位會提升第一電源VDD的準位；此時第一掃描電路與第二掃描電路工作中，所以抗雜訊電路未啟用抗雜訊工作。In the first interval T1, the start signal S0 is at a high level, and the first setting component M1 and the transistor M8 are in an on state; thus, the level of the control signal A is charged to the level of the first power source VDD, and because The clock signal CLK1 and the second clock signal CLK2 are the reference level REF, and there is no coupling noise, so the control signal C is discharged through the transistor M8 as the reference level REF; at this time, the anti-noise circuit is not enabled. The first scan signal S1 and the first clock signal CLK1 are also reference levels REF. In the second interval T2, the first clock signal CLK1 is changed to a high level, and the level of the control signal A is raised to the level of the first power source VDD plus the first clock signal CLK1 via charging of the capacitor C1. At the same time, the first scan signal S1 can also be raised to a high level, the first scan signal S1 and the scan line is charged to a high level; further, the first scan signal S1 controls the transistor M5 of the second scan circuit to be turned on. Therefore, the level of the control signal B increases the level of the first power supply VDD; at this time, the first scanning circuit and the second scanning circuit operate, so the anti-noise circuit does not enable anti-noise operation.
於第三區間T3，第一時脈訊號CLK1降低至參考準位REF，則控制訊號A的準位降低至第一電源VDD的準位，且第一掃描訊號S1降低為參考準位REF；第二時脈訊號CLK2由參考準位REF改變為高準位，因此控制訊號B的準位為第一電源VDD的準位加上第二時脈訊號CLK2的準位；此時第二掃描訊號S2亦可以提升至高準位並充電掃描線；同理，第二掃描訊號S2會控制下一級閘級驅動電路的設定單元。於第四區間T4，第二時脈訊號CLK2降低為參考準位REF，控制訊號B的準位亦降低至第一電源VDD的準位，且第二掃描訊號S2也降低至參考準位REF；再者，因第三時脈訊號CLK3為高準位，所以第二單級閘極驅動電路2（第一圖）的第三掃描訊號S3提升至高準位，而第三掃描訊號S3更控制第一掃描電路的第二設定元件M2，將控制訊號A的準位從第一電源VDD的準位降低至第二電源VSS的準位（例如：參考準位REF）。In the third interval T3, the first clock signal CLK1 is lowered to the reference level REF, the level of the control signal A is lowered to the level of the first power source VDD, and the first scan signal S1 is lowered to the reference level REF; The second clock signal CLK2 is changed from the reference level REF to the high level. Therefore, the level of the control signal B is the level of the first power supply VDD plus the level of the second clock signal CLK2; at this time, the second scanning signal S2 It is also possible to raise the high level and charge the scan line; similarly, the second scan signal S2 controls the setting unit of the next stage gate drive circuit. In the fourth interval T4, the second clock signal CLK2 is lowered to the reference level REF, the level of the control signal B is also lowered to the level of the first power source VDD, and the second scan signal S2 is also lowered to the reference level REF; Furthermore, since the third clock signal CLK3 is at a high level, the third scan signal S3 of the second single-stage gate driving circuit 2 (first picture) is raised to a high level, and the third scanning signal S3 is further controlled. The second setting component M2 of the scanning circuit reduces the level of the control signal A from the level of the first power source VDD to the level of the second power source VSS (for example, the reference level REF).
於第五區間T5，此時於第一單級閘極驅動電路1內控制訊號B的準位維持於第一電源VDD的準位，而第四時脈訊號CLK4控制第二單級閘極驅動電路2產生第四掃描訊號S4。於第六區間T6，此時第一時脈訊號CLK1週期性的又為高準位，並控制控制單元14的電晶體M10導通，如此控制訊號C的準位為第一電源VDD的準位；而且，由於第一單級閘極驅動電路1目前不工作，所以為避免第一時脈訊號CLK1對掃描線有耦合雜訊，此區間不利用放電機制降低控制訊號C的準位，並且控制訊號C控制抗雜訊單元15啟用抗雜訊工作，如此可以使驅動單元11、13的控制端與輸出端為參考準位REF，而降低第一時脈訊號CLK1的耦合雜訊。In the fifth interval T5, the level of the control signal B in the first single-stage gate driving circuit 1 is maintained at the level of the first power supply VDD, and the fourth clock signal CLK4 controls the second single-stage gate driving. Circuit 2 produces a fourth scan signal S4. In the sixth interval T6, the first clock signal CLK1 is periodically at a high level, and the transistor M10 of the control unit 14 is turned on, so that the level of the control signal C is the level of the first power source VDD; Moreover, since the first single-stage gate driving circuit 1 is not currently working, in order to avoid coupling noise of the first clock signal CLK1 to the scan line, the interval does not use the discharge mechanism to lower the level of the control signal C, and the control signal The C control anti-noise unit 15 enables the anti-noise operation, so that the control terminal and the output terminal of the driving unit 11, 13 are reference level REF, and the coupling noise of the first clock signal CLK1 is reduced.
於第七區間T7，第一時脈訊號CLK1為低準位（例如:參考準位REF），則電晶體M6為截止狀態，又第二時脈訊號CLK2週期性的又為高準位，但是控制訊號C的準位並未經由放電而降低，所以抗雜訊單元15仍執行抗雜訊工作中，而第二時脈訊號CLK2並不會對掃描線有耦合雜訊。於第八區間T8，第三時脈訊號CLK3控制電晶體M13導通，而將控制訊號C的準位降低至參考準位REF，則抗雜訊單元15停止執行抗雜訊工作；再者，因此區間內第一時脈訊號CLK1與第二時脈訊號CLK2為低準位，所以不會有耦合雜訊，而無須啟用抗雜訊工作。後續第九區間T9至第十一區間T11如前述第五區間T5至第七區間T7的說明，於此不再覆述。In the seventh interval T7, the first clock signal CLK1 is at a low level (for example, the reference level REF), the transistor M6 is in an off state, and the second clock signal CLK2 is periodically at a high level, but The level of the control signal C is not lowered by the discharge, so the anti-noise unit 15 still performs anti-noise operation, and the second clock signal CLK2 does not have coupling noise to the scan line. In the eighth interval T8, the third clock signal CLK3 controls the transistor M13 to be turned on, and the level of the control signal C is lowered to the reference level REF, and the anti-noise unit 15 stops performing anti-noise operation; The first clock signal CLK1 and the second clock signal CLK2 in the interval are at a low level, so there is no coupling noise, and no anti-noise operation is required. The following description of the ninth interval T9 to the eleventh interval T11 as in the aforementioned fifth interval T5 to seventh interval T7 will not be repeated here.
由上述說明可以得知，顯示器之複數單級閘極驅動電路1、2、3，於運作時，第三時脈訊號CLK3同時控制單級閘極驅動電路1、2、3的第一單級閘極驅動電路1放電與第二單級閘極驅動電路2充電，第一時脈訊號CLK1同時控制單級閘極驅動電路1、2、3的第二單級閘極驅動電路2放電與第三單級閘極驅動電路3充電。As can be seen from the above description, the plurality of single-stage gate driving circuits 1, 2, and 3 of the display, during operation, the third clock signal CLK3 simultaneously controls the first single stage of the single-stage gate driving circuits 1, 2, and 3. The gate driving circuit 1 discharges and the second single-stage gate driving circuit 2 is charged, and the first clock signal CLK1 simultaneously controls the discharging of the second single-stage gate driving circuit 2 of the single-stage gate driving circuits 1, 2, and 3. The three single-stage gate drive circuit 3 is charged.
請參閱第四圖，其係為本發明第三圖之下一級閘極驅動電路之多輸出設計的電路圖。如圖所示，其為第二單級閘極驅動電路2，第四圖所欲呈現出與第二圖不同的是，第四圖的閘極驅動電路2運作時接收的訊號是前一級閘極驅動電路1的第二掃描訊號S2、後一級的一第五掃描訊號S5、第三時脈訊號CLK3、第四時脈訊號CLK4與第一時脈訊號CLK1，但是其運作方式與第二圖所示的閘極驅動電路1相同。再者，此差異可以參閱第一圖，就可以明顯的看出運作時第二單級閘極驅動電路2所接收的訊號與第一單級閘極驅動電路1的差異之處。Please refer to the fourth figure, which is a circuit diagram of the multi-output design of the first-level gate driving circuit in the third figure of the present invention. As shown in the figure, it is a second single-stage gate driving circuit 2. The fourth figure is different from the second figure. The signal received by the gate driving circuit 2 of the fourth figure is the first-stage gate. a second scan signal S2 of the pole drive circuit 1, a fifth scan signal S5, a third clock signal CLK3, a fourth clock signal CLK4, and a first clock signal CLK1 of the subsequent stage, but the operation mode and the second figure The gate drive circuit 1 shown is the same. Moreover, the difference can be seen in the first figure, and the difference between the signal received by the second single-stage gate driving circuit 2 and the first single-stage gate driving circuit 1 during operation can be clearly seen.
綜上所述，本發明提供一種單級閘極驅動電路，其具有多個掃描電路而為多輸出設計，其中一第一掃描電路包含一設定單元與一驅動單元，設定單元接收一起始訊號產生一控制訊號，驅動單元耦接設定單元並接收控制訊號及一第一時脈訊號，控制訊號及第一時脈訊號使驅動單元產生一第一掃描訊號。驅動單元依據第一時脈訊號驅動第一掃描訊號提升至一第一準位，驅動單元依據第一時脈訊號驅動第一掃描訊號降低至一第二準位，第一準位高於第二準位。一第二掃描電路耦接第一掃描電路，並接收第一掃描訊號及一第二時脈訊號，第二掃描電路依據第一掃描訊號及第二時脈訊號產生一第二掃描訊號。In summary, the present invention provides a single-stage gate driving circuit having a plurality of scanning circuits and a multi-output design, wherein a first scanning circuit includes a setting unit and a driving unit, and the setting unit receives a start signal. a control signal, the driving unit is coupled to the setting unit and receives the control signal and a first clock signal, and the control signal and the first clock signal cause the driving unit to generate a first scanning signal. The driving unit drives the first scanning signal to a first level according to the first clock signal, and the driving unit drives the first scanning signal to decrease to a second level according to the first clock signal, and the first level is higher than the second level. Level. A second scanning circuit is coupled to the first scanning circuit and receives the first scanning signal and the second clock signal. The second scanning circuit generates a second scanning signal according to the first scanning signal and the second clock signal.
1‧‧‧第一單級閘極驅動電路 1‧‧‧First single-stage gate drive circuit
10‧‧‧設定單元 10‧‧‧Setting unit
11‧‧‧驅動單元 11‧‧‧Drive unit
12‧‧‧設定單元 12‧‧‧Setting unit
13‧‧‧驅動單元 13‧‧‧Drive unit
14‧‧‧控制單元 14‧‧‧Control unit
15‧‧‧抗雜訊單元 15‧‧‧Anti-noise unit
16‧‧‧保護單元 16‧‧‧Protection unit
A‧‧‧控制訊號 A‧‧‧ control signal
B‧‧‧控制訊號 B‧‧‧Control signal
C‧‧‧控制訊號 C‧‧‧Control signal
CLK1‧‧‧第一時脈訊號 CLK1‧‧‧ first clock signal
CLK2‧‧‧第二時脈訊號 CLK2‧‧‧ second clock signal
CLK3‧‧‧第三時脈訊號 CLK3‧‧‧ third clock signal
M1‧‧‧第一設定元件 M1‧‧‧ first setting component
M2‧‧‧第二設定元件 M2‧‧‧Second setting component
M3‧‧‧驅動元件 M3‧‧‧ drive components
M4‧‧‧設定元件 M4‧‧‧Set components
M5‧‧‧驅動元件 M5‧‧‧ drive components
M6‧‧‧電晶體 M6‧‧‧O crystal
M7‧‧‧電晶體 M7‧‧‧O crystal
M8‧‧‧電晶體 M8‧‧‧O crystal
M9‧‧‧第一電晶體 M9‧‧‧First transistor
M10‧‧‧第二電晶體 M10‧‧‧second transistor
M11‧‧‧第三電晶體 M11‧‧‧ third transistor
M12‧‧‧第四電晶體 M12‧‧‧4th transistor
M13‧‧‧電晶體 M13‧‧‧O crystal
REF‧‧‧參考準位 REF‧‧‧ reference level
S0‧‧‧起始訊號 S0‧‧‧ start signal
S1‧‧‧第一掃描訊號 S1‧‧‧ first scan signal
S2‧‧‧第二掃描訊號 S2‧‧‧ second scan signal
S3‧‧‧第三掃描訊號 S3‧‧‧ third scan signal
VDD‧‧‧第一電源 VDD‧‧‧first power supply
VSS‧‧‧第二電源 VSS‧‧‧second power supply
Claims (10)
一第一掃描電路，其包含：
一設定單元，接收一起始訊號，產生一控制訊號；
一驅動單元，耦接該設定單元，接收該控制訊號及一第一時脈訊號，該控制訊號及該第一時脈訊號使該驅動單元產生一第一掃描訊號，該驅動單元依據該第一時脈訊號驅動該第一掃描訊號提升至一第一準位，該驅動單元依據該第一時脈訊號驅動該第一掃描訊號降低至一第二準位，該第一準位高於該第二準位；及
一第二掃描電路，耦接該第一掃描電路，接收該第一掃描訊號及一第二時脈訊號，該第二掃描電路依據該第一掃描訊號及該第二時脈訊號產生一第二掃描訊號；
其中，該單級閘極驅動電路輸出該第一掃描訊號及該第二掃描訊號至複數像素，控制該些像素。A multi-output design of a single-stage gate driving circuit, the single-stage gate driving circuit having a plurality of scanning circuits, comprising:
a first scanning circuit comprising:
a setting unit that receives a start signal and generates a control signal;
a driving unit coupled to the setting unit, receiving the control signal and a first clock signal, wherein the control signal and the first clock signal cause the driving unit to generate a first scanning signal, and the driving unit is configured according to the first The clock signal drives the first scan signal to a first level, and the driving unit drives the first scan signal to decrease to a second level according to the first clock signal, where the first level is higher than the first level And a second scanning circuit coupled to the first scanning circuit to receive the first scanning signal and a second clock signal, wherein the second scanning circuit is configured according to the first scanning signal and the second clock The signal generates a second scan signal;
The single-stage gate driving circuit outputs the first scanning signal and the second scanning signal to the plurality of pixels to control the pixels.
一第一設定元件，具有一輸入端、一控制端及一輸出端，該輸入端接收一第一電源，該控制端接收該起始訊號，該輸出端耦接該驅動單元，該第一設定元件依據該起始訊號及該第一電源產生該控制訊號；及
一第二設定元件，具有一輸入端、一控制端及一輸出端，該輸入端接收一第二電源，該控制端接收一第三掃描訊號，該輸出端耦接該驅動單元，該第二設定元件依據該第三掃描訊號及該第二電源設定該控制訊號。The multi-output design of the single-stage gate driving circuit as described in claim 1 of the patent application, wherein the setting unit comprises:
a first setting component having an input terminal, a control terminal and an output terminal, the input terminal receiving a first power source, the control terminal receiving the start signal, the output terminal coupled to the driving unit, the first setting The component generates the control signal according to the start signal and the first power source; and a second setting component has an input terminal, a control terminal and an output terminal, the input terminal receives a second power source, and the control terminal receives a control signal The third scanning signal is coupled to the driving unit, and the second setting component sets the control signal according to the third scanning signal and the second power source.
一驅動元件，具有一輸入端、一控制端及一輸出端，該輸入端接收該第一時脈訊號，該控制端耦接該設定單元，該輸出端耦接該第二掃描電路，該驅動元件依據該第一時脈訊號及該控制訊號而產生該第一掃描訊號；及
一電容器，耦接於該驅動元件的該控制端與該輸出端之間，依據該控制訊號及該第一時脈訊號提升該第一掃描訊號的準位。The multiple output design of the single-stage gate driving circuit as described in claim 1, wherein the driving unit comprises:
a driving component having an input terminal, a control terminal and an output terminal, wherein the input terminal receives the first clock signal, the control terminal is coupled to the setting unit, and the output terminal is coupled to the second scanning circuit, the driving The component generates the first scan signal according to the first clock signal and the control signal; and a capacitor coupled between the control end of the driving component and the output terminal, according to the control signal and the first time The pulse signal raises the level of the first scan signal.
一抗雜訊電路，耦接該第一掃描電路及該第二掃描電路，接收該第一時脈訊號，降低該第一掃描電路的雜訊及該第二掃描電路的雜訊。The multi-output design of the single-stage gate driving circuit described in claim 1 of the patent application further includes:
The first anti-noise circuit is coupled to the first scan circuit and the second scan circuit to receive the first clock signal, and reduce noise of the first scan circuit and noise of the second scan circuit.
一控制單元，接收一第一電源、該第一時脈訊號及該控制訊號，該控制訊號控制該抗雜訊電路未啟用抗雜訊工作，該第一電源及該第一時脈訊號控制該抗雜訊電路啟用抗雜訊工作。The multi-output design of the single-stage gate driving circuit as described in claim 4, wherein the anti-noise circuit comprises:
a control unit that receives a first power source, the first clock signal, and the control signal, the control signal controls the anti-noise circuit to not enable anti-noise operation, and the first power source and the first clock signal control the The anti-noise circuit enables anti-noise operation.
一第一電晶體，具有一輸入端、一控制端及一輸出端，該輸入端耦接該第一掃描電路之該驅動單元，該控制端耦接該控制單元，該輸出端耦接一參考準位，該第一電晶體使該第一掃描電路之該驅動單元之一控制端的準位穩定於該參考準位；
一第二電晶體，具有一輸入端、一控制端及一輸出端，該輸入端耦接該第一掃描電路之該驅動單元，該控制端耦接該控制單元，該輸出端耦接該參考準位，該第二電晶體使該第一掃描電路之該驅動單元之一輸出端的準位穩定於該參考準位；
一第三電晶體，具有一輸入端、一控制端及一輸出端，該輸入端耦接該第二掃描電路之一驅動單元，該控制端耦接該控制單元，該輸出端耦接該參考準位，該第三電晶體使該第二掃描電路之該驅動單元之一控制端的準位穩定於該參考準位；及
一第四電晶體，具有一輸入端、一控制端及一輸出端，該輸入端耦接該第二掃描電路之該驅動單元，該控制端耦接該控制單元，該輸出端耦接該參考準位，該第四電晶體使該第二掃描電路之該驅動單元之一輸出端的準位穩定於該參考準位。The multi-output design of the single-stage gate driving circuit as described in claim 4, wherein the anti-noise circuit comprises an anti-noise unit, the anti-noise unit comprising:
a first transistor having an input terminal, a control terminal and an output terminal, the input terminal is coupled to the driving unit of the first scanning circuit, the control terminal is coupled to the control unit, and the output terminal is coupled to a reference Positioning, the first transistor stabilizes a level of a control end of the driving unit of the first scanning circuit at the reference level;
a second transistor having an input terminal, a control terminal and an output terminal, the input terminal being coupled to the driving unit of the first scanning circuit, the control terminal coupled to the control unit, the output terminal coupled to the reference Positioning, the second transistor stabilizes a level of an output end of the driving unit of the first scanning circuit at the reference level;
a third transistor having an input terminal, a control terminal and an output terminal, the input terminal being coupled to a driving unit of the second scanning circuit, the control terminal coupled to the control unit, the output terminal coupled to the reference Positioning, the third transistor stabilizes the level of the control end of the driving unit of the second scanning circuit at the reference level; and a fourth transistor having an input end, a control end, and an output end The input end is coupled to the driving unit of the second scanning circuit, the control end is coupled to the control unit, the output end is coupled to the reference level, and the fourth transistor is configured to drive the driving unit of the second scanning circuit The level of one of the outputs is stabilized at the reference level.
一保護單元，具有一輸入端、一控制端及一輸出端，該輸入端耦接該第一電晶體、該第二電晶體、該第三電晶體與該第四電晶體，該控制端接收一第三時脈訊號，該輸出端耦接該參考準位，該保護單元依據該第三時脈訊號而週期性的將該第一電晶體、該第二電晶體、該第三電晶體與該第四電晶體的該控制端維持於該參考準位。The multi-output design of the single-stage gate driving circuit 1 as described in claim 6 of the patent application, wherein the anti-noise circuit comprises:
a protection unit having an input terminal, a control terminal and an output terminal, the input terminal being coupled to the first transistor, the second transistor, the third transistor and the fourth transistor, the control terminal receiving a third clock signal, the output end is coupled to the reference level, and the protection unit periodically periodically connects the first transistor, the second transistor, and the third transistor according to the third clock signal The control terminal of the fourth transistor is maintained at the reference level.
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