TWI584431B - 超薄半導體元件封裝結構的製造方法 - Google Patents

超薄半導體元件封裝結構的製造方法 Download PDF

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TWI584431B
TWI584431B TW104101993A TW104101993A TWI584431B TW I584431 B TWI584431 B TW I584431B TW 104101993 A TW104101993 A TW 104101993A TW 104101993 A TW104101993 A TW 104101993A TW I584431 B TWI584431 B TW I584431B
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Taiwan
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electrode
layer
semiconductor device
device package
package structure
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TW104101993A
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TW201628144A (zh
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謝智正
許修文
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尼克森微電子股份有限公司
帥群微電子股份有限公司
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Priority to TW104101993A priority Critical patent/TWI584431B/zh
Priority to US14/954,981 priority patent/US9881897B2/en
Publication of TW201628144A publication Critical patent/TW201628144A/zh
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Publication of TWI584431B publication Critical patent/TWI584431B/zh

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Description

超薄半導體元件封裝結構的製造方法
本發明係有關於一種半導體封裝製程，特別是指一種利用晶圓級晶片尺寸封裝製程來形成超薄半導體元件封裝結構的方法。
在晶圓級晶片尺寸封裝(Wafer Level Chip Scale Packaging,WLCSP)技術中，整片晶圓生產完成後可以直接對晶圓進行封裝，之後再將多個單顆晶粒從晶圓上予以分離，所以最終獲得的晶片的尺寸幾乎等同於原晶粒的大小。因此，當前的晶圓級封裝技術廣泛應用在功率元件的封裝。
另外，垂直型功率元件，如垂直型金氧半場效電晶體、絕緣閘雙極電晶體(IGBT)以及二極體等大都應用於電源電路中。然而，垂直型功率元件在導通狀態下，其功率損失發生電流垂直流動的路徑中。以垂直式金氧半場效電晶體為例，電流是由主動面的源極流向晶片背面的汲極。若能降低電流路徑中的電阻，就能提高效率。
隨著對電源效率的要求日趨嚴格，除了透過變更晶片結構設計與材料來提升電源效率之外，將晶片的基底薄化亦可降低電流路徑中的電阻而提高電源效率。在不影響機械結構以及崩潰電壓的情況下，減薄晶圓是用來降低垂直型功率元件的電阻的有效手段。但晶圓愈薄越容易發生翹曲，這會導致在運輸過程或是在製備流程中，晶圓容易破裂。
本發明實施例在於提供一種超薄半導體元件封裝結構的製造方法，其在施以薄化製程之前，先在晶圓主動面完成部分線路重分佈層，再將晶圓固定於一支撐治具上進行薄化，以避免晶圓在薄化後發生翹曲。
本發明其中一實施例所提供的一種超薄半導體元件封裝結構的製造方法，包括下列步驟。首先，提供一晶圓，晶圓包含多個半導體元件，其中多個半導體元件中的一第一半導體元件具有一主動面與一背面，且主動面具有一主動區與一外部區，所述主動區設有第一電極及第二電極，所述外部區區分為一切割部與一通道部。後續，形成圖案化保護層於主動面上，其中圖案化保護層具多個開口以暴露第一電極、第二電極以及外部區。接著，形成一開槽於所述通道部，其中開槽具有一第一深度，且第一深度小於晶圓的厚度。接著，形成一導電結構於開槽內。另外，提供一支撐治具，並將晶圓固定於支撐治具上，其中主動面是面向支撐治具而設置。隨後，執行一薄化製程於第一半導體元件背面，以暴露開槽內的導電結構，再將背電極層形成於第一半導體元件的背面。在移除支撐治具之後，形成多個外部接觸墊於所述第一電極、所述第二電極以及所述導電結構上，再沿切割部執行切割步驟。
本發明的有益效果在於，本發明實施例所提供的超薄半導體元件封裝結構的製造方法，其藉由在執行薄化製程之前，先完成部分線路重分佈層的製作，並且在薄化製程中，將晶圓固定於一支撐治具上，可避免晶圓在薄化後發生翹曲的機率，從而避免晶圓在後續製程中崩裂。另外，支撐治具是在完成背電極層的製作之後才移除，因此，在移除支撐治具之後，背電極層也可對晶圓提供支撐強度，可降低晶圓的破損率。
為使能更進一步瞭解本發明的特徵及技術內容，請參閱以下 有關本發明的詳細說明與附圖，然而所附圖式僅提供參考與說明用，並非用來對本發明加以限制者。
1‧‧‧第一半導體元件
10‧‧‧主動面
11、11’‧‧‧背面
103‧‧‧第一電極
104‧‧‧第二電極
101‧‧‧外部區
101h‧‧‧開槽
102‧‧‧主動區
101a‧‧‧切割部
101b‧‧‧通道部
12‧‧‧圖案化保護層
12a~12c‧‧‧開口
13‧‧‧第一光阻層
130‧‧‧圖案
19‧‧‧背電極層
20、20’‧‧‧導電結構
20a、20a’‧‧‧連接部
20b‧‧‧接觸墊
21‧‧‧第一接墊
22‧‧‧第二接墊
14‧‧‧金屬障壁層
15‧‧‧第二光阻層
16‧‧‧金屬導電結構
17‧‧‧金屬導電層
18‧‧‧介電層
18a~18d‧‧‧開口區
6‧‧‧支撐治具
60‧‧‧板體
61‧‧‧黏著層
7a~7c‧‧‧外部接觸墊
3‧‧‧導線架
30‧‧‧晶粒座
31‧‧‧框條
8‧‧‧金屬片
9‧‧‧導電膠
4、5‧‧‧切割線
M1、M2‧‧‧半導體元件封裝結構
W‧‧‧開槽寬度
h1‧‧‧第一深度
h2‧‧‧第二深度
T‧‧‧晶圓厚度
S100~S109‧‧‧流程步驟
圖1為本發明實施例的超薄半導體元件封裝結構的製造方法的流程圖。
圖2A至2M顯示本發明一實施例的超薄半導體元件封裝結構在各步驟中的局部剖面示意圖。
圖3A顯示本發明一實施例的超薄半導體元件封裝結構的剖面示意圖。
圖3B顯示本發明另一實施例的超薄半導體元件封裝結構的剖面示意圖。
圖4顯示圖3B的超薄半導體元件封裝結構放置於導線架的俯視示意圖。
請參閱圖1，其顯示本發明一實施例的超薄半導體元件封裝結構的製造方法的流程圖。請配合參照圖2A至圖2L，其顯示本發明實施例的超薄半導體元件封裝結構在各步驟中的局部剖面示意圖。
在步驟S100中，提供包含多個半導體元件的晶圓。構成晶圓的材料通常為矽，但也可以是其他半導體材料，例如砷化鎵。在本發明實施例中，晶圓的厚度大約是250至700μm。在本發明實施例中，晶圓已經完成元件製作的製程，且包括多個半導體元件。
本發明所提供的超薄半導體元件封裝結構的製造方法所形成的封裝結構中，只有一個半導體元件，例如僅包括第一半導體元件1。但在其他實施例中，也可以由兩個半導體元件形成一個封裝結構。因此，封裝結構中所包含的半導體元件的數量並不限制。本發明實施例中，第一半導體元件1為垂直式功率元件，例如是垂直式金氧半場效電晶體(MOSFET)。
請參照圖2A。圖2A中顯示晶圓的局部剖面示意圖，也就是第一半導體元件的局部剖面示意圖。第一半導體元件1具有一主動面10以及與主動面10相反的一背面11，其中第一半導體元件1的背面11為晶圓的背面的一部份。
第一半導體元件1在主動面10上定義出外部區101與主動區102。外部區101環繞主動區102，也就是位於第一半導體元件1的周邊區域。主動區102位於半導體元件1的中間區域，並且主動區102內配設有一第一電極103及一第二電極104。在本發明實施例中，第一電極103為閘極電極，而第二電極104為源極電極。
第一半導體元件1的外部區101可被區分為切割部101a及通道部101b。在本發明實施例中，是一個半導體元件對應一個通道部，或者是有多個半導體元件對應同一通道部，在本發明中不限制半導體元件與通道部之間的配置與對應關係。
接著進行步驟S101，形成圖案化保護層於主動面上。如圖2A中所示，第一半導體元件1的主動面10上已形成圖案化保護層12。圖案化保護層12可以是介電層，可保護第一半導體元件1的主動區102，以免主動區102在後續的製程中受到汙染，而影響元件特性。
圖案化保護層12具有複數個開口12a~12c。在本實施例中，開口12a~12c分別暴露第一半導體元件1的第一電極103、第二電極104以及外部區101。圖案化保護層12的材料可以是磷矽玻璃(phosphosilicate glass)、聚醯亞胺(polyimide)、氮化矽(silicon nitride)或是氧化矽(silicon oxide,SiO4)。在本實施例中，圖案化保護層12的厚度範圍大約介於0.5至5μm之間。
詳細而言，在本發明實施例中，第一半導體元件1的第一電極103與第二電極104的部分邊緣區域會被圖案化保護層12覆蓋，而第一電極103與第二電極104的中間區域則會分別通過開口12a與開口12b而裸露出來。另外，在本實施例中，圖案化保 護層12的開口12c是暴露第一半導體元件1的外部區101。在其他實施例中，若是在主動面10上已經形成保護層，則可省略步驟S101。請再參照圖1，在步驟S102中，形成開槽於通道部。請參照圖2B與圖2C，顯示本發明實施例的超薄半導體元件封裝結構在步驟S102中的剖面示意圖。在本實施例中，形成開槽101h於通道部101b的步驟是利用曝光、顯影及蝕刻製程來實現。詳細而言，如圖2B所示，先形成一第一光阻層13於第一半導體元件1的主動面10上，其中第一光阻層13的圖案130預先定義出開槽101h的位置。接著，如圖2C所示，利用蝕刻製程，例如濕式或乾式蝕刻製程，對第一半導體元件1進行蝕刻而形成開槽101h,其中開槽101h的位置位於通道部101b。然而，在其他實施例中，也可以利用機械切割或者是雷射切割，來形成開槽101h。
在本發明實施例中，開槽101h具有一第一深度h1，而第一深度h1是小於晶圓的厚度T。換言之，開槽101h為盲孔(blind hole)。當利用濕式蝕刻製程來形成開槽101h時，可透過調整蝕刻劑的種類、濃度和溫度來控制蝕刻速率，從而控制開槽101h的第一深度h1。在本發明實施例中，開槽101h的第一深度h1會根據薄化後晶圓的厚度來調整。在較佳實施例中，開槽101h的第一深度h1是大於薄化後晶圓的厚度。舉例而言，若預設薄化後晶圓的厚度為50μm，則開槽101h的第一深度h1大於50μm，較佳為60μm。
要特別說明的是，開槽101h在後續的製程中會填入導電結構以電性連接第一半導體元件1的汲極。若開槽101h的寬度W太小，不利於半導體元件封裝結構輸出大電流，若開槽101h的寬度W太寬，則會壓縮切割部101a的面積。因此，在本實施例中，開槽101h寬度W的範圍是介於5μm至50μm之間。形成開槽101h之後，將第一光阻層13去除。
請再參照圖1，在步驟S103中，形成導電結構於開槽內。請參照圖2D至圖2F，分別顯示本發明實施例的超薄半導體元件封 裝結構在步驟S103中的剖面示意圖。如圖2D所示，至少一金屬障壁層14形成於主動面10上。金屬障壁層14順形地覆蓋開槽101h的內側壁、圖案化保護層12、第一電極103與第二電極104。在本實施例中，是利用濺鍍的方式來形成金屬障壁層14，且構成金屬障壁層14的材質可選自由鈦、銅、鎢及其任意組合所組成的群組其中之一種。另外，金屬障壁層14的厚度可介於0.2μm至10μm。
請參照圖2E，接著形成第二光阻層15於金屬障壁層14上，其中第二光阻層15具有多個開口圖案(未標號)。第二光阻層15的多個開口圖案是分別對應定義第一電極103、第二電極104及開槽101h的位置，以分別用來定義在後續製程中所要形成的多個外部接觸墊的位置與形狀。
在一實施例中，外部區101的切割部101a會完全被第二光阻層15所覆蓋。並且，其中一開口圖案對應於開槽101h的的孔徑大於開槽101h的寬度W，以暴露開槽101h以及部分位於通道部101b與主動區102上的金屬障壁層14。第二光阻層15的多個開口圖案將定義出多個接觸墊的形狀與位置，而接觸墊將在後續製程中用以使第一半導體元件1和電路板上的電子元件電性連接。
繼續參照圖2E。如圖2E所示，接著形成金屬導電結構16於開槽101h中，並在第二光阻層15的多個開口圖案中形成金屬導電層17。詳細而言，金屬導電結構16會先填滿開槽101h，再分別在多個開口圖案所定義的位置形成金屬導電層17。在本實施例中，是採用電鍍的製程來形成金屬導電結構16與金屬導電層17,且金屬導電結構16與金屬導電層17的材料為銅、鎳或其他合金。金屬導電層17的厚度介於5至30μm。
接著，請參照圖2F，去除第二光阻層15以及第二光阻層15所覆蓋的金屬障壁層14，以形成第一接墊21、第二接墊22與導電結構20。導電結構20包括一連接部20a與一接觸墊20b。填入 開槽101h中的金屬障壁層14與金屬導電結構16共同形成連接部20a，而主動面10上的金屬障壁層14與金屬導電層17共同形成接觸墊20a。
接著，請參照圖2G，形成一介電層18於主動面10，其中介電層18具有多個開口區18a~18d，以分別暴露部分第一接墊21、部分第二接墊22、部分接觸墊20b以及切割部101a，其中開口區18a~18c分別在第一接墊21、第二接墊22與接觸墊20b上，定義在後續製程中所形成的多個電氣接點的位置。
另一方面，介電層18可用來輔助保護主動面10，且介電層18的材料可選擇聚醯亞胺(polyimide,PI)或是苯並環丁烯(benzocyclobutene,BCB)聚合物。在一實施例中，介電層18的厚度介於5至20μm。其中形成介電層18的步驟為選擇性步驟。在另一實施例中，形成介電層18的步驟也可以被省略。
請再參照圖1，在步驟S104中，提供一支撐治具，並將晶圓固定於支撐治具上，其中主動面面向支撐治具而設置。請參照圖2H，顯示本發明實施例的超薄半導體元件封裝結構在步驟S104中的剖面示意圖。
如圖2H所示，晶圓被固定於支撐治具6上時，第一半導體元件1的主動面10是面向支撐治具6而設置。另外，在本發明實施例中，支撐治具6包括一板體61及一黏著層60，當晶圓被固定在支撐治具6上時，黏著層60是形成於主動面10與板體61之間。也就是說，晶圓是藉由黏著層60連接於板體61，但黏著層60與金屬導電層17以及介電層18之間的結合力偏弱，因此當支撐治具6由晶圓上移除時，可以利用手或機器將支撐治具6與第一半導體元件1分離。
黏著層60可以是雙面膠帶或者是其他可剝離膠，例如紫外光固化膠、熱固化膠或金屬膠帶。在其他實施例中，黏著層60可以是能重複黏貼的感壓膠(pressure sensitive adhesives)，其例如是橡 膠系感壓膠、壓克力系感壓膠或矽氧樹脂(silicone)系感壓膠。
請再參照圖1，接著進行步驟S105。在步驟S105中，由背面執行一薄化製程，以暴露開槽內的導電結構。請參照圖2I，顯示本發明實施例的超薄半導體元件封裝結構在步驟S105中的剖面示意圖。薄化製程可以是機械式背面研磨製程，也就是利用機械磨薄機由第一半導體元件1的背面11進行薄化製程，直到開槽101h內的導電結構20’的連接部20a’由第一半導體元件1的底部露出。也就是說，在執行薄化製程之後，開槽101h由主動面10延伸至第一半導體元件1被研磨後的背面11’，並具有第二深度h2，其中第二深度h2即為薄化後第一半導體元件1的厚度，且第二深度h2是小於第一深度h1。
要說明的是，雖然在圖2I中僅繪示對第一半導體元件1的背面11執行薄化製程，然而熟知本技術領域之人員應可了解，進行薄化製程時，實際上是對整個晶圓的背面進行研磨，以將晶圓減薄至預定的厚度。在一實施例中，薄化後第一半導體元件1的厚度，也就是薄化後晶圓的厚度約50μm至60μm。
請接著參照圖1。在步驟S106中，形成背電極層於背面。詳細而言，請配合參照圖2J，圖2J顯示本發明實施例的超薄半導體元件封裝結構在步驟S106的剖面示意圖。如圖2J所示，背電極層19被形成於第一半導體元件1被研磨後的背面11’。在形成背電極層19時，可以利用物理氣相沉積法或者化學氣相沉積來形成背電極層19，其中物理氣相沉積法例如是蒸鍍或濺鍍，但並非用來限制本發明之範圍。
背電極層19可以是一導電材料層，以作為第一半導體元件1的汲極電極。在一實施例中，背電極層19為金屬疊層，例如是鈦/銅疊層，且背電極層19的厚度可以從幾微米至數百微米。在另一實施例中，背電極層19也可以是鈦/鎳/銀疊層，其中鈦層的厚度為200nm，鎳層的厚度約300nm，而銀層的厚度為2000nm。然 而，背電極層19的材料與結構並不限於前述的材料，也可以使用其他材料。
圖2J中繪示背電極層19形成於第一半導體元件1被研磨後的背面11’，然而本領域技術人員應可了解，實際上背電極層19是形成於薄化後晶圓的整個背面。
接著請參照圖1與圖2K，圖2K顯示本發明實施例的超薄半導體元件封裝結構在步驟S107中的剖面示意圖。在步驟S107中，移除支撐治具6。由於在移除支撐治具6之前，已先形成具有一定厚度的背電極層19，因此，背電極層19可以對薄化後的晶圓提供支撐力，以免在支撐治具6移除之後，晶圓因太薄而翹曲，從而可降低晶圓在後續製程或運送過程中破裂的機率。
當移除支撐治具6時，由於黏著層60與第一半導體元件1之間的結合力小於黏著層60與板體61之間的黏著力。因此，不須施加太大的外力即可使支撐治具6與第一半導體元件1分離。在移除支撐治具6之後，可以對第一半導體元件1執行一清潔步驟，以避免黏著層60殘留在第一半導體元件1的第一接墊21、第二接墊22或接觸墊20b上，而影響第一半導體元件1的電性。在另一實施例中，支撐治具6也可僅包括板體61，並且板體61可以其他方式固定於晶圓上。
在本發明實施例中，在移除支撐治具6之後，可以使用導電膠將一金屬片黏貼於背電極層19，以加強半導體元件封裝結構的散熱能力與機械支撐強度，並降低因背電極層19過厚所升高的成本。請參照圖2L，顯示本發明另一實施例的超薄半導體元件封裝結構在移除支撐治具的步驟之後的剖面示意圖。
本發明實施例的超薄半導體元件封裝結構的製造方法可包括以導電膠9將金屬片8貼附於背電極層19上，在這個實施例中，金屬片8的厚度大於背電極層19的厚度，且金屬片8也可用來電性連接第一半導體元件1的汲極。因此，相較於沒有貼附金屬片8 的實施例而言，本實施例的背電極層19可具有較薄的厚度。舉例而言，背電極層19的厚度可藉於2至3微米之間，而金屬片8的厚度是介於200μm至300μm。此外，金屬片8的尺寸可和晶圓尺寸相同。
然而，在其他實施例中，也可以利用其他方式來加強半導體元件封裝結構的散熱能力與機械支撐強度。因此，將金屬片8貼附於背電極層19的步驟為選擇性的步驟。
接著，參照圖1與圖2M。在步驟S108中，形成多個外部接觸墊於第一電極、第二電極以及導電結構上。詳細而言，如圖2M所示在主動面10之介電層18的開口區18a~18c，分別形成多個外部接觸墊7a~7c於第一接墊21、第二接墊22與接觸墊20b上，以電性連接於外部電路。形成這些外部接觸墊7a~7c的方式可以利用植球(solder ball)製程、柱凸塊(pillar bump)製程、焊料凸塊(solder bump)製程、電鍍製程或者是網版印刷焊料(screen printing solder paste)製程等技術手段。
請參照圖1，接著在步驟S109中，沿著切割部執行切割步驟，形成多個相互分離的半導體元件封裝結構。在一實施例中，是藉由晶粒切割機來執行切割步驟。外部區101的切割部101a並未形成導電結構20’，因此在執行切割步驟時，晶粒切割機的刀具較不需要對金屬材進行切割，較不容易損耗。另外，在其他實施例中也可利用雷射進行切割。
另外，如圖3A所示，執行切割步驟之後，形成多個相互分離的半導體元件封裝結構M1，其中位於半導體元件封裝結構M1背面的汲極可透過背電極層19與導電結構20’而電性連接於位於主動面10的外部接觸墊7c。當半導體元件封裝結構M1組裝於電路板(未圖示)時，是以主動面10朝向電路板設置。因此，半導體元件封裝結構M1背面的汲極可透過外部接觸墊7c電性連接位於相反側的電路板。如前所述，在另一實施例中，當省略貼附金屬片8 於背電極層19的步驟時，在執行切割步驟之後，形成多個相互分離的半導體元件封裝結構M2，如圖3B所示。由於半導體元件封裝結構M2並未具有金屬片8，因此，可利用其他方式來輔助半導體元件封裝結構M2散熱以及提供支撐強度。
請參照圖4,顯示本發明另一實施例的半導體元件封裝結構放置於導線架的俯視示意圖。半導體元件封裝結構例如是圖3B所示的半導體元件封裝結構M2。另外，本發明實施例的超薄半導體元件封裝結構的製程方法可以更包括下列步驟： 首先，提供一導線架3。詳細而言，導線架3包括多個晶粒座30，且每一晶粒座30具有一表面，以接觸半導體元件封裝結構M1，如圖4所示。
接著，將切割後的每一半導體元件封裝結構M2以一導熱膠材分別固設於晶粒座30上。詳細而言，在將半導體元件封裝結構M1放置於晶粒座30之前，先在晶粒座30的表面塗佈導熱膠材，而導熱膠材例如是導電膠、絕緣導熱膠或者是錫膏。接著，可利用晶粒拾取機將已切割的每一半導體元件封裝結構M2分別放置在這些晶粒座30上。
隨後，施以一加熱製程，使導熱膠材固化，從而使半導體元件封裝結構M2固定於晶粒座30上。在加熱製程中，可將整個導線架3放入烤箱中進行加熱。最後，切割導線架3，以將多個晶粒座30由導線架3上分離。
在本實施例中，如圖4所示，導線架3具有用來固定每一晶粒座30的多個框條31。當要將多個晶粒座30由導線架3上分離時，可直接利用刀具沿著圖4中所示的切割線5，將框條31切斷，即可使晶粒座30相互分離，而得到最後的成品。
切割後的半導體元件封裝結構M2的厚度較薄，導線架3的晶粒座30可對半導體元件封裝結構M2提供保護，以免在運送過程中破裂。此外，晶粒座30也可使半導體元件封裝結構M2更容易 散熱。
〔實施例的可能功效〕
綜上所述，本發明的有益效果可以在於，本發明實施例所提供的超薄半導體元件封裝結構的製造方法，其藉由在執行薄化製程之前，先完成部分線路重分佈層的製作，並且在薄化製程中，將晶圓固定於一支撐治具上，可避免晶圓在薄化後發生翹曲的機率，從而避免晶圓在後續製程中崩裂。
另外，支撐治具是在完成背電極層的製作之後才移除，因此，在移除支撐治具之後，背電極層也可對晶圓提供支撐強度，可降低晶圓的破損率。
另外，本發明實施例的半導體元件封裝結構會再以導熱膠材被固定於晶粒座上，或者是在執行切割步驟之前先貼附金屬片於背電極層上。據此，晶粒座與金屬片可強化半導體元件封裝結構的機械強度。除此之外，藉由導熱膠材及晶粒座，或者是藉由導電膠與金屬片，可將半導體元件封裝結構在運作時所產生的熱散出，以盡量避免半導體元件封裝結構的性能因高溫而受到影響。
以上所述僅為本發明的較佳可行實施例，非因此侷限本發明的專利範圍，故舉凡運用本發明說明書及圖式內容所做的等效技術變化，均包含於本發明的保護範圍內。
S100~S109‧‧‧流程步驟

Claims (11)

  1. 一種超薄半導體元件封裝結構的製造方法，其包括：提供一晶圓，有多個半導體元件，其中所述多個半導體元件中的一第一半導體元件具有一主動面與相對於所述主動面的一背面，且所述主動面具有一主動區與一外部區，所述主動區設有一第一電極及一第二電極，所述外部區區分為一切割部與一通道部；形成一圖案化保護層於所述主動面上，所述圖案化保護層具有多個開口以暴露所述第一電極、所述第二電極以及所述外部區；形成一開槽於所述通道部，其中所述開槽具有一第一深度，且所述第一深度小於所述晶圓的厚度；形成一導電結構於所述開槽內；提供一支撐治具，並固定所述晶圓於所述支撐治具上，其中所述主動面面向所述支撐治具設置；執行一薄化製程於所述背面，以暴露所述開槽內的所述導電結構；形成一背電極層於所述背面；移除所述支撐治具；形成多個外部接觸墊於所述第一電極、所述第二電極以及所述導電結構上；以及沿所述切割部執行一切割步驟。
  2. 如請求項1所述的超薄半導體元件封裝結構的製造方法，其中在執行所述薄化製程後，所述開槽具有一第二深度，且所述第二深度小於所述第一深度。
  3. 如請求項1所述的超薄半導體元件封裝結構的製造方法，其中所述第一電極為閘極電極、所述第二電極為源極電極且所述背 電極層為汲極電極。
  4. 如請求項1所述的超薄半導體元件封裝結構的製造方法，其中所述支撐治具包括一板體與一黏著層，當所述晶圓被固定於所述支撐治具時，所述黏著層形成於所述主動面與所述板體之間。
  5. 如請求項1所述的超薄半導體元件封裝結構的製造方法，其中在形成一開槽於所述通道部之後，更包括：形成一金屬障壁層順形地覆蓋所述開槽的內側壁、所述圖案化保護層、所述第一電極與所述第二電極；形成一光阻層於所述金屬障壁層上，其中所述光阻層具有多個開口圖案，分別對應定義所述第一電極、所述第二電極以及所述通道部的位置；形成一金屬導電結構填入所述開槽內，並形成一金屬導電層於多個所述開口圖案中；以及去除所述光阻層及所述光阻層覆蓋的所述金屬障壁層，以形成一第一接墊、一第二接墊及該導電結構。
  6. 如請求項5所述的超薄半導體元件封裝結構的製造方法，其中所述導電結構包括位於所述主動面上的一接觸墊與位於所述開槽中的一連接部。
  7. 如請求項5所述的超薄半導體元件封裝結構的製造方法，其中在形成所述第一接墊、第二接墊與所述導電結構之後，且在將所述晶圓固定於所述支撐治具之前，更包括：形成一介電層於所述主動面上，其中所述介電層具有多個開口區，以暴露部分所述第一接墊、部分所述第二接墊、部分所述接觸墊及所述切割部。
  8. 如請求項7所述的超薄半導體元件封裝結構的製造方法，在形成所述介電層於所述主動面之後，更包括透過多個所述開口 區，分別在所述第一接墊、所述第二接墊及所述接觸墊上形成形成多個所述外部接觸墊。
  9. 如請求項5所述的超薄半導體元件封裝結構的製造方法，其中所述金屬障壁層的材料可選自由鈦、銅、鎢及其任意組合所組成的群組其中之一種。
  10. 如請求項1所述的超薄半導體元件封裝結構的製造方法，其中在移除所述支撐治具的步驟後，且在執行所述切割步驟之前，更包括以一導電膠將一金屬片貼附於所述背電極層上。
  11. 如請求項1所述的超薄半導體元件封裝結構的製造方法，在執行所述切割步驟之後，形成多個相互分離的半導體元件封裝結構，且所述製造方法更包括：提供一導線架，所述導線架包括多個晶粒座；將已切割的所述每一半導體元件封裝結構以一導熱膠材分別固設於多個所述晶粒座上；以及切割所述導線架，以將多個所述晶粒座由所述導線架上分離。
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