TWI583035B - Multi-layer memory array and manufacturing method of the same - Google Patents
Multi-layer memory array and manufacturing method of the same Download PDFInfo
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Description
本揭露書是有關於一種多層記憶體陣列及其製作方法。特別是有關於一種包含硬罩幕層的多層記憶體陣列。 The present disclosure relates to a multilayer memory array and a method of fabricating the same. In particular, there is a multilayer memory array that includes a hard mask layer.
三維多層記憶體陣列係由複數個彼此平行的脊狀多層疊層(ridge-shaped multi-layer stacks)所構成。當三維多層記憶體陣列的尺寸縮小時，多層疊層的密度會增加，且多層疊層的深寬比(aspect ratio即，高度對寬度的比值)也會提高。製作深寬比漸增的脊狀多層疊層出現了許多挑戰。 The three-dimensional multilayer memory array is composed of a plurality of ridge-shaped multi-layer stacks that are parallel to each other. When the size of the three-dimensional multilayer memory array is reduced, the density of the multilayer laminate is increased, and the aspect ratio (height ratio of height to width) of the multilayer laminate is also increased. There are many challenges in making ridge multilayer laminates with increasing aspect ratios.
根據本說明書的一實施例，提供一種記憶體陣列的製作方法，其包括：於基材的表面上形成多層疊層，並且形成複數個第一通孔，沿著多層疊層的垂直方向，由多層疊層的頂部表面到基材的表面貫穿多層疊層。這些第一通孔以等距的方式沿著基 材之表面的第一方向配置成行(row)，並且以等距的方式沿著與第一方向直交(orthogonal)的第二方向配置成列(column)。這個方法還包括，形成複數個犧牲柱狀體填充這些第一通孔，並且在具有這些犧牲柱狀體的多層疊層上形成硬罩幕層。此硬罩幕層具有複數個硬罩幕通孔，可將多層疊層位於每一列這些犧牲柱狀體中相鄰之犧牲柱狀體之間的多個區域暴露於外。此方法更包括，形成複數個第二通孔，沿著多層疊層的垂直方向，由多層疊層的頂部表面到基材的表面貫穿多層疊層，以及移除填充於第一通孔中的犧牲柱狀體。這些第二通孔垂直地對準這些硬罩幕通孔。第二通孔連接第一通孔而形成沿著第二方向延伸的複數個溝槽。這些溝槽將多層疊層區隔成沿著第二方向延伸的複數個脊狀疊層。 According to an embodiment of the present specification, a method of fabricating a memory array is provided, comprising: forming a multilayer stack on a surface of a substrate, and forming a plurality of first vias along a vertical direction of the multilayer stack, The top surface of the multilayer laminate to the surface of the substrate extends through the multilayer stack. These first through holes are along the base in an equidistant manner The first direction of the surface of the material is arranged in rows and arranged in an equidistant manner along a second direction orthogonal to the first direction. The method also includes forming a plurality of sacrificial cylinders to fill the first vias and forming a hard mask layer on the multilayer stack having the sacrificial pillars. The hard mask layer has a plurality of hard mask vias that expose a plurality of regions of the multilayer stack between adjacent sacrificial cylinders in each of the sacrificial columns. The method further includes forming a plurality of second vias extending through the plurality of layers from the top surface of the multilayer stack to the surface of the substrate along the vertical direction of the multilayer stack, and removing the filling in the first via hole Sacrifice the columnar body. These second through holes are vertically aligned with the hard mask through holes. The second via connects the first via to form a plurality of trenches extending along the second direction. The trenches separate the multilayer stack into a plurality of ridge stacks extending in a second direction.
根據本說明書的另一實施例，提供一種記憶體陣列，其包括：沿著第一方向延伸的複數個脊狀多層疊層以及形成於複數個脊狀多層疊層頂部的硬罩幕層。此硬罩幕層包括：分別垂直地對準複數個脊狀多層疊層的複數個條帶，分別沿著與第一方向直交的第二方向連結相鄰之條帶的複數個連接橋以及位於複數個連接橋與複數個條帶之間的複數個硬罩幕通孔。此記憶體陣列更包括位於複數個脊狀多層疊層之間的多個溝槽中，並且覆蓋脊狀多層疊層之多個側壁的記憶體層；位於這些溝槽之中，沿著脊狀多層疊層的垂直方向延伸，且分別垂直地對準複數個硬罩幕通孔的複數個導電柱狀體以及位於硬罩幕層上，且沿著第二方向延伸的複數個導電條帶。這些導電條帶與這些導電柱狀體沿著 第二方向形成的一行電性連接。 In accordance with another embodiment of the present specification, a memory array is provided that includes a plurality of ridge multilayer laminates extending along a first direction and a hard mask layer formed on top of the plurality of ridge multilayer laminates. The hard mask layer comprises: a plurality of strips respectively vertically aligned with the plurality of ridge-shaped multilayer stacks, respectively connecting a plurality of connecting bridges adjacent to the adjacent strips in a second direction orthogonal to the first direction and located A plurality of hard mask through holes between a plurality of connecting bridges and a plurality of strips. The memory array further includes a plurality of trenches between the plurality of ridge-like multilayer stacks and covering the memory layers of the plurality of sidewalls of the ridge multilayer stack; among the trenches, along the ridges The stacked layers extend in a vertical direction and respectively vertically align a plurality of conductive pillars of the plurality of hard mask vias and a plurality of conductive strips on the hard mask layer and extending along the second direction. These conductive strips along with these conductive pillars A row of electrical connections formed in the second direction.
根據本說明書的又一實施例，提供一種記憶體陣列，其包括：沿著第一方向延伸的複數個脊狀疊層以及形成於複數個脊狀多層疊層頂部的硬罩幕層。此硬罩幕層包括：分別垂直地對準複數個脊狀多層疊層的複數個條帶以及分別沿著與第一方向直交的第二方向連結相鄰之條帶的複數個連接橋。此記憶體陣列更包括：位於複數個脊狀多層疊層之間的多個溝槽中，並且覆蓋脊狀多層疊層之多個側壁的記憶體層；位於這些溝槽之中，沿著脊狀多層疊層的垂直方向延伸的複數個導電柱狀體以及位於硬罩幕層上，且沿著第二方向延伸的複數個導電條帶。其中這些導電柱狀體沿著第二方向所形成的每一行與多於一個導電條帶重疊並且相互連接。 In accordance with yet another embodiment of the present specification, a memory array is provided that includes a plurality of ridge stacks extending along a first direction and a hard mask layer formed on top of the plurality of ridge multilayer laminates. The hard mask layer includes a plurality of strips vertically aligned with a plurality of ridge-like multilayer stacks, and a plurality of connecting bridges respectively joining adjacent strips along a second direction orthogonal to the first direction. The memory array further includes: a memory layer in a plurality of trenches between the plurality of ridge multilayer laminates and covering a plurality of sidewalls of the ridge multilayer laminate; among the trenches, along the ridges a plurality of conductive pillars extending in a vertical direction of the multilayer stack and a plurality of conductive strips on the hard mask layer extending along the second direction. Each of the rows of the conductive pillars formed along the second direction overlaps and is connected to each other with more than one conductive strip.
1‧‧‧製程構造 1‧‧‧Process construction
2‧‧‧製程構造 2‧‧‧Process construction
3‧‧‧製程構造 3‧‧‧Process construction
4‧‧‧製程構造 4‧‧‧Process construction
5‧‧‧製程構造 5‧‧‧Process construction
6‧‧‧製程構造 6‧‧‧Process construction
7‧‧‧製程構造 7‧‧‧Process construction
8‧‧‧製程構造 8‧‧‧Process construction
9‧‧‧製程構造 9‧‧‧Process construction
10‧‧‧製程構造 10‧‧‧Process construction
11‧‧‧製程構造 11‧‧‧Process construction
12‧‧‧製程構造 12‧‧‧Process construction
12’‧‧‧製程構造 12’‧‧‧Process construction
100‧‧‧基材 100‧‧‧Substrate
100a‧‧‧基材 100a‧‧‧Substrate
110‧‧‧多層疊層 110‧‧‧Multilayer laminate
110’‧‧‧脊狀疊層 110’‧‧‧ ridge stack
110a‧‧‧通孔 110a‧‧‧through hole
110b‧‧‧通孔 110b‧‧‧through hole
110c‧‧‧溝槽 110c‧‧‧ trench
111‧‧‧導電層 111‧‧‧ Conductive layer
112‧‧‧導電層 112‧‧‧ Conductive layer
113‧‧‧導電層 113‧‧‧ Conductive layer
114‧‧‧導電層 114‧‧‧ Conductive layer
115‧‧‧導電層 115‧‧‧ Conductive layer
116‧‧‧導電層 116‧‧‧ Conductive layer
117‧‧‧導電層 117‧‧‧ Conductive layer
118‧‧‧導電層 118‧‧‧ Conductive layer
121‧‧‧絕緣層 121‧‧‧Insulation
122‧‧‧絕緣層 122‧‧‧Insulation
123‧‧‧絕緣層 123‧‧‧Insulation
124‧‧‧絕緣層 124‧‧‧Insulation
125‧‧‧絕緣層 125‧‧‧Insulation
126‧‧‧絕緣層 126‧‧‧Insulation
127‧‧‧絕緣層 127‧‧‧Insulation
128‧‧‧絕緣層 128‧‧‧Insulation
130‧‧‧硬罩幕層 130‧‧‧hard mask layer
130a‧‧‧通孔 130a‧‧‧through hole
140‧‧‧犧牲柱體 140‧‧‧ Sacrifice cylinder
150‧‧‧硬罩幕層 150‧‧‧hard mask layer
150a‧‧‧條帶 150a‧‧‧
150b‧‧‧連接橋 150b‧‧‧Connected Bridge
150c‧‧‧通孔 150c‧‧‧through hole
155‧‧‧罩幕層 155‧‧‧ Cover layer
155a‧‧‧條帶 155a‧‧‧
155b‧‧‧連接橋 155b‧‧‧Connected Bridge
155b’‧‧‧連接橋 155b’‧‧‧ Connection Bridge
155c’‧‧‧通孔 155c’‧‧‧through hole
160‧‧‧記憶體層 160‧‧‧ memory layer
170‧‧‧導電脊狀部 170‧‧‧ Conductive ridge
170a‧‧‧導電柱狀體 170a‧‧‧conductive columnar body
170a’‧‧‧導電柱狀體 170a’‧‧‧ conductive columnar body
180‧‧‧導電層 180‧‧‧ Conductive layer
180a‧‧‧條帶 180a‧‧‧
180a’‧‧‧條帶 180a’‧‧‧
190‧‧‧硬罩幕層 190‧‧‧hard mask layer
190a‧‧‧條帶 190a‧‧‧
190b‧‧‧連接橋 190b‧‧‧Connected Bridge
190c‧‧‧通孔 190c‧‧‧through hole
200‧‧‧通孔 200‧‧‧through hole
200’‧‧‧通孔 200’‧‧‧through hole
d2‧‧‧距離 D2‧‧‧ distance
d2‧‧‧距離 D2‧‧‧ distance
B-B’‧‧‧切線 B-B’‧‧‧ tangent
C-C’‧‧‧切線 C-C’‧‧‧ tangent
D-D’‧‧‧切線 D-D’‧‧‧ tangent
第1圖係根據本說明書的一實施例之記憶體陣列初步製程階段中的製程構造所繪示的結構透視圖。 1 is a perspective view of a structure depicted in a process configuration in a preliminary process stage of a memory array in accordance with an embodiment of the present specification.
第2A圖至第2C圖係根據本說明書前述實施例之第1圖後續製程階段中的製程構造所繪示的結構示意圖。 2A to 2C are schematic views showing the structure of the process in the subsequent process stage according to the first embodiment of the foregoing embodiment of the present specification.
第3A圖至第3C圖係根據本說明書的前述實施例第2A圖至第2C圖之後續製程階段中的製程構造所繪示的結構示意圖。 3A to 3C are schematic views showing the structure of the process in the subsequent process stages according to the second embodiment to the second embodiment of the present embodiment.
第4A圖至第4C圖係根據本說明書的前述實施例第3A圖至第3C圖之後續製程階段中的製程構造所繪示的結構示意圖。 4A to 4C are schematic views showing the structure of the process in the subsequent process stages according to the third embodiment to the third embodiment of the foregoing embodiment of the present specification.
第5A圖至第5C圖係根據本說明書前述實施例第4A圖至第 4C圖之後續製程階段中的製程構造所繪示的結構示意圖。 5A to 5C are diagrams 4A to 3 according to the foregoing embodiment of the present specification A schematic diagram of the structure depicted in the process construction in the subsequent process stages of the 4C diagram.
第6A圖至第6C圖係根據本說明書前述實施例第5A圖至第5C圖之後續製程階段中的製程構造所繪示的結構示意圖。 6A to 6C are schematic views showing the structure of the process in the subsequent process stages according to the fifth embodiment to the fifth embodiment of the foregoing embodiment of the present specification.
第6D圖係根據本說明書的另一實施例第5A圖至第5C圖之後續製程階段中的製程構造所繪示的結構上視圖。 Fig. 6D is a structural top view showing the process configuration in the subsequent process stages of Figs. 5A to 5C of another embodiment of the present specification.
第7A圖至第7C圖係根據本說明書的前述實施例第6A圖至第6C圖之後續製程階段中的製程構造所繪示的結構示意圖。 7A to 7C are schematic views showing the structure of the process in the subsequent process stages according to the sixth embodiment to the sixth embodiment of the foregoing embodiment of the present specification.
第8A圖至第8E圖係根據本說明書的前述實施例第7A圖至第7C圖之後續製程階段中的製程構造所繪示的結構示意圖。 8A to 8E are schematic views showing the structure of the process in the subsequent process stages according to the seventh embodiment to the seventh embodiment of the foregoing embodiment of the present specification.
第9A圖至第9D圖係根據本說明書的前述實施例第8A圖至第8E圖之後續製程階段中的製程構造所繪示的結構示意圖。 9A to 9D are schematic views showing the structure of the process in the subsequent process stages according to the eighth embodiment to the eighth embodiment of the foregoing embodiment of the present specification.
第10A圖至第10C圖係根據本說明書的前述實施例第9A圖至第9D圖之後續製程階段中的製程構造所繪示的結構示意圖。 10A to 10C are schematic views showing the structure of the process in the subsequent process stages according to the 9A to 9D drawings of the foregoing embodiment of the present specification.
第11A圖至第11D圖係根據本說明書的前述實施例第10A圖至第10C圖之後續製程階段中的製程構造所繪示的結構示意圖。 11A to 11D are schematic views showing the structure of the process in the subsequent process stages according to the 10A to 10C drawings of the foregoing embodiment of the present specification.
第12A圖至第12E圖圖係根據本說明書的前述實施例第11A圖至第11D圖之後續製程階段中的製程構造所繪示的結構示意圖。 12A to 12E are schematic views showing the structure of the process in the subsequent process stages according to the 11Ath to 11thth drawings of the foregoing embodiment of the present specification.
第13圖係根據本說明書的又一實施例之記憶體陣列最終製程階段中的製程構造所繪示的結構透視圖。 Figure 13 is a perspective view of the structure depicted in a process configuration in a final process stage of a memory array in accordance with yet another embodiment of the present specification.
以下配合圖式提供本技術實施例的詳細說明。可能的話，圖式中所有相同的元件符號將用來代表相同或相似的元件。 The detailed description of the embodiments of the present technology is provided below in conjunction with the drawings. All the same component symbols in the drawings will be used to represent the same or similar components.
第1圖係根據本說明書的一實施例繪示記憶體陣列初步製程階段中之製程構造1的結構透視圖。請參照第1圖，多層疊層110形成於基材100上。疊層110包括複數個導電層111-118以及複數個絕緣層121-128。絕緣層121-128與導電層111-118沿著第1圖所繪示的Z軸方向，在基材100上彼此交錯堆疊，使導電層111位於疊層110的底層，而絕緣層128位於疊層110的頂層。導電層111-118可以由導電半導體材料，例如n型多晶矽，或n型磊晶單晶矽所構成，其摻雜有摻雜濃度介於約1017到1020atoms/cm3(原子數/立方公分)的磷或砷。此外，導電層111-118也可以由p型多晶矽，或p型磊晶單晶矽所構成，其摻雜有摻雜濃度介於約1017到1020atoms/cm3的硼。另一方面，導電層111-118也可以由無摻雜的半導體材料，例如無摻雜的多晶矽，所構成。當導電層111-118係由無摻雜多晶矽所構成時，無摻雜多晶矽的晶粒尺寸(grain size)可以介於約400奈米(nm)到600奈米之間；無摻雜多晶矽的片電阻(sheet resistance)可以介於約107 ohm/square到1011 ohm/square之間。導電層111-118每一者的厚度可以介於約30奈米到40奈米之間。絕緣層121-128可以由介電材料，例如矽氧化物(oxide)、矽氮化物(nitride)、矽氮氧化物(oxynitride)、矽酸鹽(silicate)或其他材料，所構成。絕緣 層121-128每一者的厚度可以介於約20奈米到40奈米之間。導電層111-118和絕緣層121-128可藉由，例如低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition，LPCVD)製程，製作而成。 1 is a perspective view showing the structure of a process configuration 1 in a preliminary process stage of a memory array in accordance with an embodiment of the present specification. Referring to FIG. 1, a multilayer laminate 110 is formed on a substrate 100. Stack 110 includes a plurality of conductive layers 111-118 and a plurality of insulating layers 121-128. The insulating layers 121-128 and the conductive layers 111-118 are staggered on the substrate 100 along the Z-axis direction depicted in FIG. 1 such that the conductive layer 111 is located on the bottom layer of the laminate 110, and the insulating layer 128 is located on the stack. The top layer of layer 110. The conductive layers 111-118 may be composed of a conductive semiconductor material such as an n-type polysilicon or an n-type epitaxial single crystal germanium doped with a doping concentration of about 10 17 to 10 20 atoms/cm 3 (atoms/ Cubic or arsenic of cubic centimeters. Further, the conductive layers 111-118 may also be composed of p-type polycrystalline germanium or p-type epitaxial single crystal germanium doped with boron having a doping concentration of about 10 17 to 10 20 atoms/cm 3 . On the other hand, the conductive layers 111-118 may also be composed of an undoped semiconductor material, such as an undoped polysilicon. When the conductive layers 111-118 are composed of undoped polysilicon, the grain size of the undoped polysilicon may be between about 400 nm (nm) and 600 nm; undoped polysilicon The sheet resistance can be between about 10 7 ohm/square to 10 11 ohm/square. The thickness of each of the conductive layers 111-118 can be between about 30 nm and 40 nm. The insulating layers 121-128 may be composed of a dielectric material such as an oxide, a nitride, an oxynitride, a silicate or other materials. The thickness of each of the insulating layers 121-128 may be between about 20 nm and 40 nm. The conductive layers 111-118 and the insulating layers 121-128 can be fabricated by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) process.
第2A圖至第2C圖係根據本說明書的前述實施例第1圖之後續製程階段中的製程構造2所繪示的結構示意圖。第2A圖係繪示製程構造2的上視圖。第2B圖係沿著第2A圖的切線B-B’所繪示之製程構造2的剖面圖。第2C圖係沿著第2A圖的切線C-C’所繪示之製程構造2的剖面圖。請參照第2A圖至第2C圖，圖案化硬罩幕層130係形成於疊層110之上，意即是，形成於絕緣層128的頂部表面。圖案化硬罩幕層130包括複數個沿著Z軸方向延伸的通孔130a。通孔130a沿著X軸方向配置成行；沿著Y軸方向配置成列。每一通孔都以具有相同尺寸的方孔型式來形成。通孔130a的每一行都以相同距離d1彼此相隔；通孔130a的每一列都以相同距離d2彼此相隔。距離d1可以等於距離d2。硬罩幕層130可以包括先進圖案化膜(Advanced Patterning Film，APF)，且可以藉由在疊層110的整個頂部表面沉積此一先進圖案化膜的化學氣相沉積(Chemical Vapor Deposition，CVD)製程、用來於先進圖案化膜上定義出要形成通孔130a之部分的光微影(photolithography)製程以及用來移除定義部分的蝕刻製程來形成。 2A to 2C are schematic views showing the structure of the process structure 2 in the subsequent process stage according to the first embodiment of the present embodiment. Fig. 2A is a top view showing the process structure 2. Fig. 2B is a cross-sectional view of the process structure 2 taken along the line B-B' of Fig. 2A. Fig. 2C is a cross-sectional view of the process structure 2 taken along the line C-C' of Fig. 2A. Referring to FIGS. 2A-2C, a patterned hard mask layer 130 is formed over the stack 110, that is, formed on the top surface of the insulating layer 128. The patterned hard mask layer 130 includes a plurality of through holes 130a extending in the Z-axis direction. The through holes 130a are arranged in a row along the X-axis direction, and are arranged in a row along the Y-axis direction. Each of the through holes is formed in a square hole pattern having the same size. Each row of the through holes 130a is spaced apart from each other by the same distance d1; each column of the through holes 130a is spaced apart from each other by the same distance d2. The distance d1 can be equal to the distance d2. The hard mask layer 130 may include an Advanced Patterning Film (APF), and may be deposited by chemical vapor deposition (CVD) of the advanced patterned film on the entire top surface of the layer 110. The process, an optical lithography process for defining a portion of the via 130a to be formed on the advanced patterned film, and an etching process for removing the defined portion are formed.
第3A圖至第3C圖係根據本說明書的前述實施例第 2A圖至第2C圖之後續製程階段中的製程構造3所繪示的結構示意圖。第3A圖係繪示製程構造3的上視圖。第3B圖係沿著第3A圖的切線B-B’所繪示之製程構造3的剖面圖。第3C圖係沿著第3A圖的切線C-C’所繪示之製程構造3的剖面圖。請參照第3A圖至第3C圖，以硬罩幕層130為蝕刻罩幕對疊層110進行蝕刻，以形成沿著Z軸方向延伸的通孔110a，直到將基材100的部分區域經由通孔110a曝露於外為止。在第3B圖中，為了更清楚呈現通孔110a，並未將位於通孔110a後方的疊層110未蝕刻的部分繪示出來。每一通孔110a分別垂直地對準一個通孔130a。疊層110可藉由非等向蝕刻製程(anisotropic etching process)，例如反應離子蝕刻(Reactive Ion Etching，RIE)製程，來加以蝕刻。在蝕刻製程之後，移除硬罩幕層130。雖然在第3A圖所繪示的上視圖中，通孔110a為方形，但該領域中具有通常知識者可以理解，實際上，通孔110a的上視圖可能因為形成通孔110a的非等向蝕刻製程對通孔110a的側壁進行圓化(rounding)而呈現圓形。 3A to 3C are diagrams according to the foregoing embodiment of the present specification 2 is a schematic diagram showing the structure of the process structure 3 in the subsequent process stages of FIG. 2A to FIG. 2C. Figure 3A is a top view showing the process configuration 3. Fig. 3B is a cross-sectional view of the process structure 3 taken along the tangential line B-B' of Fig. 3A. Figure 3C is a cross-sectional view of the process structure 3 taken along the line C-C' of Figure 3A. Referring to FIGS. 3A to 3C, the laminate 110 is etched with the hard mask layer 130 as an etching mask to form the via hole 110a extending along the Z-axis direction until a portion of the substrate 100 is passed through. The hole 110a is exposed to the outside. In Fig. 3B, in order to present the via hole 110a more clearly, the unetched portion of the laminate 110 located behind the via hole 110a is not shown. Each of the through holes 110a is vertically aligned with one through hole 130a. The laminate 110 can be etched by an anisotropic etching process, such as a reactive ion etch (RIE) process. After the etching process, the hard mask layer 130 is removed. Although the through hole 110a is square in the upper view depicted in FIG. 3A, it will be understood by those of ordinary skill in the art that, in fact, the upper view of the via hole 110a may be due to the non-isotropic etching of the via hole 110a. The process rounds the side walls of the through holes 110a to form a circular shape.
第4A圖至第4C圖係根據本說明書的前述實施例第3A圖至第3C圖之後續製程階段中的製程構造4所繪示的結構示意圖。第4A圖係繪示製程構造4的上視圖。第4B圖係沿著第4A圖的切線B-B’所繪示之製程構造4的剖面圖。第4C圖係沿著第4A圖的切線C-C所繪示之製程構造4的剖面圖。請參照第4A圖至第4C圖，多個犧牲柱體140形成於對應的通孔110a之中。犧牲柱體140可以由氮化矽(Si3N4)所構成。這是因為氮化 矽具有較佳的蝕刻選擇特性(selectivity)且具有可承受由後續濕式清潔製程所使用之濕式清潔溶液所造成之毛細管作用力(capillary force)的強度。犧牲柱體140可以藉由用來沉積氮化矽層以覆蓋絕緣層128的頂部表面並填充通孔110a的低壓化學氣相沉積製程，以及用來移除覆蓋絕緣層128的頂部表面之氮化矽層上方部分，直到將絕緣層128的頂部表面曝露於外的回蝕製程來形成。 4A to 4C are schematic views showing the structure of the process structure 4 in the subsequent process stages according to the third embodiment to the third embodiment of the foregoing embodiment of the present specification. Figure 4A is a top view showing the process configuration 4. Figure 4B is a cross-sectional view of the process structure 4 taken along line BB' of Figure 4A. Figure 4C is a cross-sectional view of the process structure 4 taken along line CC of Figure 4A. Referring to FIGS. 4A to 4C, a plurality of sacrificial pillars 140 are formed in the corresponding through holes 110a. The sacrificial cylinder 140 may be composed of tantalum nitride (Si 3 N 4 ). This is because tantalum nitride has better etch selectivity and has the strength to withstand the capillary force caused by the wet cleaning solution used in subsequent wet cleaning processes. The sacrificial pillar 140 may be nitrided by a low pressure chemical vapor deposition process for depositing a tantalum nitride layer to cover the top surface of the insulating layer 128 and filling the via hole 110a, and for removing nitridation of the top surface of the capping insulating layer 128. The upper portion of the germanium layer is formed until the top surface of the insulating layer 128 is exposed to an etch back process.
第5A圖至第5C圖係根據本說明書的前述實施例第4A圖至第4C圖之後續製程階段中的製程構造5所繪示的結構示意圖。第5A圖係繪示製程構造5的上視圖。第5B圖係沿著第5A圖的切線B-B’所繪示之製程構造5的剖面圖。第5C圖係沿著第5A圖的切線C-C’所繪示之製程構造5的剖面圖。請參照第5A圖至第5C圖，硬罩幕層150形成在第4A圖至第4C圖所繪示的整個製程構造4上。硬罩幕層150可以由矽、矽氧化物、矽氮氧化物所構成，並由低壓化學氣相沉積製程所製作而成。 5A to 5C are schematic views showing the structure of the process structure 5 in the subsequent process stages according to the fourth embodiment to the fourth embodiment of the present embodiment. Figure 5A is a top view showing the process configuration 5. Fig. 5B is a cross-sectional view showing the process structure 5 taken along the line B-B' of Fig. 5A. Figure 5C is a cross-sectional view of the process structure 5 taken along the line C-C' of Figure 5A. Referring to FIGS. 5A to 5C, the hard mask layer 150 is formed on the entire process structure 4 illustrated in FIGS. 4A to 4C. The hard mask layer 150 may be composed of tantalum, niobium oxide, niobium oxynitride and fabricated by a low pressure chemical vapor deposition process.
第6A圖至第6C圖係根據本說明書的前述實施例第5A圖至第5C圖之後續製程階段中的製程構造6所繪示的結構示意圖。第6A圖係繪示製程構造6的上視圖。第6B圖係沿著第6A圖的切線B-B’所繪示之製程構造6的剖面圖。第6C圖係沿著第6A圖的切線C-C’所繪示之製程構造6的剖面圖。請參照第6A圖至第6C圖，在硬罩幕層150之上形成罩幕層155。之後，圖案化罩幕層155以形成複數個條帶155a、複數個連接橋155b 和複數個通孔155c。複數個條帶155a沿著Y軸方向延伸，且與位於各列犧牲柱體140之間的空間重疊。複數個連接橋155b連結相鄰的條帶155a，並沿著X軸方向延伸，且與犧牲柱體140重疊。複數個通孔155c形成於複數個連接橋155b之間。罩幕層155係由光阻或先進圖案化膜層所構成。罩幕層155的圖案化，可以藉由用來定義罩幕層155要移除(即，用來形成通孔155c)之部分的光微影製程以及用來移除被定義之部分的蝕刻製程來進行。 6A to 6C are schematic views showing the structure of the process structure 6 in the subsequent process stages according to the fifth embodiment to the fifth embodiment of the foregoing embodiment of the present specification. Figure 6A is a top view showing the process configuration 6. Fig. 6B is a cross-sectional view of the process structure 6 taken along the line B-B' of Fig. 6A. Figure 6C is a cross-sectional view of the process structure 6 taken along the line C-C' of Figure 6A. Referring to FIGS. 6A to 6C, a mask layer 155 is formed over the hard mask layer 150. Thereafter, the mask layer 155 is patterned to form a plurality of strips 155a and a plurality of connecting bridges 155b. And a plurality of through holes 155c. A plurality of strips 155a extend in the Y-axis direction and overlap the spaces between the columns of sacrificial cylinders 140. A plurality of connecting bridges 155b join the adjacent strips 155a and extend in the X-axis direction and overlap the sacrificial cylinders 140. A plurality of through holes 155c are formed between the plurality of connecting bridges 155b. The mask layer 155 is composed of a photoresist or an advanced patterned film layer. The patterning of the mask layer 155 can be performed by an optical lithography process for defining a portion of the mask layer 155 to be removed (i.e., to form vias 155c) and an etch process for removing the defined portions. Come on.
第6D圖係根據本說明書的另一實施例第5A圖至第5C圖之後續製程階段中的製程構造6’所繪示的結構上視圖。請參照第6D圖，連接橋155b’只與犧牲柱體140的中間部分重疊。因此，犧牲柱體140沿著Y軸方向的上緣和下緣會經由通孔155c’曝露於外。 Fig. 6D is a top view of the structure shown in the process configuration 6' in the subsequent process stages of Figs. 5A to 5C of another embodiment of the present specification. Referring to Fig. 6D, the connecting bridge 155b' overlaps only the intermediate portion of the sacrificial cylinder 140. Therefore, the upper and lower edges of the sacrificial cylinder 140 along the Y-axis direction are exposed to the outside via the through holes 155c'.
第7A圖至第7C圖係根據本說明書的前述實施例第6A圖至第6C圖之後續製程階段中的製程構造7所繪示的結構示意圖。第7A圖係繪示製程構造7的上視圖。第7B圖係沿著第7A圖的切線B-B’所繪示之製程構造7的剖面圖。第7C圖係沿著第7A圖的切線C-C’所繪示之製程構造7的剖面圖。請參照第7A圖至第7C圖，以罩幕層155為蝕刻罩幕對疊層110進行蝕刻，以形成沿著Z軸方向延伸的通孔110b，將基材100曝露於外。在第7C圖中，為了更清楚呈現通孔110b，並未將位於通孔110b後方的犧牲柱體140繪示出來。此一蝕刻製程的結果，使罩幕層 150包括沿著Y軸方向延伸，並且與位於各列犧牲柱體140之間的空間重疊的複數個條帶150a、連結相鄰條帶150a，並沿著X軸方向延伸，且與犧牲柱體140之頂部表面(即，Z軸方向的頂部表面)重疊的複數個連接橋150b以及位於連接橋150b之間的複數個通孔150c。每一通孔110b分別沿著Z軸方向垂直對準一個通孔150c。疊層110可藉由非等向蝕刻製程，例如反應離子蝕刻製程，來加以蝕刻。請參照第7C圖，經由通孔150c曝露於外的一部分基材100，也被蝕刻而形成基材100a。 7A to 7C are schematic views showing the structure of the process structure 7 in the subsequent process stages according to the sixth embodiment to the sixth embodiment of the foregoing embodiment of the present specification. Figure 7A is a top view showing the process configuration 7. Fig. 7B is a cross-sectional view showing the process structure 7 taken along the line B-B' of Fig. 7A. Figure 7C is a cross-sectional view of the process structure 7 taken along the line C-C' of Figure 7A. Referring to FIGS. 7A to 7C, the laminate 110 is etched by the mask layer 155 as an etching mask to form a via hole 110b extending in the Z-axis direction to expose the substrate 100. In Fig. 7C, in order to present the through hole 110b more clearly, the sacrificial cylinder 140 located behind the through hole 110b is not shown. The result of this etching process, making the mask layer 150 includes a plurality of strips 150a extending along the Y-axis direction and overlapping the space between the columns of sacrificial cylinders 140, joining adjacent strips 150a, extending along the X-axis direction, and the sacrificial cylinder The top surface of 140 (i.e., the top surface in the Z-axis direction) overlaps a plurality of connecting bridges 150b and a plurality of through holes 150c between the connecting bridges 150b. Each of the through holes 110b is vertically aligned with one through hole 150c in the Z-axis direction. The laminate 110 can be etched by an anisotropic etch process, such as a reactive ion etch process. Referring to FIG. 7C, a part of the substrate 100 exposed through the through hole 150c is also etched to form the substrate 100a.
第8A圖至第8E圖係根據本說明書的前述實施例第7A圖至第7C圖之後續製程階段中的製程構造8所繪示的結構示意圖。第8A圖係繪示製程構造8的上視圖。第8B圖係沿著第8A圖的切線B-B’所繪示之製程構造8的剖面圖。第8C圖係沿著第8A圖的切線C-C’所繪示之製程構造8的剖面圖。第8D圖係沿著第8B圖的切線D-D’所繪示之製程構造8的剖面圖。第8E圖係繪示製程構造8的結構透視圖。請參照第8A圖至第8E圖，移除犧牲柱體140以留下未填充的通孔110a。通孔110a和相鄰的通孔110b連接而形成分隔疊層110的溝槽110c，進而形成複數個沿著Y軸方向延伸的脊狀疊層110’。在第8C圖中，為了更清楚呈現通孔110b，並未將位於通孔110b後方之硬罩幕層150未蝕刻的部分繪示出來。脊狀疊層110’分別垂直地對準硬罩幕層150的其中一條帶150a。犧牲柱體140可藉由濕式清洗製程加以移除。例如可以將第7A圖至第7C所繪示的製程構造7浸泡於溶 液，例如熱磷酸，之中，使溶液進入通孔110b並與犧牲柱體140接觸，藉以蝕刻並移除犧牲柱體140。在濕式清洗製程之中，複數個連接橋150b並不會被移除。相反的，複數個連接橋150b被留下來作為相鄰脊狀疊層110’間的支架。因此，相鄰脊狀疊層110’不會因為濕式清潔製程所使用之清潔溶液造成之毛細管作用力而相互接觸。 8A to 8E are schematic views showing the structure of the process structure 8 in the subsequent process stages according to the seventh embodiment to the seventh embodiment of the foregoing embodiment of the present specification. Figure 8A is a top view showing the process configuration 8. Fig. 8B is a cross-sectional view of the process structure 8 taken along the tangential line B-B' of Fig. 8A. Figure 8C is a cross-sectional view of the process structure 8 taken along line C-C' of Figure 8A. Fig. 8D is a cross-sectional view of the process structure 8 taken along the tangential line D-D' of Fig. 8B. Figure 8E is a perspective view showing the structure of the process configuration 8. Referring to FIGS. 8A-8E, the sacrificial cylinder 140 is removed to leave the unfilled via 110a. The through hole 110a and the adjacent through hole 110b are joined to form a groove 110c partitioning the laminate 110, thereby forming a plurality of ridge laminates 110' extending in the Y-axis direction. In Fig. 8C, in order to present the through hole 110b more clearly, the unetched portion of the hard mask layer 150 located behind the through hole 110b is not shown. The ridge stacks 110' are vertically aligned with one of the strips 150a of the hard mask layer 150, respectively. The sacrificial cylinder 140 can be removed by a wet cleaning process. For example, the process structure 7 shown in FIGS. 7A to 7C can be immersed in the solution. The liquid, such as hot phosphoric acid, causes the solution to enter the via 110b and contact the sacrificial post 140, thereby etching and removing the sacrificial post 140. In the wet cleaning process, a plurality of connecting bridges 150b are not removed. Conversely, a plurality of connecting bridges 150b are left as a support between adjacent ridge stacks 110'. Therefore, the adjacent ridge stacks 110' do not come into contact with each other due to the capillary force caused by the cleaning solution used in the wet cleaning process.
第9A圖至第9D圖係根據本說明書的前述實施例第8A圖至第8E圖之後續製程階段中的製程構造9所繪示的結構示意圖。第9A圖係繪示製程構造9的上視圖。第9B圖係沿著第9A圖的切線B-B’所繪示之製程構造9的剖面圖。第9C圖係沿著第9A圖的切線C-C’所繪示之製程構造9的剖面圖。第9D圖係沿著第9B圖的切線D-D’所繪示之製程構造9的剖面圖。請參照第9A圖至第9D圖，形成記憶體層160以覆蓋位於脊狀疊層110’之間的溝槽110c。也就是說，記憶體層160形成於脊狀疊層110’的側壁、經由溝槽110’暴露於外的一部分基材100以及硬罩幕層150暴露於外的部分上。如第9A圖所繪示，記憶體層160也形成硬罩幕層150之通孔150c的側壁上。為了方便說明起見，圖式中的部分結構，例如通孔150a-150c的部分側壁可能會省略部而未出來。記憶體層160可以由包含氧化矽(silicon oxide)層、氮化矽(silicon nitride)層和氧化矽層的複合層(即，ONO層)所構成，並且由低壓化學氣相沉積製程所製作而成。在形成記憶體層160之後，在具有記憶體層160的整個製程構造上形成導電材料，以填 充溝槽110c以及覆蓋有記憶體層160的通孔150c。之後，藉由蝕刻移除導電材料的頂部層以及記憶體層160的頂部層，以將硬罩幕層150曝露出來。進而形成複數個由著Y軸方向延伸的導電脊狀部170。導電脊狀部170可以由導電材質，例如摻雜有硼，摻雜濃度介於1017到1019atoms/cm3的p型多晶矽、摻雜有磷或砷，摻雜濃度介於1017到1019atoms/cm3的n型多晶矽或無摻雜的多晶矽，所構成。另一方面，導電脊狀部170也可以由金屬矽化物(silicides)，例如矽化鈦(TiSi)、矽化鈷(CoSi)或矽鍺(SiGe)、氧化物半導體(oxide semiconductors)，例如氧化銦鋅(InZnO)或氧化銦鎵鋅(InGaZnO)、金屬，例如鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鈷(Co)、鎳(Ni)、氮化鈦(TiN)、氮化鉭(TaN)或氮化鉭鋁(TaAlN)，或兩種或多種上述材質之組合物所構成。導電脊狀部170可以藉由低壓化學氣相沉積製程製作而成。 9A to 9D are schematic views showing the structure of the process structure 9 in the subsequent process stages according to the eighth embodiment to the eighth embodiment of the foregoing embodiment of the present specification. Figure 9A is a top view showing the process configuration 9. Figure 9B is a cross-sectional view of the process structure 9 taken along the line BB' of Figure 9A. Figure 9C is a cross-sectional view of the process structure 9 taken along line C-C' of Figure 9A. Figure 9D is a cross-sectional view of the process structure 9 taken along line DD' of Figure 9B. Referring to FIGS. 9A through 9D, a memory layer 160 is formed to cover the trench 110c between the ridge stacks 110'. That is, the memory layer 160 is formed on the sidewall of the ridge stack 110', a portion of the substrate 100 exposed to the outside via the trench 110', and a portion of the hard mask layer 150 exposed to the outside. As depicted in FIG. 9A, the memory layer 160 also forms the sidewalls of the vias 150c of the hard mask layer 150. For the sake of convenience of explanation, some of the structures in the drawings, such as the side walls of the through holes 150a-150c, may be omitted. The memory layer 160 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a tantalum oxide layer, and is formed by a low pressure chemical vapor deposition process. . After the memory layer 160 is formed, a conductive material is formed over the entire process structure having the memory layer 160 to fill the trench 110c and the via 150c covered with the memory layer 160. Thereafter, the top layer of the conductive material and the top layer of the memory layer 160 are removed by etching to expose the hard mask layer 150. Further, a plurality of conductive ridges 170 extending in the Y-axis direction are formed. The conductive ridge 170 may be made of a conductive material such as boron doped with a doping concentration of 10 17 to 10 19 atoms/cm 3 , doped with phosphorus or arsenic, and doped at a concentration of 10 17 to 10 19 atoms/cm 3 of n-type polycrystalline germanium or undoped polycrystalline germanium. On the other hand, the conductive ridges 170 may also be composed of metal silicides such as titanium telluride (TiSi), cobalt telluride (CoSi) or germanium (SiGe), oxide semiconductors such as indium zinc oxide. (InZnO) or indium gallium zinc oxide (InGaZnO), metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), titanium nitride (TiN ), tantalum nitride (TaN) or tantalum aluminum nitride (TaAlN), or a combination of two or more of the above materials. The conductive ridges 170 can be fabricated by a low pressure chemical vapor deposition process.
第10A圖至第10C圖係根據本說明書的前述實施例第9A圖至第9D圖之後續製程階段中的製程構造10所繪示的結構示意圖。第10A圖係繪示製程構造10的上視圖。第10B圖係沿著第10A圖的切線B-B’所繪示之製程構造10的剖面圖。第10C圖係沿著第10A圖的切線C-C’所繪示之製程構造10的剖面圖。請參照第10A圖至第10C圖，於第9A圖至第9D圖所繪示的製程構造9上形成導電層180。導電層180可以由導電材質，例如摻雜有硼，摻雜濃度介於1017到1019atoms/cm3的p型多晶矽、摻雜有磷或砷，摻雜濃度介於1017到1019atoms/cm3的n型多晶 矽或無摻雜的多晶矽，所構成。另一方面，導電層180也可以由金屬矽化物，例如矽化鈦、矽化鈷或矽鍺、氧化半導體，例如氧化銦鋅或氧化銦鎵鋅、金屬，例如鋁、銅、鎢、鈦、鈷、鎳、氮化鈦、氮化鉭或氮化鉭鋁，或兩種或多種上述材質之組合物所構成。導電層180可以由構成導電脊狀部170的材質所組成。導電層180可以藉由低壓化學氣相沉積製程製作而成。之後，在導電層180上形成圖案化的硬罩幕層190。圖案化的硬罩幕層190包括複數個沿著Y軸方向延伸的條帶190a。這些複數個條帶190a垂直(沿著Z軸方向)對準複數個脊狀疊層110’。圖案化的硬罩幕層190也包括複數個連接橋190b，其位於複數個條帶190a之間，且沿X軸方向，用來垂直對準導電脊狀部170經由硬罩幕層150的通孔150c曝露於外的部分。圖案化的硬罩幕層190更包括複數個通孔190c位於連接橋190b之間，用來將導電層180曝露於外。圖案化的硬罩幕層190可以由先進圖案化膜所形成。圖案化的硬罩幕層190可以藉由在導電層180的整個表面沉積先進圖案化膜的低壓化學氣相沉積製程、用來在先進圖案化膜上定義出先進圖案化膜要移除之部分的光微影製程以及用來移除定義部分的蝕刻製程來形成。 10A to 10C are schematic views showing the structure of the process structure 10 in the subsequent process stages according to the 9Ath to 9thth drawings of the foregoing embodiment of the present specification. FIG. 10A is a top view showing the process configuration 10. Figure 10B is a cross-sectional view of the process structure 10 taken along line BB' of Figure 10A. Figure 10C is a cross-sectional view of process architecture 10 taken along line C-C' of Figure 10A. Referring to FIGS. 10A to 10C, a conductive layer 180 is formed on the process structure 9 illustrated in FIGS. 9A to 9D. The conductive layer 180 may be made of a conductive material such as boron doped with p-type polysilicon having a doping concentration of 10 17 to 10 19 atoms/cm 3 , doped with phosphorus or arsenic, and doped at a concentration of 10 17 to 10 19 . It is composed of an n-type polycrystalline germanium of atoms/cm 3 or an undoped polycrystalline germanium. On the other hand, the conductive layer 180 may also be made of a metal telluride such as titanium telluride, cobalt or germanium, an oxidized semiconductor such as indium zinc oxide or indium gallium zinc oxide, a metal such as aluminum, copper, tungsten, titanium, cobalt, Nickel, titanium nitride, tantalum nitride or tantalum nitride, or a combination of two or more of the above materials. The conductive layer 180 may be composed of a material constituting the conductive ridge 170. The conductive layer 180 can be fabricated by a low pressure chemical vapor deposition process. Thereafter, a patterned hard mask layer 190 is formed on the conductive layer 180. The patterned hard mask layer 190 includes a plurality of strips 190a extending along the Y-axis direction. The plurality of strips 190a are aligned vertically (along the Z-axis direction) with a plurality of ridge stacks 110'. The patterned hard mask layer 190 also includes a plurality of connecting bridges 190b between the plurality of strips 190a and in the X-axis direction for vertically aligning the conductive ridges 170 through the hard mask layer 150. The hole 150c is exposed to the outer portion. The patterned hard mask layer 190 further includes a plurality of vias 190c between the connection bridges 190b for exposing the conductive layer 180 to the outside. The patterned hard mask layer 190 can be formed from an advanced patterned film. The patterned hard mask layer 190 can be used to define a portion of the advanced patterned film to be removed on the advanced patterned film by a low pressure chemical vapor deposition process that deposits an advanced patterned film over the entire surface of the conductive layer 180. The photolithography process and the etching process used to remove the defined portions are formed.
第11A圖至第11D圖係根據本說明書的前述實施例第10A圖至第10C圖之後續製程階段中的製程構造11所繪示的結構示意圖。第11A圖係繪示製程構造11的上視圖。第11B圖係沿著第11A圖的切線B-B’所繪示之製程構造11的剖面圖。第 11C圖係沿著第11A圖的切線C-C’所繪示之製程構造11的剖面圖。第11D圖係沿著第11B圖的切線D-D’所繪示之製程構造11的剖面圖。請參照第11A圖至第11D圖，以圖案化的硬罩幕層190為蝕刻罩幕，對第10A圖至第10C圖所繪示的製程構造10進行蝕刻，以形成複數個沿著Z軸方向延伸的通孔200，以將基材100曝露於外。在第11B圖中，為了更清楚呈現通孔200，並未將位於通孔200後方的導電層180、硬罩幕層150、導電脊狀部170以及記憶體層160未被蝕刻的部分繪示出來。每一個通孔200分別垂直對準硬罩幕層190的一個通孔190c。藉由通孔200可以將導電脊狀部170切割成複數個導電柱狀體170a。製程構造10可藉由非等向蝕刻製程，例如反應離子蝕刻製程，來加以蝕刻。在蝕刻製程之後，圖案化的硬罩幕層190可以藉由濕式蝕刻製程加以移除。 11A through 11D are schematic views showing the structure of the process structure 11 in the subsequent process stages according to the 10A to 10C drawings of the foregoing embodiment of the present specification. Figure 11A is a top view showing the process configuration 11. Fig. 11B is a cross-sectional view showing the process structure 11 taken along the tangential line B-B' of Fig. 11A. First The 11C pattern is a cross-sectional view of the process structure 11 taken along the tangent line C-C' of Fig. 11A. Figure 11D is a cross-sectional view of the process structure 11 taken along the line D-D' of Figure 11B. Referring to FIGS. 11A-11D, the patterned hard mask layer 190 is an etch mask, and the process structures 10 illustrated in FIGS. 10A-10C are etched to form a plurality of along the Z axis. The through hole 200 is extended in the direction to expose the substrate 100 to the outside. In FIG. 11B, in order to present the via 200 more clearly, the conductive layer 180, the hard mask layer 150, the conductive ridge 170, and the portion of the memory layer 160 that are not etched behind the via 200 are not depicted. . Each of the through holes 200 is vertically aligned with a through hole 190c of the hard mask layer 190, respectively. The conductive ridges 170 can be cut into a plurality of conductive pillars 170a by the through holes 200. Process structure 10 can be etched by an anisotropic etch process, such as a reactive ion etch process. After the etching process, the patterned hard mask layer 190 can be removed by a wet etch process.
第12A圖至第12E圖係根據本說明書的前述實施例第11A圖至第11D圖之後續製程階段中的製程構造12所繪示的結構示意圖。第12A圖係繪示製程構造12的上視圖。第12B圖係沿著第12A圖的切線B-B’所繪示之製程構造12的剖面圖。第12C圖係沿著第12A圖的切線C-C’所繪示之製程構造12的剖面圖。第12D圖係沿著第12B圖的切線D-D’所繪示之製程構造12的剖面圖。第12E圖係繪示製程構造12的結構透視圖。請參照第12A圖至第12E圖，將導電層180加以圖案化，以形成沿著X軸方向延伸的條帶180a。每一個條帶180a垂直(沿著Z軸方向) 對準並連接沿著X軸方向排成一行的導電柱狀體170a。導電層180的圖案化，可以藉由用來定義導電層180要移除之部分的光微影製程以及用來移除被定義之部分的蝕刻製程來進行。為了方便說明起見，第12E圖省略部份記憶體層160將一部分導電柱狀體170a顯現出來。 12A to 12E are schematic views showing the structure of the process structure 12 in the subsequent process stages according to the 11Ath to 11thth drawings of the foregoing embodiment of the present specification. Figure 12A is a top view showing the process configuration 12. Fig. 12B is a cross-sectional view of the process structure 12 taken along the tangential line B-B' of Fig. 12A. Figure 12C is a cross-sectional view of the process structure 12 taken along line C-C' of Figure 12A. Fig. 12D is a cross-sectional view of the process structure 12 taken along the tangential line D-D' of Fig. 12B. Figure 12E is a perspective view showing the structure of the process configuration 12. Referring to FIGS. 12A to 12E, the conductive layer 180 is patterned to form a strip 180a extending in the X-axis direction. Each strip 180a is vertical (along the Z axis) The conductive columnar bodies 170a lined up in the X-axis direction are aligned and connected. The patterning of the conductive layer 180 can be performed by an optical lithography process for defining a portion of the conductive layer 180 to be removed and an etching process for removing the defined portion. For convenience of explanation, a portion of the memory layer 160 is omitted from the portion of the memory pillar 160 in Fig. 12E.
在製程構造12中，每一個導電柱狀體170a可作為閘極；每一個導電條帶180a可作為條字元線；每一個脊狀疊層110’可作為位元線；位於每一個脊狀疊層110’中的每一個導電層111-118可作為通道。 In the process configuration 12, each of the conductive pillars 170a can serve as a gate; each of the conductive strips 180a can serve as a strip line; each of the ridge stacks 110' can serve as a bit line; Each of the conductive layers 111-118 in the stack 110' can serve as a channel.
雖然第12A圖至第12E圖所繪示的每一個脊狀疊層110’包含八個導電層和八個絕緣層。但導電層和絕緣層的數量是可以改變的。另外，雖然第12A圖至第12E圖所繪示的製程構造12包含四個脊狀疊層110’和四個條帶180a。但脊狀疊層110’和條帶180a的數量是也可以改變。 Although each of the ridge stacks 110' illustrated in Figures 12A through 12E comprises eight conductive layers and eight insulating layers. However, the number of conductive layers and insulating layers can be varied. Additionally, the process configuration 12 illustrated in Figures 12A through 12E includes four ridge stacks 110' and four strips 180a. However, the number of ridge stacks 110' and strips 180a can also vary.
第13圖係根據本說明書的又一實施例之記憶體陣列最終製程階段中的製程構造12’所繪示的結構透視圖。請參照第13圖，通孔200’的數目少於第12A圖所繪示者。因此導電柱狀體170a’沿著Y軸方向延伸的距離比第12A圖所繪示的導電柱狀體170a要長。然後，形成一個以上的導電條帶180a’，例如3個導電條帶180a’，來與沿著X軸方向排列導電柱狀體170a’的每一行重疊並且連接。另外，在形成導電條帶180a’之前，先移除了位於硬罩幕層150中的複數個連接橋150b。形成在連接橋150b 之側壁上的一部分記憶體層160也被移除。結果，可以增加沿著Y軸方向之閘極(藉由導電柱狀體170a來實施)的長度，且可以使一條以上的字元線(藉由導電條帶180a’來實施)連接至每一個閘極。 Figure 13 is a perspective view of the structure depicted in the process configuration 12' of the final process stage of the memory array in accordance with yet another embodiment of the present specification. Referring to Figure 13, the number of through holes 200' is less than that shown in Fig. 12A. Therefore, the conductive columnar body 170a' extends in the Y-axis direction a longer distance than the conductive columnar body 170a shown in Fig. 12A. Then, one or more conductive strips 180a', for example, three conductive strips 180a' are formed to overlap and connect with each row in which the conductive pillars 170a' are arranged along the X-axis direction. Additionally, a plurality of connecting bridges 150b located in the hard mask layer 150 are removed prior to forming the conductive strips 180a'. Formed on the connecting bridge 150b A portion of the memory layer 160 on the sidewalls is also removed. As a result, the length of the gate along the Y-axis direction (implemented by the conductive pillar 170a) can be increased, and more than one word line (implemented by the conductive strip 180a') can be connected to each Gate.
第13A圖所繪的製程構造12’代表通孔200’對準其下方結構的一個理想狀況。當通孔200’因為，例如光微影製程中所產生的對位失準，而沒有對準其下方結構時，通孔200’可沿著X軸方向稍微移動。在這種情形下，部分記憶體層160可以保留於脊狀疊層110’的側壁上。 The process configuration 12' depicted in Figure 13A represents an ideal condition for the via 200' to be aligned with the underlying structure. When the through hole 200' is misaligned due to, for example, misalignment generated in the photolithography process, the through hole 200' is slightly movable in the X-axis direction. In this case, a portion of the memory layer 160 may remain on the sidewalls of the ridge stack 110'.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
12‧‧‧製程構造 12‧‧‧Process construction
100‧‧‧基材 100‧‧‧Substrate
100a‧‧‧基材 100a‧‧‧Substrate
110‧‧‧多層疊層 110‧‧‧Multilayer laminate
111‧‧‧導電層 111‧‧‧ Conductive layer
112‧‧‧導電層 112‧‧‧ Conductive layer
113‧‧‧導電層 113‧‧‧ Conductive layer
114‧‧‧導電層 114‧‧‧ Conductive layer
115‧‧‧導電層 115‧‧‧ Conductive layer
116‧‧‧導電層 116‧‧‧ Conductive layer
117‧‧‧導電層 117‧‧‧ Conductive layer
118‧‧‧導電層 118‧‧‧ Conductive layer
121‧‧‧絕緣層 121‧‧‧Insulation
122‧‧‧絕緣層 122‧‧‧Insulation
123‧‧‧絕緣層 123‧‧‧Insulation
124‧‧‧絕緣層 124‧‧‧Insulation
125‧‧‧絕緣層 125‧‧‧Insulation
126‧‧‧絕緣層 126‧‧‧Insulation
127‧‧‧絕緣層 127‧‧‧Insulation
128‧‧‧絕緣層 128‧‧‧Insulation
150‧‧‧硬罩幕層 150‧‧‧hard mask layer
180a‧‧‧條帶 180a‧‧‧
160‧‧‧記憶體層 160‧‧‧ memory layer
170a‧‧‧導電柱狀體 170a‧‧‧conductive columnar body
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