TWI668799B - Memory device and method of fabricating the same - Google Patents
Memory device and method of fabricating the same Download PDFInfo
- Publication number
- TWI668799B TWI668799B TW107123982A TW107123982A TWI668799B TW I668799 B TWI668799 B TW I668799B TW 107123982 A TW107123982 A TW 107123982A TW 107123982 A TW107123982 A TW 107123982A TW I668799 B TWI668799 B TW I668799B
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit structure
- conductive pillars
- memory
- conductive
- pillars
- Prior art date
Links
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
一種記憶元件及其製造方法。記憶元件包括基底、第一電路結構、多個第一導電柱、第二電路結構以及多個第二導電柱。第一電路結構設置於基底上。多個第一導電柱設置於第一電路結構中且沿第一方向排列，多個第一導電柱自第一電路結構的上層延伸至基底。第二電路結構設置於第一電路結構上。多個第二導電柱設置於第二電路結構中且沿第一方向排列，多個第二導電柱自第二電路結構的上層延伸至第一電路結構，且每一多個第二導電柱分別電性連接至每一多個第一導電柱。A memory element and a method of manufacturing the same. The memory component includes a substrate, a first circuit structure, a plurality of first conductive pillars, a second circuit structure, and a plurality of second conductive pillars. The first circuit structure is disposed on the substrate. A plurality of first conductive pillars are disposed in the first circuit structure and arranged in the first direction, and the plurality of first conductive pillars extend from the upper layer of the first circuit structure to the substrate. The second circuit structure is disposed on the first circuit structure. The plurality of second conductive pillars are disposed in the second circuit structure and arranged along the first direction, and the plurality of second conductive pillars extend from the upper layer of the second circuit structure to the first circuit structure, and each of the plurality of second conductive pillars respectively Electrically connected to each of the plurality of first conductive pillars.
Description
本發明是有關於一種半導體元件及其製造方法，且特別是有關於一種記憶元件及其製造方法。The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.
隨著科技日新月異，電子元件的進步增加了對更大儲存能力的需要。為了滿足高儲存密度（high storage density）的需求，記憶元件尺寸變得更小而且積集度更高。因此，記憶元件的型態已從平面型閘極（planar gate）結構的二維記憶元件（2D memory device）發展到具有垂直通道（vertical channel，VC）結構的三維記憶元件（3D memory device）。As technology advances, advances in electronic components have increased the need for greater storage capacity. In order to meet the demand for high storage density, the memory element size becomes smaller and the accumulation is higher. Therefore, the type of memory element has evolved from a 2D memory device of a planar gate structure to a 3D memory device having a vertical channel (VC) structure.
然而，隨著三維記憶元件的積集度提高，在記憶元件的製造過程中，需要在記憶元件的疊層結構中形成高高寬比的溝槽並且於溝槽中填入導電材料，這會對疊層結構造成應力，進而導致溝渠以及溝渠附近的元件產生形變，而形變將可能導致下層結構與上層結構之間的對準問題，或導致疊層結構與後段製程（BEOL）配線的錯誤連接及/或造成後段製程配線的錯誤對準。因此，如何改善高高寬比的溝槽所導致記憶元件的結構產生形變是目前有待解決的問題。However, as the degree of integration of the three-dimensional memory element increases, in the manufacturing process of the memory element, it is necessary to form a trench having a high aspect ratio in the stacked structure of the memory element and filling the trench with a conductive material. The laminated structure causes stress, which in turn causes deformation of the trench and the components in the vicinity of the trench, and the deformation may cause alignment problems between the underlying structure and the upper structure, or may cause a wrong connection between the laminated structure and the back end of line (BEOL) wiring and / or cause misalignment of the back-end process wiring. Therefore, how to improve the structure of the memory element caused by the improvement of the high aspect ratio trench is a problem to be solved.
本發明提供一種記憶元件及其製造方法，其可改善高高寬比的溝槽所導致記憶元件的結構產生形變的問題。The present invention provides a memory element and a method of fabricating the same that can improve the deformation of the structure of the memory element caused by the high aspect ratio trench.
本發明提供一種記憶元件，包括：基底、第一電路結構、多個第一導電柱、第二電路結構以及多個第二導電柱。第一電路結構設置於基底上。多個第一導電柱設置於第一電路結構中且沿第一方向排列，其中多個第一導電柱自第一電路結構的上層延伸至基底。第二電路結構設置於第一電路結構上。多個第二導電柱設置於第二電路結構中且沿第一方向排列，其中多個第二導電柱自第二電路結構的上層延伸至第一電路結構，且每一多個第二導電柱分別電性連接至每一多個第一導電柱。The present invention provides a memory device comprising: a substrate, a first circuit structure, a plurality of first conductive pillars, a second circuit structure, and a plurality of second conductive pillars. The first circuit structure is disposed on the substrate. A plurality of first conductive pillars are disposed in the first circuit structure and arranged in the first direction, wherein the plurality of first conductive pillars extend from the upper layer of the first circuit structure to the substrate. The second circuit structure is disposed on the first circuit structure. The plurality of second conductive pillars are disposed in the second circuit structure and arranged in the first direction, wherein the plurality of second conductive pillars extend from the upper layer of the second circuit structure to the first circuit structure, and each of the plurality of second conductive pillars Each of the plurality of first conductive pillars is electrically connected to each other.
在本發明的一些實施例中，多個第一導電柱以及多個第二導電柱的截面形狀包括圓形、橢圓形、方形、多邊形或其組合。In some embodiments of the invention, the cross-sectional shapes of the plurality of first conductive pillars and the plurality of second conductive pillars comprise a circle, an ellipse, a square, a polygon, or a combination thereof.
在本發明的一些實施例中，多個第一導電柱的截面沿第二方向具有第一寬度，第一方向與第二方向互相垂直，且多個第一導電柱的高度與第一寬度的比值介於15至28之間。In some embodiments of the present invention, the plurality of first conductive pillars have a first width in a second direction, the first direction and the second direction are perpendicular to each other, and the heights of the plurality of first conductive pillars and the first width The ratio is between 15 and 28.
在本發明的一些實施例中，多個第二導電柱的截面沿第二方向具有第二寬度，第一方向與第二方向互相垂直，且多個第二導電柱的高度與第二寬度的比值介於15至28之間。In some embodiments of the present invention, a plurality of second conductive pillars have a second width in a second direction, the first direction and the second direction being perpendicular to each other, and the heights of the plurality of second conductive pillars and the second width The ratio is between 15 and 28.
在本發明的一些實施例中，相鄰兩個第一導電柱之間以及相鄰兩個第二導電柱之間在第一方向上的間隔分別大於或等於750奈米。In some embodiments of the invention, the spacing between the two adjacent first conductive pillars and between the adjacent two second conductive pillars in the first direction is greater than or equal to 750 nanometers, respectively.
在本發明的一些實施例中，第一電路結構以及第二電路結構分別包括多個第一記憶體柱以及多個第二記憶體柱，且每一多個第一記憶體柱分別電性連接至每一多個第二記憶體柱。In some embodiments of the present invention, the first circuit structure and the second circuit structure respectively include a plurality of first memory columns and a plurality of second memory columns, and each of the plurality of first memory columns is electrically connected To each of the plurality of second memory columns.
本發明提供一種記憶元件的製造方法，包括以下步驟。形成第一電路結構於基底上。形成多個第一導電柱於第一電路結構中，其中多個第一導電柱沿第一方向排列且自第一電路結構的上層延伸至基底。形成第二電路結構於第一電路結構上。形成多個第二導電柱於第二電路結構中，其中多個第二導電柱沿第一方向排列且自第二電路結構的上層延伸至第一電路結構，且每一多個第二導電柱分別電性連接至每一多個第一導電柱。The present invention provides a method of manufacturing a memory element comprising the following steps. A first circuit structure is formed on the substrate. A plurality of first conductive pillars are formed in the first circuit structure, wherein the plurality of first conductive pillars are arranged in the first direction and extend from the upper layer of the first circuit structure to the substrate. A second circuit structure is formed on the first circuit structure. Forming a plurality of second conductive pillars in the second circuit structure, wherein the plurality of second conductive pillars are arranged in the first direction and extend from the upper layer of the second circuit structure to the first circuit structure, and each of the plurality of second conductive pillars Each of the plurality of first conductive pillars is electrically connected to each other.
在本發明的一些實施例中，記憶元件的製造方法的步驟更包括以下步驟。形成多個第一溝渠於第一電路結構中，其中多個第一溝渠沿第二方向排列且暴露基底的一部分，第一方向與第二方向互相垂直。形成第一介電層填滿多個第一溝渠，其中多個第一導電柱是形成於填滿第一介電層的多個第一溝渠中。In some embodiments of the invention, the steps of the method of fabricating the memory element further comprise the following steps. Forming a plurality of first trenches in the first circuit structure, wherein the plurality of first trenches are arranged in the second direction and exposing a portion of the substrate, the first direction and the second direction being perpendicular to each other. Forming a first dielectric layer to fill the plurality of first trenches, wherein the plurality of first conductive pillars are formed in the plurality of first trenches filling the first dielectric layer.
在本發明的一些實施例中，記憶元件的製造方法的步驟更包括以下步驟。形成多個第二溝渠於第二電路結構中，其中多個第二溝渠沿第二方向排列且暴露第一電路結構的一部分。形成第二介電層填滿多個第二溝渠，其中多個第二導電柱是形成於填滿第二介電層的多個第二溝渠中。In some embodiments of the invention, the steps of the method of fabricating the memory element further comprise the following steps. Forming a plurality of second trenches in the second circuit structure, wherein the plurality of second trenches are aligned in the second direction and exposing a portion of the first circuit structure. Forming a second dielectric layer to fill the plurality of second trenches, wherein the plurality of second conductive pillars are formed in the plurality of second trenches filling the second dielectric layer.
在本發明的一些實施例中，第一電路結構以及第二電路結構分別包括多個第一記憶體柱以及多個第二記憶體柱，且每一多個第一記憶體柱分別電性連接至每一多個第二記憶體柱。In some embodiments of the present invention, the first circuit structure and the second circuit structure respectively include a plurality of first memory columns and a plurality of second memory columns, and each of the plurality of first memory columns is electrically connected To each of the plurality of second memory columns.
基於上述，在本發明的記憶元件中，形成多個導電柱取代傳統細長的導體溝渠結構。相較於細長的導體溝渠結構，導電柱所受的應力較為均勻，因此，記憶元件中電路結構的堆疊結構較不易發生傾斜的問題，即電路結構較不易產生形變。也就是說，本發明的記憶元件不僅可改善電路結構之間的對準問題，亦可改善電路結構與後段製程（BEOL）配線的錯誤連接問題及/或後段製程（BEOL）配線的錯誤對準問題。Based on the above, in the memory element of the present invention, a plurality of conductive pillars are formed in place of the conventional elongated conductor trench structure. Compared with the elongated conductor trench structure, the stress on the conductive pillar is relatively uniform. Therefore, the stack structure of the circuit structure in the memory component is less prone to tilting, that is, the circuit structure is less susceptible to deformation. That is to say, the memory element of the present invention not only improves alignment problems between circuit structures, but also improves misconnection of circuit structures and back end of line (BEOL) wiring and/or misalignment of back end of line (BEOL) wiring. problem.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A至圖1J是本發明一些實施例的記憶元件的製造流程剖面示意圖。圖2以及圖3分別是圖1A以及圖1B的上視圖。圖4是圖1F以及圖1G的上視圖。1A through 1J are schematic cross-sectional views showing a manufacturing process of a memory element according to some embodiments of the present invention. 2 and 3 are top views of Figs. 1A and 1B, respectively. Figure 4 is a top view of Figure 1F and Figure 1G.
圖1A為圖2中沿線A-A’的剖面圖。請同時參照圖1A以及圖2，形成第一電路結構100於基底10上。基底10包括半導體基底，例如是矽基底。在一些實施例中，可依據設計需求而於基底10中形成摻雜區（如，N+摻雜區）（未繪示）。第一電路結構100包括堆疊結構110以及多個第一記憶體柱120。Fig. 1A is a cross-sectional view taken along line A-A' of Fig. 2. Referring to FIG. 1A and FIG. 2 simultaneously, the first circuit structure 100 is formed on the substrate 10. Substrate 10 includes a semiconductor substrate, such as a germanium substrate. In some embodiments, a doped region (eg, an N+ doped region) (not shown) may be formed in the substrate 10 depending on design requirements. The first circuit structure 100 includes a stacked structure 110 and a plurality of first memory pillars 120.
在一些實施例中，堆疊結構110包括交替地堆疊的多個絕緣層112與多個犧牲層114。絕緣層112的材料包括介電材料，例如是氧化矽。犧牲層114的材料與絕緣層112的材料不同，犧牲層114的材料與絕緣層112的材料具有足夠的蝕刻選擇比。在一些實施例中，犧牲層114的材料例如是氮化矽。絕緣層112與犧牲層114例如是藉由進行多次化學氣相沈積製程所形成。堆疊結構110中的絕緣層112以及犧牲層114的層數可以是8層、16層、24層、48層、96層或更多層，但本發明不限於此。堆疊結構110中的絕緣層112以及犧牲層114的層數可取決於記憶元件的設計以及密度。In some embodiments, the stacked structure 110 includes a plurality of insulating layers 112 and a plurality of sacrificial layers 114 that are alternately stacked. The material of the insulating layer 112 includes a dielectric material such as yttrium oxide. The material of the sacrificial layer 114 is different from the material of the insulating layer 112, and the material of the sacrificial layer 114 has a sufficient etching selectivity ratio with the material of the insulating layer 112. In some embodiments, the material of the sacrificial layer 114 is, for example, tantalum nitride. The insulating layer 112 and the sacrificial layer 114 are formed, for example, by performing a plurality of chemical vapor deposition processes. The number of layers of the insulating layer 112 and the sacrificial layer 114 in the stacked structure 110 may be 8 layers, 16 layers, 24 layers, 48 layers, 96 layers or more, but the invention is not limited thereto. The number of layers of insulating layer 112 and sacrificial layer 114 in stacked structure 110 may depend on the design and density of the memory elements.
在一些實施例中，多個第一記憶體柱120的形成方法如下所述。詳細地說，首先，於堆疊結構110中形成多個開口（未繪示）。開口貫穿堆疊結構110以暴露出基底10的一部分。在一些實施例中，開口的形成方法包括對堆疊結構110進行圖案化製程。在一具體實施例中，圖案化製程例如包括孔蝕刻，以形成穿過堆疊結構110的多個圓柱體形開口，但本發明不限於此。然後，於開口中形成電荷儲存結構122。詳細地說，於基底10上形成電荷儲存材料（未繪示）。電荷儲存材料共形地覆蓋開口的底面與側壁以及堆疊結構110的頂面。之後，進行蝕刻製程，以移除開口底面上以及堆疊結構110頂面上的電荷儲存材料，使得電荷儲存結構122共形地形成在開口的側壁上。在一些實施例中，電荷儲存結構122例如是包括氧化物層/氮化物層/氧化物層（ONO）的複合結構。在一些實施例中，電荷儲存材料的形成方法例如包括化學氣相沉積法（CVD）或原子層沉積法（ALD）。在一些實施例中，蝕刻製程例如包括非等向性蝕刻製程，例如是反應性離子蝕刻（RIE）製程。然後，於基底10上形成薄膜124。薄膜124共形地覆蓋開口的底面以及電荷儲存結構122的表面。在一些實施例中，薄膜124的材料包括半導體材料，例如多晶矽。薄膜124的形成方法例如是CVD。在一些實施例中，薄膜124後續可作為垂直通道結構。然後，於開口中形成絕緣結構126。絕緣結構126填入開口中，且絕緣結構126的頂面低於堆疊結構110的頂面。也就是說，絕緣結構126並未填滿整個開口。在一些實施例中，絕緣結構126的材料例如包括旋塗式介電質（SOD），旋塗式介電質例如是氧化矽或其他絕緣材料。最後，於開口中形成插塞128，詳細地說，沉積導電材料以填充開口的上部，接著，進行化學機械研磨（CMP）製程及/或回蝕製程，以移除堆疊結構110頂面上的導電材料。在一些實施例中，插塞128的材料例如包括多晶矽或摻雜多晶矽。至此，多個第一記憶體柱120的製程完成。在一些實施例中，第一記憶體柱120可以例如為陣列排列、交錯排列或隨機排列。在本實施例中，如圖2所示，位於中間區域的第一記憶體柱120例如為交錯排列，但本發明不限於此。In some embodiments, the method of forming the plurality of first memory pillars 120 is as follows. In detail, first, a plurality of openings (not shown) are formed in the stacked structure 110. An opening extends through the stacked structure 110 to expose a portion of the substrate 10. In some embodiments, the method of forming the opening includes patterning the stacked structure 110. In a specific embodiment, the patterning process includes, for example, hole etching to form a plurality of cylindrical openings through the stacked structure 110, although the invention is not limited thereto. A charge storage structure 122 is then formed in the opening. In detail, a charge storage material (not shown) is formed on the substrate 10. The charge storage material conformally covers the bottom surface and sidewalls of the opening and the top surface of the stacked structure 110. Thereafter, an etching process is performed to remove the charge storage material on the bottom surface of the opening and on the top surface of the stacked structure 110 such that the charge storage structure 122 is conformally formed on the sidewall of the opening. In some embodiments, the charge storage structure 122 is, for example, a composite structure including an oxide layer/nitride layer/oxide layer (ONO). In some embodiments, the method of forming the charge storage material includes, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). In some embodiments, the etch process includes, for example, an anisotropic etch process, such as a reactive ion etch (RIE) process. Then, a film 124 is formed on the substrate 10. The film 124 conformally covers the bottom surface of the opening and the surface of the charge storage structure 122. In some embodiments, the material of film 124 includes a semiconductor material, such as polysilicon. The method of forming the film 124 is, for example, CVD. In some embodiments, the film 124 can subsequently be used as a vertical channel structure. An insulating structure 126 is then formed in the opening. The insulating structure 126 is filled into the opening, and the top surface of the insulating structure 126 is lower than the top surface of the stacked structure 110. That is, the insulating structure 126 does not fill the entire opening. In some embodiments, the material of the insulating structure 126 includes, for example, a spin-on dielectric (SOD), and the spin-on dielectric is, for example, tantalum oxide or other insulating material. Finally, a plug 128 is formed in the opening, in detail, a conductive material is deposited to fill the upper portion of the opening, and then a chemical mechanical polishing (CMP) process and/or an etch back process is performed to remove the top surface of the stacked structure 110. Conductive material. In some embodiments, the material of the plug 128 includes, for example, polysilicon or doped polysilicon. So far, the process of the plurality of first memory pillars 120 is completed. In some embodiments, the first memory pillars 120 can be, for example, arrayed, staggered, or randomly arranged. In the present embodiment, as shown in FIG. 2, the first memory pillars 120 located in the intermediate portion are, for example, staggered, but the present invention is not limited thereto.
圖1B為圖3中沿線B-B’的剖面圖。請同時參照圖1B以及圖3，形成多個溝渠T1於第一電路結構100中且沿X方向排列。具體來說，對堆疊結構110進行圖案化製程，以形成穿過絕緣層112以及犧牲層114的溝渠T1。溝渠T1貫穿堆疊結構110以暴露出基底10的一部分。Figure 1B is a cross-sectional view taken along line B-B' of Figure 3. Referring to FIG. 1B and FIG. 3 simultaneously, a plurality of trenches T1 are formed in the first circuit structure 100 and arranged in the X direction. Specifically, the stacked structure 110 is patterned to form trenches T1 that pass through the insulating layer 112 and the sacrificial layer 114. The trench T1 extends through the stacked structure 110 to expose a portion of the substrate 10.
請參照圖1C，進行閘極置換（gate replacement）製程，將堆疊結構110中的犧牲層114置換為作為閘極的導電材料。詳細來說，首先，移除溝渠T1所暴露的犧牲層114，以形成暴露部分電荷儲存結構122以及絕緣層112表面的側向開口（未示出）。移除溝渠T1所暴露的犧牲層114的方法例如是溼式蝕刻法。在溼式蝕刻法中所使用的蝕刻液例如是磷酸（H 3PO 4）溶液。接著，形成緩衝材料層130於電荷儲存結構122以及絕緣層112暴露的表面上。緩衝材料層130的材料例如是介電常數大於7的高介電常數的材料，例如氧化鋁（Al 2O 3）。緩衝材料層130的形成方法例如是CVD或ALD。然後，形成閘極導電材料層132填入側向開口中。閘極導電材料層132的材料例如包括鎢（W）、氮化鎢（WN）、鉭（Ta）、氮化鉭（TaN）、鈦（Ti）、氮化鈦（TiN）或其組合。閘極導電材料層132的形成方法例如是CVD或物理氣相沉積法（PVD）。 Referring to FIG. 1C, a gate replacement process is performed to replace the sacrificial layer 114 in the stacked structure 110 with a conductive material as a gate. In detail, first, the sacrificial layer 114 exposed by the trench T1 is removed to form a lateral opening (not shown) exposing a portion of the charge storage structure 122 and the surface of the insulating layer 112. A method of removing the sacrificial layer 114 exposed by the trench T1 is, for example, a wet etching method. The etching liquid used in the wet etching method is, for example, a phosphoric acid (H 3 PO 4 ) solution. Next, a buffer material layer 130 is formed on the exposed surface of the charge storage structure 122 and the insulating layer 112. The material of the buffer material layer 130 is, for example, a material having a high dielectric constant having a dielectric constant of more than 7, such as alumina (Al 2 O 3 ). The method of forming the buffer material layer 130 is, for example, CVD or ALD. Then, a gate conductive material layer 132 is formed to fill the lateral opening. The material of the gate conductive material layer 132 includes, for example, tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof. The method of forming the gate conductive material layer 132 is, for example, CVD or physical vapor deposition (PVD).
請參照圖1D，移除部分的閘極導電材料層132以及緩衝材料層130，以在溝渠T1的側壁上形成凹陷。也就是說，閘極導電材料層132a以及緩衝材料層130a的側壁會內凹於絕緣層112的側壁。在一些實施例中，移除部分的閘極導電材料層132以及緩衝材料層130的方法可以是回蝕刻法，例如濕式蝕刻法。Referring to FIG. 1D, a portion of the gate conductive material layer 132 and the buffer material layer 130 are removed to form a recess on the sidewall of the trench T1. That is, the sidewalls of the gate conductive material layer 132a and the buffer material layer 130a are recessed in the sidewalls of the insulating layer 112. In some embodiments, the method of removing portions of the gate conductive material layer 132 and the buffer material layer 130 may be an etch back process, such as a wet etch process.
請參照圖1E，形成介電層140以填滿溝槽T1。在一些實施例中，介電層140的材料例如是氧化矽。形成介電層140的方法例如是CVD或ALD。Referring to FIG. 1E, a dielectric layer 140 is formed to fill the trench T1. In some embodiments, the material of the dielectric layer 140 is, for example, yttrium oxide. The method of forming the dielectric layer 140 is, for example, CVD or ALD.
圖1F為圖4中沿線C-C’的剖面圖，圖1G為圖4中沿線D-D’的剖面圖。請同時參照圖1F、圖1G以及圖4，形成多個開口150於第一電路結構100中且沿Y方向排列。具體來說，多個開口150是形成於填滿介電層140的溝槽T1。開口150貫穿介電層140以暴露出基底10的一部分。在一些實施例中，開口150的形成方法包括對介電層140進行圖案化製程。在一具體實施例中，圖案化製程例如包括孔蝕刻，以形成穿過介電層140的多個圓柱體形開口150，但本發明不限於此。開口150的截面形狀可以包括圓形、橢圓形、方形、多邊形或其組合，因此後續步驟形成的第一導電柱152的截面形狀可以包括圓形、橢圓形、方形、多邊形或其組合。在一些實施例中，開口150（或第一導電柱152）的截面形狀可取決於記憶元件的設計或製程的條件。在一些實施例中，於X方向上，開口150的位置可以與第一記憶體柱120位於一直線上（如圖1F所示）。在另一些實施例中，於X方向上，開口150的位置也可以與第一記憶體柱120非位於一直線上（如圖1G所示），但本發明不限於此。在一些實施例中，多個開口150（或第一導電柱152）為非連續地沿Y方向排列，即兩個相鄰開口150之間有間隔。換句話說，開口150（或第一導電柱152）的位置和數量可取決於記憶元件的設計。舉例來說，為降低阻值，可增加開口150（或第一導電柱152）設置的密度，即縮小兩個相鄰開口150之間的間距。1F is a cross-sectional view taken along line C-C' in Fig. 4, and Fig. 1G is a cross-sectional view taken along line D-D' in Fig. 4. Referring to FIG. 1F, FIG. 1G and FIG. 4 simultaneously, a plurality of openings 150 are formed in the first circuit structure 100 and arranged in the Y direction. Specifically, the plurality of openings 150 are formed in the trench T1 filling the dielectric layer 140. Opening 150 extends through dielectric layer 140 to expose a portion of substrate 10. In some embodiments, the method of forming the opening 150 includes patterning the dielectric layer 140. In a specific embodiment, the patterning process includes, for example, hole etching to form a plurality of cylindrical openings 150 through the dielectric layer 140, although the invention is not limited thereto. The cross-sectional shape of the opening 150 may include a circle, an ellipse, a square, a polygon, or a combination thereof, and thus the cross-sectional shape of the first conductive pillar 152 formed in the subsequent step may include a circle, an ellipse, a square, a polygon, or a combination thereof. In some embodiments, the cross-sectional shape of the opening 150 (or the first conductive pillar 152) may depend on the design of the memory element or the conditions of the process. In some embodiments, the position of the opening 150 may be in a straight line with the first memory pillar 120 in the X direction (as shown in FIG. 1F). In other embodiments, the position of the opening 150 may also be non-linear with the first memory pillar 120 in the X direction (as shown in FIG. 1G), but the invention is not limited thereto. In some embodiments, the plurality of openings 150 (or first conductive pillars 152) are non-continuously aligned in the Y direction, ie, there is a space between two adjacent openings 150. In other words, the location and number of openings 150 (or first conductive posts 152) may depend on the design of the memory element. For example, to reduce the resistance, the density of the opening 150 (or the first conductive pillar 152) may be increased, that is, the spacing between two adjacent openings 150 may be reduced.
值得一提的是，在一些實施例中，開口150於X方向上的寬度可以小於或等於溝渠T1於X方向上的寬度。在另一些實施例中，開口150於X方向上的寬度也可以大於溝渠T1於X方向上的寬度，只要在後續步驟所形成的第一導電柱152不會與閘極導電材料層132a直接接觸即可。也就是說，在後續步驟所形成的第一導電柱152與閘極導電材料層132a之間仍有介電層隔離。It is worth mentioning that in some embodiments, the width of the opening 150 in the X direction may be less than or equal to the width of the trench T1 in the X direction. In other embodiments, the width of the opening 150 in the X direction may also be greater than the width of the trench T1 in the X direction, as long as the first conductive pillar 152 formed in the subsequent step does not directly contact the gate conductive material layer 132a. Just fine. That is, there is still dielectric layer isolation between the first conductive pillar 152 and the gate conductive material layer 132a formed in the subsequent steps.
請參照圖1H，形成導電材料層以填滿開口150。在一些實施例中，導電材料層的材料例如是多晶矽、非晶矽、鈦（Ti）、氮化鈦（TiN）、鎢（W）、氮化鎢（WN）、鉭（Ta）、氮化鉭（TaN）、鋁（Al）、銅（Cu）、鈷（Co）或其組合。形成導電材料層的方法例如是CVD或ALD。接著，可進行CMP製程及/或回蝕製程，以移除堆疊結構110頂面上的導電材料層。至此，多個第一導電柱152形成於第一電路結構100中且沿Y方向排列，其中多個第一導電柱152自第一電路結構100的上層延伸至基底10。在一些實施例中，由於多個開口150是形成於填滿介電層140的溝槽T1，因此所形成的多個第一導電柱152亦是形成於填滿介電層140的溝渠T1中。Referring to FIG. 1H, a layer of conductive material is formed to fill the opening 150. In some embodiments, the material of the conductive material layer is, for example, polycrystalline germanium, amorphous germanium, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), nitride. TaN, aluminum (Al), copper (Cu), cobalt (Co) or a combination thereof. A method of forming a layer of a conductive material is, for example, CVD or ALD. Next, a CMP process and/or an etch back process can be performed to remove the layer of conductive material on the top surface of the stacked structure 110. To this end, a plurality of first conductive pillars 152 are formed in the first circuit structure 100 and arranged in the Y direction, wherein the plurality of first conductive pillars 152 extend from the upper layer of the first circuit structure 100 to the substrate 10. In some embodiments, since the plurality of openings 150 are formed in the trench T1 filling the dielectric layer 140, the plurality of first conductive pillars 152 formed are also formed in the trench T1 filled with the dielectric layer 140. .
值得一提的是，在本實施例中，多個導電柱取代傳統細長的導體溝渠結構。相較於細長的導體溝渠結構，導電柱自周圍所受的應力較為均勻，特別是當導電柱的截面為圓形時，所受應力最為均勻。因此，電路結構的堆疊結構較不易發生傾斜（tilt）的問題。也就是說，在本實施例中，藉由形成多個導電柱取代傳統細長的導體溝渠結構，電路結構較不易產生形變，因此，在後續製程中，可改善電路結構與上層結構之間的對準問題，亦可改善電路結構與後段製程（BEOL）配線的錯誤連接問題及/或後段製程（BEOL）配線的錯誤對準問題。It is worth mentioning that in the present embodiment, a plurality of conductive posts replace the conventional elongated conductor trench structures. Compared with the elongated conductor trench structure, the stress on the conductive column from the surrounding is relatively uniform, especially when the cross section of the conductive column is circular, the stress is most uniform. Therefore, the stacked structure of the circuit structure is less prone to the problem of tilt. That is to say, in the embodiment, by replacing a conventional elongated conductor trench structure by forming a plurality of conductive pillars, the circuit structure is less susceptible to deformation, and therefore, in a subsequent process, the pair between the circuit structure and the upper structure can be improved. The quasi-problem can also improve the wrong connection of the circuit structure and the back-end process (BEOL) wiring and/or the misalignment of the back-end process (BEOL) wiring.
請參照圖1I，在本實施例中，依照前述形成第一電路結構100的方法形成第二電路結構200。第二電路結構200與第一電路結構100的結構、材料、層數以及形成方法可以相同也可以不同，可依據設計需求而調整。在本實施例中，第二電路結構200的結構與第一電路結構100的結構相同，但本發明不限於此。具體來說，第二電路結構200包括多個第二記憶體柱220。將第二電路結構200堆疊於第一電路結構100上，其中第二記憶體柱220分別自第二電路結構200的上層延伸至第一電路結構100，且每一第二記憶體柱220分別電性連接至每一第一記憶體柱120。在一些實施例中，將第二電路結構200堆疊於第一電路結構100上的方法並沒有特別限制。舉例來說，第二電路結構200可以是直接堆疊於第一電路結構100上，第二電路結構200的基底可以是完全移除或是部分移除，只要每一第二記憶體柱220可分別電性連接至每一第一記憶體柱120。在本實施例中，第二電路結構200的基底例如是部分移除（如圖1I所示），但本發明不限於此。Referring to FIG. 1I, in the present embodiment, the second circuit structure 200 is formed in accordance with the foregoing method of forming the first circuit structure 100. The structure, material, number of layers, and formation method of the second circuit structure 200 and the first circuit structure 100 may be the same or different, and may be adjusted according to design requirements. In the present embodiment, the structure of the second circuit structure 200 is the same as that of the first circuit structure 100, but the invention is not limited thereto. In particular, the second circuit structure 200 includes a plurality of second memory pillars 220. The second circuit structure 200 is stacked on the first circuit structure 100, wherein the second memory column 220 extends from the upper layer of the second circuit structure 200 to the first circuit structure 100, and each of the second memory columns 220 is electrically separated. Sexually connected to each of the first memory pillars 120. In some embodiments, the method of stacking the second circuit structure 200 on the first circuit structure 100 is not particularly limited. For example, the second circuit structure 200 may be directly stacked on the first circuit structure 100. The substrate of the second circuit structure 200 may be completely removed or partially removed, as long as each second memory column 220 can be separately Electrically connected to each of the first memory pillars 120. In the present embodiment, the substrate of the second circuit structure 200 is, for example, partially removed (as shown in FIG. 1I), but the invention is not limited thereto.
請參照圖1J，接著，在本實施例中，依照前述形成第一導電柱152的方法於第二電路結構200中形成多個第二導電柱252。第二導電柱252與第一導電柱152的結構、材料、以及形成方法可以相同也可以不同，可依據設計需求而調整。具體來說，形成多個溝渠（未繪示）於第二電路結構200中且沿X方向排列，其中溝渠暴露第一電路結構100的一部分。接著，形成介電層（未繪示）填滿溝渠。然後，形成多個開口（未繪示）於第二電路結構200中且沿Y方向排列，接著，填入導電材料於多個開口中以形成多個第二導電柱252。多個第二導電柱252形成於第二電路結構200中且沿Y方向排列，其中多個第二導電柱252自第二電路結構200的上層延伸至第一電路結構100，且每一第二導電柱252分別電性連接至每一第一導電柱152。在一些實施例中，多個第二導電柱252是形成於填滿介電層的多個溝渠中。Referring to FIG. 1J, then, in the present embodiment, a plurality of second conductive pillars 252 are formed in the second circuit structure 200 in accordance with the foregoing method of forming the first conductive pillars 152. The structure, material, and formation method of the second conductive pillar 252 and the first conductive pillar 152 may be the same or different, and may be adjusted according to design requirements. Specifically, a plurality of trenches (not shown) are formed in the second circuit structure 200 and arranged in the X direction, wherein the trench exposes a portion of the first circuit structure 100. Next, a dielectric layer (not shown) is formed to fill the trench. Then, a plurality of openings (not shown) are formed in the second circuit structure 200 and arranged in the Y direction, and then a conductive material is filled in the plurality of openings to form a plurality of second conductive pillars 252. A plurality of second conductive pillars 252 are formed in the second circuit structure 200 and arranged in the Y direction, wherein the plurality of second conductive pillars 252 extend from the upper layer of the second circuit structure 200 to the first circuit structure 100, and each second The conductive pillars 252 are electrically connected to each of the first conductive pillars 152, respectively. In some embodiments, the plurality of second conductive pillars 252 are formed in a plurality of trenches filled with a dielectric layer.
在一些實施例中，閘極導電材料層可作為字元線，薄膜可作為位元線，導電柱可作為共源極線，但本發明不限於此。In some embodiments, the gate conductive material layer can serve as a word line, the thin film can serve as a bit line, and the conductive pillar can serve as a common source line, but the invention is not limited thereto.
值得一提的是，在本實施例中，如上所述，多個導電柱取代傳統細長的導體溝渠結構，由於導電柱自周圍所受應力較為均勻，故電路結構的堆疊結構較不易發生傾斜的問題。也就是說，在本實施例中，由於第一電路結構100較不易產生形變，因此，第二電路結構200在堆疊於第一電路結構100上時，較不易產生錯誤對準的問題。然而，在本實施例中，是以堆疊兩個相同結構的電路結構做說明，但本發明不限於此。在其他實施例中，亦可堆疊兩個不同結構的電路結構。此外，在其他實施例中，亦可堆疊兩個以上的電路結構，並不僅限於堆疊兩個電路結構。因此，在本發明的實施例中，除了可改善電路結構之間的對準問題，亦可改善電路結構與後段製程（BEOL）配線的錯誤連接問題及/或後段製程（BEOL）配線的錯誤對準問題。It is worth mentioning that, in this embodiment, as described above, a plurality of conductive pillars replace the traditional elongated conductor trench structure, and since the conductive pillars are relatively uniformly stressed from the surroundings, the stacked structure of the circuit structure is less prone to tilting. problem. That is to say, in the present embodiment, since the first circuit structure 100 is less susceptible to deformation, the second circuit structure 200 is less prone to misalignment when stacked on the first circuit structure 100. However, in the present embodiment, the description is made by stacking two circuit structures of the same structure, but the present invention is not limited thereto. In other embodiments, two different configurations of circuit structures may also be stacked. In addition, in other embodiments, more than two circuit structures may be stacked, and are not limited to stacking two circuit structures. Therefore, in the embodiment of the present invention, in addition to improving alignment problems between circuit structures, it is also possible to improve the wrong connection of the circuit structure and the back end of line (BEOL) wiring and/or the error of the back end of the process (BEOL) wiring. Quasi-problem.
以下，將參照圖1J說明本發明記憶元件的結構。此外，本實施例的記憶元件的製造方法雖然是以上述方法為例進行說明，然而本發明的記憶元件的製造方法並不以此為限。Hereinafter, the structure of the memory element of the present invention will be described with reference to FIG. 1J. Further, although the method of manufacturing the memory element of the present embodiment has been described by taking the above method as an example, the method of manufacturing the memory element of the present invention is not limited thereto.
請參照圖1J，記憶元件包括基底10、第一電路結構100、多個第一導電柱152、第二電路結構200以及多個第二導電柱252。第一電路結構100設置於基底上10。多個第一導電柱152設置於第一電路結構100中且沿Y方向排列，其中多個第一導電柱152自第一電路結構100的上層延伸至基底10。第二電路結構200設置於第一電路結構100上。多個第二導電柱252設置於第二電路結構200中且沿Y方向排列，其中多個第二導電柱252自第二電路結構200的上層延伸至第一電路結構100，且每一第二導電柱252分別電性連接至每一第一導電柱152。Referring to FIG. 1J, the memory element includes a substrate 10, a first circuit structure 100, a plurality of first conductive pillars 152, a second circuit structure 200, and a plurality of second conductive pillars 252. The first circuit structure 100 is disposed on the substrate 10. A plurality of first conductive pillars 152 are disposed in the first circuit structure 100 and arranged in the Y direction, wherein the plurality of first conductive pillars 152 extend from the upper layer of the first circuit structure 100 to the substrate 10. The second circuit structure 200 is disposed on the first circuit structure 100. A plurality of second conductive pillars 252 are disposed in the second circuit structure 200 and arranged in the Y direction, wherein the plurality of second conductive pillars 252 extend from the upper layer of the second circuit structure 200 to the first circuit structure 100, and each second The conductive pillars 252 are electrically connected to each of the first conductive pillars 152, respectively.
在一些實施例中，多個第一導電柱152以及多個第二導電柱252的截面形狀包括圓形、橢圓形、方形、多邊形或其組合。在一些實施例中，第一導電柱152的截面沿X方向具有第一寬度，第一導電柱152的高度與第一寬度的比值介於15至28之間。在一些實施例中，第二導電柱252的截面沿X方向具有第二寬度，第二導電柱252的高度與寬度的比值介於15至28之間。在一些實施例中，相鄰兩個第一導電柱152之間以及相鄰兩個第二導電柱252之間在Y方向上的間隔例如分別大於或等於750奈米，但本發明不限於此。在一些實施例中，第一電路結構100以及第二電路結構200分別包括多個第一記憶體柱152以及多個第二記憶體柱252，且每一第一記憶體柱152分別電性連接至每一第二記憶體柱252。In some embodiments, the cross-sectional shapes of the plurality of first conductive pillars 152 and the plurality of second conductive pillars 252 include a circle, an ellipse, a square, a polygon, or a combination thereof. In some embodiments, the cross section of the first conductive pillar 152 has a first width in the X direction, and the ratio of the height of the first conductive pillar 152 to the first width is between 15 and 28. In some embodiments, the cross section of the second conductive pillar 252 has a second width in the X direction, and the ratio of the height to the width of the second conductive pillar 252 is between 15 and 28. In some embodiments, the spacing between adjacent two first conductive pillars 152 and between adjacent two second conductive pillars 252 in the Y direction is, for example, greater than or equal to 750 nm, respectively, but the invention is not limited thereto. . In some embodiments, the first circuit structure 100 and the second circuit structure 200 respectively include a plurality of first memory pillars 152 and a plurality of second memory pillars 252, and each of the first memory pillars 152 is electrically connected To each second memory column 252.
綜上所述，在本發明的記憶元件中，形成多個導電柱取代傳統細長的導體溝渠結構。相較於細長的導體溝渠結構，導電柱所受的應力較為均勻，因此，記憶元件中電路結構的堆疊結構較不易發生傾斜的問題，即電路結構較不易產生形變。也就是說，本發明的記憶元件不僅可改善電路結構之間的對準問題，亦可改善電路結構與後段製程（BEOL）配線的錯誤連接問題及/或後段製程（BEOL）配線的錯誤對準問題。In summary, in the memory element of the present invention, a plurality of conductive pillars are formed in place of the conventional elongated conductor trench structure. Compared with the elongated conductor trench structure, the stress on the conductive pillar is relatively uniform. Therefore, the stack structure of the circuit structure in the memory component is less prone to tilting, that is, the circuit structure is less susceptible to deformation. That is to say, the memory element of the present invention not only improves alignment problems between circuit structures, but also improves misconnection of circuit structures and back end of line (BEOL) wiring and/or misalignment of back end of line (BEOL) wiring. problem.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10‧‧‧基底10‧‧‧Base
100‧‧‧第一電路結構100‧‧‧First circuit structure
110‧‧‧堆疊結構110‧‧‧Stack structure
112‧‧‧絕緣層112‧‧‧Insulation
114‧‧‧犧牲層114‧‧‧ Sacrifice layer
120‧‧‧第一記憶體柱120‧‧‧First memory column
122‧‧‧電荷儲存結構122‧‧‧Charge storage structure
24‧‧‧薄膜24‧‧‧film
126‧‧‧絕緣結構126‧‧‧Insulation structure
128‧‧‧插塞128‧‧‧ Plug
130、130a‧‧‧緩衝材料層130, 130a‧‧‧ cushioning material layer
132、132a‧‧‧閘極導電材料層132, 132a‧‧‧ gate conductive material layer
140‧‧‧介電層140‧‧‧Dielectric layer
150‧‧‧開口150‧‧‧ openings
152‧‧‧第一導電柱152‧‧‧First conductive column
200‧‧‧第二電路結構200‧‧‧Second circuit structure
220‧‧‧第二記憶體柱220‧‧‧Second memory column
252‧‧‧第二導電柱 252‧‧‧second conductive column
A-A’、B-B’、C-C’、D-D’‧‧‧線 A-A’, B-B’, C-C’, D-D’‧‧‧ lines
T1‧‧‧溝渠 T1‧‧‧ Ditch
X、Y、Z‧‧‧方向 X, Y, Z‧‧ Direction
圖1A至圖1J是本發明一些實施例的記憶元件的製造流程剖面示意圖。 圖2以及圖3分別是圖1A以及圖1B的上視圖。 圖4是圖1F以及圖1G的上視圖。1A through 1J are schematic cross-sectional views showing a manufacturing process of a memory element according to some embodiments of the present invention. 2 and 3 are top views of Figs. 1A and 1B, respectively. Figure 4 is a top view of Figure 1F and Figure 1G.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107123982A TWI668799B (en) | 2018-07-11 | 2018-07-11 | Memory device and method of fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107123982A TWI668799B (en) | 2018-07-11 | 2018-07-11 | Memory device and method of fabricating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI668799B true TWI668799B (en) | 2019-08-11 |
| TW202006888A TW202006888A (en) | 2020-02-01 |
Family
ID=68316552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107123982A TWI668799B (en) | 2018-07-11 | 2018-07-11 | Memory device and method of fabricating the same |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI668799B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI770869B (en) * | 2020-04-14 | 2022-07-11 | 南亞科技股份有限公司 | Vertical memory stucture with air gaps and method for preparing the same |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI727761B (en) * | 2020-04-23 | 2021-05-11 | 旺宏電子股份有限公司 | Memory device and method of fabricating the same |
| US11348941B2 (en) | 2020-04-23 | 2022-05-31 | Macronix International Co., Ltd. | Memory device and method of fabricating the same |
| US11538827B2 (en) | 2020-07-23 | 2022-12-27 | Macronix International Co., Ltd. | Three-dimensional memory device with increased memory cell density |
| TWI785764B (en) * | 2021-08-30 | 2022-12-01 | 旺宏電子股份有限公司 | 3d and flash memory device and method of fabricating the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201334121A (en) * | 2012-02-01 | 2013-08-16 | Macronix Int Co Ltd | Three dimensional memory array adjacent to trench sidewalls and manufacturing method thereof |
| US20160104715A1 (en) * | 2014-02-20 | 2016-04-14 | Sandisk Technologies Inc. | Multilevel memory stack structure and methods of manufacturing the same |
-
2018
- 2018-07-11 TW TW107123982A patent/TWI668799B/en active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201334121A (en) * | 2012-02-01 | 2013-08-16 | Macronix Int Co Ltd | Three dimensional memory array adjacent to trench sidewalls and manufacturing method thereof |
| US20160104715A1 (en) * | 2014-02-20 | 2016-04-14 | Sandisk Technologies Inc. | Multilevel memory stack structure and methods of manufacturing the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI770869B (en) * | 2020-04-14 | 2022-07-11 | 南亞科技股份有限公司 | Vertical memory stucture with air gaps and method for preparing the same |
| US11411019B2 (en) | 2020-04-14 | 2022-08-09 | Nanya Technology Corporation | Vertical memory structure with air gaps and method for preparing the same |
| US11877455B2 (en) | 2020-04-14 | 2024-01-16 | Nanya Technology Corporation | Method for preparing vertical memory structure with air gaps |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202006888A (en) | 2020-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI668799B (en) | Memory device and method of fabricating the same | |
| US10886289B2 (en) | Integrated circuit device including vertical memory device and method of manufacturing the same | |
| US10461153B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| EP3271944B1 (en) | Honeycomb cell structure three-dimensional non-volatile memory device | |
| US9899394B2 (en) | Vertical memory devices having contact plugs contacting stacked gate electrodes | |
| US9343475B2 (en) | Vertical memory devices and methods of manufacturing the same | |
| US20150214242A1 (en) | Vertical non-volatile memory devices and methods of manufacturing the same | |
| US10797071B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| US9953985B2 (en) | Method of manufacturing integrated circuit device | |
| US10804363B2 (en) | Three-dimensional semiconductor memory device and method of fabricating the same | |
| CN112310080A (en) | Semiconductor memory device and method of manufacturing the same | |
| KR20180126210A (en) | Vertical semiconductor devices | |
| US20210265385A1 (en) | Three-dimensional memory device including discrete memory elements and method of making the same | |
| US20190157275A1 (en) | Semiconductor devices | |
| US10522350B2 (en) | Method of fabricating three-dimensional semiconductor devices | |
| US11244953B2 (en) | Three-dimensional memory device including molybdenum word lines and metal oxide spacers and method of making the same | |
| US20170200723A1 (en) | Semiconductor devices having a gate structure and a conductive line and methods of manufacturing the same | |
| US20220052073A1 (en) | Three-dimensional memory device including discrete memory elements and method of making the same | |
| US11139197B2 (en) | Method of fabricating semiconductor device | |
| US10438802B2 (en) | Method of fabricating a semiconductor device | |
| US11398392B2 (en) | Integrated circuit device and method of manufacturing the same | |
| US20200020711A1 (en) | Memory device and method of fabricating the same | |
| CN110729305A (en) | Memory element and method for manufacturing the same | |
| US20220406786A1 (en) | Semiconductor devices having dummy gate structures | |
| US11785763B2 (en) | Semiconductor devices having contact plugs |