TWI581554B

TWI581554B - Interleaved flyback converter

Info

Publication number: TWI581554B
Application number: TW105115618A
Authority: TW
Inventors: 鄭宏良; 謝時淵; 蘇鵬宇
Original assignee: 義守大學
Priority date: 2016-05-19
Filing date: 2016-05-19
Publication date: 2017-05-01
Also published as: TW201810909A

Description

交錯式返馳轉換器 Interleaved flyback converter

本發明係關於一種交錯式返馳轉換器，尤其是一種將二組返馳電路交錯設置的返馳轉換器。 The present invention relates to an interleaved flyback converter, and more particularly to a flyback converter in which two sets of flyback circuits are interleaved.

為了維持電力或信號的傳輸穩定性，電源轉換器可謂電子電路中不可或缺的必要構件。隨著科技的發展，人們對於電源轉換器之效能的重視程度更是與日俱增，如何使電源轉換器可降低切換損失以提升電路效率，始終是研發人員致力追尋的目標。 In order to maintain the transmission stability of power or signals, power converters are an indispensable component in electronic circuits. With the development of technology, people pay more attention to the performance of power converters. How to make power converters reduce switching losses to improve circuit efficiency is always the goal that R&D personnel are striving for.

以習知單級返馳轉換器(Flyback Converter)為例，當整體電路運作於高頻環境時，該習知單級返馳轉換器的主動開關亦必須操作在高頻環境，當該主動開關無法以零電壓或零電流等方式進行柔性切換時，該主動開關將於每一次的切換中產生切換損失，且該切換損失與該操作頻率成正比，亦即當整體電路運作於越高頻時，該切換損失就越大，連帶造成電路效率愈低，導致該習知單級返馳轉換器僅能適用於低頻或低功率的電路中。 Taking the conventional single-stage flyback converter as an example, when the whole circuit operates in a high frequency environment, the active switch of the conventional single-stage flyback converter must also operate in a high frequency environment, when the active switch When the flexible switching cannot be performed in a zero voltage or zero current manner, the active switch will generate a switching loss in each switching, and the switching loss is proportional to the operating frequency, that is, when the overall circuit operates at a higher frequency. The greater the switching loss, the lower the circuit efficiency caused by the connection, resulting in the conventional single-stage flyback converter being only applicable to low frequency or low power circuits.

有鑑於此，本發明提供一種交錯式返馳轉換器，以解決習知單級返馳轉換器之電路效率不佳的問題。 In view of this, the present invention provides an interleaved flyback converter to solve the problem of poor circuit efficiency of the conventional single stage flyback converter.

本發明之目的係提供一種交錯式返馳轉換器，該交錯式返馳轉換器可使二組返馳電路互用二組開關的本質二極體，使該二組開關可在零電壓下進行切換以減少切換損失，具有提升電路效率的效果。 The object of the present invention is to provide an interleaved flyback converter that can use two sets of flyback circuits to mutually use the essential diodes of two sets of switches, so that the two sets of switches can be operated at zero voltage. Switching to reduce switching losses has the effect of improving circuit efficiency.

本發明全文所述之「耦接」(coupling)，係指二裝置之間藉由有線實體、無線媒介或其組合(例如：異質網路)等方式，而使二裝置間具有訊號或電力傳遞之連接關係。 "Coupling" as used throughout the present invention means that there is a wired entity, a wireless medium, or a combination thereof (for example, a heterogeneous network) between two devices to provide signal or power transfer between the two devices. The connection relationship.

為達到前述發明目的，本發明之交錯式返馳轉換器，包含：一電力輸入埠，該電力輸入埠具有一第一端及一第二端，該電力輸入埠的第二端耦接一接地端；一第一返馳電路，該第一返馳電路具有一第一變壓器、一第一開關及一第一二極體，該第一變壓器具有一第一初級側繞組及一第一次級側繞組，該第一初級側繞組耦接該電力輸入埠之該第一端，該第一開關耦接於該第一初級側繞組及該接地端之間，該第一二極體之一陰極端耦接該第一次級側繞組；一第二返馳電路，該第二返馳電路具有一第二變壓器、一第二開關及一第二二極體，該第二變壓器具有一第二初級側繞組及一第二次級側繞組，該第二初級側繞組耦接該電力輸入埠之該第一端及該第一二極體之一陽極端，該第二次級側繞組耦接該第一次級側繞組，該第二開關耦接該第二初級側繞組及該接地端之間，該第二二極體之一陽極端耦接於該第一初級側繞組及該第一開關之間的接點，該第二二極體之一陰極端耦接該第二次級側繞組；及一電力輸出埠，該電力輸出埠具有一第一端及一第二端，該電力輸出埠之該第一端耦接該第一次級側繞組及該第二次級側繞組，該電力輸出埠之該第二端耦接該接地端，且該電力輸出埠之該第一端及該第二端之間耦接一輸出電容。藉此，該第一返馳電路與該第二返馳電路可互用該第一開關及該第二開關，並使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果。 In order to achieve the foregoing object, the interleaved flyback converter of the present invention comprises: a power input port having a first end and a second end, the second end of the power input port being coupled to a ground a first flyback circuit, the first flyback circuit has a first transformer, a first switch and a first diode, the first transformer having a first primary side winding and a first secondary a side winding, the first primary side winding is coupled to the first end of the power input port, the first switch is coupled between the first primary side winding and the ground end, and the first diode is Extremely coupling the first secondary side winding; a second flyback circuit, the second flyback circuit has a second transformer, a second switch and a second diode, the second transformer has a second a primary side winding and a second secondary side winding, the second primary side winding is coupled to the first end of the power input port and one of the first diodes, the second secondary side winding is coupled to the first side winding a first secondary side winding, the second switch is coupled to the second primary side winding and the connection The anode end of the second diode is coupled to the junction between the first primary side winding and the first switch, and the cathode end of the second diode is coupled to the second secondary a side winding; and a power output port having a first end and a second end, the first end of the power output port being coupled to the first secondary side winding and the second secondary side winding The second end of the power output port is coupled to the ground end, and an output capacitor is coupled between the first end and the second end of the power output port. Thereby, the first flyback circuit and the second flyback circuit can mutually use the first switch and the second switch, and the first switch and the second switch can satisfy zero voltage switching conduction to reduce Switching losses, in turn, has the effect of improving overall circuit efficiency.

其中，該第一開關具有一第一端、一第二端及一控制端，該第一開關之該第一端耦接該第一初級側繞組，該第一開關之該第二端耦接該接地端。藉此，該第一返馳電路與該第二返馳電路可互用該第一開關及該第二開關，並使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果。 The first switch has a first end, a second end, and a control end. The first end of the first switch is coupled to the first primary side winding, and the second end of the first switch is coupled. The ground terminal. Thereby, the first flyback circuit and the second flyback circuit can mutually use the first switch and The second switch enables the first switch and the second switch to meet the zero voltage switching conduction to reduce the switching loss, thereby improving the overall circuit efficiency.

其中，該第一開關為一第一電晶體，並具有一第一寄生電容及一第一本質二極體，該第一電晶體之一汲極係為該第一開關之該第一端，該第一電晶體之一源極係為該第一開關之該第二端，該第一電晶體之一閘極係為該第一開關之該控制端。該第一返馳電路與該第二返馳電路可互用該第一開關的第一本質二極體及該第二開關的第二本質二極體，並使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果。 The first switch is a first transistor, and has a first parasitic capacitance and a first intrinsic diode. One of the first transistors is the first end of the first switch. One source of the first transistor is the second end of the first switch, and one of the gates of the first transistor is the control end of the first switch. The first flyback circuit and the second flyback circuit can mutually use the first essential diode of the first switch and the second essential diode of the second switch, and make the first switch and the second The switch can meet the zero voltage switching conduction to reduce the switching loss, thereby improving the overall circuit efficiency.

其中，該第二開關具有一第一端、一第二端及一控制端，該第二開關之該第一端耦接該第二初級側繞組及該第一二極體之該陽極端，該第二開關之該第二端耦接該第一開關之該第二端及該接地端。藉此，該第一返馳電路與該第二返馳電路可互用該第一開關及該第二開關，並使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果。 The second switch has a first end, a second end, and a control end. The first end of the second switch is coupled to the second primary side winding and the anode end of the first diode. The second end of the second switch is coupled to the second end of the first switch and the ground end. Thereby, the first flyback circuit and the second flyback circuit can mutually use the first switch and the second switch, and the first switch and the second switch can satisfy zero voltage switching conduction to reduce Switching losses, in turn, has the effect of improving overall circuit efficiency.

其中，該第二開關為一第二電晶體，並具有一第二寄生電容及一第二本質二極體，該第二電晶體之一汲極係為該第二開關之該第一端，該第二電晶體之一源極係為該第二開關之該第二端，該第二電晶體之一閘極係為該第二開關之該控制端。藉此，該第一返馳電路與該第二返馳電路可互用該第一開關的第一本質二極體及該第二開關的第二本質二極體，並使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果。 The second switch is a second transistor and has a second parasitic capacitance and a second intrinsic diode. One of the second transistors is the first end of the second switch. One source of the second transistor is the second end of the second switch, and one of the gates of the second transistor is the control end of the second switch. Thereby, the first flyback circuit and the second flyback circuit can mutually use the first essential diode of the first switch and the second essential diode of the second switch, and make the first switch and The second switch can satisfy the zero voltage switching conduction to reduce the switching loss, thereby improving the overall circuit efficiency.

其中，該第一初級側繞組具有一第一端及一第二端，該第一初級側繞組之該第一端耦接該電力輸入埠之該第一端，該第一初級側繞組之該第二端耦接該第一開關之該第一端及該第二二極體之該陽極端；該第一次級側繞組具有一第一端及一第二端，該第一次級側繞組之該第一端耦接該第一二極體之該陰極端，該第一次級側繞組之該第二端耦接該電力輸出埠之該第一端。藉此，該第一返馳電路與該第二返馳電路可互用該第一開關的第一本質二極體及該第二開關的第二本質二極體，並使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果。 Wherein the first primary side winding has a first end and a second end, the first end of the first primary side winding is coupled to the first end of the power input port, the first primary side winding The second end is coupled to the first end of the first switch and the anode end of the second diode; a second side winding has a first end and a second end, the first end of the first secondary side winding is coupled to the cathode end of the first diode, the first side of the first side winding The two ends are coupled to the first end of the power output port. Thereby, the first flyback circuit and the second flyback circuit can mutually use the first essential diode of the first switch and the second essential diode of the second switch, and make the first switch and The second switch can satisfy the zero voltage switching conduction to reduce the switching loss, thereby improving the overall circuit efficiency.

其中，該第二初級側繞組具有一第一端及一第二端，該第二初級側繞組之該第一端耦接該電力輸入埠之該第一端及該第一初級側繞組之該第一端，該第二初級側繞組之該第二端耦接該第二開關之該第一端及該第一二極體之該陽極端；該第二次級側繞組具有一第一端及一第二端，該第二次級側繞組之該第一端耦接該第二二極體之該陰極端，該第二次級側繞組之該第二端耦接該第一次級側繞組之該第二端及該電力輸出埠之該第一端。藉此，該第一返馳電路與該第二返馳電路可互用該第一開關的第一本質二極體及該第二開關的第二本質二極體，並使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果。 The second primary winding has a first end and a second end, and the first end of the second primary winding is coupled to the first end of the power input port and the first primary side winding a first end, the second end of the second primary side winding is coupled to the first end of the second switch and the anode end of the first diode; the second secondary side winding has a first end And a second end, the first end of the second secondary winding is coupled to the cathode end of the second diode, and the second end of the second secondary winding is coupled to the first secondary The second end of the side winding and the first end of the power output port. Thereby, the first flyback circuit and the second flyback circuit can mutually use the first essential diode of the first switch and the second essential diode of the second switch, and make the first switch and The second switch can satisfy the zero voltage switching conduction to reduce the switching loss, thereby improving the overall circuit efficiency.

其中，另具有一控制器，該控制器耦接該第一開關之該控制端以傳輸一第一控制信號，該控制器耦接該第二開關之該控制端以傳輸一第二控制信號。藉此，可使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，且可避免該第一開關及該第二開關因同時導通而燒毀，進而具有提高整體電路效率及維持電路正常運作等效果。 The controller further includes a controller, the controller is coupled to the control end of the first switch to transmit a first control signal, and the controller is coupled to the control end of the second switch to transmit a second control signal. Thereby, the first switch and the second switch can satisfy the zero voltage switching conduction to reduce the switching loss, and the first switch and the second switch can be prevented from being burned due to simultaneous conduction, thereby improving the overall circuit. Efficiency and maintaining the normal operation of the circuit.

其中，該第一控制信號及該第二控制信號係分別具有一操作區段及一怠遲區段，在該操作區段中，該第一控制信號的準位及該第二控制信號的準位係彼此相反；在該怠遲區段中，該第一控制信號的準位及該第二控制信號的準位均呈低準位。藉此，可使該第一開關及該第二開關皆可滿足零電壓切換導通，以降低切換損失，且可避免該第一開關及該第二開關因同時導通而燒毀，進而具有提高整體電路效率及維持電路正常運作等效果。 The first control signal and the second control signal respectively have an operation section and a delay section. In the operation section, the level of the first control signal and the second control signal are accurate. The bit lines are opposite to each other; in the late phase, the level of the first control signal and the level of the second control signal are both at a low level. Thereby, the first switch and the second switch can be both The zero voltage switching conduction can be satisfied to reduce the switching loss, and the first switch and the second switch can be prevented from being burnt due to simultaneous conduction, thereby improving the overall circuit efficiency and maintaining the normal operation of the circuit.

〔本發明〕〔this invention〕

1‧‧‧電力輸入埠 1‧‧‧Power input埠

11‧‧‧第一端 11‧‧‧ first end

12‧‧‧第二端 12‧‧‧ second end

2‧‧‧第一返馳電路 2‧‧‧First flyback circuit

3‧‧‧第二返馳電路 3‧‧‧second flyback circuit

4‧‧‧電力輸出埠 4‧‧‧Power output埠

41‧‧‧第一端 41‧‧‧ first end

42‧‧‧第二端 42‧‧‧second end

5‧‧‧控制器 5‧‧‧ Controller

A1‧‧‧操作區段 A1‧‧‧Operation section

A2‧‧‧怠遲區段 A2‧‧‧ Late section

C‧‧‧輸出電容 C‧‧‧ output capacitor

C_S1‧‧‧第一寄生電容 C _S1 ‧‧‧First parasitic capacitance

C_S2‧‧‧第二寄生電容 C _S2 ‧‧‧Second parasitic capacitance

D1‧‧‧第一二極體 D1‧‧‧First Diode

D2‧‧‧第二二極體 D2‧‧‧ second diode

D_S1‧‧‧第一本質二極體 D _S1 ‧‧‧First Essential Dipole

D_S2‧‧‧第二本質二極體 D _S2 ‧‧‧Second essential diode

N11‧‧‧第一初級側繞組 N11‧‧‧First primary side winding

N12‧‧‧第一次級側繞組 N12‧‧‧First secondary winding

N21‧‧‧第二初級側繞組 N21‧‧‧second primary side winding

N22‧‧‧第二次級側繞組 N22‧‧‧second secondary winding

R‧‧‧輸出電阻 R‧‧‧ output resistance

S1‧‧‧第一開關 S1‧‧‧ first switch

S2‧‧‧第二開關 S2‧‧‧ second switch

T1‧‧‧第一變壓器 T1‧‧‧ first transformer

T2‧‧‧第二變壓器 T2‧‧‧second transformer

V1‧‧‧第一控制信號 V1‧‧‧ first control signal

V2‧‧‧第二控制信號 V2‧‧‧second control signal

第1圖：本發明交錯式返馳轉換器之電路圖。 Figure 1 is a circuit diagram of an interleaved flyback converter of the present invention.

第2圖：本發明交錯式返馳轉換器之控制信號圖。 Figure 2: Control signal diagram of the interleaved flyback converter of the present invention.

第3A圖：本發明交錯式返馳轉換器之工作模式I電流示意圖。 Figure 3A is a schematic diagram of the operation mode I current of the interleaved flyback converter of the present invention.

第3B圖：本發明交錯式返馳轉換器之工作模式II電流示意圖。 Figure 3B: Schematic diagram of the operation mode II of the interleaved flyback converter of the present invention.

第3C圖：本發明交錯式返馳轉換器之工作模式III電流示意圖。 Figure 3C: Schematic diagram of the operation mode III of the interleaved flyback converter of the present invention.

第3D圖：本發明交錯式返馳轉換器之工作模式IV電流示意圖。 Figure 3D is a schematic diagram of the operation mode IV current of the interleaved flyback converter of the present invention.

第3E圖：本發明交錯式返馳轉換器之工作模式V電流示意圖。 Figure 3E is a schematic diagram of the operating mode V current of the interleaved flyback converter of the present invention.

第3F圖：本發明交錯式返馳轉換器之工作模式VI電流示意圖。 Figure 3F is a schematic diagram of the operation mode VI current of the interleaved flyback converter of the present invention.

第3G圖：本發明交錯式返馳轉換器之工作模式VII電流示意圖。 Figure 3G: Schematic diagram of the operation mode VII of the interleaved flyback converter of the present invention.

第3H圖：本發明交錯式返馳轉換器之工作模式VIII電流示意圖。 Figure 3H: Schematic diagram of the operation mode VIII current of the interleaved flyback converter of the present invention.

第4圖：本發明交錯式返馳轉換器之電壓電流波形示意圖。 Figure 4 is a diagram showing the voltage and current waveforms of the interleaved flyback converter of the present invention.

為讓本發明之上述及其他目的、特徵及優點能更明顯易懂，下文特舉本發明之較佳實施例，並配合所附圖式，作詳細說明如下： The above and other objects, features and advantages of the present invention will become more <RTIgt;

請參照第1圖所示，本發明之交錯式返馳轉換器包含一電力輸入埠1、一第一返馳電路2、一第二返馳電路3及一電力輸出埠4。該第一返馳電路2係耦接該第二返馳電路3，該電力輸入埠1及該電力輸出埠4均同時耦接該第一返馳電路2及該第二返馳電路3。 Referring to FIG. 1 , the interleaved flyback converter of the present invention includes a power input port 1 , a first flyback circuit 2 , a second flyback circuit 3 , and a power output port 4 . The first flyback circuit 2 is coupled to the second flyback circuit 3, and the power input port 1 and the power output port 4 are both coupled to the first flyback circuit 2 and the second flyback circuit 3.

該電力輸入埠1具有一第一端11及一第二端12，該電力輸入埠1可耦接一直流電壓源，或者耦接用以輸出直流電之電力裝置，且該電力輸入埠1的第二端12耦接一接地端。 The power input port 1 has a first end 11 and a second end 12. The power input port 1 can be coupled to a DC voltage source or coupled to a power device for outputting DC power. The second end 12 of the power input port 1 is coupled to a ground end.

該第一返馳電路2具有一第一變壓器T1、一第一開關S1及一第一二極體D1，該第一變壓器T1具有一第一初級側繞組N11及一第一次級側繞組N12，該第一初級側繞組N11耦接該電力輸入埠1之該第一端11，該第一開關S1具有一第一端、一第二端及一控制端，該第一開關S1之該第一端耦接該第一初級側繞組N11，該第一開關S1之該第二端耦接該接地端，該第一二極體D1之一陰極端耦接該第一次級側繞組N12。 The first flyback circuit 2 has a first transformer T1, a first switch S1 and a first diode D1. The first transformer T1 has a first primary side winding N11 and a first secondary side winding N12. The first primary side winding N11 is coupled to the first end 11 of the power input port 1. The first switch S1 has a first end, a second end, and a control end. The first switch S1 is One end of the first switch S1 is coupled to the ground end, and one end of the first diode D1 is coupled to the first secondary side winding N12.

該第二返馳電路3具有一第二變壓器T2、一第二開關S2及一第二二極體D2，該第二變壓器T2具有一第二初級側繞組N21及一第二次級側繞組N22，該第二初級側繞組N21耦接該電力輸入埠1之該第一端11及該第一二極體D1之一陽極端，該第二次級側繞組N22耦接該第一次級側繞組N12，該第二開關S2具有一第一端、一第二端及一控制端，該第二開關S2之該第一端耦接該第二初級側繞組N21及該第一二極體D1之該陽極端，該第二開關S2之該第二端耦接該接地端，該第二二極體D2之一陽極端耦接該第一初級側繞組N11及該第一開關S1之該第一端，該第二二極體D2之一陰極端耦接該第二次級側繞組N22。 The second flyback circuit 3 has a second transformer T2, a second switch S2 and a second diode D2. The second transformer T2 has a second primary winding N21 and a second secondary winding N22. The second primary side winding N21 is coupled to the first end 11 of the power input port 1 and the anode end of the first diode D1. The second secondary side winding N22 is coupled to the first secondary side winding. N12, the second switch S2 has a first end, a second end, and a control end. The first end of the second switch S2 is coupled to the second primary side winding N21 and the first diode D1. The anode end of the second switch S2 is coupled to the ground end. The anode end of the second diode D2 is coupled to the first primary side winding N11 and the first end of the first switch S1. The cathode end of one of the second diodes D2 is coupled to the second secondary side winding N22.

為了能清楚了解該第一返馳電路2與該第二返馳電路3的交錯式連接關係，以下特別針對該第一初級側繞組N11、該第一次級側繞組N12、該第二初級側繞組N21及該第二次級側繞組N22的連接關係作詳細的描述。 In order to clearly understand the interleaved connection relationship between the first flyback circuit 2 and the second flyback circuit 3, the following is particularly directed to the first primary side winding N11, the first secondary side winding N12, and the second primary side. The connection relationship between the winding N21 and the second secondary side winding N22 will be described in detail.

更詳言之，該第一初級側繞組N11具有一第一端及一第二端，該第一初級側繞組N11之該第一端耦接該電力輸入埠1之該第一端11，該第一初級側繞組N11之該第二端耦接該第一開關S1之該第一端及該第二二極體D2之該陽極端；該第一次級側繞組N12具有一第一端及一第二端，該第一次級側繞組N12之該第一端耦接該第一二極體D1之該陰極端，該第一次級側繞組N12之該第二端耦接該電力輸出埠4。 In more detail, the first primary side winding N11 has a first end and a second end, and the first end of the first primary side winding N11 is coupled to the first end 11 of the power input port 1, The second end of the first primary side winding N11 is coupled to the first end of the first switch S1 and the anode end of the second diode D2; the first secondary side winding N12 has a first end and a second end, the first end of the first secondary side winding N12 is coupled to the cathode of the first diode D1 Extremely, the second end of the first secondary side winding N12 is coupled to the power output 埠4.

其中，該第二初級側繞組N21具有一第一端及一第二端，該第二初級側繞組N21之該第一端耦接該電力輸入埠1之該第一端及該第一初級側繞組N11之該第一端，該第二初級側繞組N21之該第二端耦接該第二開關S2之該第一端及該第一二極體D1之該陽極端；該第二次級側繞組N22具有一第一端及一第二端，該第二次級側繞組N22之該第一端耦接該第二二極體D2之該陰極端，該第二次級側繞組N22之該第二端耦接該第一次級側繞組N12之該第二端及該電力輸出埠4。 The first primary side winding N21 has a first end and a second end. The first end of the second primary side winding N21 is coupled to the first end of the power input port 1 and the first primary side. The first end of the winding N11, the second end of the second primary winding N21 is coupled to the first end of the second switch S2 and the anode end of the first diode D1; the second secondary The side winding N22 has a first end and a second end, the first end of the second secondary side winding N22 is coupled to the cathode end of the second diode D2, and the second secondary side winding N22 The second end is coupled to the second end of the first secondary side winding N12 and the power output 埠4.

又，在本實施例中，該第一開關S1為一第一電晶體，並具有一第一寄生電容C_S1及一第一本質二極體(Intrinsic Diode)D_S1，該第一電晶體之一汲極係為該第一開關S1之該第一端，該第一電晶體之一源極係為該第一開關S1之該第二端，該第一電晶體之一閘極係為該第一開關S1之該控制端。 In this embodiment, the first switch S1 is a first transistor, and has a first parasitic capacitance C _S1 and a first intrinsic diode D _S1 , the first transistor One of the first transistors is the first end of the first switch S1, and one of the first transistors is the second end of the first switch S1, and one of the first transistors is the gate The control end of the first switch S1.

同理，該第二開關S2為一第二電晶體，並具有一第二寄生電容C_S2及一第二本質二極體D_S2，該第二電晶體之一汲極係為該第二開關S2之該第一端，該第二電晶體之一源極係為該第二開關S2之該第二端，該第二電晶體之一閘極係為該第二開關S2之該控制端。 Similarly, the second switch S2 is a second transistor, and has a second parasitic capacitance C _S2 and a second intrinsic diode D _S2 , and one of the second transistors is the second switch The first end of the second transistor, the source of one of the second transistors is the second end of the second switch S2, and one of the gates of the second transistor is the control end of the second switch S2.

藉由上述設置，可使該第一返馳電路2與該第二返馳電路3能互用該第一開關S1的第一本質二極體D_S1及該第二開關S2的第二本質二極體D_S2，並使該第一開關S1及該第二開關S2皆可滿足零電壓切換導通(Zero-Voltage Switching-on，ZVS)，以降低切換損失，進而具有提高整體電路效率的效果。 With the above arrangement, the first flyback circuit 2 and the second flyback circuit 3 can mutually use the first essential diode D _S1 of the first switch _S1 and the second essence 2 of the second switch S2. The pole body D _S2 and the first switch S1 and the second switch S2 can satisfy the Zero-Voltage Switching-on (ZVS) to reduce the switching loss, thereby improving the overall circuit efficiency.

該電力輸出埠4具有一第一端41及一第二端42，該電力輸出埠4之該第一端41耦接該第一次級側繞組N12之該第二端及該第二次級側繞組N22之該第二端，該電力輸出埠4之該第二端42耦接該接地端其中，該電力輸出埠4之該第一端41及該第二端42之間耦接一輸出電容C，且該電力輸出埠4之該第一端41及該第二端42之間可另耦接具有一輸出電阻R之一負載。藉此，該輸出電容C可用以儲能，進而具有維持該電力輸出埠4的輸出電壓的效果。 The power output port 4 has a first end 41 and a second end 42. The first end 41 of the power output port 4 is coupled to the second end of the first secondary side winding N12 and the second end. The second end of the side winding N22, the second end 42 of the power output 埠4 is coupled to the ground end An output capacitor C is coupled between the first end 41 and the second end 42 of the power output port 4, and the first end 41 and the second end 42 of the power output port 4 are additionally The coupling is coupled to one of the output resistors R. Thereby, the output capacitor C can be used to store energy, and thus has the effect of maintaining the output voltage of the power output 埠4.

本發明之交錯式返馳轉換器可另設有一控制器5，該控制器5耦接該第一開關S1之該控制端以傳輸一第一控制信號V1，且該控制器5耦接該第二開關S2之該控制端以傳輸一第二控制信號V2。其中，該第一控制信號V1及該第二控制信號V2可均為脈波調變(Pulse Width Modulation，PWM)信號。 The interleaved flyback converter of the present invention may be further provided with a controller 5, the controller 5 is coupled to the control end of the first switch S1 to transmit a first control signal V1, and the controller 5 is coupled to the first The control terminal of the second switch S2 transmits a second control signal V2. The first control signal V1 and the second control signal V2 may both be Pulse Width Modulation (PWM) signals.

請參照第2圖所示，更詳言之，該第一控制信號V1及該第二控制信號V2係分別具有一操作區段A1及一怠遲區段A2，在該操作區段A1中，該第一控制信號V1的準位及該第二控制信號V2的準位係彼此相反(例如該第一控制信號V1的電壓V_GS1在低準位，該第二控制信號V2的電壓V_GS2在高準位)；在該怠遲區段A2中，該第一控制信號V1的準位及該第二控制信號V2的準位均呈低準位，亦即呈現禁能(disable)的狀態。其中，該操作區段A1及該怠遲區段A2可依時間順序而交錯配置。 Referring to FIG. 2, in more detail, the first control signal V1 and the second control signal V2 respectively have an operation section A1 and a delay section A2. In the operation section A1, The level of the first control signal V1 and the level of the second control signal V2 are opposite to each other (for example, the voltage V _{GS1 of} the first control signal V1 is at a low level, and the voltage V _{GS2 of} the second control signal V2 is at In the late stage A2, the level of the first control signal V1 and the level of the second control signal V2 are both at a low level, that is, a state of being disabled. The operation section A1 and the delay section A2 may be alternately arranged in time series.

藉由使該第一控制信號V1的準位及該第二控制信號V2的準位在該操作區段A1中彼此相反，可使該第一返馳電路2與該第二返馳電路3可互用該第一開關S1的第一本質二極體D_S1及該第二開關S2的第二本質二極體D_S2，並使該第一開關S1及該第二開關S2皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果。此外，藉由使該第一控制信號V1的準位及該第二控制信號V2的準位在該怠遲區段A2中均呈低準位，可避免該第一開關S1及該第二開關S2因同時導通而燒毀，具有維持電路正常運作的效果。 The first flyback circuit 2 and the second flyback circuit 3 can be made possible by making the level of the first control signal V1 and the level of the second control signal V2 opposite to each other in the operating section A1. Interacting with the first intrinsic diode D _S1 of the first switch _S1 and the second intrinsic diode D _{S2 of} the second switch S2, and the first switch S1 and the second switch S2 can satisfy zero voltage The switching is turned on to reduce the switching loss, thereby having the effect of improving the overall circuit efficiency. In addition, the first switch S1 and the second switch can be avoided by setting the level of the first control signal V1 and the level of the second control signal V2 to a low level in the late section A2. S2 burns out due to simultaneous conduction, which has the effect of maintaining the normal operation of the circuit.

以下係介紹本發明之交錯式返馳轉換器的八種工作模式：請同時參照本案第3A及4圖所示，在進入工作模式I(t₀~t₁)之前，該第二開關S2為導通狀態，該第二變壓器T2的第二初級側繞組N21的電流i _{T2_P}係流經該第二開關S2，該電流i _{T2_P}呈線性上升並且在該第二開關S2截止前之瞬間到達峰值，且該電流i _{T2_P}在第二變壓器T2產生的磁通包含只通過該第二初級側繞組N21的漏磁通和耦合到該第二次級側繞組N22的互感磁通，當該第二開關S2於時點t0截止時，整體電路進入工作模式I。該電流i _{T2_P}迅速下降，為了保持該第二變壓器T2的互感磁通連續，該第二變壓器T2之該第二次級側繞組N22感應產生一電流i _{T2_S}，該電流i _{T2_S}係流經該第一開關S1的第一寄生電容C_S1和第二二極體D2以對該輸出電容C充電，其中，電流i _S1及電流i _S2分別為流過該第一開關S1及該第二開關S2的電流，電壓v _DS1及電壓v _DS2分別為該第一開關S1及該第二開關S2的端電壓。 The following describes the eight modes of operation of the interleaved flyback converter of the present invention: Please refer to the third and fourth figures of the present case, before entering the working mode I (t ₀ ~ t ₁ ), the second switch S2 is In the on state, the current i _{T2_P} of the second primary winding N21 of the second transformer T2 flows through the second switch S2, and the current i _{T2_P} rises linearly and reaches a peak immediately before the second switch S2 is _turned off, and The magnetic flux generated by the current i _{T2_P} at the second transformer T2 includes a leakage magnetic flux passing only through the second primary side winding N21 and a mutual magnetic flux coupled to the second secondary side winding N22, when the second switch S2 is When the time point t0 is turned off, the overall circuit enters the operating mode I. The current i _{T2_P is} rapidly decreased. In order to keep the mutual magnetic flux of the second transformer T2 continuous, the second secondary winding N22 of the second transformer T2 induces a current i _{T2_S} , and the current i _{T2_S} flows through the first The first parasitic capacitance C _S1 and the second diode D2 of the switch S1 are used to charge the output capacitor C, wherein the current i _S1 and the current i _S2 are respectively flowing through the first switch S1 and the second switch S2 The current, the voltage v _DS1 and the voltage v _DS2 are the terminal voltages of the first switch S1 and the second switch S2, respectively.

另一方面，當該第二開關S2截止時，該電流i _{T2_P}所產生的漏磁通無法感應到該第二變壓器T2的該第二次級側繞組N22，為了保持漏磁通連續，該電流i _{T2_P}在該第二開關S2截止時繼續流通，漏磁通的電感電流路徑可分成兩個迴路，部分漏電感電流流經第一二極體D1及該第一變壓器T1的第一次級側繞組N12以對該輸出電容C充電，再流經該電力輸入埠1(其中，該電力輸入埠1所傳輸的電壓可為一整流後輸入電壓，且該整流後輸入電壓可為一正弦波，為使後續之作動敘述能更為明確，以下提及該電力輸入埠時，將以該整流後輸入電壓替代)；另一部分的漏電感電流流經第二開關S2的第二寄生電容C_S2、第一開關S1的第一寄生電容C_S1與第一變壓器T1之該第一初級側繞組N11，此時該第二寄生電容C_S2充電而該第一寄生電容C_S1放電。另外，對於該第一變壓器T1而言，電流係由該第一初級側繞組N11的第一端流出，並由該第一次級側的第一端流入，此時該第一變壓器T1係正常運作。由於互感及漏電感很小，因此、漏電感電流存在的時間極為短暫，當漏電感電流等於零時，整體電路進入工作模式II。 On the other hand, when the second switch S2 is turned off, the leakage flux generated by the current i _{T2_P} cannot be sensed to the second secondary side winding N22 of the second transformer T2, and the current is kept in order to keep the leakage flux continuous. i _{T2_P} continues to flow when the second switch S2 is turned off, and the inductor current path of the leakage flux can be divided into two loops, and part of the leakage inductor current flows through the first diode D1 and the first secondary side of the first transformer T1 The winding N12 charges the output capacitor C and flows through the power input port 1 (wherein the voltage transmitted by the power input port 1 can be a rectified input voltage, and the rectified input voltage can be a sine wave, In order to make the subsequent operation description more clear, when the power input port is mentioned below, the rectified input voltage will be replaced; and another part of the leakage inductance current flows through the second parasitic capacitance C _{S2 of the} second switch _S2 , The first parasitic capacitance C _{S1 of the} first switch S1 and the first primary side winding N11 of the first transformer T1 are charged, and the second parasitic capacitance C _{S2 is} charged and the first parasitic capacitance C _{S1 is} discharged. In addition, for the first transformer T1, the current flows out from the first end of the first primary side winding N11, and flows in from the first end of the first secondary side, and the first transformer T1 is normal. Operation. Since the mutual inductance and the leakage inductance are small, the leakage inductor current is extremely short. When the leakage inductance current is equal to zero, the overall circuit enters the operating mode II.

請同時參照本案第3B及4圖所示，在工作模式II(t₁~t₂)中，該第二變壓器T2之該第二初級側繞組N21的漏電感電流已經等於零，只剩下該第二變壓器T2之該第二次級側繞組N22的感應電流繼續導通，如工作模式I所述，該電流i _{T2_S}流經該第一開關S1的第一寄生電容C_S1，由於第一寄生電容C_S1很小，當第一寄生電容C_S1電壓迅速下降至-0.7V時，該第一開關S1的第一本質二極體D_S1導通。此時該電流i _{T2_S}有兩個路徑，一開始該i _{T2_S}係全部流經該第一本質二極體D_S1和第二二極體D2對輸出電容C充電，該第二變壓器T2之該第二次級側繞組N22的兩端電壓等於-Vo，其電流從峰值開始線性下降，呈釋能狀態，若忽略工作模式I的短暫時間，該第二變壓器T2之該第二次級側繞組N22的電壓與電流方程式如下所示：v _{T2_S}(t)=-V _o (1) Please refer to FIG. 3B and FIG. 4 of the present case. In the working mode II (t ₁ ~ t ₂ ), the leakage inductance current of the second primary winding N21 of the second transformer T2 is already equal to zero, and only the first The induced current of the second secondary side winding N22 of the second transformer T2 continues to be turned on. As described in the operation mode I, the current i _{T2_S} flows through the first parasitic capacitance C _{S1 of} the first switch S1 due to the first parasitic capacitance C. _{S1 is} small, and when the voltage of the first parasitic capacitance C _S1 rapidly drops to -0.7 V, the first essential diode D _{S1 of} the first switch S1 is turned on. At this time, the current i _{T2_S} has two paths. At the beginning, the i _{T2_S} system all flows through the first intrinsic diode D _S1 and the second diode D2 to charge the output capacitor C, and the second transformer T2 The voltage across the two secondary side windings N22 is equal to -Vo, and its current linearly decreases from the peak value, showing a release state. If the working mode I is ignored for a short time, the second secondary side winding N22 of the second transformer T2 The voltage and current equations are as follows: v _{T2_S} ( t )=- V _o (1)

其中，該n為該第一初級側繞組N11與該第一次級側繞組N12的圈數比(n=N11/N12)；該電流i _{T2_S}為該第二開關S2截止前的瞬間電流；該L_S為該第一變壓器次級側繞組之一耦合電感。 Wherein n is a turns ratio of the first primary side winding N11 and the first secondary side winding N12 (n=N11/N12); the current i _{T2_S} is an instantaneous current before the second switch S2 is _turned off; L _{S is} one of the coupled inductors of the secondary side winding of the first transformer.

同時、因為該第一本質二極體D_S1導通，整流後輸入電壓v_rec(t)跨於第一變壓器T1之該第一初級側繞組N11兩端，由於該第一返馳電路2及該第二返馳電路3皆設計操作於不連續導通模式(Discontinuous Conduction Mode，DCM)，該第一變壓器T1之該第一初級側繞組N11的電流i _{T1_P}從零開始線性上升，並且為該電流i _{T2_S}的另一個電流路徑，此部分之電流i _{T2_S}流經整流後輸入電壓v_rec(t)、該第一變壓器T1之該第一初級側繞組N11與該第二二極體D2對該輸出電容C充電，該第一變壓器T1之耦合電感開始儲能，該第一初級側繞組N11的電壓與電流方程式表示如下：v _{T1_P}(t)=v _rec(t) (3) At the same time, since the first intrinsic diode D _{S1 is} turned on, the rectified input voltage v _rec (t) is across the first primary side winding N11 of the first transformer T1 due to the first flyback circuit 2 and the The second flyback circuit 3 is designed to operate in a discontinuous conduction mode (DCM), and the current i _{T1_P} of the first primary side winding N11 of the first transformer T1 linearly rises from zero, and is the current i Another current path of _{T2_S} , the current i _{T2_S of the portion} flows through the rectified input voltage v _rec (t), the first primary side winding N11 of the first transformer T1 and the second diode D2 to the output capacitor C is charged, the coupled inductor of the first transformer T1 starts to store energy, and the voltage and current equation of the first primary side winding N11 is expressed as follows: v _{T 1_ P} ( t )= v _rec ( t ) (3)

其中，該L_P為該第一變壓器T1初級側繞組之一耦合電感；v_rec(t)為該整流後輸入電壓，且為一正弦波。 Wherein, the L _{P is a} coupled inductor of one of the primary side windings of the first transformer T1; v _rec (t) is the rectified input voltage and is a sine wave.

當該第二開關S2截止時，其兩端電壓V_DS2等於整流後的輸入電壓與該第二變壓器T2之第二初級側繞組N21之差值，且可表示如下：v _DS2(t)=v _rec(t)-v _{T2_P}(t)=v _rec(t)+nV _o (5) When the second switch S2 is turned off, the voltage V _DS2 across it is equal to the difference between the rectified input voltage and the second primary side winding N21 of the second transformer T2, and can be expressed as follows: v _DS2 ( t )= v _Rec ( t )- v _{T 2_ P} ( t )= v _rec ( t )+ nV _o (5)

當該第一開關S1兩端的跨壓被箝位在-0.7V時，會經過極短的怠遲時間，該第一開關S1的閘極電壓V_GS1由低電位變為高電位，部分電流i _{T2_S}持續流過該第一本質二極體D_S1。由方程式(2)與(4)可知，電流i _{T2_S}由峰值下降；電流i _{T1_P}由零線性上升，當該電流i _{T1_P}大於該電流i _{T2_S}時，該第一開關S1導通，電路將會進入工作模式III。因該第一開關S1導通之前，其兩端的跨壓被箝位在-0.7V，因此該第一開關S1滿足零電壓切換導通。 When the voltage across the first switch S1 is clamped at -0.7V, a very short delay time elapses, and the gate voltage V _{GS1 of} the first switch S1 changes from a low potential to a high potential, and a part of the current i _{T2_S} continues to flow through the first essential diode D _S1 . It can be seen from equations (2) and (4) that the current i _{T2_S} is decreased by the peak value; the current i _{T1_P} rises linearly from zero, and when the current i _{T1_P is} greater than the current i _{T2_S} , the first switch S1 is turned on, and the circuit will enter the work. Mode III. Before the first switch S1 is turned on, the voltage across the two ends is clamped at -0.7V, so the first switch S1 satisfies the zero voltage switching conduction.

請同時參照第3C及4圖所示，在工作模式III(t₂~t₃)中，該第一開關S1為導通狀態，且該電流i _{T1_P}大於該電流i _{T2_S}。該電流i _{T1_P}具有兩個電流路徑，部分的電流i _{T1_P}流經該第一開關S1與整流後的輸入電壓v_rec(t)；另一部分的電流i _{T1_P}等於該電流i _{T2_S}並且流經該第二二極體D2且持續對該輸出電容C充電，最後流回整流後的輸入電壓源v_rec(t)。在此模式下該v _{T1_P}、v _{T2_S}、i _{T1_P}與i _{T2_S}的方程式與工作模式II相同，電流i _{T2_S}持續線性下降，而該電流i _{T1_P}持續線性上升。由於該第一返馳電路2及該第二返馳電路3皆操作於不連續導通模式，所以當該電流i _{T2_S}下降至零時，電路進入工作模式IV。 Referring to FIGS. 3C and 4 simultaneously, in the operation mode III (t ₂ to t ₃ ), the first switch S1 is in an on state, and the current i _{T1_P is} greater than the current i _{T2_S} . The current i _{T1_P} has two current paths, a part of the current i _{T1_P} flows through the first switch S1 and the rectified input voltage v _rec (t); another part of the current i _{T1_P} is equal to the current i _{T2_S} and flows through the first The diode D2 continues to charge the output capacitor C and finally flows back to the rectified input voltage source v _rec (t). In this mode, the _{equations of} v _{T1_P} , v _{T2_S} , i _{T1_P} and i _{T2_S} are the same as the operating mode II, the current i _{T2_S} continues to decrease linearly, and the current i _{T1_P} continues to rise linearly. Since the first flyback circuit 2 and the second flyback circuit 3 both operate in the discontinuous conduction mode, when the current i _{T2_S} falls to zero, the circuit enters the operational mode IV.

請同時參照第3D及4圖所示，在工作模式IV(t₃~t₄)時，該電流i _{T2_S}等於零，該第一開關S1保持導通，該電流i _{T1_P}持續線性上升。當該第一開關S1截止之瞬間，電路進入工作模式V。 Referring to FIGS. 3D and 4 simultaneously, in the operation mode IV (t ₃ ~ t ₄ ), the current i _{T2_S is} equal to zero, the first switch S1 remains turned on, and the current i _{T1_P} continues to rise linearly. When the first switch S1 is turned off, the circuit enters the operating mode V.

請同時參照第3E及4圖所示，工作模式V(t₄~t₅)開始於該第一開關S1於時點t4截止時，該電流i _{T1_P}迅速下降，為了保持該第一變壓器T1的互感磁通連續，該第一變壓器T1之該第一次級側繞組N12感應出電流i _{T1_S}，電流i _{T1_S}流經該第二開關S2的第二寄生電容C_S2和第一二極體D1而對該輸出電容C充電。 Referring to FIG. 3E and FIG. 4 simultaneously, the operation mode V(t ₄ ~t ₅ ) starts when the first switch S1 is turned off at the time point t4, and the current i _{T1_P drops} rapidly, in order to maintain the mutual inductance of the first transformer T1. The magnetic flux is continuous, the first secondary side winding N12 of the first transformer T1 induces a current i _{T1_S} , and the current i _{T1_S} flows through the second parasitic capacitance C _{S2 of} the second switch _S2 and the first diode D1. The output capacitor C is charged.

另一方面，當第一開關S1截止時，該電流i _{T1_P}所產生的漏磁通無法感應到該第一變壓器T1的該第一次級側繞組N12，為了保持漏磁通連續，該電流i _{T1_P}在該第一開關S1截止時繼續流通，漏磁通的電感電流路徑可分成兩個迴路，部分漏電感電流流經第二二極體D2、該第二變壓器T2之第二次級側繞組N22對該輸出電容C充電，再流經整流後輸入電壓v_rec(t)；另一部分的漏電感電流流經該第一開關S1的第一寄生電容C_S1、該第二開關S2的第二寄生電容C_S2與第二變壓器T2之該第二初級側繞組N21，此時該第一寄生電容C_S1充電而該第二寄生電容C_S2放電。對於第二變壓器T2而言，該第二初級側繞組N21的第一端流出電流，該第二次級側繞組N22的第一端流入電流，此時該第二變壓器T2係正常運作。因為漏電感很小，漏電感電流存在的時間極為短暫，當漏電感電流等於零時，電路進入工作模式VI。 On the other hand, when the first switch S1 is turned off, the leakage magnetic flux generated by the current i _{T1_P} cannot be sensed to the first secondary side winding N12 of the first transformer T1, and the current i is maintained in order to keep the leakage flux continuous. _{T1_P} continues to flow when the first switch S1 is turned off, and the inductor current path of the leakage flux can be divided into two loops, and part of the leakage inductor current flows through the second diode D2 and the second secondary winding of the second transformer T2. N22 charges the output capacitor C, and then flows through the rectified input voltage v _rec (t); another portion of the leakage inductor current flows through the first parasitic capacitor C _S1 of the first switch _S1 and the second switch S2 The parasitic capacitance C _{S2 is} opposite to the second primary side winding N21 of the second transformer T2, and the first parasitic capacitance C _{S1 is} charged and the second parasitic capacitance C _{S2 is} discharged. For the second transformer T2, the first end of the second primary side winding N21 flows current, and the first end of the second secondary side winding N22 flows current, and the second transformer T2 operates normally. Because the leakage inductance is small, the leakage inductor current is extremely short-lived. When the leakage inductance current is equal to zero, the circuit enters the operating mode VI.

請同時參照第3F及4圖所示，在工作模式VI(t₅~t₆)中，該第一變壓器T1之該第一初級側繞組N11的漏電感電流已經等於零，只剩下該第一變壓器T1該第一次級側繞組N12的感應電流繼續導通，如工作模式V所述，電流i _{T1_S}流經第二開關S2的第二寄生電容C_S2，因為該第二寄生電容C_S2很小，當該第二寄生電容C_S2電壓迅速下降至-0.7V時，該第二開關S2的該第二本質二極體D_S2導通。此時電流i _{T1_S}有兩個路徑，一開始全部電流i _{T1_S}流經該第二本質二極體D_S2和第一二極體D1而對該輸出電容C充電，該第一變壓器T1之該第一次級側繞組N12兩端電壓等於-Vo，其電流從峰值開始線性下降，呈釋能狀態，若忽略模式V的短暫時間，該第一變壓器T1之第一次級側繞組N12的電壓與電流方程式如下所示：v _{T1_S}(t)=-V _o (6) Referring to FIG. 3F and FIG. 4 simultaneously, in the operation mode VI (t ₅ ~ t ₆ ), the leakage inductance current of the first primary side winding N11 of the first transformer T1 is already equal to zero, leaving only the first The induced current of the first secondary side winding N12 of the transformer T1 continues to be turned on. As described in the operation mode V, the current i _{T1_S} flows through the second parasitic capacitance C _{S2 of the} second switch S2 because the second parasitic capacitance C _{S2 is} small. When the voltage of the second parasitic capacitor C _S2 rapidly drops to -0.7 V, the second intrinsic diode D _{S2 of} the second switch S2 is turned on. At this time, the current i _{T1_S} has two paths, and at the beginning, all the currents i _{T1_S} flow through the second intrinsic diode D _S2 and the first diode D1 to charge the output capacitor C, and the first transformer T1 The voltage across a secondary side winding N12 is equal to -Vo, and its current linearly decreases from the peak value, showing a release state. If the mode V is ignored for a short time, the voltage of the first secondary side winding N12 of the first transformer T1 is The current equation is as follows: v _{T 1_ S} ( t )=- V _o (6)

其中，該i _{T1_P} (t _{4_} )為該第一開關S1截止前，該第一變壓器T1之該第一初級側繞組N11的電流。 Wherein, before S1 is turned off, the current of the first switch of the first primary side winding N11 of the first transformer T1 _i T1_P (t _{4_)} for.

同時、因為該第二本質二極體D_S2導通，整流後輸入電壓v_rec(t)跨於該第二變壓器T2之該第二初級側繞組N21兩端，該第二變壓器T2之該第二初級側繞組N21的電流i _{T2_P}從零開始線性上升，並且為該電流i _{T1_S}的另一個電流路徑，此部分之該電流i _{T1_S}流經輸入電壓v_rec(t)、該第二變壓器T2之該第二初級側繞組N21與該第一二極體D1而對該輸出電容C充電，該第二變壓器T2之耦合電感開始儲能，該第二初級側繞組N21的電壓與電流方程式表示如下：v _{T2_P}(t)=v _rec(t) (8) At the same time, because the second intrinsic diode D _{S2 is} turned on, the rectified input voltage v _rec (t) spans across the second primary side winding N21 of the second transformer T2, and the second of the second transformer T2 the primary side winding N21 of the current _i T2_P scratch linear increase, and another current path _{T1_S} current i of the current flowing through this portion of the input voltage i _{T1_S} v _rec (t), of the second transformer T2 for the The second primary winding N21 and the first diode D1 charge the output capacitor C. The coupled inductor of the second transformer T2 starts to store energy. The voltage and current equation of the second primary winding N21 is expressed as follows: v _{T 2_ P} ( t )= v _rec ( t ) (8)

其中，該L_P為該第二變壓器T2之該第二初級側繞組N21的電感值。 Wherein, the L _{P is} an inductance value of the second primary side winding N21 of the second transformer T2.

當該第一開關S1截止時，其兩端電壓V_DS1等於整流後的輸入電壓與垓第一變壓器T1之該第一初級側繞組N11之差值，且可表示如下：v _DS1(t)=v _rec(t)-v _{T1_P}(t)=v _rec(t)+nV _o (10) When the first switch S1 is turned off, the voltage V _DS1 across it is equal to the difference between the rectified input voltage and the first primary side winding N11 of the first transformer T1, and can be expressed as follows: v _DS1 ( t )= v _rec ( t )- v _{T 1_ P} ( t )= v _rec ( t )+ nV _o (10)

在工作模式VI下，該第二開關S2兩端的跨壓被箝位在-0.7V，經過極短的怠遲區段之時間後，該第二開關S2的閘極電壓V_GS2由低電位變為高電位，部分電流i _{T1_S}持續流過該第二本質二極體D_S2。根據方程式(7)及(9)，該電流i_{T1_S}由峰值下降；電流i _{T2_P}由零線性上升，當該電流i _{T2_P}大於該電流i _{T1_S}時，該第二開關S2導通，電路進入工作模式VII。且該第二開關S2導通之前，其兩端的跨壓被箝位在-0.7V，因此該第二開關S2滿足零電壓切換導通。 In the working mode VI, the voltage across the second switch S2 is clamped at -0.7V, and after a very short period of time, the gate voltage V _{GS2 of} the second switch S2 is changed from a low potential. To be high, part of the current i _{T1_S} continues to flow through the second intrinsic diode D _S2 . According to equations (7) and (9), the current i _{T1_S} is decreased by the peak value; the current i _{T2_P} is linearly increased by zero, and when the current i _{T2_P is} greater than the current i _{T1_S} , the second switch S2 is turned on, and the circuit enters the operating mode VII. . Before the second switch S2 is turned on, the voltage across the two ends is clamped at -0.7V, so the second switch S2 satisfies the zero voltage switching conduction.

請同時參照第3G及4圖所示，在工作模式VII(t₆~t₇)中，該第二開關S2為導通狀態，且該電流i _{T2_P}大於該電流i _{T1_S}。該電流i _{T2_P}具有兩個電流路徑，部分的電流i _{T2_P}流經該第二開關S2與整流後輸入電壓v_rec(t)；另一部分的電流i _{T2_P}等於該電流i _{T1_S}並且流經該第一二極體D1而持續對該輸出電容C充電，最後流回整流後輸入電壓v_rec(t)。在此模式下，v _{T2_P}、v _{T1_S}、i _{T2_P}與i _{T1_S}的方程式與工作模式VI相同，電流i _{T1_S}持續線性下降，而電流i _{T2_P}持續線性上升。當該電流i _{T1_S}下降至零時，電路進入工作模式VIII。 Referring to FIGS. 3G and 4 simultaneously, in the operation mode VII (t ₆ to t ₇ ), the second switch S2 is in an on state, and the current i _{T2_P is} greater than the current i _{T1_S} . The current i _{T2_P} has two current paths, a part of the current i _{T2_P} flows through the second switch S2 and the rectified input voltage v _rec (t); another part of the current i _{T2_P} is equal to the current i _{T1_S} and flows through the first The diode D1 continues to charge the output capacitor C, and finally flows back to the rectified input voltage v _rec (t). In this mode, the equations for v _{T2_P} , v _{T1_S} , i _{T2_P} and i _{T1_S} are the same as the operating mode VI, the current i _{T1_S} continues to decrease linearly, and the current i _{T2_P} continues to rise linearly. When the current i _{T1_S} drops to zero, the circuit enters operating mode VIII.

請同時參照第3H及4圖所示，在工作模式VIII(t₇~t₈)下，電流i _{T1_S}等於零，該第二開關S2保持導通，電流i _{T2_P}持續線性上升。在該第二開關S2截止之瞬間，該電流i _{T2_P}上升到達峰值，電路進入下一個高頻週期的工作模式I。 Referring to Figures 3H and 4 simultaneously, in operation mode VIII (t ₇ ~ t ₈ ), the current i _{T1_S is} equal to zero, the second switch S2 remains on, and the current i _{T2_P} continues to rise linearly. At the instant when the second switch S2 is _turned off, the current i _{T2_P} rises to a peak value, and the circuit enters the operating mode I of the next high frequency period.

綜上所述，本發明之交錯式返馳轉換器，可使該第一返馳電路2與該第二返馳電路3能互用該第一開關S1的第一本質二極體D_S1及該第二開關S2的第二本質二極體D_S2，並使該第一開關S1及該第二開關S2皆可滿足零電壓切換導通，以降低切換損失，進而具有提高整體電路效率的效果效果。 In summary, the interleaved flyback converter of the present invention can enable the first flyback circuit 2 and the second flyback circuit 3 to mutually interact with the first essential diode D _{S1 of} the first switch _S1 and The second inverting body D _{S2 of} the second switch S2 can make the first switch S1 and the second switch S2 meet the zero voltage switching conduction to reduce the switching loss, thereby improving the overall circuit efficiency. .

雖然本發明已利用上述較佳實施例揭示，然其並非用以限定本發明，任何熟習此技藝者在不脫離本發明之精神和範圍之內，相對上述實施例進行各種更動與修改仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described in connection with the preferred embodiments described above, it is not intended to limit the scope of the invention. The technical scope of the invention is protected, and therefore the scope of the invention is defined by the scope of the appended claims.

1‧‧‧電力輸入埠 1‧‧‧Power input埠

11‧‧‧第一端 11‧‧‧ first end

12‧‧‧第二端 12‧‧‧ second end

2‧‧‧第一返馳電路 2‧‧‧First flyback circuit

3‧‧‧第二返馳電路 3‧‧‧second flyback circuit

4‧‧‧電力輸出埠 4‧‧‧Power output埠

41‧‧‧第一端 41‧‧‧ first end

42‧‧‧第二端 42‧‧‧second end

5‧‧‧控制器 5‧‧‧ Controller

C‧‧‧輸出電容 C‧‧‧ output capacitor

C_S1‧‧‧第一寄生電容 C _S1 ‧‧‧First parasitic capacitance

C_S2‧‧‧第二寄生電容 C _S2 ‧‧‧Second parasitic capacitance

D1‧‧‧第一二極體 D1‧‧‧First Diode

D2‧‧‧第二二極體 D2‧‧‧ second diode

D_S1‧‧‧第一本質二極體 D _S1 ‧‧‧First Essential Dipole

D_S2‧‧‧第二本質二極體 D _S2 ‧‧‧Second essential diode

N11‧‧‧第一初級側繞組 N11‧‧‧First primary side winding

N12‧‧‧第一次級側繞組 N12‧‧‧First secondary winding

N21‧‧‧第二初級側繞組 N21‧‧‧second primary side winding

N22‧‧‧第二次級側繞組 N22‧‧‧second secondary winding

R‧‧‧輸出電阻 R‧‧‧ output resistance

S1‧‧‧第一開關 S1‧‧‧ first switch

S2‧‧‧第一開關 S2‧‧‧ first switch

T1‧‧‧第一變壓器 T1‧‧‧ first transformer

T2‧‧‧第二變壓器 T2‧‧‧second transformer

V1‧‧‧第一控制信號 V1‧‧‧ first control signal

V2‧‧‧第二控制信號 V2‧‧‧second control signal

Claims

一種交錯式返馳轉換器，包含：一電力輸入埠，該電力輸入埠具有一第一端及一第二端，該電力輸入埠的第二端耦接一接地端；一第一返馳電路，該第一返馳電路具有一第一變壓器、一第一開關及一第一二極體，該第一變壓器具有一第一初級側繞組及一第一次級側繞組，該第一初級側繞組耦接該電力輸入埠之該第一端，該第一開關耦接於該第一初級側繞組及該接地端之間，該第一二極體之一陰極端耦接該第一次級側繞組；一第二返馳電路，該第二返馳電路具有一第二變壓器、一第二開關及一第二二極體，該第二變壓器具有一第二初級側繞組及一第二次級側繞組，該第二初級側繞組耦接該電力輸入埠之該第一端及該第一二極體之一陽極端，該第二次級側繞組耦接該第一次級側繞組，該第二開關耦接該第二初級側繞組及該接地端之間，該第二二極體之一陽極端耦接於該第一初級側繞組及該第一開關之間的接點，該第二二極體之一陰極端耦接該第二次級側繞組；及一電力輸出埠，該電力輸出埠具有一第一端及一第二端，該電力輸出埠之該第一端耦接該第一次級側繞組及該第二次級側繞組，該電力輸出埠之該第二端耦接該接地端，且該電力輸出埠之該第一端及該第二端之間耦接一輸出電容。 An interleaved flyback converter includes: a power input port having a first end and a second end, the second end of the power input port being coupled to a ground end; a first flyback circuit The first flyback circuit has a first transformer, a first switch and a first diode, the first transformer having a first primary side winding and a first secondary side winding, the first primary side a winding is coupled to the first end of the power input port, the first switch is coupled between the first primary side winding and the ground end, and a cathode end of the first diode is coupled to the first secondary a second winding circuit, the second flyback circuit has a second transformer, a second switch and a second diode, the second transformer has a second primary winding and a second a second side winding coupled to the first end of the power input port and an anode end of the first diode, the second secondary side winding being coupled to the first secondary side winding, a second switch is coupled between the second primary side winding and the ground end, and the second diode The anode end is coupled to the junction between the first primary side winding and the first switch, the cathode end of the second diode is coupled to the second secondary side winding; and a power output port, the power The output port has a first end and a second end, the first end of the power output port is coupled to the first secondary side winding and the second secondary side winding, and the second end coupling of the power output port Connected to the ground, and an output capacitor is coupled between the first end and the second end of the power output port.

如申請專利範圍第1項所述之交錯式返馳轉換器，其中該第一開關具有一第一端、一第二端及一控制端，該第一開關之該第一端耦接該第一初級側繞組，該第一開關之該第二端耦接該接地端。 The interleaved flyback converter of claim 1, wherein the first switch has a first end, a second end, and a control end, and the first end of the first switch is coupled to the first end a primary side winding, the second end of the first switch is coupled to the ground.

如申請專利範圍第2項所述之交錯式返馳轉換器，其中該第一開關為一第一電晶體，並具有一第一寄生電容及一第一本質二極體，該第一電晶體之一汲極係為該第一開關之該第一端，該第一電晶體之一源極係為該第一開關之該第二端，該第一電晶體之一閘極係為該第一開關之該控制端。 The interleaved flyback converter of claim 2, wherein the first switch is a first transistor and has a first parasitic capacitance and a first intrinsic diode, the first dimorph One of the first drains is the first end of the first switch, and one of the first transistors is the second end of the first switch, and one of the first transistors is the gate The control end of the first switch.

如申請專利範圍第2項所述之交錯式返馳轉換器，其中該第二開關具有一第一端、一第二端及一控制端，該第二開關之該第一端耦接該第二初級側繞組及該第一二極體之該陽極端，該第二開關之該第二端耦接該第一開關之該第二端及該接地端。 The interleaved flyback converter of claim 2, wherein the second switch has a first end, a second end, and a control end, and the first end of the second switch is coupled to the first end The second side of the second switch and the second end of the second switch are coupled to the second end of the first switch and the ground.

如申請專利範圍第4項所述之交錯式返馳轉換器，其中該第二開關為一第二電晶體，並具有一第二寄生電容及一第二本質二極體，該第二電晶體之一汲極係為該第二開關之該第一端，該第二電晶體之一源極係為該第二開關之該第二端，該第二電晶體之一閘極係為該第二開關之該控制端。 The interleaved flyback converter of claim 4, wherein the second switch is a second transistor and has a second parasitic capacitance and a second intrinsic diode, the second transistor One of the gates is the first end of the second switch, and one of the second transistors is the second end of the second switch, and one of the gates of the second transistor is the first The control end of the second switch.

如申請專利範圍第4項所述之交錯式返馳轉換器，其中該第一初級側繞組具有一第一端及一第二端，該第一初級側繞組之該第一端耦接該電力輸入埠之該第一端，該第一初級側繞組之該第二端耦接該第一開關之該第一端及該第二二極體之該陽極端；該第一次級側繞組具有一第一端及一第二端，該第一次級側繞組之該第一端耦接該第一二極體之該陰極端，該第一次級側繞組之該第二端耦接該電力輸出埠之該第一端。 The interleaved flyback converter of claim 4, wherein the first primary side winding has a first end and a second end, the first end of the first primary side winding being coupled to the power The first end of the first primary side winding is coupled to the first end of the first switch and the anode end of the second diode; the first secondary side winding has a first end and a second end, the first end of the first secondary winding is coupled to the cathode end of the first diode, and the second end of the first secondary winding is coupled to the first end The first end of the power output port.

如申請專利範圍第6項所述之交錯式返馳轉換器，其中該第二初級側繞組具有一第一端及一第二端，該第二初級側繞組之該第一端耦接該電力輸入埠之該第一端及該第一初級側繞組之該第一端，該第二初級側繞組之該第二端耦接該第二開關之該第一端及該第一二極體之該陽極端；該第二次級側繞組具有一第一端及一第二端，該第二次級側繞組之該第一端耦接該第二二極體之該陰極端，該第二次級側繞組之該第二端耦接該第一次級側繞組之該第二端及該電力輸出埠之該第一端。 The interleaved flyback converter of claim 6, wherein the second primary side winding has a first end and a second end, the first end of the second primary side winding being coupled to the power Inputting the first end of the first end and the first end of the first primary side winding, the second end of the second primary side winding is coupled to the first end of the second switch and the first diode The second secondary winding has a first end and a second end, the first end of the second secondary winding is coupled to the cathode end of the second diode, the second The second end of the secondary side winding is coupled to the second end of the first secondary side winding and the first end of the power output port.

如申請專利範圍第4項所述之交錯式返馳轉換器，其中另具有一控制器，該控制器耦接該第一開關之該控制端以傳輸一第一控制信號，該控制器耦接該第二開關之該控制端以傳輸一第二控制信號。 The interleaved flyback converter of claim 4, wherein the controller further has a controller coupled to the control end of the first switch to transmit a first control signal, the controller is coupled The control terminal of the second switch transmits a second control signal.

如申請專利範圍第8項所述之交錯式返馳轉換器，其中該第一控制信號及該第二控制信號係分別具有一操作區段及一怠遲區段，在該操作區段中，該第一控制信號的準位及該第二控制信號的準位係彼此相反；在該怠遲區段中，該第一控制信號的準位及該第二控制信號的準位均呈低準位。 The interleaved flyback converter of claim 8, wherein the first control signal and the second control signal respectively have an operation section and a delay section, in the operation section, The level of the first control signal and the level of the second control signal are opposite to each other; in the delay section, the level of the first control signal and the level of the second control signal are both low Bit.