TWI581553B

TWI581553B - Interleaved high step-up? dc-dc converter

Info

Publication number: TWI581553B
Application number: TW105106121A
Authority: TW
Inventors: 陳信助; 楊松霈; 黃昭明; 林川凱
Original assignee: 崑山科技大學
Priority date: 2016-03-01
Filing date: 2016-03-01
Publication date: 2017-05-01
Also published as: TW201733256A

Description

交錯式高升壓DC-DC轉換器 Interleaved high-boost DC-DC converter

本發明係有關於一種交錯式高升壓DC-DC轉換器，尤其是指一種能增加了電壓增益的設計自由度，令高電壓增益的達成不必操作在極大的導通比，且可降低導通損失，並能令反向恢復問題與功率損失得以改善，同時能避免造成電壓突波問題，及降低系統整體成本，而在其整體施行使用上更增實用功效特性之交錯式高升壓DC-DC轉換器創新設計者。 The present invention relates to an interleaved high-boost DC-DC converter, and more particularly to a design freedom that increases the voltage gain, so that the achievement of the high voltage gain does not have to be operated at a large conduction ratio, and the conduction loss can be reduced. And can improve the reverse recovery problem and power loss, while avoiding the voltage surge problem, and reducing the overall cost of the system, and the intertwined high-boost DC-DC with more practical functions in its overall implementation. Innovative designer of the converter.

按，再生能源的利用是各國產業發展的重點方向，包含太陽能、風力能、水力能、地熱能、潮汐能、生質能及燃料電池等。例如在歐洲、日本與美國裝設於屋頂的住宅型太陽能併網電力系統，最近成為成長快速的市場。在再生能源電力系統應用中，太陽能發電系統及燃料電池發電系統的技術發展越來越成熟，常常在分散式發電系統〔distributed generation system〕扮演重要的角色。而由於住宅型應用〔reside ntial applications〕的安全性與可靠性的問題，太陽能電池模組與燃料電池所產生的輸出電壓是屬於低電壓，一般不超過40V，為了達到併網發電系統或直流微電網的需求，必須先將此低電壓利用高升壓DC-DC轉換器，升壓至一個高直流排電壓。例如：對於一個單相220V_ac的電網系統而言，此高直流排電壓常為380~400V_dc，以利全橋換流器〔inverter〕的DC-AC轉換。理論上，操作在極高導通比的傳統升壓型〔boost〕轉換器能夠得到高電壓增益，但是實務上受到寄生元件的影響，電壓轉換比受限在約5倍以下，因此當電壓增益超過5倍的需求時，研發嶄新的高升壓轉換器拓樸是必要的。因此最近幾年高升壓DC-DC轉換器是電力電子工程領域中常見的研究主題之一。 According to the use of renewable energy, it is the key direction of industrial development in various countries, including solar energy, wind energy, hydropower, geothermal energy, tidal energy, biomass energy and fuel cells. For example, residential solar-powered grid-connected power systems installed in Europe, Japan, and the United States have recently become fast-growing markets. In the application of renewable energy power systems, the technological development of solar power generation systems and fuel cell power generation systems is becoming more and more mature, often playing an important role in distributed generation systems. Due to the safety and reliability of residential ntial applications, the output voltage generated by solar modules and fuel cells is low voltage, generally not exceeding 40V, in order to achieve grid-connected power generation systems or DC micro- For grid demand, this low voltage must first be boosted to a high DC rail voltage using a high-boost DC-DC converter. For example, for a single-phase 220V _ac grid system, this high DC voltage is often 380~400V _dc to facilitate DC-AC conversion of the full bridge inverter. In theory, a conventional boost converter operating at very high turn-on ratio can achieve high voltage gain, but in practice it is affected by parasitic components, and the voltage conversion ratio is limited to less than about 5 times, so when the voltage gain exceeds When developing 5 times of demand, it is necessary to develop a new high-boost converter topology. Therefore, in recent years, high-boost DC-DC converters have been one of the common research topics in the field of power electronics engineering.

其中，就一般常見之轉換器而言，請參閱公告於103年11月1日之第I459705號「單級式高升壓比直流-直流轉換器」，其係包括有一一次側電路、一二次側電路及一輸出負載端，其中該二次側電路係電性連接前述一次側電路，而該輸出負載端係電性連接前述一次側電路及二次側電路，且一次側電路包含有一一次側電感，而二次側電路包含有一二次側電感，該一次側電感與該二次側電感互為耦合電感，其主要目的在於可適當調整該一次側電感與該二次側電感之匝數比，藉以得到較高之電壓增益比。然而，上述結構並非為交錯式設計，且僅為單級式設計，造成其轉換效率不佳，容易產生很大的輸入電流漣波。 Among them, for the common converters, please refer to No. I459705 “Single-stage high-boost DC-DC converter” announced on November 1, 103, which includes a primary circuit, one or two. a secondary side circuit and an output load end, wherein the secondary side circuit is electrically connected to the primary side circuit, and the output load end is electrically connected to the primary side circuit and the secondary side circuit, and the primary side circuit includes one time The side inductance includes a secondary side inductance, and the primary side inductance and the secondary side inductance are mutually coupled inductors, and the main purpose thereof is to appropriately adjust the primary side inductance and the secondary side inductance. The ratio is used to obtain a higher voltage to gain ratio. However, the above structure is not an interlaced design, and is only a single-stage design, resulting in poor conversion efficiency and easy generation of large input current chopping.

另，請再參閱公告於104年9月21日之第I501527號「單輔助開關之交錯式高升壓比柔切式轉換器」，包含一第一升壓電路、一第二升壓電路、一第一阻絕二極體、一第二阻絕二極體、一共振電感、一輔助開關、一共振電容、一輔助開關二極體及一輔助二極體，其中第一升壓電路包含一第一主開關，第二升壓電路包含一第二主開關且與第一升壓電路電性連接，第一阻絕二極體與第一主開關電性連接，第二阻絕二極體與第二主開關電性連接，輔助開關透過共振電感而與第一阻絕二極體及第二阻絕二極體電性連接，輔助開關二極體、共振電容及輔助二極體分別與輔助開關電性連接以達成柔切。然而，上述轉換器於整體結構設計上較為繁雜，開關設計較多，造成不僅製作成本無法有效降低，且連帶亦會導致其故障損壞機率增加，致令其在整體結構設計上仍存在有改進之空間。 In addition, please refer to No. I501527, "Single Auxiliary Switch Interleaved High Boost Ratio Flexible Switching Converter", which is announced on September 21, 104, and includes a first boosting circuit and a second boosting circuit. a first blocking diode, a second blocking diode, a resonant inductor, an auxiliary switch, a resonant capacitor, an auxiliary switching diode and an auxiliary diode, wherein the first boosting circuit comprises a first a main switch, the second boosting circuit includes a second main switch and is electrically connected to the first boosting circuit, the first blocking diode is electrically connected to the first main switch, and the second blocking diode is connected to the second The main switch is electrically connected, and the auxiliary switch is electrically connected to the first blocking diode and the second blocking diode through the resonant inductor, and the auxiliary switching diode, the resonant capacitor and the auxiliary diode are respectively electrically connected to the auxiliary switch To achieve a soft cut. However, the above-mentioned converter is complicated in the overall structural design, and the switch design is more, which not only can not effectively reduce the manufacturing cost, and the associated damage will also lead to an increase in the probability of failure damage, resulting in an improvement in the overall structural design. space.

又，請再參閱第二十二圖現有之轉換器電路圖所示，其係為登錄於電機電子工程師學會第14057343號之學術文獻W. Li, W. Li, X. Xiang, Y. Hu, and X. He, “High step-up interleaved converter with built-in transformer voltage multiplier cells for sustainable energy applications,” IEEE Trans. Power Electronics, Vol. 29, No. 6, pp. 2829-2836, 2014.中所揭露的轉換器電路，該轉換器(2)之功率二極體的電壓應力為，電壓應力值較高，且元件總數較高，並於耦合電感的設計上較為繁雜困難，造成其同樣在整體結構設計上存在有改進之空間。 In addition, please refer to the circuit diagram of the converter shown in the twenty-second figure, which is the academic literature of W. Li, W. Li, X. Xiang, Y. Hu, and X. He, "High step-up interleaved converter with built-in transformer voltage multiplier cells for built energy applications," IEEE Trans. Power Electronics , Vol. 29, No. 6, pp. 2829-2836, 2014. Converter circuit, the voltage stress of the power diode of the converter (2) is The voltage stress value is higher, and the total number of components is higher, and the design of the coupled inductor is more complicated, which results in the same improvement in the overall structural design.

緣是，發明人有鑑於此，秉持多年該相關行業之豐富設計開發及實際製作經驗，針對現有之結構及缺失再予以研究改良，提供一種交錯式高升壓DC-DC轉換器，以期達到更佳實用價值性之目的者。 In view of this, the inventors have provided a kind of interleaved high-boost DC-DC converter to achieve more and more, based on years of rich experience in design, development and actual production of related industries, and research and improvement on existing structures and defects. The purpose of good practical value.

本發明之主要目的在於提供一種交錯式高升壓DC-DC轉換器，其主要係能增加了電壓增益的設計自由度，令高電壓增益的達成不必操作在極大的導通比，且可降低導通損失，並能令反向恢復問題與功率損失得以改善，同時能避免造成電壓突波問題，及降低系統整體成本，而在其整體施行使用上更增實用功效特性者。 The main object of the present invention is to provide an interleaved high-boost DC-DC converter, which is mainly capable of increasing the design freedom of voltage gain, so that the achievement of high voltage gain does not have to be operated at an extremely large conduction ratio, and the conduction can be reduced. Loss, and can improve the reverse recovery problem and power loss, while avoiding voltage surge problems, and reducing the overall cost of the system, and more practical features in its overall implementation.

本發明交錯式高升壓DC-DC轉換器之主要目的與功效，係由以下具體技術手段所達成：其主要係令轉換器由並聯輸入串聯輸出升壓型轉換器、電壓倍增模組及輸出負載R_O所相連接組成；其中：該並聯輸入串聯輸出升壓型轉換器，其係於電源端V_in之正極並聯有第一耦合電感之初級側N_P1的第一端及第二耦合電感之初級側N_P2的第一端，而該電源端V_in之負極則並聯有第一功率開關S₁的第二端、第二功率開關S₂的第二端及第一輸出二極體D₁的第一端，該第二耦合電感之初級側N_P2的第二端與該第二功率開關S₂的第一端相連接、同時連接有第二輸出二極體D₂的第二端，該第一耦合電感之初級側N_P1的第二端與該第一功率開關S₁的第一端相連接、同時連接有第一輸出電容C₁的第一端及第二輸出電容C₂第二端，該第一輸出電容C₁的第二端與該第一輸出二極體D₁的第二端連接後同時連接至該輸出負載R_O的第二端，該第二輸出二極體D₂的第一端則與該第二輸出電容C₂第一端相連接後同時連接至該電壓倍增模組；該電壓倍增模組，其係令第一倍壓二極體D₃之第二端與第三輸出電容C₃之第二端相連接、同時亦與該並聯輸入串聯輸出升壓型轉換器之該第二輸出二極體D₂的第一端及該第二輸出電容C₂第一端相連接，該第一倍壓二極體D₃之第一端與該第二耦合電感之次級側N_S2的第一端及第二倍壓二極體D₄之第二端相連接，該第三輸出電容C₃之第一端與該第一耦合電感之次級側N_S1的第一端及第四輸出電容C₄之第二端相連接，該第一耦合電感之次級側N_S1的第二端則與該第二耦合電感之次級側N_S2的第二端相連接，而該第二倍壓二極體D₄之第一端與該第四輸出電容C₄之第一端相連接後同時連接至該輸出負載R_O的第一端。 The main purpose and effect of the interleaved high-boost DC-DC converter of the present invention are achieved by the following specific technical means: the main reason is that the converter is connected by a parallel input series output boost converter, a voltage multiplying module and an output. The load R _O is connected to each other; wherein: the parallel input series output boost converter is connected to the first end of the primary side of the first coupled inductor N _P1 and the second coupled inductor connected to the positive terminal of the power terminal V _in a first end of the primary side N _P2 , and a negative end of the power supply terminal V _in parallel with a second end of the first power switch S _{1 ,} a second end of the second power switch S ₂ , and a first output diode D _a first end of the primary side inductor of the N _P2 of the second coupling a first end connected to the second end of the second power switch S _2, while a second output terminal connected to a second diode D ₂ is The second end of the primary side N _P1 of the first coupled inductor is connected to the first end of the first power switch S ₁ , and the first end of the first output capacitor C ₁ and the second output capacitor C ₂ are connected at the same time. a second end, the first output terminal of the second capacitor C ₁ to the first output of the second diode D _1, After simultaneously connected to a second end connected to the output load R _O, and the second output terminal of the first diode D ₂ is connected to the second output terminal of the first capacitor C ₂ is connected to the voltage multiplication mode simultaneously The voltage multiplying module is configured to connect the second end of the first voltage doubled diode D _{3 to} the second end of the third output capacitor C ₃ , and simultaneously output the boost converter with the parallel input The first end of the second output diode D _{2 and} the first end of the second output capacitor C _{2 are} connected, the first end of the first voltage doubled diode D ₃ and the second coupled inductor The first end of the secondary side N _S2 and the second end of the second voltage doubled diode D _{4 are} connected, and the first end of the third output capacitor C ₃ and the secondary side of the first coupled inductor N _S1 The first end is connected to the second end of the fourth output capacitor C _{4 , and} the second end of the secondary side N _S1 of the first coupled inductor is opposite to the second end of the second side of the second coupled inductor N _S2 The first end of the second voltage doubled diode D ₄ is connected to the first end of the fourth output capacitor C ₄ and is simultaneously connected to the first end of the output load R _O .

(1)‧‧‧轉換器 (1)‧‧‧ converter

(11)‧‧‧並聯輸入串聯輸出升壓型轉換器 (11)‧‧‧Parallel input series output boost converter

(12)‧‧‧電壓倍增模組 (12)‧‧‧Voltage multiplying module

第一圖：本發明之電路圖 First picture: circuit diagram of the invention

第二圖：本發明之主要元件時序波形圖 Second picture: timing waveform diagram of the main components of the present invention

第三圖：本發明之第一操作階段等效電路示意圖 Third figure: schematic diagram of the equivalent circuit of the first operation stage of the present invention

第四圖：本發明之第二操作階段等效電路示意圖 Fourth figure: schematic diagram of the equivalent circuit of the second operation stage of the present invention

第五圖：本發明之第三操作階段等效電路示意圖 Figure 5: Schematic diagram of the equivalent circuit of the third operation stage of the present invention

第六圖：本發明之第四操作階段等效電路示意圖 Figure 6: Schematic diagram of the equivalent circuit of the fourth operation stage of the present invention

第七圖：本發明之第五操作階段等效電路示意圖 Figure 7: Schematic diagram of the equivalent circuit of the fifth operation stage of the present invention

第八圖：本發明之第六操作階段等效電路示意圖 Figure 8: Schematic diagram of the equivalent circuit of the sixth operation stage of the present invention

第九圖：本發明之第七操作階段等效電路示意圖 Ninth diagram: schematic diagram of the equivalent circuit of the seventh operation stage of the present invention

第十圖：本發明之第八操作階段等效電路示意圖 Figure 11: Schematic diagram of the equivalent circuit of the eighth operation stage of the present invention

第十一圖：本發明之不同耦合係數和電壓增益的關係曲線圖 Figure 11: Relationship between different coupling coefficients and voltage gain of the present invention

第十二圖：本發明之電壓增益與導通比及耦合電感匝數比的曲線圖 Twelfth figure: graph of voltage gain and conduction ratio and coupling inductance turns ratio of the present invention

第十三圖：本發明之模擬電路示意圖 Thirteenth Diagram: Schematic diagram of the analog circuit of the present invention

第十四圖：本發明之開關驅動信號、輸入電壓與輸出電壓波形圖 Figure 14: Waveform diagram of the switch drive signal, input voltage and output voltage of the present invention

第十五圖：本發明之開關應力驗證波形圖 Figure 15: Switching stress verification waveform diagram of the present invention

第十六圖：本發明降低漣波電流之驗證波形圖 Figure 16: The verification waveform of the invention for reducing chopping current

第十七圖：本發明之連續電流模式〔CCM〕驗證波形圖 Figure 17: Continuous current mode (CCM) verification waveform diagram of the present invention

第十八圖：本發明之各輸出二極體的電流及電壓波形圖 Figure 18: Current and voltage waveforms of the output diodes of the present invention

第十九圖：本發明之各倍壓二極體的電流及電壓波形圖 Figure 19: Current and voltage waveforms of the voltage doubled diodes of the present invention

第二十圖：本發明之各輸出電容電壓波形圖 Figure 20: Voltage waveform diagram of each output capacitor of the present invention

第二十一圖：本發明之各功率開關零電流切換性能波形圖 Twenty-first graph: waveform diagram of zero current switching performance of each power switch of the present invention

第二十二圖：現有之轉換器電路圖 Figure 22: Existing converter circuit diagram

為令本發明所運用之技術內容、發明目的及其達成之功效有更完整且清楚的揭露，茲於下詳細說明之，並請一併參閱所揭之圖式及圖號：首先，請參閱第一圖本發明之電路圖所示，本發明之轉換器(1)主要係由並聯輸入串聯輸出升壓型轉換器(11)、電壓倍增模組(12)及輸出負載R_O所相連接組成；其中：該並聯輸入串聯輸出升壓型轉換器(11)，其係於電源端V_in之正極並聯有第一耦合電感之初級側N_P1的第一端及第二耦合電感之初級側N_P2的第一端，而該電源端V_in之負極則並聯有第一功率開關S₁的第二端、第二功率開關S₂的第二端及第一輸出二極體D₁的第一端，該第二耦合電感之初級側N_P2的第二端與該第二功率開關S₂的第一端相連接、同時連接有第二輸出二極體D₂的第二端，該第一耦合電感之初級側N_P1的第二端與該第一功率開關S₁的第一端相連接、同時連接有第一輸出電容C₁的第一端及第二輸出電容C₂第二端，該第一輸出電容C₁的第二端與該第一輸出二極體D₁的第二端連接後同時連接至該輸出負載R_O的第二端，該第二輸出二極體D₂的第一端則與該第二輸出電容C₂第一端相連接後同時連接至該電壓倍增模組(12)。 For a more complete and clear disclosure of the technical content, the purpose of the invention and the effects thereof achieved by the present invention, the following is a detailed description, and please refer to the drawings and drawings: First, please refer to The first diagram shows the circuit diagram of the present invention. The converter (1) of the present invention is mainly composed of a parallel input series output boost converter (11), a voltage multiplication module (12) and an output load R _O. Wherein: the parallel input series output boost converter (11) is connected to the first end of the primary side N _P1 of the first coupled inductor and the primary side of the second coupled inductor N _in parallel with the positive terminal of the power supply terminal V _in a first end of _P2 , and a negative end of the power terminal V _in parallel with a second end of the first power switch S _{1 ,} a second end of the second power switch S ₂ , and a first end of the first output diode D ₁ The second end of the primary side N _P2 of the second coupled inductor is connected to the first end of the second power switch S _{2 and} the second end of the second output diode D ₂ is connected at the same time. a second end connected to _a first end of the first power switch S N _P1 of the primary side of the coupled inductor, is connected simultaneously A first output terminal of the first capacitor C ₁ and a second output terminal of the second capacitor C _2, the first output terminal of the second capacitor C ₁ and the output of the first diode D ₁ is connected to the second end of the connector while To the second end of the output load R _O , the first end of the second output diode D ₂ is connected to the first end of the second output capacitor C ₂ and is simultaneously connected to the voltage multiplying module (12) .

該電壓倍增模組(12)，其係令第一倍壓二極體D₃之第二端與第三輸出電容C₃之第二端相連接、同時亦與該並聯輸入串聯輸出升壓型轉換器(11)之該第二輸出二極體D₂的第一端及該第二輸出電容C₂第一端相連接，該第一倍壓二極體D₃之第一端與該第二耦合電感之次級側N_S2的第一端及第二倍壓二極體D₄之第二端相連接，該第三輸出電容C₃之第一端與該第一耦合電感之次級側N_S1的第一端及第四輸出電容C₄之第二端相連接，該第一耦合電感之次級側N_S1的第二端則與該第二耦合電感之次級側N_S2的第二端相連接，而該第二倍壓二極體D₄之第一端與該第四輸出電容C₄之第一端相連接後同時連接至該輸出負載R_O的第一端。 The voltage multiplier module (12), so that a first fold line voltage of diode D ₃ is connected to the third output terminal of the second capacitor C ₃ of the second end, but also the parallel input series output boost a first end of the second output diode D ₂ of the converter (11) and a first end of the second output capacitor C _{2 are} connected, and the first end of the first voltage doubled diode D _{3 and} the first end The first end of the secondary side N _S2 of the two coupled inductors is connected to the second end of the second voltage doubled diode D _{4 , and} the first end of the third output capacitor C _{3 and} the second end of the first coupled inductor The first end of the side N _{S1 and} the second end of the fourth output capacitor C _{4 are} connected, and the second end of the secondary side N _S1 of the first coupled inductor is opposite to the secondary side of the second coupled inductor N _S2 The second end is connected, and the first end of the second voltage doubled diode D ₄ is connected to the first end of the fourth output capacitor C ₄ and is simultaneously connected to the first end of the output load R _O .

如此一來，使得本發明於操作使用上，該轉換器(1)由於設有該並聯輸入串聯輸出升壓型轉換器(11)，且利用該電壓倍增模組(12)疊接在輸出端，以提升電壓增益；而該電壓倍增模組(12)係令第一耦合電感之次級側N_S1與該第二耦合電感之次級側N_S2串聯連接及該第三輸出電容C₃與該第四輸出電容C₄組成，該第一功率開關S₁及該第二功率開關S₂係採用相差半切換週期的交錯式操作，使得第一耦合電感之初級側N_P1與該第二耦合電感之初級側N_P2的電流漣波能部份相消，降低輸入電流i_in漣波大小。 In this way, the converter (1) is provided with the parallel input series output boost converter (11), and is connected to the output terminal by using the voltage multiplying module (12). To increase the voltage gain; and the voltage multiplying module (12) is such that the secondary side N _S1 of the first coupled inductor is connected in series with the secondary side N _{S2 of} the second coupled inductor and the third output capacitor C ₃ is The fourth output capacitor C _{4 is configured} , and the first power switch S ₁ and the second power switch S ₂ are interleaved by a phase difference half switching period, so that the primary side N _P1 of the first coupled inductor and the second coupling The current ripple energy of the primary side of the inductor N _P2 is partially canceled, reducing the input current i _{in the} ripple size.

而該轉換器(1)操作在連續導通模式〔CCM〕，為了達到高升壓性能，導通比大於0．5，而且該第一功率開關S₁及該第二功率開關S₂以工作相位相差半切換週期的交錯式操作。穩態分析時，根據該第一功率開關S₁、該第二功率開關S₂及該第一輸出二極體D₁、該第二輸出二極體D₂、該第一倍壓二極體D₃、該第二倍壓二極體D₄的ON/OFF狀態，該轉換器(1)在一個切換週期內可分成8個線性操作階段，假設： And the converter (1) [operating] CCM in continuous conduction mode, in order to achieve high performance booster, the conduction ratio is greater than 0.5, and the switch S ₁ is the first power and said second power switch S ₂ to the working phase by Interleaved operation of half-switching cycles. In the steady state analysis, according to the first power switch S ₁ , the second power switch S ₂ and the first output diode D ₁ , the second output diode D ₂ , the first voltage doubled diode D ₃ , the ON/OFF state of the second voltage doubled diode D ₄ , the converter (1) can be divided into 8 linear operation stages in one switching cycle, assuming:

1.所有功率半導體元件均為理想，即導通壓降為零。 1. All power semiconductor components are ideal, that is, the turn-on voltage drop is zero.

2.該第一輸出電容C₁、該第二輸出電容C₂、該第三輸出電容C₃、該第四輸出電容C₄夠大，電容電壓V_C1、V_C2、V_C3、V_C4可視為定電壓，輸出電壓V_O可視為常數。 2. The first output capacitor C ₁ , the second output capacitor C ₂ , the third output capacitor C ₃ , and the fourth output capacitor C ₄ are large enough, and the capacitor voltages V _C1 , V _C2 , V _C3 , and V _{C4 are} visible For a constant voltage, the output voltage V _O can be regarded as a constant.

3.該第一耦合電感與該第二耦合電感之匝數比相等〔n=N_S1/N_P1=N_S2/N_P2〕，且磁化電感值相等〔L_m1=L_m2=L_m〕，漏電感值相等〔L_k1=L_k2=L_k〕，磁化電感遠大於漏電感，耦合電感的耦合係數k=L_m/(L_m+L_k)。 3. The turns ratio of the first coupled inductor to the second coupled inductor is equal [n=N _S1 /N _P1 =N _S2 /N _P2 ], and the magnetization inductance values are equal [L _m1 =L _m2 =L _m ], The leakage inductance values are equal [L _k1 = L _k2 = L _k ], the magnetizing inductance is much larger than the leakage inductance, and the coupling coefficient of the coupled inductor is k = L _m / (L _m + L _k ).

4.該第一耦合電感與該第二耦合電感的磁化電感電流操作在連續導通模式〔Continuous Conduction Mode，CCM〕。 4. The magnetizing inductor current of the first coupled inductor and the second coupled inductor is operated in a continuous conduction mode (CCM).

分析該轉換器(1)在一個切換週期內之8個線性操作階段如下，請再一併參閱第二圖本發明之主要元件時序波形圖所示：第一階段〔t₀~t₁〕〔第一功率開關S₁：OFF→ON、第二功率開關S₂：ON、第一輸出二極體D₁：OFF、第二輸出二極體D₂：OFF、第一倍壓二極體D₃：OFF、第二倍壓二極體D₄：ON〕：請再一併參閱第三圖本發明之第一操作階段等效電路示意圖所示，第一階段開始於t=t₀，第一功率開關S₁切換成ON，且第二功率開關S₂仍保持ON，由於漏電感L_k1的存在，第一功率開關S₁具有零電流切換〔ZCS〕的柔切性能，降低切換損失。漏電感電流i_Lk1上升，當i_Lk1<i_Lm1時，磁化電感L_m1所儲存的能量仍藉由耦合電感傳送至次級側N_S1，因此第二倍壓二極體D₄仍保持如前一階段的導通狀態。第一輸出二極體D₁、第二輸出二極體D₂、第一倍壓二極體D₃均為逆向偏壓而OFF，僅有第二倍壓二極體D₄導通，電流i_D4下降，而且漏電感L_k1和L_k2控制了第二倍壓二極體D₄電流的下降速率，緩和了第二倍壓二極體D₄反向恢復問題。當t=t₁，電流i_D4下降至0，第二倍壓二極體D₄轉態成OFF時，本階段結束。 The eight linear operation stages of the converter (1) in one switching cycle are as follows. Please refer to the second diagram of the main component timing waveform diagram of the present invention as shown in the following figure: First stage [t ₀ ~ t ₁ ] [ The first power switch S ₁ :OFF→ON, the second power switch S ₂ :ON, the first output diode D ₁ :OFF, the second output diode D ₂ :OFF, the first voltage doubled body D ₃ : OFF, second voltage doubled body D ₄ : ON]: Please refer to the third figure again. The first stage of the invention shows the equivalent circuit diagram, the first stage starts at t=t ₀ , the first A power switch S _{1 is} switched to ON, and the second power switch S ₂ remains ON. Due to the presence of the leakage inductance L _k1 , the first power switch S ₁ has a soft switching performance of zero current switching [ZCS], reducing switching loss. The leakage inductance current i _Lk1 rises. When i _Lk1 <i _Lm1 , the energy stored by the magnetizing inductance L _m1 is still transmitted to the secondary side N _S1 through the coupled inductor, so the second voltage doubled diode D ₄ remains as before. One-stage conduction state. The first output diode D ₁ , the second output diode D ₂ , and the first voltage doubled diode D ₃ are all reverse biased and turned OFF, and only the second voltage doubled diode D _{4 is} turned on, current i _D4 decreased, and the leakage inductance L _k1 and L _k2 controls the rate of descent of the second voltage doubler current diode D _4, easing the second voltage doubler diode D ₄ reverse recovery. When t=t ₁ , the current i _D4 drops to 0, and the second voltage doubled body D ₄ turns OFF, the phase ends.

第二階段〔t₁~t₂〕〔第一功率開關S₁：ON、第二功率開關S₂：ON、第一輸出二極體D₁：OFF、第二輸出二極體D₂：OFF、第一倍壓二極體D₃：OFF、第二倍壓二極體D₄：ON→OFF〕：請再一併參閱第四圖本發明之第二操作階段等效電路示意圖所示，第二階段開始於t=t₁，第二倍壓二極體D₄轉態成OFF，且第一輸出二極體D₁、第二輸出二極體D₂、第一倍壓二極體D₃均為逆向偏壓而OFF，第一功率開關S₁和第二功率開關S₂皆為ON，輸入電壓V_in跨於第一耦合電感之初級側N_P1及第二耦合電感之初級側N_P2，即跨於磁化電感L_m1和L_m2以及漏電感L_k1和L_k2，電流i_Lk1和i_Lk2呈線性上升，斜率均為V_in/(L_m+L_k)，從能量觀點而言，第一耦合電感之初級側N_P1及第二耦合電感之初級側N_P2在本階段作儲存能量的動作。當t=t₂，第二功率開關S₂切換為OFF時，本階段結束。 Second stage [t ₁ ~ t ₂ ] [first power switch S ₁ : ON, second power switch S ₂ : ON, first output diode D ₁ : OFF, second output diode D ₂ : OFF , the first voltage doubled diode D ₃ :OFF, the second voltage doubled body D ₄ :ON→OFF]: Please refer to the fourth figure again, the second circuit of the present invention is shown in the equivalent circuit diagram. The second phase starts at t=t ₁ , the second voltage doubled diode D ₄ turns OFF, and the first output diode D ₁ , the second output diode D ₂ , and the first voltage doubled diode D ₃ is reverse biased and turned OFF, the first power switch S ₁ and the second power switch S ₂ are both ON, and the input voltage V _in spans the primary side of the first coupled inductor N _P1 and the primary side of the second coupled inductor N _P2 , that is, across the magnetizing inductances L _m1 and L _m2 and the leakage inductances L _k1 and L _k2 , the currents i _Lk1 and i _Lk2 rise linearly with a slope of V _in /(L _m +L _k ), from the energy point of view. In other words, the primary side N _P1 of the first coupled inductor and the primary side N _{P2 of the} second coupled inductor perform an action of storing energy at this stage. When t=t ₂ and the second power switch S _{2 is} switched OFF, this phase ends.

第三階段〔t₂~t₃〕〔第一功率開關S₁：ON、第二功率開關S₂：ON→OFF、第一輸出二極體D₁：OFF、第二輸出二極體D₂：ON、第一倍壓二極體D₃：ON、第二倍壓二極體D₄：OFF〕：請再一併參閱第五圖本發明之第三操作階段等效電路示意圖所示，第三階段開始於t=t₂，第二功率開關S₂切換為OFF，漏電感電流i_Lk2的連續性使得第二輸出二極體D₂轉態為ON，漏電感電流i_Lk2流經第二輸出二極體D₂、第二輸出電容C₂和第一功率開關S₁，對第二輸出電容C₂充電。第二耦合電感之磁化電感L_m2以返馳式模式傳送能量至第二耦合電感之次級側N_S2使得第一倍壓二極體D₃轉態為ON，第一倍壓二極體電流i_D3對第三輸出電容C₃充電，第一功率開關S₁保持為ON，此時漏電感電流i_Lk2呈線性下降。當t=t₃，漏電感L_k2儲存的能量完全釋放完畢，即i_Lk2=0，第二輸出二極體D₂轉態成OFF時，本階段結束。由於流經第二輸出二極體D₂的電流先降至0，第二輸出二極體D₂才轉態成OFF，因此第二輸出二極體D₂沒有反向恢復損失的問題。 The third stage [t ₂ ~ t ₃ ] [the first power switch S ₁ :ON, the second power switch S ₂ :ON→OFF, the first output diode D ₁ :OFF, the second output diode D ₂ :ON, first voltage doubled diode D ₃ :ON, second voltage doubled diode D ₄ :OFF]: Please refer to the fifth diagram of the equivalent circuit diagram of the third operation stage of the present invention. The third phase starts at t=t ₂ , the second power switch S _{2 is} switched OFF, the continuity of the leakage inductor current i _Lk2 causes the second output diode D ₂ to be turned ON, and the leakage inductor current i _Lk2 flows through the first The second output capacitor D ₂ , the second output capacitor C ₂ and the first power switch S ₁ charge the second output capacitor C ₂ . The magnetizing inductance L _{m2 of the} second coupled inductor transmits energy in a flyback mode to the secondary side N _{S2 of the} second coupled inductor such that the first voltage doubled diode D _{3 is} turned ON, and the first voltage doubled diode current i _D3 charges the third output capacitor C ₃ , and the first power switch S ₁ remains ON, at which time the leakage inductor current i _Lk2 decreases linearly. When t=t ₃ , the energy stored in the leakage inductance L _k2 is completely released, that is, i _Lk2 =0, and the second output diode D _{2 is} turned OFF, the phase ends. Since the current flowing through the second output diode D ₂ first drops to zero, the second output diode D ₂ is turned OFF, so the second output diode D ₂ has no problem of reverse recovery loss.

第四階段〔t₃~t₄〕〔第一功率開關S₁：ON、第二功率開關S₂：OFF、第一輸出二極體D₁：OFF、第二輸出二極體D₂：ON→OFF、第一倍壓二極體D₃：ON、第二倍壓二極體D₄：OFF〕：請再一併參閱第六圖本發明之第四操作階段等效電路示意圖所示，第四階段開始於t=t₃，此時漏電感L_k2的能量完全釋放到第二輸出電容C₂，第二輸出二極體D₂轉態成OFF。磁化電感電流i_Lm2完全由第二耦合電感之初級側N_P2反射到次級側N_S2，因此i_D3=(1/n)i_Lm2=(N_P2/N_S2)i_Lm2，i_D3對第三輸出電容C₃充電，此時第一功率開關S₁的電流等於磁化電感L_m1和L_m2的電流總和，即i_S1=i_Lk1=i_Lm1+i_NP1=i_Lm1+i_Lm2。當t=t₄，第二功率開關S₂切換為ON時，本階段結束。 The fourth stage [t ₃ ~ t ₄ ] [the first power switch S ₁ :ON, the second power switch S ₂ :OFF, the first output diode D ₁ :OFF, the second output diode D ₂ :ON →OFF, first voltage doubled diode D ₃ :ON, second voltage doubled diode D ₄ :OFF]: Please refer to the sixth circuit diagram of the fourth circuit of the present invention as shown in the equivalent circuit diagram. The fourth phase begins at t=t ₃ , at which time the energy of the leakage inductance L _k2 is completely released to the second output capacitor C ₂ , and the second output diode D _{2 is} turned OFF. The magnetizing inductor current i _{Lm2 is} completely reflected by the primary side N _{P2 of the} second coupled inductor to the secondary side N _S2 , so i _D3 =(1/n)i _Lm2 =(N _P2 /N _S2 )i _Lm2 , i _D3 The three output capacitors C _{3 are} charged, at which time the current of the first power switch S ₁ is equal to the sum of the currents of the magnetizing inductances L _m1 and L _m2 , ie i _S1 =i _Lk1 =i _Lm1 +i _NP1 =i _Lm1 +i _Lm2 . When t=t ₄ and the second power switch S _{2 is} switched ON, this phase ends.

第五階段〔t₄~t₅〕〔第一功率開關S₁：ON、第二功率開關S₂：OFF→ON、第一輸出二極體D₁：OFF、第二輸出二極體D₂：OFF、第一倍壓二極體D₃：ON、第二倍壓二極體D₄：OFF〕：請再一併參閱第七圖本發明之第五操作階段等效電路示意圖所示，第五階段開始於t=t₄，第二功率開關S₂切換成ON，且第一功率開關S₁保持ON，由於漏電感L_k2的存在，第二功率開關S₂具有零電流切換(ZCS)的柔切性能，降低切換損失。漏電感電流i_Lk2上升，當i_Lk2<i_Lm2時，磁化電感L_m2的儲能仍然藉由耦合電感傳送至次級側N_S2，因此第一倍壓二極體D₃仍保持如前一階段的導通狀態。電流i_D3下降，第一輸出二極體D₁、第二輸出二極體D₂、第二倍壓二極體D₄逆向偏壓而OFF。漏電感L_k1和L_k2控制了第一倍壓二極體D₃電流下降速率，因此可緩和第一倍壓二極體D₃反向恢復問題。當t=t₅，電流i_D3下降至0，第一倍壓二極體D₃轉態成OFF時，本階段結束。 The fifth stage [t ₄ ~ t ₅ ] [the first power switch S ₁ :ON, the second power switch S ₂ :OFF→ON, the first output diode D ₁ :OFF, the second output diode D ₂ :OFF, first voltage doubled diode D ₃ :ON, second voltage doubled diode D ₄ :OFF]: Please refer to the seventh diagram of the fifth circuit of the present invention as shown in the equivalent circuit diagram. The fifth phase starts at t=t ₄ , the second power switch S _{2 is} switched to ON, and the first power switch S ₁ remains ON, and the second power switch S ₂ has zero current switching due to the presence of the leakage inductance L _k2 (ZCS) ) The soft cut performance reduces switching losses. I _Lk2 increased current leakage inductance, when i _Lk2 <i _Lm2, the magnetizing inductance L remains _m2 by the storage inductor coupled to the secondary side transfer N _S2, and thus the first voltage doubler diode D ₃ remains as before a The conduction state of the phase. When the current i _D3 falls, the first output diode D ₁ , the second output diode D ₂ , and the second voltage doubled diode D _{4 are} reverse biased and turned OFF. The leakage inductances L _k1 and L _k2 control the rate of current drop of the first voltage doubled diode D ₃ , thereby alleviating the problem of reverse recovery of the first voltage doubled diode D ₃ . When t=t ₅ , the current i _D3 drops to 0, and the first voltage doubled diode D ₃ turns OFF, the phase ends.

第六階段〔t₅~t₆〕〔第一功率開關S₁：ON、第二功率開關S₂：ON、第一輸出二極體D₁：OFF、第二輸出二極體D₂：OFF、第一倍壓二極體D₃：ON→OFF、第二倍壓二極體D₄：OFF〕：請再一併參閱第八圖本發明之第六操作階段等效電路示意圖所示，第六階段開始於t=t₅，第一倍壓二極體D₃轉態成OFF，第一輸出二極體D₁、第二輸出二極體D₂、第二倍壓二極體D₄均為逆向偏壓而OFF，第一功率開關S₁和第二功率開關S₂皆為ON。輸入電壓V_in跨於第一耦合電感之初級側N_P1及第二耦合電感之初級側N_P2，即跨於磁化電感L_m1和L_m2以及漏電感L_k1和L_k2，電流i_Lk1和i_Lk2呈線性上升，斜率均為V_in/(L_m+L_k)，從能量觀點而言，第一耦合電感之初級側N_P1及第二耦合電感之初級側N_P2在本階段作儲存能量。當t=t₆，第一功率開關S₁切換為OFF時，本階段結束。 The sixth stage [t ₅ ~ t ₆ ] [the first power switch S ₁ :ON, the second power switch S ₂ :ON, the first output diode D ₁ :OFF, the second output diode D ₂ :OFF , the first voltage doubled body D ₃ : ON → OFF, the second voltage doubled body D ₄ : OFF]: Please refer to the eighth figure, the sixth circuit of the present invention, the equivalent circuit diagram, The sixth phase starts at t=t ₅ , the first voltage doubled diode D _{3 is} turned OFF, the first output diode D ₁ , the second output diode D ₂ , and the second voltage doubled diode D ₄ is reverse biased and turned OFF, and both the first power switch S ₁ and the second power switch S ₂ are ON. The input voltage V _in spans the primary side N _P1 of the first coupled inductor and the primary side N _{P2 of the} second coupled inductor, that is, across the magnetizing inductances L _m1 and L _m2 and the leakage inductances L _k1 and L _k2 , the currents i _Lk1 and i _Lk2 rises linearly and the slope is V _in /(L _m +L _k ). From the energy point of view, the primary side N _P1 of the first coupled inductor and the primary side N _{P2 of the} second coupled inductor store energy at this stage. . When t=t ₆ and the first power switch S _{1 is} switched OFF, this phase ends.

第七階段〔t₆~t₇〕〔第一功率開關S₁：ON→OFF、第二功率開關S₂：ON、第一輸出二極體D₁：ON、第二輸出二極體D₂：OFF、第一倍壓二極體D₃：OFF、第二倍壓二極體 D₄：ON〕：請再一併參閱第九圖本發明之第七操作階段等效電路示意圖所示，第七階段開始於t=t₆，第一功率開關S₁切換為OFF，漏電感電流i_Lk1的連續性使得第一輸出二極體D₁轉態為ON，漏電感電流i_Lk1流經第一輸出電容C₁和第一輸出二極體D₁，對第一輸出電容C₁充電。第一耦合電感之磁化電感L_m1以返馳式模式傳送至第一耦合電感之次級側N_S1使得第二倍壓二極體D₄轉態為ON，第二倍壓二極體i_D4對第四輸出電容C₄充電，第二功率開關S₂保持為ON，此時漏電感電流i_Lk1呈線性下降。當t=t₇，漏電感L_k1儲存的能量完全釋放完畢，即i_Lk1=0，第一輸出二極體D₁轉態成OFF時，本階段結束。由於流經第一輸出二極體D₁的電流先降至0，第一輸出二極體D₁才轉態成OFF，因此第一輸出二極體D₁沒有反向恢復損失的問題。 The seventh stage [t ₆ ~ t ₇ ] [the first power switch S ₁ : ON → OFF, the second power switch S ₂ : ON, the first output diode D ₁ : ON, the second output diode D ₂ :OFF, first voltage doubled diode D ₃ :OFF, second voltage doubled diode D ₄ :ON]: Please refer to the ninth diagram of the seventh operation stage of the present invention as shown in the equivalent circuit diagram. The seventh phase starts at t=t ₆ , the first power switch S _{1 is} switched to OFF, and the continuity of the leakage inductor current i _Lk1 causes the first output diode D ₁ to be turned ON, and the leakage inductor current i _Lk1 flows through the first an output capacitor C ₁ and outputs a first diode D _{_1, 1} charges the first output capacitor C. The magnetizing inductance L _{m1 of the} first coupled inductor is transmitted to the secondary side N _{S1 of the} first coupled inductor in a flyback mode such that the second voltage doubled diode D _{4 is} turned ON, and the second voltage doubled diode i _D4 The fourth output capacitor C _{4 is} charged, and the second power switch S _{2 is} kept ON, at which time the leakage inductor current i _Lk1 linearly decreases. When t=t ₇ , the energy stored in the leakage inductance L _k1 is completely released, that is, i _Lk1 =0, and the first output diode D _{1 is} turned OFF, the phase ends. Since the current flowing through the first output diode D ₁ first drops to zero, the first output diode D ₁ is turned OFF, so the first output diode D ₁ has no problem of reverse recovery loss.

第八階段〔t₇~t₈〕〔第一功率開關S₁：OFF、第二功率開關S₂：ON、第一輸出二極體D₁：ON→OFF、第二輸出二極體D₂：OFF、第一倍壓二極體D₃：OFF、第二倍壓二極體D₄：ON〕：請再一併參閱第十圖本發明之第八操作階段等效電路示意圖所示，第八階段開始於t=t₇，此時漏電感L_k1的能量完全釋放到第一輸出電容C₁，第一輸出二極體D₁轉態成OFF。磁化電感電流i_Lm1完全由第一耦合電感之初級側N_P1反射到次級側N_S1，i_D4=(1/n)i_Lm1=(N_P1/N_S1)i_Lm1，因此i_D4對第四輸出電容C₄充電，此時第二功率開關S₂的電流等於磁化電感L_m1和L_m2的電流總和，即i_S2=i_Lk2=i_Lm2+i_N _P2=i_Lm1+i_Lm2。當t=t₈=T_S+t₀第一功率開關S₁切換為ON時，本階段結束，進入下一個切換週期。 The eighth stage [t ₇ ~ t ₈ ] [the first power switch S ₁ :OFF, the second power switch S ₂ :ON, the first output diode D ₁ :ON→OFF, the second output diode D ₂ :OFF, first voltage doubled diode D ₃ :OFF, second voltage doubled diode D ₄ :ON]: Please refer to the tenth figure, the eighth circuit diagram of the equivalent circuit diagram of the present invention, The eighth phase starts at t=t ₇ , at which time the energy of the leakage inductance L _k1 is completely released to the first output capacitor C ₁ , and the first output diode D _{1 is} turned OFF. The magnetizing inductor current i _{Lm1 is} completely reflected by the primary side N _{P1 of the} first coupled inductor to the secondary side N _S1 , i _D4 =(1/n)i _Lm1 =(N _P1 /N _S1 )i _Lm1 , so i _D4 pairs four charging the output capacitor C _4, when the current second power switch S ₂ is equal to the sum of the currents magnetizing inductance L _m1 and L _m2, i.e. _{_{_{i S2 = i Lk2 = i Lm2}}} + i N P2 = i Lm1 + i Lm2. When t=t ₈ =T _S +t _{0, the} first power switch S _{1 is} switched ON, the phase ends and the next switching cycle is entered.

由以上該轉換器(1)電路動作分析可知，該轉換器(1)之該第一功率開關S₁和該第二功率開關S₂具有零電流切換性能，可減少切換損失及EMI雜訊；該第一輸出二極體D₁和該第二輸出二極體D₂沒有反向恢復的問題；因漏電感的存在，能夠緩和該第一倍壓二極體D₃及該第二倍壓二極體D₄的反向恢復問題。該第一功率開關S₁和該第二功率開關S₂由ON切換成OFF時，漏電感電流i_Lk1和i_Lk2可分別對該第一輸出電容C₁和該第二輸出電容C₂充電，不但可改善效率，也可避免造成突波電壓。 It can be seen from the above operation analysis of the converter (1) that the first power switch S ₁ and the second power switch S _{2 of} the converter (1) have zero current switching performance, which can reduce switching loss and EMI noise; The first output diode D ₁ and the second output diode D ₂ have no reverse recovery problem; the first voltage doubled diode D ₃ and the second voltage doubled can be alleviated due to the presence of leakage inductance The reverse recovery problem of diode D ₄ . When the first power switch S ₁ and the second power switch S ₂ are switched from ON to OFF, the leakage inductor currents i _Lk1 and i _Lk2 can respectively charge the first output capacitor C ₁ and the second output capacitor C ₂ . Not only can it improve efficiency, but it can also avoid the surge voltage.

以下分析該轉換器(1)的穩態特性，為了簡化分析，假設第一功率開關S₁、第二功率開關S₂、第一輸出二極體D₁、第二輸出二極體D₂、第一倍壓二極體D₃、第二倍壓二極體D₄導通壓降為零，以及忽略時間極短的暫態階段，包括第一、四、五及八階段，只考慮第二、三、六及七階段。該第一輸出電容C₁、該第二輸出電容C₂、該第三輸出電容C₃、該第四輸出電容C₄夠大，忽略電壓漣波，使得電容電壓在一個切換週期內視為常數。 The steady state characteristics of the converter (1) are analyzed below. To simplify the analysis, it is assumed that the first power switch S ₁ , the second power switch S ₂ , the first output diode D ₁ , the second output diode D ₂ , The first voltage doubled diode D ₃ and the second voltage doubled diode D _{4 have} a zero voltage drop and ignore the transient phase with a very short time, including the first, fourth, fifth and eighth stages, only the second , three, six and seven stages. The first output capacitor C ₁ , the second output capacitor C ₂ , the third output capacitor C ₃ , and the fourth output capacitor C ₄ are large enough to ignore the voltage chopping, so that the capacitor voltage is regarded as a constant in one switching period. .

電壓增益分析：由於第一輸出電容C₁和第二輸出電容C₂的電壓可視為傳統升壓型轉換器的輸出電壓，因此根據磁化電感L_m1和L_m2滿足伏秒平衡定理，可推導得到電壓V_C1和V_C2為 Voltage gain analysis: Since the voltages of the first output capacitor C ₁ and the second output capacitor C ₂ can be regarded as the output voltage of the conventional boost converter, the volt-second equilibrium theorem is satisfied according to the magnetizing inductances L _m1 and L _m2 , which can be derived Voltages V _C1 and V _C2 are

第一耦合電感之次級側N_S1與第二耦合電感之次級側N_S2連接的第三輸出電容C₃和第四輸出電容C₄的電壓V_C3和V_C4，可藉由第一耦合電感之初級側N_P1及第二耦合電感之初級側N_P2電壓反射至次級側電壓推導而得到。在第三階段，第一功率開關S₁：ON、第二功率開關S₂：OFF，而且第一倍壓二極體D₃導通，電壓V_C3為 The secondary side inductor of the first coupling N _S1 of the second coupling inductor connected in the secondary side of the third N _S2 output capacitor C ₃ and the fourth output voltage V ₄ of capacitor C _C3 and V _C4, may be coupled by a first The primary side N _{P1 of the} inductor and the primary side N _P2 voltage of the second coupled inductor are reflected to the secondary side voltage derived. In the third stage, the first power switch S ₁ :ON, the second power switch S ₂ :OFF, and the first voltage doubled diode D _{3 is} turned on, and the voltage V _C3 is

在第七階段，第一功率開關S₁：OFF、第二功率開關S₂：ON，而且第二倍壓二極體D₄導通，電壓V_C4為 In the seventh stage, the first power switch S ₁ :OFF, the second power switch S ₂ :ON, and the second voltage doubled diode D _{4 is} turned on, and the voltage V _C4 is

總輸出電壓V_O為 The total output voltage V _O is

因此該轉換器(1)的電壓增益G為 Therefore, the voltage gain G of the converter (1) is

當n=1時，電壓增益G與不同耦合電感的耦合係數k(k=1、0.95、0.9)的關係曲線，請再一併參閱第十一圖本發明之不同耦合係數和電壓增益的關係曲線圖所示，由該第十一圖可知耦合係數k對電壓增益的影響非常小。若耦合係數k=1，則理想的電壓增益為 When n=1, the relationship between the voltage gain G and the coupling coefficient k (k=1, 0.95, 0.9) of different coupled inductors, please refer to the relationship between the different coupling coefficients and voltage gain of the present invention. As shown in the graph, it can be seen from the eleventh figure that the coupling coefficient k has a very small influence on the voltage gain. If the coupling coefficient k=1, the ideal voltage gain is

從上式可知該轉換器(1)的電壓增益具有耦合電感匝數比n和導通比D兩個設計自由度。該轉換器(1)可藉由適當設計耦合電感的匝數比，達到高升壓比，且不必操作在極大的導通比。對應於耦合電感匝數比n及導通比D的電壓增益曲線，請再一併參閱第十二圖本發明之電壓增益與導通比及耦合電感匝數比的曲線圖所示，由該第十二圖可知，當導通比D=0.6、n=1時，電壓增益為10倍；當導通比D=0.6、n=3時，電壓增益為20倍。 It can be seen from the above equation that the voltage gain of the converter (1) has two design degrees of freedom of the coupled inductor turns ratio n and the turn-on ratio D. The converter (1) can achieve a high step-up ratio by appropriately designing the turns ratio of the coupled inductor, and does not have to operate at a very large conduction ratio. Corresponding to the voltage gain curve of the coupled inductor turns ratio n and the turn-on ratio D, please refer to the graph of the voltage gain and the turn-on ratio and the coupled inductor turns ratio of the present invention as shown in the twelfth figure. As can be seen from the second figure, when the conduction ratio D=0.6, n=1, the voltage gain is 10 times; when the conduction ratio is D=0.6, n=3, the voltage gain is 20 times.

由該轉換器(1)之操作階段的第七階段可知第一功率開關S₁的電壓應力 The voltage stress of the first power switch S ₁ can be known from the seventh stage of the operation phase of the converter (1)

由第三階段可知第二功率開關S₂的電壓應力 The voltage stress of the second power switch S ₂ is known from the third stage.

另一方面，由第三和七階段也可知二極體的電壓應力 On the other hand, the voltage stress of the diode is also known from the third and seventh stages.

由於傳統交錯式升壓型轉換器的功率開關電壓應力為輸出電壓V_O，而本發明之該轉換器(1)之第一功率開關S₁的電壓應力與第二功率開關S₂的電壓應力僅為輸出電壓V_O的1/(2n+2)倍，因此可使用低額定耐壓具有較低導通電阻的MOSFET，可降低開關導通損失。另一方面，較低電壓應力的二極體可採用蕭特基二極體，因為蕭特基二極體典型的順向壓降為0.3V，比一般的功率二極體導通壓降低，可降低導通損失。 Since the power switching voltage stress of the conventional interleaved boost converter is the output voltage V _O , the voltage stress of the first power switch S ₁ of the converter (1) of the present invention and the voltage stress of the second power switch S ₂ It is only 1/(2n+2) times the output voltage V _O , so a MOSFET with a low on-resistance and a low on-resistance can be used to reduce the switch conduction loss. On the other hand, the lower voltage stress diode can use the Schottky diode, because the typical forward voltage drop of the Schottky diode is 0.3V, which is lower than the general power diode. Reduce conduction losses.

而根據電路動作分析結果，利用Is-Spice軟體作先期的模擬，該轉換器(1)之規格輸入電壓40V、輸出電壓400V、最大輸出功率1000W、切換頻率40kHz，耦合電感匝數比n=1，驗證本發明該轉換器(1)的特點，請再一併參閱第十三圖本發明之模擬電路示意圖所示；以下以模擬波形驗證與說明轉換器的特點： According to the circuit action analysis result, the Is-Spice software is used for the early simulation. The converter (1) has the input voltage of 40V, the output voltage of 400V, the maximum output power of 1000W, the switching frequency of 40kHz, and the coupled inductor turns ratio n=1. To verify the characteristics of the converter (1) of the present invention, please refer to the schematic diagram of the analog circuit of the present invention as shown in the thirteenth diagram; the following is an analog waveform verification and description of the characteristics of the converter:

A.驗證穩態特性：驗證該轉換器(1)之穩態特性，滿載1000W時，請再一併參閱第十四圖本發明之開關驅動信號、輸入電壓與輸出電壓波形圖所示，當V_in=40V、V_O=400V，n=1，則理論值導通比大約D=0.6，模擬結果符合〔6〕式電壓增益的公式。 A. Verify the steady-state characteristics: verify the steady-state characteristics of the converter (1). When the load is 1000W, please refer to the fourteenth diagram of the switch drive signal, input voltage and output voltage waveform diagram of the present invention. V _in = 40V, V _O = 400V, n = 1, the theoretical value conduction ratio is about D = 0.6, and the simulation result is in accordance with the formula of the voltage gain of [6].

B.驗證開關電壓應力：請再一併參閱第十五圖本發明之開關應力驗證波形圖所示，由該第十五圖可知，當第一功率開關S₁或第二功率開關S₂OFF時，其跨壓V_ds1或V_ds2都約為100V，僅為輸出電壓400V的四分之一，符合〔7〕和〔8〕式的分析結果，比較傳統的升壓型轉換器，開關電壓應力為輸出電壓值，該轉換器(1)的開關具有低電壓應力的優點。 B. Verifying the switch voltage stress: Please refer to the fifteenth diagram of the switch stress verification waveform diagram of the present invention. As shown in the fifteenth figure, when the first power switch S ₁ or the second power switch S ₂ OFF When the voltage across the voltage V _ds1 or V _ds2 is about 100V, it is only a quarter of the output voltage of 400V, which is consistent with the analysis results of [7] and [8], comparing the conventional boost converter, switching voltage The stress is the output voltage value and the switch of the converter (1) has the advantage of low voltage stress.

C.驗證具有低輸入漣波電流性能與CCM操作：請再一併參閱第十六圖本發明降低漣波電流之驗證波形圖所示，於滿載1000W時，耦合電感的漏電感電流i_LK1、i_LK2的漣波電流大小約為25A，而輸入電流i_in的漣波電流大小僅約為2A，使得本發明之交錯式操作具有降低輸入漣波電流之效用；而請再一併參閱第十七圖本發明之連續電流模式〔CCM〕驗證波形圖所示，由該耦合電感之磁化電感電流波形可知，該轉換器(1)操作在連續導通模式〔CCM〕。 C. Verification with low input chopping current performance and CCM operation: Please refer to the sixteenth figure. The verification waveform diagram of the present invention for reducing chopping current shows the leakage inductance current i _{LK1 of the} coupled inductor at 1000W full load. i _{LK2 has} a chopping current of about 25A, and the input current i _{in has} a chopping current of only about 2A, making the interleaved operation of the present invention have the effect of reducing the input chopping current; In the continuous current mode (CCM) verification waveform diagram of the present invention, it is known from the magnetizing inductor current waveform of the coupled inductor that the converter (1) operates in the continuous conduction mode [CCM].

D.驗證二極體反向恢復電流問題：請再一併參閱第十八圖本發明之各輸出二極體的電流及電壓波形圖所示，由該第十八圖可知，該第一輸出二極體電流i_D1和該第二輸出二極體電流i_D2都沒有反向恢復問題，因此沒有反向恢復損失，另一方面可得知，該第一輸出二極體D₁電壓應力為100V，只有輸出電壓的四分之一，該第二輸出二極體D₂電壓應力大約為200V，只有輸出電壓的二分之一，符合〔9〕和〔10〕式的分析結果。請再一併參閱第十九圖本發明之各倍壓二極體的電流及電壓波形圖所示，由該第十九圖可知，該第一倍壓二極體D₃及該第二倍壓二極體D₄的電壓應力均為200V，符合〔11〕式的分析結果，該第一倍壓二極體D₃及該第二倍壓二極體D₄的電流之反向恢復電流極小，因為第一耦合電感和第二耦合電感中的漏電感L_K1和L_K2的存在緩和了反向恢復問題。 D. Verification of the diode reverse recovery current problem: Please refer to FIG. 18 again for the current and voltage waveform diagrams of the output diodes of the present invention. As shown in the eighteenth figure, the first output Both the diode current i _D1 and the second output diode current i _D2 have no reverse recovery problem, so there is no reverse recovery loss. On the other hand, the first output diode D ₁ voltage stress is 100V, only a quarter of the output voltage, the second output diode D ₂ voltage stress is about 200V, only one-half of the output voltage, in line with the analysis results of [9] and [10]. Please refer to FIG. 19 again for the current and voltage waveform diagrams of the voltage doubled diodes of the present invention. As shown in FIG. 19, the first voltage doubled diode D ₃ and the second multiple are shown. The voltage stress of the voltage diode D ₄ is 200V, which is in accordance with the analysis result of the equation [11], and the reverse recovery current of the current of the first voltage doubled diode D ₃ and the second voltage doubled diode D ₄ Very small, because the presence of leakage inductances L _K1 and L _K2 in the first coupled inductor and the second coupled inductor mitigates the reverse recovery problem.

E.驗證輸出電容電壓：請再一併參閱第二十圖本發明之各輸出電容電壓波形圖所示，由第二十圖可知，該第一輸出電容電壓V_C1、該第二輸出電容電壓V_C2、該第三輸出電容電壓V_C3、該第四輸出電容電壓V_C4大約都等於100V，符合〔1〕、〔2〕、〔3〕式的推導結果。 E. Verifying the output capacitor voltage: Please refer to the twenty-fifth diagram of the output capacitor voltage waveform diagram of the present invention. As shown in the twentieth diagram, the first output capacitor voltage V _C1 and the second output capacitor voltage V _C2 , the third output capacitor voltage V _C3 , and the fourth output capacitor voltage V _C4 are both equal to 100V, which is in accordance with the derivation results of the equations [1], [2], and [3].

F.驗證功率開關零電流切換〔ZCS〕性能：請再一併參閱第二十一圖本發明之各功率開關零電流切換性能波形圖所示，由該第一功率開關S₁及該第二功率開關S₂的電流波形i_dS1和i_dS2與跨壓波形v_ds1和v_ds2可知，該第一功率開關S₁及該第二功率開關S₂的跨壓v_dS1和v_dS2先降至0才有開關電流，因此達到零電流切換〔ZCS〕的柔切性能，可降低切換損失。 F. Verify the power switch zero current switching [ZCS] performance: Please refer to the twenty-first figure of the power switch zero current switching performance waveform diagram of the present invention, by the first power switch S ₁ and the second The current waveforms i _dS1 and i _{dS2 of the} power switch S _{2 and} the voltage across the voltage waveforms v _ds1 and v _{ds2 show} that the voltages v _dS1 and v _{dS2 of} the first power switch S ₁ and the second power switch S ₂ first drop to zero. Only the switching current is available, so the soft-cutting performance of the zero current switching [ZCS] is achieved, which reduces the switching loss.

藉由以上所述，本發明之使用實施說明可知，本發明與現有技術手段相較之下，本發明主要係具有下列優點： From the above, the implementation description of the present invention shows that the present invention has the following advantages in comparison with the prior art means:

1.本發明之轉換器係為輸入並聯輸出串聯的交錯式升壓型，於其輸出端疊接電壓倍增模組，增加了電壓增益的設計自由度，所以高電壓增益的達成，不必操作在極大的導通比。 1. The converter of the present invention is an interleaved boost type in which the input parallel output is connected in series, and the voltage multiplying module is overlapped at the output end thereof, thereby increasing the design freedom of the voltage gain, so that the high voltage gain is achieved without operating Great turn-on ratio.

2.本發明之第一功率開關和第二功率開關的電壓應力遠低於輸出電壓，使得能使用R_DS(_ON)較小的低額定耐壓MOSFET，所以可降低導通損失。 2. The voltage stress of the first power switch and the second power switch of the present invention is much lower than the output voltage, so that a low rated voltage MOSFET having a small R _DS ( _ON) can be used, so that the conduction loss can be reduced.

3.本發明之第一輸出二極體和第二輸出二極體在轉態成OFF之前，其流經的電流先降為零，所以第一輸出二極體和第二輸出二極體的反向恢復問題與功率損失得以改善。 3. Before the first output diode and the second output diode of the present invention are turned OFF, the current flowing through the first output diode is first reduced to zero, so the first output diode and the second output diode are Reverse recovery problems and power loss are improved.

4.本發明之第一耦合電感和第二耦合電感初級側的漏電感能量能夠傳送至輸出側，不但能改善效率，也能避免造成電壓突波問題。 4. The leakage inductance energy of the first coupled inductor and the second coupled inductor primary side of the present invention can be transmitted to the output side, which not only improves efficiency, but also avoids voltage surge problems.

5.本發明由於係以交錯式操作，第一耦合電感和第二耦合電感初級側繞組的電流漣波能部份相消，降低輸入電流漣波大小，可減少太陽能電池模組輸出端的電解電容數量與延長燃料電池的使用壽命，可降低系統整體成本。 5. The present invention is interleaved, the current coupling chopping energy of the first coupled inductor and the second coupled inductor primary side winding is partially canceled, reducing the input current chopping size, and reducing the electrolytic capacitor at the output end of the solar cell module. The quantity and extended fuel cell life can reduce the overall cost of the system.

然而前述之實施例或圖式並非限定本發明之產品結構或使用方式，任何所屬技術領域中具有通常知識者之適當變化或修飾，皆應視為不脫離本發明之專利範疇。 However, the above-described embodiments or drawings are not intended to limit the structure or the use of the present invention, and any suitable variations or modifications of the invention will be apparent to those skilled in the art.

綜上所述，本發明實施例確能達到所預期之使用功效，又其所揭露之具體構造，不僅未曾見諸於同類產品中，亦未曾公開於申請前，誠已完全符合專利法之規定與要求，爰依法提出發明專利之申請，懇請惠予審查，並賜准專利，則實感德便。 In summary, the embodiments of the present invention can achieve the expected use efficiency, and the specific structure disclosed therein has not been seen in similar products, nor has it been disclosed before the application, and has completely complied with the provisions of the Patent Law. And the request, the application for the invention of a patent in accordance with the law, please forgive the review, and grant the patent, it is really sensible.

(1)‧‧‧轉換器 (1)‧‧‧ converter

(12)‧‧‧電壓倍增模組 (12)‧‧‧Voltage multiplying module

Claims

一種交錯式高升壓DC-DC轉換器，其主要係令該轉換器由並聯輸入串聯輸出升壓型轉換器、電壓倍增模組及輸出負載R_O所相連接組成；其中：該並聯輸入串聯輸出升壓型轉換器，其係於電源端V_in之正極並聯有第一耦合電感之初級側N_P1的第一端及第二耦合電感之初級側N_P2的第一端，而該電源端V_in之負極則並聯有第一功率開關S₁的第二端、第二功率開關S₂的第二端及第一輸出二極體D₁的第一端，該第二耦合電感之初級側N_P2的第二端與該第二功率開關S₂的第一端相連接、同時連接有第二輸出二極體D₂的第二端，該第一耦合電感之初級側N_P1的第二端與該第一功率開關S₁的第一端相連接、同時連接有第一輸出電容C₁的第一端及第二輸出電容C₂第二端，該第一輸出電容C₁的第二端與該第一輸出二極體D₁的第二端連接後同時連接至該輸出負載R_O的第二端，該第二輸出二極體D₂的第一端則與該第二輸出電容C₂第一端相連接後同時連接至該電壓倍增模組；該電壓倍增模組，其係令第一倍壓二極體D₃之第二端與第三輸出電容C₃之第二端相連接、同時亦與該並聯輸入串聯輸出升壓型轉換器之該第二輸出二極體D₂的第一端及該第二輸出電容C₂第一端相連接，該第一倍壓二極體D₃之第一端與該第二耦合電感之次級側N_S2的第一端及第二倍壓二極體D₄之第二端相連接，該第三輸出電容C₃之第一端與該第一耦合電感之次級側N_S1的第一端及第四輸出電容C₄之第二端相連接，該第一耦合電感之次級側N_S1的第二端則與該第二耦合電感之次級側N_S2的第二端相連接，而該第二倍壓二極體D₄之第一端與該第四輸出電容C₄之第一端相連接後同時連接至該輸出負載R_O的第一端。 An interleaved high-boost DC-DC converter mainly comprises a parallel input series output boost converter, a voltage multiplying module and an output load R _O ; wherein: the parallel input is connected in series The output boost converter is connected to the first end of the primary side N _P1 of the first coupled inductor and the first end of the primary side N _P2 of the second coupled inductor _in parallel with the positive terminal of the power terminal V _in , and the power terminal V _in the negative electrode is in parallel to a second terminal of the first switch S ₁ is the power, the second power terminal of the second switch S ₂ and a first diode output terminals D ₁ of the first primary side of the second coupling inductor The second end of the N _P2 is connected to the first end of the second power switch S ₂ , and the second end of the second output diode D ₂ is connected at the same time, and the second side of the first coupled inductor is N _P1 end of the first end connected to the first switch S ₁ is the power, while the output is connected to a first terminal of the first capacitor C ₁ and a second output terminal of the second capacitor C _2, the first output capacitor C _1, a second a first output terminal and the second terminal of diode D ₁ while the connection connected to the second terminal of the output load R _O in the second A first end of the output diode D ₂ is connected to the second output terminal of the first capacitor C ₂ is connected simultaneously to the voltage multiplier module; the voltage multiplier module, so that a first line doubler diode _{D. 3} of a second end connected to the output of the third capacitor C ₃ of the second end, but also the parallel input series output and the second output diode D of the boost converter and the first end ₂ of The first end of the second output capacitor C _{2 is} connected, the first end of the first voltage doubled diode D _{3 and} the first end of the second coupled inductor N _S2 and the second voltage doubled diode D the second end ₄ connected to a first output terminal and the fourth capacitor C ₄ connected to the second end of the third capacitor C ₃ of the first output terminal and the secondary side of the first coupling inductor N _S1, which The second end of the secondary side N _S1 of the first coupled inductor is connected to the second end of the secondary side N _S2 of the second coupled inductor, and the first end of the second voltage doubled diode D ₄ is The first end of the fourth output capacitor C ₄ is connected and simultaneously connected to the first end of the output load R _O .