TWI581459B

TWI581459B - Light-emitting device and manufacturing method thereof

Info

Publication number: TWI581459B
Application number: TW102122910A
Authority: TW
Inventors: 黃建富; 呂志強; 林俊宇; 邱新智
Original assignee: 晶元光電股份有限公司
Priority date: 2013-06-26
Filing date: 2013-06-26
Publication date: 2017-05-01
Also published as: TW201501350A

Description

發光元件及其製造方法 Light-emitting element and method of manufacturing same

本發明係關於一種發光元件及其製造方法；特別是關於一種具複數個半導體疊層塊之發光元件及其製造方法。 The present invention relates to a light-emitting element and a method of fabricating the same, and more particularly to a light-emitting element having a plurality of semiconductor stacked blocks and a method of fabricating the same.

發光二極體(Light-Emitting Diode，LED)具有耗能低、低發熱、操作壽命長、防震、體積小、以及反應速度快等良好特性，因此適用於各種照明及顯示用途。隨著其應用技術的發展，多元(multi-cell)發光二極體之元件，即由多個發光二極體組成之元件，例如陣列式發光二極體之元件，在市場上的應用漸為廣泛。例如，光學顯示裝置、交通號誌、以及照明裝置等，其中高壓發光二極體(High Voltage LED，HV LED)之照明元件即為一例。 Light-Emitting Diode (LED) has good characteristics such as low energy consumption, low heat generation, long operating life, shock resistance, small size, and fast response. It is suitable for various lighting and display applications. With the development of its application technology, components of multi-cell light-emitting diodes, that is, components composed of a plurality of light-emitting diodes, such as components of array type light-emitting diodes, are gradually being applied in the market. widely. For example, an optical display device, a traffic sign, a lighting device, and the like, wherein an illumination element of a high voltage LED (HV LED) is an example.

習知的陣列式發光二極體元件1，如第7A圖與第7B圖所示，包含一基板10、複數個發光二極體單元12以二維方式排列於基板10上，每一個發光二極體單元12包含一發光疊層，包含一p型半導體層121、一發光層122、以及一n型半導體層123。這些發光二極體單元 12係對基板10上之發光疊層施以蝕刻製程，形成溝渠14而分割出此複數個發光二極體單元12。由於基板10不導電，因此於複數個發光二極體單元12間形成之溝渠14可使各發光二極體單元12彼此絕緣，另外再藉由部分蝕刻發光二極體單元12至n型半導體層123，分別於n型半導體層123的暴露區域以及p型半導體層121上形成一第一電極18以及一第二電極16。再藉由導電配線結構19選擇性連接複數個發光二極體單元12之第一電極18及第二電極16，使得複數個發光二極體單元12之間形成串聯或並聯之電路。例如，若形成串聯之電路，即為直流之高壓發光二極體(High Voltage LED，HV LED)。 The conventional array type LED device 1 includes a substrate 10 and a plurality of LED units 12 arranged on the substrate 10 in two dimensions, each of which is shown in FIGS. 7A and 7B. The polar body unit 12 includes a light emitting laminate including a p-type semiconductor layer 121, a light emitting layer 122, and an n-type semiconductor layer 123. These LED units The 12 series is subjected to an etching process on the light-emitting stack on the substrate 10, and the trenches 14 are formed to divide the plurality of light-emitting diode units 12. Since the substrate 10 is not electrically conductive, the trenches 14 formed between the plurality of light emitting diode units 12 can insulate the light emitting diode units 12 from each other, and further partially etch the light emitting diode units 12 to the n-type semiconductor layer. 123. A first electrode 18 and a second electrode 16 are formed on the exposed region of the n-type semiconductor layer 123 and the p-type semiconductor layer 121, respectively. The first electrode 18 and the second electrode 16 of the plurality of LED units 12 are selectively connected by the conductive wiring structure 19, so that a plurality of LED units 12 form a circuit connected in series or in parallel. For example, if a circuit connected in series is formed, it is a high voltage LED (HV LED) of DC.

然而，此種製程所形成之元件，常常會因各個發光二極體單元12間彼此互相吸收所發出的光，而造成元件整體亮度降低。此外，此種製程所形成之元件，其複數個發光二極體單元12係對同一基板之一區域的發光疊層施以蝕刻製程，以形成上述溝渠14而分割出複數個發光二極體單元，故元件與元件間可能因形成自基板不同區域，而有元件間在光學特性上或電性上均勻性不佳之問題。 However, the components formed by such a process are often caused by individual light-emitting diodes. The body units 12 absorb the emitted light from each other, causing the overall brightness of the element to decrease. In addition, in the device formed by the process, the plurality of LED units 12 are subjected to an etching process for the light-emitting layer of one region of the same substrate to form the trench 14 to divide a plurality of LED units. Therefore, there may be a problem that the components and the components are formed from different regions of the substrate, and the optical characteristics or electrical uniformity between the components is poor.

本發明係揭露一種發光元件之製造方法，包括：提供一第一基板；提供一半導體疊層於上述第一基板上，其中上述半導體疊層包括一第一電性半導體層、一發光層位於上述第一電性半導體層之上、以及一第二電性半導體層位於上述發光層之上，且上述半導體疊層係經圖形化而形成彼此分隔之複數個半導體疊層塊，其中上述複數個半導體疊層塊包括一第一半導體疊層塊及一第二半導體疊層塊；實行一分離步驟將上述第一半導體疊層塊與上述第一基板分離，且上述第一基板保留有上述第二半導體疊層塊；提供一永久基板具有一第一表面、一第二表面、以及一第三半導體疊層塊於上述第一表面上；以及接合上述第一半導體疊層塊及上述第二半導體疊層塊之其中之一於上述第二表面上。 The present invention discloses a method of fabricating a light-emitting device, comprising: providing a first substrate; providing a semiconductor layer on the first substrate, wherein the semiconductor layer comprises a first electrical semiconductor layer, and a light-emitting layer is located above a first electrical semiconductor layer and a second electrical semiconductor layer are disposed on the light emitting layer, and the semiconductor laminate is patterned to form a plurality of semiconductor stacked blocks separated from each other, wherein the plurality of semiconductors Lamination The block includes a first semiconductor stacked block and a second semiconductor stacked block; a separating step is performed to separate the first semiconductor stacked block from the first substrate, and the first substrate retains the second semiconductor stacked a permanent substrate having a first surface, a second surface, and a third semiconductor stacked block on the first surface; and bonding the first semiconductor stacked block and the second semiconductor stacked block One of them is on the second surface.

1‧‧‧習知的陣列式發光二極體元件 1‧‧‧Prevention of arrayed light-emitting diode components

10‧‧‧基板 10‧‧‧Substrate

101‧‧‧基板 101‧‧‧Substrate

103‧‧‧區分界線 103‧‧‧ distinction line

104v,104h‧‧‧分隔道 104v, 104h‧‧‧ divider

12‧‧‧發光二極體單元 12‧‧‧Lighting diode unit

121‧‧‧p型半導體層 121‧‧‧p-type semiconductor layer

122‧‧‧發光層 122‧‧‧Lighting layer

123‧‧‧n型半導體層 123‧‧‧n type semiconductor layer

131,132,133,134及135‧‧‧半導體疊層塊 131, 132, 133, 134 and 135‧‧ ‧ semiconductor laminated blocks

14‧‧‧溝渠 14‧‧‧ Ditch

16‧‧‧第二電極 16‧‧‧second electrode

18‧‧‧第一電極 18‧‧‧First electrode

19‧‧‧導電配線結構 19‧‧‧Electrical wiring structure

201‧‧‧基板 201‧‧‧Substrate

202‧‧‧半導體疊層 202‧‧‧Semiconductor laminate

202a‧‧‧第一電性半導體層 202a‧‧‧First electrical semiconductor layer

202b‧‧‧發光層 202b‧‧‧Lighting layer

202c‧‧‧第二電性半導體層 202c‧‧‧Second electrical semiconductor layer

d‧‧‧分隔道寬度 D‧‧‧ divider width

211‧‧‧第一犧牲層 211‧‧‧First Sacrifice Layer

212‧‧‧分隔道 212‧‧‧ divider

221‧‧‧第一暫時基板 221‧‧‧First temporary substrate

231,232,233,234及235‧‧‧半導體疊層塊 231, 232, 233, 234 and 235‧‧ ‧ semiconductor laminated blocks

23X‧‧‧半導體疊層塊 23X‧‧‧Semiconductor laminated block

241‧‧‧雷射光 241‧‧‧Laser light

301‧‧‧永久基板 301‧‧‧Permanent substrate

301P1‧‧‧第一表面 301P1‧‧‧ first surface

301P2‧‧‧第二表面 301P2‧‧‧ second surface

301P3‧‧‧第三表面 301P3‧‧‧ third surface

312B1,312B2及312B3‧‧‧接合層 312B1, 312B2 and 312B3‧‧‧ joint layer

320‧‧‧介電層 320‧‧‧ dielectric layer

330‧‧‧金屬線 330‧‧‧Metal wire

301’‧‧‧永久基板 301'‧‧‧Permanent substrate

301’P1‧‧‧第一表面 301’P1‧‧‧ first surface

301’P2‧‧‧第二表面 301’P2‧‧‧ second surface

301’P3‧‧‧第三表面 301’P3‧‧‧ third surface

312’B1‧‧‧第一接合層 312’B1‧‧‧First joint layer

312’B2P2‧‧‧第二接合層 312'B2P2‧‧‧Second joint layer

312’B3‧‧‧第三接合層 312'B3‧‧‧ third joint layer

500a,500b及500c‧‧‧發光元件 500a, 500b and 500c‧‧‧Lighting elements

501‧‧‧永久基板 501‧‧‧Permanent substrate

501a,501b,501c及501d‧‧‧半導體疊層塊 501a, 501b, 501c and 501d‧‧‧ semiconductor laminated blocks

第1圖所示為本發明發光元件之製造方法之一實施例所使用之一基板的上視圖。 Fig. 1 is a top plan view showing a substrate used in an embodiment of a method for producing a light-emitting device of the present invention.

第2A至2E圖所示為本發明之發光元件之製造方法所使用之分離方法之實施例。 2A to 2E are views showing an embodiment of a separation method used in the method of producing a light-emitting element of the present invention.

第3A至3E圖所示為本發明之發光元件之製造方法之第一實施例。 3A to 3E are views showing a first embodiment of a method of manufacturing a light-emitting element of the present invention.

第3F圖所示為本發明之發光元件之製造方法之第四實施例。 Fig. 3F is a view showing a fourth embodiment of the method of manufacturing a light-emitting element of the present invention.

第4圖所示為本發明之發光元件之製造方法之第五實施例。 Fig. 4 is a view showing a fifth embodiment of the method of manufacturing a light-emitting element of the present invention.

第5A至5C圖所示為本發明之發光元件之製造方法之第六實施例。 5A to 5C are views showing a sixth embodiment of the method of manufacturing a light-emitting element of the present invention.

第6圖所示為本發明發光元件之製造方法之一實施例所使用之一基板的實際量測及分佈情形，(a)的部份例示一以發光強度區分出第一區域及第二區域，(b)的部份則例示一以主波長區分出第一區域及第二區域。 FIG. 6 is a view showing actual measurement and distribution of a substrate used in an embodiment of a method for manufacturing a light-emitting device of the present invention, and part of (a) exemplifies a first region and a second region by illumination intensity. The part of (b) exemplifies that the first region and the second region are distinguished by the dominant wavelength.

第7A至7B圖所示為習知的陣列式發光二極體元件。 Figures 7A through 7B show a conventional array of light emitting diode elements.

圖1為本發明發光元件之製造方法之一實施例所使用之基板的上視圖，基板101上具有複數之半導體疊層塊，例如半導體疊層塊131,132,133,134及135，這些半導體疊層塊係由一半導體疊層(圖未示)經圖形化所形成，其中圖形化一般是指經覆蓋光阻並曝光顯影後加以蝕刻之製程。經圖形化後形成複數之分隔道104v,104h，而半導體疊層被分隔道104v,104h分隔成上述之複數之半導體疊層塊。但圖形化之方法並不限於此，其他方法，例如以雷射直接切割半導體疊層亦為一實施例。此外，上述半導體疊層可能係在基板101上成長，即基板101是半導體疊層之成長基板；也可能係半導體疊層形成在另一成長基板後，經移轉技術將半導體疊層移轉至此基板101上，於此情形時，半導體疊層(或半導體疊層塊)與基板101間可能更包括一黏結層(圖未示)。移轉技術為熟悉此技術領域之人士所習知，在此不予贅述。 1 is a top view of a substrate used in an embodiment of a method of fabricating a light-emitting device of the present invention, the substrate 101 having a plurality of semiconductor stacked blocks, such as semiconductor stacked blocks 131, 132, 133, 134 and 135, which are A semiconductor stack (not shown) is formed by patterning, wherein the patterning generally refers to a process of etching after covering the photoresist and exposing it to development. The plurality of partitions 104v, 104h are formed by patterning, and the semiconductor stack is divided into the plurality of semiconductor stacked blocks by the partitions 104v, 104h. However, the method of patterning is not limited thereto, and other methods, such as direct cutting of the semiconductor stack by laser, are also an embodiment. In addition, the semiconductor stack may be grown on the substrate 101, that is, the substrate 101 is a grown substrate of the semiconductor stack; or the semiconductor stack may be formed on another grown substrate, and the semiconductor stack is transferred to the current by the transfer technique. On the substrate 101, in this case, a semiconductor layer (or semiconductor stacked block) and the substrate 101 may further include a bonding layer (not shown). The transfer technique is known to those skilled in the art and will not be described here.

值得注意的是，在本實施例中，上述之複數之半導體疊層塊在光學特性上或電性上不同，故可經由實行一量測步驟測得各半導體疊層塊之一光學特徵值或一電性特徵值，並且可依一光學特徵值或電性特徵值之差異預定值將這些半導體疊層塊在基板101上分成一第一區域及一第二區域。其中光學特徵值例如為發光強度或波長，且波長可以是主波長(dominant wave length)或峰波長(peak wave length)，而電性特徵值例如為正向電壓(forward voltage)。在本實施例中，於量測各半導體疊層塊之發光強度後，依一發光強度之差異預定值，將這些半導體疊層塊在基板101上分成一第一區域及一第二區域。在此實施例中發光強度差異預定值為差異大於或等於3%，依此區分出一第一區域大致為圓形，如圖中圓形之區分界線103內所涵蓋之圓形區域，而第二區域則大致為環繞上述第一區域之一環狀，如圖中圓形之區分界線103外圍之環狀所涵蓋之區域。其中位於第一區域之半導體疊層塊的發光強度分佈彼此相近，而位於第二區域之半導體疊層塊的發光強度分佈彼此相近。於本實施例中，位於第一區域之半導體疊層塊(例如半導體疊層塊131,132，及133)的平均發光強度為4400 mcd，此區域內之半導體疊層塊的發光強度的標準差值約在0.5~1.5mcd，而位於第二區域之半導體疊層塊(例如半導體疊層塊134及135)的平均發光強度為4000 mcd，此區域內之半導體疊層塊的發光強度的標準差值約在0.5~1.5mcd；第一區域與第二區域內之半導體疊層塊的發光強度差異約為10%((4400-4000)/4000=10%)，亦即大於或等於3%。 It should be noted that, in this embodiment, the plurality of semiconductor stacked blocks are optically or electrically different, so that one optical measurement value of each semiconductor stacked block can be measured by performing a measuring step or An electrical characteristic value, and the semiconductor stacked blocks can be divided into a first region and a second region on the substrate 101 according to a predetermined difference between an optical characteristic value or an electrical characteristic value. The optical characteristic value is, for example, an emission intensity or a wavelength, and the wavelength may be a dominant wave length or a peak wave length, and the electrical characteristic value is, for example, a forward voltage. In this embodiment, the semiconductor stacked blocks are measured. After the luminous intensity, the semiconductor stacked blocks are divided into a first region and a second region on the substrate 101 according to a predetermined difference in luminous intensity. In this embodiment, the predetermined difference in luminous intensity difference is greater than or equal to 3%, thereby distinguishing that a first region is substantially circular, as shown by a circular region covered by a circular boundary line 103 in the figure, and The two regions are substantially annular around one of the first regions, as shown by the ring around the circular boundary line 103 in the figure. The illuminating intensity distributions of the semiconductor stacked blocks located in the first region are similar to each other, and the illuminating intensity distributions of the semiconductor stacked blocks located in the second region are close to each other. In the present embodiment, the average light-emitting intensity of the semiconductor stacked blocks (for example, the semiconductor stacked blocks 131, 132, and 133) located in the first region is 4400 mcd, and the standard deviation of the luminous intensity of the semiconductor stacked block in this region is about At 0.5 to 1.5 mcd, the average luminescence intensity of the semiconductor stacked blocks (e.g., semiconductor stacked blocks 134 and 135) in the second region is 4000 mcd, and the standard deviation of the illuminating intensity of the semiconductor stacked block in this region is about The difference in luminous intensity of the semiconductor stacked block in the first region and the second region is about 10% ((4400-4000) / 4000 = 10%), that is, greater than or equal to 3%.

除了發光強度外，在其他實施例中，用以區分出第一區域及第二區域之光學特性不同則可能為峰光波長或主光波長之差異大於或等於1nm，而電性不同則可能包括正向電壓(forward voltage)之差異大於或等於2%。圖6所示為一實際量測結果之分佈圖，(a)的部份例示一以發光強度(Iv)的量測結果區分，且依一發光強度之差異預定值區分出第一區域及第二區域，在此實施例發光強度差異之差異預定值為大於或等於3%。如(a)的部份所示，各半導體疊層塊所測得之發光強度以顏色(圖中為灰階)標示，各顏色(圖中為灰階)所代表之發光強度值可參照其下方之發光強度值與顏色(圖中為灰階)對照關係之標示，如圖中虛線所圈示之區域，可看出所區分出之第一區域主要係由代表發光強度130mcd之紅色(圖中為灰階)與代表示發光強度129mcd之橘色(圖中為灰階)所構成，而僅包含少數代表發光強度124mcd之綠色(圖中為灰階)之半導體疊層塊，此第一區域大致為圓形，平均發光強度約129mcd，而第二區域則大致為環繞上述第一區域之一環狀，主要係由代表發光強度124mcd之綠色(圖中為灰階)之半導體疊層塊所構成，僅包含少數代表發光強度130mcd之紅色(圖中為灰階)與代表發光強度129mcd之橘色(圖中為灰階)，此第二區域之平均發光強度約124mcd，亦即第一區域之半導體疊層塊的發光強度平均值較位於第二區域之半導體疊層塊的發光強度平均值大，其差異約為4%((129-124)/124=4%)，大於或等於3%。(b)的部份則例示一以主波長(WLD)的量測結果區分，且依一主波長(WLD)之差異預定值，在此實施例為主波長差異預定值大於或等於1nm，而區分出第一區域及第二區域，如(b)的部份所示，所區分出第一區域及第二區域，第一區域(如圖中虛線所圈示)大致為圓形，平均主波長約685nm，而第二區域則大致為環繞上述第一區域之一環狀，平均主波長約683nm，其中第一區域之半導體疊層塊的主波長平均值較位於第二區域之半導體疊層塊的主波長平均值大，其差異為2nm，大於主波長差異預定值1nm。 In addition to the illuminance, in other embodiments, the difference in optical characteristics between the first region and the second region may be that the difference between the peak wavelength or the main wavelength is greater than or equal to 1 nm, and the difference in electrical properties may include The difference in forward voltage is greater than or equal to 2%. Fig. 6 is a distribution diagram of actual measurement results, and part of (a) is illustrated by a measurement result of luminous intensity (Iv), and the first region and the first region are distinguished by a predetermined value of difference in luminous intensity. In the two regions, the difference in the difference in luminous intensity in this embodiment is a predetermined value of 3% or more. As shown in part (a), the illuminance intensity measured by each semiconductor laminate block is indicated by a color (gray scale in the figure), and the illuminance intensity value represented by each color (gray scale in the figure) can be referred to Below The indication of the relationship between the luminous intensity value and the color (the gray scale in the figure), as shown by the dotted line in the figure, can be seen that the first region distinguished is mainly red represented by the luminous intensity 130mcd (in the figure The gray scale) is composed of the orange color (the gray scale in the figure) indicating the luminous intensity of 129mcd, and only a few semiconductor laminated blocks representing the green color (the gray scale in the figure) of the luminous intensity of 124mcd. The circular shape has an average luminous intensity of about 129 mcd, and the second region is substantially annular around one of the first regions, and is mainly composed of a semiconductor laminated block representing a green color (a gray scale in the figure) of a luminous intensity of 124 mcd. Containing only a few reds representing the illuminance of 130mcd (gray scale in the figure) and orange representing the illuminance of 129mcd (gray scale in the figure), the average illuminance of the second region is about 124mcd, that is, the first region The average of the luminous intensity of the semiconductor stacked block is larger than the average of the luminous intensity of the semiconductor stacked block located in the second region, and the difference is about 4% ((129-124) / 124 = 4%), greater than or equal to 3%. . The part of (b) is exemplified by a measurement result of a dominant wavelength (WLD), and a predetermined value according to a difference of a dominant wavelength (WLD). In this embodiment, the predetermined value of the main wavelength difference is greater than or equal to 1 nm, and Distinguishing between the first area and the second area, as shown in part (b), the first area and the second area are distinguished, and the first area (circled by a broken line in the figure) is substantially circular, and the average main The wavelength is about 685 nm, and the second region is substantially annular around one of the first regions, and the average dominant wavelength is about 683 nm, wherein the average wavelength of the main wavelength of the semiconductor stacked block of the first region is smaller than the semiconductor stack of the second region. The average wavelength of the main wavelength of the block is large, and the difference is 2 nm, which is larger than the main wavelength difference by a predetermined value of 1 nm.

圖2A至2E顯示為本發明之發光元件之製造方法所使用之分離方法之實施例。如上述圖1中所述，在圖2A中，一基板201包含一半導體疊層202於其上，此半導體疊層202包括一第一電性半導體層202a；一發光層202b位於第一電性半導體層202a之上；以及一第二電性半導體層202c位於發光層202b之上。第一電性半導體層202a和第二電性半導體層202c電性相異，例如第一電性半導體層202a是n型半導體層，而第二電性半導體層202c是p型半導體層。第一電性半導體層202a、發光層202b、及第二電性半導體層202c為III-V族材料所形成，例如為磷化鋁鎵銦(AlGaInP)系列材料或氮化鋁鎵銦(AlGaInN)系列材料。在圖2B中，實施前述之圖形化步驟後，形成寬度為d之分隔道212將半導體疊層202分隔為複數之半導體疊層塊231,232,233,234及235，分別對應於圖1中之半導體疊層塊131,132,133,134及135，而且分別具有如圖1中所述之發光強度及分別位於上述之第一區域及第二區域；亦即半導體疊層塊231,232，及233位於上述圖1中的第一區域且發光強度為4400 mcd，而半導體疊層塊234及235位於上述圖1中的第二區域且的發光強度為4000 mcd，半導體疊層塊231,232，及233與半導體疊層塊234及235就發光強度而言差異大於3%。接著，在欲移離之半導體疊層塊上形成一第一犧牲層211以利實行分離步驟，在本實施例中，欲移離之半導體疊層塊為半導體疊層塊232及234。此第一犧牲層211之形成可以是先在整個基板201上形成一整層第一犧牲層211之材料後，再以黃光及蝕刻製程選擇性地在欲移離之半導體疊層塊232及234上形成此第一犧牲層211。值得注意的是，熟悉此技術領域之人士亦了解，在製程順序上，也可以是先在欲移離之半導體疊層塊232及234之位置上形成此第一犧牲層211後，再以另一黃光及蝕刻製程以完成前述之半導體疊層202之圖形化成複數之半導體疊層塊231,232,233,234，及235之步驟。在圖2C中，實行分離步驟，包括：提供一第一暫時基板 221，使第一犧牲層211與第一暫時基板221接合；之後，如圖2D所示，將欲移離之半導體疊層塊232及234與基板201分離。在實施上述步驟時，可在欲移離之半導體疊層塊232及234與基板201之界面施以一雷射光241照射，以輔助半導體疊層塊232及234與基板201之分離。再者，半導體疊層202亦可能係在另一成長基板形成後，再經移轉技術移轉至基板201上，於此情形時，亦可在半導體疊層202移轉至基板201時，選擇性地在欲移離之半導體疊層塊232及234之位置上，先形成與基板201間之一犧牲層(圖未示)，此犧牲層本身材料較脆弱或與基板201之接合較弱，如此可在欲移離之半導體疊層塊232及234與基板201分離時，使欲移離之半導體疊層塊232及234與基板201較易分離。 2A to 2E show an embodiment of a separation method used in the method of manufacturing a light-emitting element of the present invention. As shown in FIG. 1 above, in FIG. 2A, a substrate 201 includes a semiconductor layer 202 thereon. The semiconductor layer 202 includes a first electrical semiconductor layer 202a. A light-emitting layer 202b is located at the first electrical layer. Above the semiconductor layer 202a; and a second The semiconductor layer 202c is located above the light-emitting layer 202b. The first electrical semiconductor layer 202a and the second electrical semiconductor layer 202c are electrically different, for example, the first electrical semiconductor layer 202a is an n-type semiconductor layer, and the second electrical semiconductor layer 202c is a p-type semiconductor layer. The first electrical semiconductor layer 202a, the light emitting layer 202b, and the second electrical semiconductor layer 202c are formed of a III-V material, such as an aluminum gallium indium phosphide (AlGaInP) series material or aluminum gallium indium nitride (AlGaInN). Series of materials. In FIG. 2B, after performing the foregoing patterning step, a trench 212 having a width d is formed to divide the semiconductor stack 202 into a plurality of semiconductor stacked blocks 231, 232, 233, 234 and 235, respectively corresponding to the semiconductor stacked blocks 131, 132, 133, 134 of FIG. And 135, and respectively having the luminous intensity as described in FIG. 1 and respectively located in the first region and the second region; wherein the semiconductor laminate blocks 231, 232, and 233 are located in the first region of FIG. 1 and the luminous intensity 4400 mcd, and the semiconductor stacked blocks 234 and 235 are located in the second region of FIG. 1 and the luminous intensity is 4000 mcd, and the semiconductor stacked blocks 231, 232, and 233 and the semiconductor stacked blocks 234 and 235 are in terms of luminous intensity. The difference is greater than 3%. Next, a first sacrificial layer 211 is formed on the semiconductor stacked block to be removed to facilitate the separation step. In the present embodiment, the semiconductor stacked blocks to be removed are the semiconductor stacked blocks 232 and 234. The first sacrificial layer 211 may be formed by forming a whole layer of the first sacrificial layer 211 on the entire substrate 201, and then selectively removing the semiconductor stacked block 232 and the semiconductor layer 232 to be removed by a yellow light and an etching process. This first sacrificial layer 211 is formed on 234. It should be noted that those skilled in the art also understand that, in the process sequence, the first sacrificial layer 211 may be formed at the position of the semiconductor stacked blocks 232 and 234 to be removed, and then A yellow light and etching process is performed to complete the steps of patterning the plurality of semiconductor stacked blocks 231, 232, 233, 234, and 235 of the semiconductor stack 202 described above. In FIG. 2C, performing a separation step includes: providing a first temporary substrate 221, the first sacrificial layer 211 is bonded to the first temporary substrate 221; thereafter, as shown in FIG. 2D, the semiconductor stacked blocks 232 and 234 to be removed are separated from the substrate 201. In performing the above steps, a laser beam 241 may be applied to the interface between the semiconductor stacked blocks 232 and 234 to be removed and the substrate 201 to assist in the separation of the semiconductor stacked blocks 232 and 234 from the substrate 201. Furthermore, the semiconductor stack 202 may also be transferred to the substrate 201 after the formation of another growth substrate, and in this case, when the semiconductor laminate 202 is transferred to the substrate 201, At a position of the semiconductor stacked blocks 232 and 234 to be removed, a sacrificial layer (not shown) is formed between the substrate 201 and the substrate 201. The sacrificial layer itself is weak in material or weakly bonded to the substrate 201. Thus, when the semiconductor stacked blocks 232 and 234 to be removed are separated from the substrate 201, the semiconductor stacked blocks 232 and 234 to be removed are easily separated from the substrate 201.

圖2E顯示實行分離步驟後，半導體疊層塊232及234與基板201分離，而基板201保留有半導體疊層塊231，233及235。值得注意的是，第一暫時基板221及其上之半導體疊層塊232及234，或基板201及其上之半導體疊層塊231，233及235，兩者均可以使用在下述之本發明之發光元件之製造方法之實施例中。 2E shows that after the separation step is performed, the semiconductor stacked blocks 232 and 234 are separated from the substrate 201, and the substrate 201 retains the semiconductor stacked blocks 231, 233 and 235. It should be noted that the first temporary substrate 221 and the semiconductor stacked blocks 232 and 234 thereon, or the substrate 201 and the semiconductor stacked blocks 231, 233 and 235 thereon, can be used in the present invention described below. In an embodiment of a method of manufacturing a light-emitting element.

圖3A至3E顯示為本發明之發光元件之製造方法之第一實施例。首先，如圖3A所示，提供一永久基板301，此永久基板301至少具有一第一表面301P1、一第二表面301P2，在本實施例中，永久基板301更具有一第三表面301P3。其中，如圖所繪示，第一表面301P1與第二表面301P2非共平面。在一實施例中，此非共平面係經由對一原本具有一平面表面的永久基板施以黃光及蝕刻製程而形成此非共平面之第一表面301P1及第二表面301P2。永久基板301之材料例如為玻璃，藍寶石(Al₂O₃)，或矽(Si)基板。 3A to 3E show a first embodiment of a method of manufacturing a light-emitting element of the present invention. First, as shown in FIG. 3A, a permanent substrate 301 is provided. The permanent substrate 301 has at least a first surface 301P1 and a second surface 301P2. In the embodiment, the permanent substrate 301 further has a third surface 301P3. As shown in the figure, the first surface 301P1 and the second surface 301P2 are not coplanar. In one embodiment, the non-coplanar surface forms the non-coplanar first surface 301P1 and the second surface 301P2 by applying a yellow light and an etching process to a permanent substrate having a planar surface. The material of the permanent substrate 301 is, for example, glass, sapphire (Al ₂ O ₃ ), or yttrium (Si) substrate.

接著，如圖3B所示，接合圖2E中之半導體疊層塊234於永久基板301之第一表面301P1上。例如當永久基板301之材料為藍寶石基板時，經過適當之加溫加壓，例如溫度約為300℃~420℃，壓力約為11000Kgf~14000Kgf，可使半導體疊層塊234直接接合於永久基板301；此接合亦可為選擇性地透過一接合層312B1進行接合，例如當永久基板301之材料為藍寶石基板時，可選擇二氧化矽為接合層312B1。然後將半導體疊層塊234與第一暫時基板221分離；而在實施此步驟時，係在半導體疊層塊234與第一犧牲層211之界面施以一雷射光照射(圖未示)，以輔助半導體疊層塊234與第一犧牲層211之分離。 Next, as shown in FIG. 3B, the semiconductor stacked block 234 of FIG. 2E is bonded to the first surface 301P1 of the permanent substrate 301. For example, when the material of the permanent substrate 301 is a sapphire substrate, the semiconductor laminate block 234 can be directly bonded to the permanent substrate 301 by appropriate warming and pressing, for example, a temperature of about 300 ° C to 420 ° C and a pressure of about 11,000 Kgf to 14000 Kgf. The bonding may also be selectively performed by bonding a bonding layer 312B1. For example, when the material of the permanent substrate 301 is a sapphire substrate, the germanium dioxide may be selected as the bonding layer 312B1. Then, the semiconductor stacked block 234 is separated from the first temporary substrate 221; and when this step is performed, a laser light irradiation (not shown) is applied to the interface between the semiconductor stacked block 234 and the first sacrificial layer 211 to The auxiliary semiconductor stacked block 234 is separated from the first sacrificial layer 211.

接著，如圖3C所示，接合半導體疊層塊232於永久基板301之第二表面301P2上。此接合大致與上述半導體疊層塊234之接合類似，故不再贅述。 Next, as shown in FIG. 3C, the semiconductor stacked block 232 is bonded to the second surface 301P2 of the permanent substrate 301. This bonding is substantially similar to the bonding of the above-described semiconductor stacked block 234, and therefore will not be described again.

如同在前面圖2A中所述，在一實施例中，半導體疊層塊231,232,233,234，及235對應於圖1中之半導體疊層塊131,132,133,134，及135而分別具有如圖1中所述之發光強度，亦即半導體疊層塊231,232,及233位於上述圖1中的第一區域且平均發光強度為4400 mcd，而半導體疊層塊234及235位於上述圖1中的第二區域且平均發光強度為4000 mcd，半導體疊層塊231,232及233與半導體疊層塊234及235就發光強度而言差異大於3%。經由上述實施例製造方法之所產生之發光元件，讓原本位於光學特性上或電性上有較大差異性之兩區域之複數半導體疊層塊得以重新分配組合。例如若以先前技術中所述之方法，半導體疊層塊132與133可能因位置相近且大致位於同一區域(請參圖1及圖2B)而於後續製程中組合成為一元件A。同樣地，半導體疊層塊134與135因位置相近且大致位於同一區域(請參圖1及圖2B)而於後續製程中組合成為另一元件B。如此，元件A將包含兩個平均發光強度為4400 mcd之半導體疊層塊，而元件B將包含兩個平均發光強度為4000 mcd之半導體疊層塊，兩元件發光強度均勻性不佳。依經由上述實施例製造方法之所產生之發光元件，例如圖3C中，第一表面301P1上有原本在位於圖1中平均發光強度為4000 mcd的第二區域之半導體疊層塊234；而第二表面301P2上有原本在位於圖1中平均發光強度為4400 mcd的第一區域之半導體疊層塊232。故原本位於光學特性上(如本實施例之發光強度)或電性上有較大差異性之兩區域之複數半導體疊層塊已重新分配組合。同樣地，藉由上述實施例之製造方法，亦可以得到另一元件包含有原本在位於圖1中平均發光強度為4000 mcd的第二區域之半導體疊層塊235及原本在位於圖1中平均發光強度為4400 mcd的第一區域之半導體疊層塊233。因而上述兩元件在元件間發光強度均勻性有較佳之表現。 As described above in FIG. 2A, in one embodiment, the semiconductor stacked blocks 231, 232, 233, 234, and 235 correspond to the semiconductor stacked blocks 131, 132, 133, 134, and 135 of FIG. 1, respectively, having the luminous intensity as described in FIG. That is, the semiconductor stacked blocks 231, 232, and 233 are located in the first region of FIG. 1 described above and have an average luminous intensity of 4400 mcd, and the semiconductor stacked blocks 234 and 235 are located in the second region of FIG. 1 described above and have an average luminous intensity of 4000. Mcd, the semiconductor stacked blocks 231, 232 and 233 and the semiconductor stacked blocks 234 and 235 differ by more than 3% in terms of luminous intensity. Through the light-emitting elements produced by the manufacturing method of the above embodiment, the plurality of semiconductor stacked blocks which are originally located in two regions which are optically or electrically differently are reassigned and combined. For example, if the method described in the prior art, the semiconductor The stacked blocks 132 and 133 may be combined into one element A in a subsequent process due to their close proximity and substantially in the same area (see FIGS. 1 and 2B). Similarly, the semiconductor stacked blocks 134 and 135 are combined into another element B in a subsequent process due to their close proximity and substantially in the same area (see FIGS. 1 and 2B). Thus, component A will comprise two semiconductor stacked blocks having an average luminous intensity of 4400 mcd, while component B will comprise two semiconductor stacked blocks having an average luminous intensity of 4000 mcd, and the two elements have poor uniformity of luminous intensity. According to the light-emitting element produced by the manufacturing method of the above embodiment, for example, in FIG. 3C, the first surface 301P1 has a semiconductor stacked block 234 originally located in the second region having an average luminous intensity of 4000 mcd in FIG. 1; The second surface 301P2 has a semiconductor stacked block 232 which is originally in the first region of the average luminous intensity of 4400 mcd in Fig. 1. Therefore, the plurality of semiconductor stacked blocks which are originally located in the optical characteristics (such as the luminous intensity of the present embodiment) or the two regions having large differences in electrical properties have been redistributed and combined. Similarly, by the manufacturing method of the above embodiment, it is also possible to obtain another element including the semiconductor stacked block 235 which is originally located in the second region having an average luminous intensity of 4000 mcd in FIG. 1 and which is originally located in FIG. A semiconductor stacked block 233 of a first region having an emission intensity of 4400 mcd. Therefore, the above two elements have a better performance in terms of uniformity of luminous intensity between elements.

此外，半導體疊層塊234及232經由接合至永久基板301，而分別位於非共平面之第一表面301P1與第二表面301P2上，因此可降低各個半導體疊層塊間彼此互相吸收所發出光之情形，而使元件整體亮度有較佳表現。 In addition, the semiconductor stacked blocks 234 and 232 are respectively bonded to the permanent substrate 301 on the first surface 301P1 and the second surface 301P2 of the non-coplanar plane, thereby reducing the light emitted from each other by the respective semiconductor stacked blocks. In this case, the overall brightness of the component is better.

經由如同前述之接合方法，可在永久基板301之第三表面301P3上接合另一半導體疊層塊23X，如圖3D所示。此處之半導體疊層塊23X並沒有特別之限定，熟悉此技術領域之人士當了解其重點在於如何如同上述之揭示使半導體疊層塊重新分配組合而達到產出之各元件之元件間光學特性上或電性上均勻性有較佳之表現。接著，如圖3E所示，以黃光及蝕刻製程將各半導體疊層塊部分蝕刻以暴露各半導體疊層塊至其第一電性半導體層202a，並形成介電層320於各半導體疊層塊之側壁，最後實施一金屬線形成步驟以形成一金屬線330於各半導體疊層塊間，以使各半導體疊層塊電性連接，其電性連接關係可為串聯或並聯。如圖3E所示金屬線330電性連接各半導體疊層塊形成一串聯關係。 Another semiconductor stacked block 23X may be bonded on the third surface 301P3 of the permanent substrate 301 via a bonding method as described above, as shown in FIG. 3D. Semiconductor stack here Block 23X is not particularly limited, and those skilled in the art will understand that the focus is on how to optically or electrically balance the components of the components that are produced by redistributing the semiconductor laminate blocks as disclosed above. Sex has better performance. Next, as shown in FIG. 3E, each of the semiconductor stacked blocks is partially etched by a yellow light and an etching process to expose the respective semiconductor stacked blocks to the first electrical semiconductor layer 202a thereof, and a dielectric layer 320 is formed on each of the semiconductor stacked layers. Finally, a metal wire forming step is performed to form a metal line 330 between the semiconductor stacked blocks, so that the semiconductor stacked blocks are electrically connected, and the electrical connection relationship may be serial or parallel. The metal line 330 is electrically connected to each of the semiconductor stacked blocks as shown in FIG. 3E to form a series relationship.

雖然本實施例例示接合至永久基板301之兩半導體疊層塊均為圖2E中與基板201分離之半導體疊層塊，但熟悉此技術領域之人士當明瞭不限於此，例如在圖2E中，在基板201上保留有半導體疊層塊231,233，及235，在一第二實施例中，亦可以這些存留在基板201上之半導體疊層塊接合至永久基板301。其情形大致如同圖3B至3E中所示，僅圖中第一暫時基板221及其上之半導體疊層塊對應改為基板201及其上之半導體疊層塊231,233，及235，故不再重覆繪示其圖示。因此在此情形下，其接合步驟為將基板201與永久基板301對位接合，以使半導體疊層塊231,233，或235接合至欲接合之表面上；以及使基板201與永久基板301遠離，並使接合之半導體疊層塊與基板201分離。又或者在第三實施例中，這些存留在基板201上之半導體疊層塊231,233，及235可以如同第一實施例先被自基板201分離後再接合至永久基板301，在此情形下，其接合步驟接合為將半導體疊層塊231,233，或235接合於一第二暫時基板並使半導體疊層塊231,233，或235與基板201分離；再將第二暫時基板與永久基板301對位接合，以使半導體疊層塊231,233，或235接合至欲接合之表面上；以及使第二暫時基板與永久基板301遠離，並使接合之半導體疊層塊與第二暫時基板分離。 Although the present embodiment exemplifies that the two semiconductor stacked blocks bonded to the permanent substrate 301 are the semiconductor stacked blocks separated from the substrate 201 in FIG. 2E, those skilled in the art are not limited thereto, for example, in FIG. 2E. The semiconductor stacked blocks 231, 233, and 235 are left on the substrate 201. In a second embodiment, the semiconductor stacked blocks remaining on the substrate 201 may be bonded to the permanent substrate 301. The situation is substantially as shown in FIGS. 3B to 3E. Only the first temporary substrate 221 and the semiconductor stacked block thereon are correspondingly changed to the substrate 201 and the semiconductor stacked blocks 231, 233, and 235 thereon, so that it is no longer heavy. Overlay the icon. Therefore, in this case, the bonding step is to align the substrate 201 with the permanent substrate 301 to bond the semiconductor stacked block 231, 233, or 235 to the surface to be bonded; and to move the substrate 201 away from the permanent substrate 301, and The bonded semiconductor laminate block is separated from the substrate 201. Or in the third embodiment, the semiconductor stacked blocks 231, 233, and 235 remaining on the substrate 201 may be separated from the substrate 201 and then bonded to the permanent substrate 301 as in the first embodiment, in which case Bonding step bonding to bond semiconductor stacked blocks 231, 233, or 235 a second temporary substrate separates the semiconductor stacked block 231, 233, or 235 from the substrate 201; and the second temporary substrate is alignably bonded to the permanent substrate 301 to bond the semiconductor stacked block 231, 233, or 235 to the surface to be bonded And moving the second temporary substrate away from the permanent substrate 301 and separating the bonded semiconductor stacked block from the second temporary substrate.

值得注意的是，雖然第一實施例例示永久基板301之第一表面301P1上之半導體疊層塊(即半導體疊層塊234)與第二表面301P2上之半導體疊層塊(即半導體疊層塊232)源自同一之半導體疊層202，但並不限於此，亦即在其他實施例，第一表面301P1上之半導體疊層塊與第二表面301P2上之半導體疊層塊可源自不同之半導體疊層，例如第一表面301P1上之半導體疊層塊為半導體疊層塊234，而第二表面301P2上之半導體疊層塊可源自另一不同之基板之半導體疊層。又或雖源自同一之半導體疊層，但可分別如同上述透過第一暫時基板221或基板201或第二暫時基板而被接合至永久基板301上。 It is to be noted that although the first embodiment exemplifies the semiconductor stacked block (ie, the semiconductor stacked block 234) on the first surface 301P1 of the permanent substrate 301 and the semiconductor stacked block on the second surface 301P2 (ie, the semiconductor stacked block) 232) from the same semiconductor stack 202, but is not limited thereto, that is, in other embodiments, the semiconductor stacked block on the first surface 301P1 and the semiconductor stacked block on the second surface 301P2 may be derived from different The semiconductor stack, for example, the semiconductor stacked block on the first surface 301P1 is the semiconductor stacked block 234, and the semiconductor stacked block on the second surface 301P2 can be derived from the semiconductor stack of another different substrate. Alternatively, it may be bonded to the permanent substrate 301 through the first temporary substrate 221 or the substrate 201 or the second temporary substrate as described above.

圖3F顯示本發明之第四實施例，此實施例大致與第一實施例相同，但第一實施例中之永久基板301在本實施例改為永久基板301’。相對於永久基板301具有非共平面之第一表面301P1、第二表面301P2，及第三表面301P3，本實施例之永久基板301’之第一表面301’P1、第二表面301’P2，及第三表面301’P3則為共平面，但在各半導體疊層塊接合至永久基板301’時，則透過不同厚度之接合層達到使各半導體疊層塊不共平面之效果。亦即，例如半導體疊層塊234經由一第一接合層312’B1接合於第一表面301’P1上，半導體疊層塊232經由一第二接合層312’B2接合於第二表面301’P2上，而第一接合層 312’B1與第二接合層312’B2厚度不同，以使半導體疊層塊234與半導體疊層塊232非共平面。 Fig. 3F shows a fourth embodiment of the present invention, which is substantially the same as the first embodiment, but the permanent substrate 301 in the first embodiment is changed to the permanent substrate 301' in this embodiment. The first surface 301P1, the second surface 301P2, and the third surface 301P3 having a non-coplanar surface with respect to the permanent substrate 301, the first surface 301'P1, the second surface 301'P2 of the permanent substrate 301' of the present embodiment, and The third surface 301'P3 is coplanar. However, when the respective semiconductor stacked blocks are bonded to the permanent substrate 301', the bonding layers of different thicknesses are transmitted to achieve the effect that the respective semiconductor stacked blocks are not coplanar. That is, for example, the semiconductor stacked block 234 is bonded to the first surface 301'P1 via a first bonding layer 312'B1, and the semiconductor stacked block 232 is bonded to the second surface 301'P2 via a second bonding layer 312'B2. Upper first layer The thickness of 312'B1 is different from the thickness of the second bonding layer 312'B2 such that the semiconductor stacked block 234 and the semiconductor stacked block 232 are not coplanar.

值得注意的是，雖然在第一實施例說明可使用如圖1因光學特徵值或電性特徵值不同而在基板上區分出複數區域之複數半導體疊層塊進行接合，但本發明並不限於此。第4圖顯示本發明之第五實施例，此實施例顯示半導體疊層塊在光學特性或電性上並非如同圖1在基板上即可區分出不同區域，但對於位於同一基板上之複數之半導體疊層塊，仍可對其依據一光學特徵值或電性特徵值之量測結果，將此複數之半導體疊層塊區分別歸類於一一般規格區，一低規格區，及一高規格區，其中光學特徵值或電性特徵值為高規格區大於一般規格區，且一般規格區大於低規格區。以圖4為例，係對於一基板上之複數之半導體疊層塊進行發光強度量測之結果，各半導體疊層塊於基板上之位置及發光強度可於量測後存於機台中。圖中水平軸為發光強度，垂直軸則為對應各發光強度之半導體疊層塊之數量。如圖所示，a結果區為低規格區，其發光強度平均值大致為700mcd；b結果區為一般規格區，其發光強度平均值大致為900mcd；而c結果區為高規格區，其發光強度平均值大致為1200mcd。而利用如圖2之分離方法及如圖3之接合方法，可根據存於機台中之各半導體疊層塊之位置及發光強度之資料，挑選適當之半導體疊層塊接合於如圖3A之永久基板301上，而達到半導體疊層塊之重新分配。如圖4右方所示，若一元件上設計有5個半導體疊層塊，則重新分配之結果，可挑選5個屬於一般規格區(發光強度平均值大致為900mcd)之半導體疊層塊接合於如圖3A之永久基板301上，形成元件C；而另一元件D則可挑選3個屬於低規格區(發光強度平均值大致為700mcd)之半導體疊層塊接合於如圖3A之永久基板301上，並挑選2個屬於高規格區(發光強度平均值大致為1200mcd)之半導體疊層塊接合於同一永久基板301上，以形成元件D。如此，雖然於生產基板不同位置之區域的半導體疊層塊在光學特性或電性上會有較大之差異，例如本實施例中發光強度高者，其值可高到高規格區之1200mcd，而發光強度低者，其值可低到低規格區之700mcd，但經本實施例對半導體疊層塊之重新分配，產出之各元件其元件間均勻性將獲得改善及控制，元件C與元件D之發光強度均大致為4500mcd。此外，如第一實施例所提及，半導體疊層塊經由接合至永久基板301，而分別位於非共平面之不同表面，可降低各個半導體疊層塊間彼此互相吸收所發出光之情形，而使元件整體亮度有較佳表現。 It is to be noted that although the first embodiment illustrates the use of a plurality of semiconductor stacked blocks in which a plurality of regions are distinguished on a substrate due to differences in optical characteristic values or electrical characteristic values, the present invention is not limited thereto. this. Figure 4 shows a fifth embodiment of the present invention. This embodiment shows that the semiconductor stacked blocks are not optically or electrically different from each other as shown in Figure 1 on the substrate, but for a plurality of substrates on the same substrate. The semiconductor stacked block can still be classified according to an optical characteristic value or an electrical characteristic value, and the plurality of semiconductor stacked blocks are respectively classified into a general specification area, a low specification area, and a high The specification area, wherein the optical characteristic value or the electrical characteristic value is higher than the general specification area, and the general specification area is larger than the low specification area. Taking FIG. 4 as an example, as a result of measuring the luminous intensity of a plurality of semiconductor stacked blocks on a substrate, the position and luminous intensity of each of the semiconductor stacked blocks on the substrate can be stored in the machine after measurement. In the figure, the horizontal axis is the luminous intensity, and the vertical axis is the number of semiconductor stacked blocks corresponding to the respective luminous intensities. As shown in the figure, the a result area is a low specification area, and the average luminous intensity is approximately 700mcd; the b result area is a general specification area, and the average luminous intensity is approximately 900mcd; and the c result area is a high specification area, which emits light. The average intensity is approximately 1200 mcd. By using the separation method of FIG. 2 and the bonding method of FIG. 3, an appropriate semiconductor stacked block can be selected and bonded to the permanent as shown in FIG. 3A according to the position and luminous intensity of each semiconductor stacked block stored in the machine. On the substrate 301, the redistribution of the semiconductor stacked blocks is achieved. As shown in the right side of Figure 4, if five semiconductor stacked blocks are designed on one component, the result of redistribution can select five semiconductor stacked block junctions belonging to the general specification area (the average luminous intensity is approximately 900mcd). As shown in Figure 3A On the long substrate 301, the component C is formed; and the other component D can select three semiconductor laminated blocks belonging to the low specification region (the average luminous intensity is approximately 700 mcd) to be bonded to the permanent substrate 301 of FIG. 3A, and selected. Two semiconductor stacked blocks belonging to the high specification region (having an average luminous intensity of approximately 1200 mcd) are bonded to the same permanent substrate 301 to form the element D. Thus, although the semiconductor stacked blocks in the regions where the substrate is produced at different positions may have large differences in optical characteristics or electrical properties, for example, those having high luminous intensity in the embodiment may have a value as high as 1200 mcd in the high specification region. The lower the luminous intensity, the value can be as low as 700mcd in the low specification area, but the redistribution of the semiconductor stacked block in this embodiment, the uniformity of the components of the produced components will be improved and controlled, and the components C and components The luminous intensity of D is approximately 4500 mcd. In addition, as mentioned in the first embodiment, the semiconductor stacked blocks are bonded to the permanent substrate 301, respectively, on different surfaces of the non-coplanar, which can reduce the situation in which the respective semiconductor stacked blocks absorb light from each other, and Make the overall brightness of the component better.

值得注意的是，在以上各實施例中，光學特徵值或電性特徵值可在分離步驟前，實際針對各基板之半導體疊層塊全部或採樣性地實行量測而取得；而在製程穩定之情況下，這些光學特徵值或電性特徵值也可經由一定數量之統計後得到一事先決定之統計值。例如針對圖1之情形，在製程穩定之情況下，一定數量之統計後即可確定第一區域與第二區域之邊界位置，即得到第一區域之半徑之一預定值，及對應兩個區域之光學特徵值或電性特徵值，而不必在製造過程中在對各產出之基板一一進行量測。 It should be noted that, in the above embodiments, the optical characteristic value or the electrical characteristic value may be obtained by measuring the sampling or the sampling of the semiconductor stacked blocks of the respective substrates before the separating step; and the process is stable. In this case, these optical characteristic values or electrical characteristic values can also be obtained through a certain amount of statistics to obtain a predetermined statistical value. For example, in the case of FIG. 1, in the case where the process is stable, a certain number of statistics can determine the boundary position between the first region and the second region, that is, obtain a predetermined value of the radius of the first region, and corresponding two regions. The optical characteristic value or the electrical characteristic value does not have to be measured one by one in the manufacturing process.

如第一實施例圖3E之敘述中所提及，永久基板301上接合之半導體疊層塊可源自不同之半導體疊層，例如第一表面301P1上之半導體疊層塊與第二表面301P2上之半導體疊層塊可源自不同之基板之半導體疊層。而這樣的應用更可進一步應用以增進發光元件的演色性，亦即提高發光元件之CRI值，其應用如第5圖所顯示之本發明之第六實施例。如圖5A所示，永久基板501上分別接合了兩個半導體疊層塊501a及501b，其接合方法大致如同圖3第一實施例所示，但兩個半導體疊層塊501a及501b係分離自不同之基板之半導體疊層，例如半導體疊層塊501a係分離自一具有發光主波長約620nm至645nm的半導體疊層，而半導體疊層塊501b係分離自一具有發光主波長約595nm至620nm的半導體疊層；亦即兩個半導體疊層塊501a及501b係分離自不同之基板，且半導體疊層塊501a可發出紅色主波長之光，而半導體疊層塊501b可發出橘色主波長之光。如此，當此兩半導體疊層塊被接合至永久基板501時，可成為一發光元件500a，用以取代一般之暖白光源中之紅色或橘色之僅具單一半導體疊層之晶片；亦即，此發光元件500a可用於與藍色及YAG螢光粉組合，所形成之暖白光源因具有兩個半導體疊層塊501a及501b之不同主波長之光，較僅具單一半導體疊層之晶片所形成之暖白光源有較佳之演色性。 As mentioned in the description of FIG. 3E of the first embodiment, the permanent substrate 301 is bonded The semiconductor stacked blocks can be derived from different semiconductor stacks, for example, the semiconductor stacked blocks on the first surface 301P1 and the semiconductor stacked blocks on the second surface 301P2 can be derived from semiconductor stacks of different substrates. Such an application can be further applied to enhance the color rendering of the light-emitting element, that is, to increase the CRI value of the light-emitting element, and the sixth embodiment of the present invention as shown in Fig. 5 is applied. As shown in FIG. 5A, two semiconductor stacked blocks 501a and 501b are respectively bonded to the permanent substrate 501, and the bonding method is substantially the same as that of the first embodiment of FIG. 3, but the two semiconductor stacked blocks 501a and 501b are separated from each other. A semiconductor stack of different substrates, for example, a semiconductor stacked block 501a is separated from a semiconductor stack having an emission dominant wavelength of about 620 nm to 645 nm, and the semiconductor stacked block 501b is separated from a main wavelength having an illuminating wavelength of about 595 nm to 620 nm. The semiconductor stack; that is, the two semiconductor stacked blocks 501a and 501b are separated from different substrates, and the semiconductor stacked block 501a can emit light of a dominant red wavelength, and the semiconductor stacked block 501b can emit light of an orange dominant wavelength. . Thus, when the two semiconductor stacked blocks are bonded to the permanent substrate 501, they can be used as a light-emitting element 500a to replace the red or orange color of the conventional warm white light source with only a single semiconductor stack; The light-emitting element 500a can be used in combination with blue and YAG phosphor powder. The warm white light source is formed by a wafer having a single semiconductor stack with different main wavelengths of light of the two semiconductor stacked blocks 501a and 501b. The resulting warm white light source has better color rendering properties.

或者，可以如圖5B所示，永久基板501上除了如同上述分別接合了兩個半導體疊層塊502a及502b，更直接將用以提供藍色光源之半導體疊層塊502c亦接合於永久基板501上，發光元件500b因而直接形成一暖白光源，其中三個半導體疊層塊501a,501b及501c係分離自不同之基板之半導體疊層，例如半導體疊層塊501a係分離自一具有發光主波長約620nm至645nm的半導體疊層，半導體疊層塊501b係分離自一具有發光主波長約595nm至620nm的半導體疊層，而半導體疊層塊501c係分離自一具有發光主波長約440nm至460nm的半導體疊層；亦即三個半導體疊層塊501a,501b及501c係分離自不同之基板，且半導體疊層塊501a可發出紅色主波長之光，半導體疊層塊501b可發出橘色主波長之光，而半導體疊層塊501c可發出藍色主波長之光。 Alternatively, as shown in FIG. 5B, in addition to the two semiconductor stacked blocks 502a and 502b bonded to the permanent substrate 501 as described above, the semiconductor stacked block 502c for providing the blue light source is also directly bonded to the permanent substrate 501. The light-emitting element 500b thus directly forms a warm white light source, wherein the three semiconductor stacked blocks 501a, 501b and 501c are separated from the semiconductor stack of different substrates, for example, the semiconductor stacked block 501a is separated from a light-emitting device. a semiconductor stack having a dominant wavelength of about 620 nm to 645 nm, the semiconductor stacked block 501b is separated from a semiconductor stack having an illuminating dominant wavelength of about 595 nm to 620 nm, and the semiconductor stacked block 501c is separated from a main wavelength having an illuminating wavelength of about 440 nm. 460 nm semiconductor stack; that is, three semiconductor stacked blocks 501a, 501b and 501c are separated from different substrates, and the semiconductor stacked block 501a can emit red dominant wavelength light, and the semiconductor stacked block 501b can emit orange main The light of the wavelength, and the semiconductor stacked block 501c emits light of a dominant wavelength of blue.

或者更進一步地，可以如圖5C所示，永久基板501上除了如同上述分別接合了三個半導體疊層塊503a,503b及503c外，更多加接合一第四之半導體疊層塊503d。其中，四個半導體疊層塊501a,501b,501c及501d係分離自不同之基板之半導體疊層，半導體疊層塊501a,501b及501c的顏色及波長如同圖5B所述，而半導體疊層塊503d具有發光主波長約510nm至530nm，可發出綠色主波長之光。由於多加了此綠色主波長光的半導體疊層503d，發光元件500c所形成之暖白光源之CRI值較圖5B所示之發光元件500b更高，演色性更佳。 Alternatively, as shown in Fig. 5C, in addition to the above-described three semiconductor stacked blocks 503a, 503b and 503c, as described above, a fourth semiconductor stacked block 503d is bonded to the permanent substrate 501. The four semiconductor stacked blocks 501a, 501b, 501c, and 501d are semiconductor layers separated from different substrates, and the color and wavelength of the semiconductor stacked blocks 501a, 501b, and 501c are as described in FIG. 5B, and the semiconductor stacked blocks are used. 503d has a dominant wavelength of light of about 510 nm to 530 nm and emits light of a green dominant wavelength. Since the semiconductor multilayer 503d to which the green main wavelength light is added is added, the warm white light source formed by the light emitting element 500c has a higher CRI value than the light emitting element 500b shown in Fig. 5B, and the color rendering property is better.

上述實施例僅為例示性說明本發明之原理及其功效，而非用於限制本發明。任何本發明所屬技術領域中具有通常知識者均可在不違背本發明之技術原理及精神的情況下，對上述實施例進行修改及變化。因此本發明之權利保護範圍如後述之申請專利範圍所列。 The above embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is as set forth in the appended claims.

232,234，及23X‧‧‧半導體疊層塊 232,234, and 23X‧‧‧Semiconductor laminated blocks

301‧‧‧永久基板 301‧‧‧Permanent substrate

301P1‧‧‧第一表面 301P1‧‧‧ first surface

301P2‧‧‧第二表面 301P2‧‧‧ second surface

301P3‧‧‧第三表面 301P3‧‧‧ third surface

312B1,312B2，及312B3‧‧‧接合層 312B1, 312B2, and 312B3‧‧‧ joint layers

Claims

一種發光元件之製造方法，包括：提供一第一基板；提供一半導體疊層於該第一基板上，其中該半導體疊層包括一第一電性半導體層、一發光層位於該第一電性半導體層之上、以及一第二電性半導體層位於該發光層之上，且該半導體疊層係經圖形化而形成彼此分隔之複數個半導體疊層塊，其中該複數個半導體疊層塊包括一第一半導體疊層塊及一第二半導體疊層塊；實行一分離步驟將該第一半導體疊層塊與該第一基板分離，且該第一基板保留有該第二半導體疊層塊；提供一永久基板具有一第一表面、一第二表面、以及一第三半導體疊層塊於該第一表面上，其中該第一表面及該第二表面不在同一水平面；以及接合該第一半導體疊層塊及該第二半導體疊層塊之其中之一於該第二表面上，其中該分離步驟先於該接合該第一半導體疊層塊及該第二半導體疊層塊之其中之一於該第二表面上之步驟。 A method of manufacturing a light-emitting device, comprising: providing a first substrate; providing a semiconductor layer on the first substrate, wherein the semiconductor layer comprises a first electrical semiconductor layer, and a light-emitting layer is located at the first electrical Above the semiconductor layer, and a second electrical semiconductor layer is disposed on the light emitting layer, and the semiconductor layer is patterned to form a plurality of semiconductor stacked blocks separated from each other, wherein the plurality of semiconductor stacked blocks comprise a first semiconductor stacked block and a second semiconductor stacked block; performing a separating step to separate the first semiconductor stacked block from the first substrate, and the first substrate retains the second semiconductor stacked block; Providing a permanent substrate having a first surface, a second surface, and a third semiconductor stacked block on the first surface, wherein the first surface and the second surface are not in the same horizontal plane; and bonding the first semiconductor One of the stacked block and the second semiconductor stacked block on the second surface, wherein the separating step precedes bonding the first semiconductor stacked block and the second semiconductor stacked Wherein one of the second step on the surface.

如申請專利範圍第1項所述之發光元件之製造方法，其中被接合之該第一半導體疊層塊及該第二半導體疊層塊之其中之一與該第三半導體疊層塊之主波長差異大於或等於1nm、正向電壓(forward voltage)差異大於或等於2%、或發光強度差異大於或等於3%。 The method for manufacturing a light-emitting device according to claim 1, wherein one of the first semiconductor stacked block and the second semiconductor stacked block and the main wavelength of the third semiconductor stacked block are bonded The difference is greater than or equal to 1nm, forward voltage (forward Voltage) The difference is greater than or equal to 2%, or the difference in luminous intensity is greater than or equal to 3%.

如申請專利範圍第1項所述之發光元件之製造方法，其中該分離步驟包括：形成一第一犧牲層於在該第一半導體疊層塊上；提供一暫時基板；接合該暫時基板與該第一犧牲層；以及自該第一基板分離該第一半導體疊層塊。 The method for manufacturing a light-emitting device according to claim 1, wherein the separating step comprises: forming a first sacrificial layer on the first semiconductor stacked block; providing a temporary substrate; bonding the temporary substrate to the a first sacrificial layer; and separating the first semiconductor stacked block from the first substrate.

如申請專利範圍第1項所述之發光元件之製造方法，其中包括接合該第二半導體疊層塊於該永久基板，該接合步驟包括：對位接合該第一基板與該永久基板，以使該第二半導體疊層塊接合於該第二表面上；以及自該第一基板分離該第二半導體疊層塊。 The method of manufacturing a light-emitting device according to claim 1, comprising bonding the second semiconductor stacked block to the permanent substrate, the bonding step comprising: bonding the first substrate and the permanent substrate in alignment to enable The second semiconductor stacked block is bonded to the second surface; and the second semiconductor stacked block is separated from the first substrate.

如申請專利範圍第1項所述之發光元件之製造方法，其中包括接合該第二半導體疊層塊於該永久基板，該接合步驟包括：提供一暫時基板；接合該第二半導體疊層塊於該暫時基板；自該第一基板分離該第二半導體疊層塊；對位接合該暫時基板與該永久基板，以使該第二半導體疊層塊接合於該第二表面上；以及自該暫時基板分離該第二半導體疊層塊。 The method of manufacturing a light-emitting device according to claim 1, comprising bonding the second semiconductor stacked block to the permanent substrate, the bonding step comprising: providing a temporary substrate; bonding the second semiconductor stacked block to The temporary substrate; separating the second semiconductor stacked block from the first substrate; alignably bonding the temporary substrate and the permanent substrate to bond the second semiconductor stacked block to the second surface; The second semiconductor stacked block is separated from the temporary substrate.

如申請專利範圍第1項所述之發光元件之製造方法，其中該第三半導體疊層塊係經由一第一接合層接合於該第一表面上，被接合之該第一半導體疊層塊及該第二半導體疊層塊之其中之一係經由一第二接合層接合於該第二表面上，且該第一接合層與該第二接合層之厚度不同。 The method of manufacturing a light-emitting device according to claim 1, wherein the third semiconductor stacked block is bonded to the first surface via a first bonding layer, and the first semiconductor stacked block is bonded One of the second semiconductor stacked blocks is bonded to the second surface via a second bonding layer, and the first bonding layer and the second bonding layer are different in thickness.

如申請專利範圍第1項所述之發光元件之製造方法，其中該複數半導體疊層塊被區分成一第一區域及一第二區域，其中該第一區域大致為圓形，而該第二區域大致為環繞該第一區域之一環狀。 The method of manufacturing a light-emitting device according to claim 1, wherein the plurality of semiconductor stacked blocks are divided into a first region and a second region, wherein the first region is substantially circular, and the second region It is substantially annular around one of the first regions.

如申請專利範圍第7項所述之發光元件之製造方法，其中被接合之該第一半導體疊層塊及該第二半導體疊層塊之其中之一係位於該第一區域，該第三半導體疊層塊係分離自該第二區域而接合於該永久基板上。 The method of manufacturing a light-emitting device according to claim 7, wherein one of the first semiconductor stacked block and the second semiconductor stacked block to be bonded is located in the first region, the third semiconductor The laminated block is separated from the second region and bonded to the permanent substrate.

如申請專利範圍第1項所述之發光元件之製造方法，更包括形成一金屬線電性連接被接合之該第一半導體疊層塊及該第二半導體疊層塊之其中之一與該第三半導體疊層塊。 The method for manufacturing a light-emitting device according to claim 1, further comprising forming one of the first semiconductor stacked block and the second semiconductor stacked block to which a metal wire is electrically connected and bonded to the first Three semiconductor stacked blocks.

如申請專利範圍第1項所述之發光元件之製造方法，其中該第三半導體疊層塊係分離自一第三基板而接合於該永久基板上。 The method of manufacturing a light-emitting device according to claim 1, wherein the third semiconductor stacked block is bonded to the permanent substrate by being separated from a third substrate.

如申請專利範圍第1項所述之發光元件之製造方法，更包括：依據各該複數之半導體疊層塊之一光學特徵值或一電性特徵值將該複數之半導體疊層塊區分為一般規格區，低規格區，及高規格區，且位於該高規格區之半導體疊層塊之該光學特徵值或該電性特徵值大於位於該一般規格區之半導體疊層塊之該光學特徵值或該電性特徵值，而位於該一般規格區之半導體疊層塊之該光學特徵值或該電性特徵值大於位於該低規格區之半導體疊層塊之該光學特徵值或該電性特徵值。 The method for manufacturing a light-emitting device according to claim 1, further comprising: And dividing the plurality of semiconductor stacked blocks into a general specification area, a low specification area, and a high specification area according to an optical characteristic value or an electrical characteristic value of each of the plurality of semiconductor stacked blocks, and located in the high specification area The optical characteristic value or the electrical characteristic value of the semiconductor stacked block is greater than the optical characteristic value or the electrical characteristic value of the semiconductor stacked block located in the general specification area, and the semiconductor stacked block located in the general specification area The optical characteristic value or the electrical characteristic value is greater than the optical characteristic value or the electrical characteristic value of the semiconductor stacked block located in the low specification region.

如申請專利範圍第11項所述之發光元件之製造方法，其中該第三半導體疊層塊係分離自該第一基板，且被接合之該第一半導體疊層塊及該第二半導體疊層塊之其中之一係選自於該低規格區與高規格區中之一，而該第三半導體疊層塊係選自於另一。 The method of manufacturing a light-emitting device according to claim 11, wherein the third semiconductor stacked block is separated from the first substrate, and the first semiconductor stacked block and the second semiconductor stacked are bonded One of the blocks is selected from one of the low specification region and the high specification region, and the third semiconductor stacked block is selected from the other.

如申請專利範圍第11項所述之發光元件之製造方法，其中該第三半導體疊層塊係分離自該第一基板，且被接合之該第一半導體疊層塊及該第二半導體疊層塊之其中之一與該第三半導體疊層塊均選自於該一般規格區。 The method of manufacturing a light-emitting device according to claim 11, wherein the third semiconductor stacked block is separated from the first substrate, and the first semiconductor stacked block and the second semiconductor stacked are bonded One of the blocks and the third semiconductor stacked block are each selected from the general specification area.