TWI581407B - Method for fabricating memory - Google Patents
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Description
本發明是有關於一種半導體元件的製造方法，且特別是有關於一種記憶體的製造方法。The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a memory device.
非揮發性儲存元件（non-volatile memory）由於可進行多次資料的存入、讀取、抹除等操作，且具有當電源供應中斷時，所儲存的資料不會消失、資料存取時間短、低消耗功率等優點，所以已成為個人電腦和電子設備所廣泛採用的一種記憶體。Non-volatile memory (non-volatile memory) can store, read, erase, etc. multiple data, and when the power supply is interrupted, the stored data will not disappear, and the data access time is short. It has the advantages of low power consumption and so on, so it has become a kind of memory widely used in personal computers and electronic devices.
典型的非揮發性記憶體元件一般是被設計成具有堆疊閘極(stacked-gate)結構，其中包括以摻雜多晶矽製作的浮置閘極(floating gate)與控制閘極(control gate)。浮置閘極位於控制閘極和基底之間且處於浮置狀態，而控制閘極則與字元線(word line)相接。此外，非揮發性記憶體元件還包括穿隧介電層(tunneling dielectric layer)和閘間介電層(inter-gate dielectric layer)分別位於基底和浮置閘極之間以及浮置閘極和控制閘極之間。A typical non-volatile memory component is typically designed to have a stacked-gate structure including a floating gate and a control gate fabricated with doped polysilicon. The floating gate is located between the control gate and the substrate and is in a floating state, and the control gate is connected to the word line. In addition, the non-volatile memory component further includes a tunneling dielectric layer and an inter-gate dielectric layer between the substrate and the floating gate, and a floating gate and control. Between the gates.
在目前提高記憶體元件積集度的趨勢下，會依據設計規則縮小元件的尺寸。在此情況下，為了防止浮置閘極間的耦合干擾升高，進而提高閘極耦合率，會藉由在堆疊閘極結構之間形成氣隙來解決上述問題。In the current trend of increasing the memory component accumulation, the size of the component is reduced according to the design rules. In this case, in order to prevent the coupling interference between the floating gates from increasing and thereby increasing the gate coupling ratio, the above problem is solved by forming an air gap between the stacked gate structures.
在目前形成的氣隙製造方法中，通常會利用在電荷儲存結構的側壁形成介電襯層，以保護電荷儲存結構中的穿遂介電層，而可避免穿遂介電層在形成氣隙的過程受到傷害。In the currently formed air gap manufacturing method, a dielectric liner is generally formed on the sidewall of the charge storage structure to protect the through dielectric layer in the charge storage structure, and the dielectric layer is prevented from forming an air gap. The process is hurt.
然而，當記憶體元件的特徵尺寸持續縮小時，介電襯層的厚度也會相對地受到限制。當介電襯層的厚度太厚時，無法順利地在堆疊閘極結構之間的溝渠中形成介電襯層。另一方面，當介電襯層的厚度太薄時，則介電襯層對於穿遂介電層的保護能力變差，而會使得穿遂介電層在形成氣隙的過程受到傷害，進而使得記憶體的良率及可靠度降低。However, as the feature size of the memory element continues to shrink, the thickness of the dielectric liner is also relatively limited. When the thickness of the dielectric liner is too thick, a dielectric liner cannot be formed smoothly in the trench between the stacked gate structures. On the other hand, when the thickness of the dielectric liner is too thin, the dielectric liner has poor protection against the dielectric layer, and the dielectric layer is damaged during the process of forming the air gap. Reduces the yield and reliability of the memory.
本發明提供一種記憶體的製造方法，其可有效提升記憶體的良率及可靠度。The invention provides a method for manufacturing a memory, which can effectively improve the yield and reliability of the memory.
本發明提出一種記憶體的製造方法，包括以下步驟。在基底上形成多個電荷儲存結構，其中相鄰兩個電荷儲存結構之間具有第一溝渠，且第一溝渠延伸至基底中。在第一溝渠的表面形成介電襯層。在介電襯層上形成氮化物層。在第一溝渠中填入第一介電層。在電荷儲存結構與第一介電層上形成第二介電層。在第二介電層上形成導體層。移除第一介電層，而在相鄰兩個電荷儲存結構之間的第二介電層下方形成第一氣隙。The present invention provides a method of manufacturing a memory, comprising the following steps. A plurality of charge storage structures are formed on the substrate, wherein a first trench is provided between adjacent two charge storage structures, and the first trench extends into the substrate. A dielectric liner is formed on the surface of the first trench. A nitride layer is formed on the dielectric liner. A first dielectric layer is filled in the first trench. A second dielectric layer is formed on the charge storage structure and the first dielectric layer. A conductor layer is formed on the second dielectric layer. The first dielectric layer is removed and a first air gap is formed beneath the second dielectric layer between adjacent two charge storage structures.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，電荷儲存結構包括電荷儲存層與穿隧介電層。電荷儲存層設置在基底上。穿隧介電層設置於電荷儲存層與基底之間。According to an embodiment of the invention, in the method of fabricating the memory, the charge storage structure includes a charge storage layer and a tunnel dielectric layer. A charge storage layer is disposed on the substrate. The tunneling dielectric layer is disposed between the charge storage layer and the substrate.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，在形成該氮化物層之前，更包括下列步驟。在第一溝渠中形成保護層，且保護層的頂面高於穿隧介電層的頂面。以保護層為罩幕，移除部分介電襯層，以暴露出部分電荷儲存層。在移除部分介電襯層之後，移除保護層。According to an embodiment of the invention, in the method of fabricating the memory, the following steps are further included before the formation of the nitride layer. A protective layer is formed in the first trench, and a top surface of the protective layer is higher than a top surface of the tunneling dielectric layer. A protective layer is used as a mask to remove a portion of the dielectric liner to expose a portion of the charge storage layer. After removing a portion of the dielectric liner, the protective layer is removed.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，第一介電層的頂面例如是低於電荷儲存層的頂面。According to an embodiment of the invention, in the method of fabricating the memory, the top surface of the first dielectric layer is, for example, lower than the top surface of the charge storage layer.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，電荷儲存層例如是浮置閘極。According to an embodiment of the invention, in the method of fabricating the memory, the charge storage layer is, for example, a floating gate.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，氮化物層的形成方法例如是對介電襯層進行氮化製程。According to an embodiment of the present invention, in the method of fabricating the memory, the method of forming the nitride layer is, for example, a nitridation process on the dielectric liner.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，氮化製程例如是電漿氮化製程、氣體氮化製程、離子氮化製程或真空氮化製程。According to an embodiment of the invention, in the method of fabricating the memory, the nitridation process is, for example, a plasma nitridation process, a gas nitridation process, an ion nitridation process, or a vacuum nitridation process.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，更包括對導體層進行圖案化製程，而形成多條字元線，其中字元線的延伸方向例如是與第一氣隙的延伸方向相交。According to an embodiment of the invention, in the method for manufacturing a memory device, the method further includes: performing a patterning process on the conductor layer to form a plurality of word lines, wherein the extending direction of the word lines is, for example, the first The extension directions of the air gaps intersect.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，圖案化製程更包括移除位於相鄰兩條字元線之間的第二介電層與至少部分電荷儲存結構，而在相鄰兩條字元線之間形成第二溝渠。According to an embodiment of the present invention, the patterning process further includes removing a second dielectric layer and at least a portion of the charge storage structure between adjacent two word lines. A second trench is formed between adjacent two word lines.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，更包括在字元線上形成覆蓋層，且覆蓋層在第二溝渠的頂部進行封口，而形成第二氣隙。According to an embodiment of the invention, in the method of manufacturing a memory device, the method further includes forming a cap layer on the word line, and the cap layer is sealed on the top of the second trench to form a second air gap.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，第二氣隙的延伸方向例如是與第一氣隙的延伸方向相交。According to an embodiment of the invention, in the method of manufacturing the memory device, the extending direction of the second air gap is, for example, intersecting the extending direction of the first air gap.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，在形成第一氣隙之後，更包括對氮化物層進行氧化製程，而將氮化物層轉變成氧化物層。According to an embodiment of the invention, in the method of fabricating the memory, after forming the first air gap, the method further includes: performing an oxidation process on the nitride layer to convert the nitride layer into an oxide layer.
依照本發明的一實施例所述，在上述之記憶體的製造方法中，第一氣隙可延伸至基底中。According to an embodiment of the invention, in the method of fabricating the memory, the first air gap may extend into the substrate.
基於上述，在本發明所提出的記憶體的製造方法中，由於會在介電襯層上形成氮化物層，且氮化物層在形成氣隙的過程中可用以保護介電襯層，而可利用氮化物層與介電襯層來防止穿遂介電層在形成氣隙的過程中受到傷害。因此，即使記憶體元件的特徵尺寸不斷縮小，仍可有效地提升記憶體的良率及可靠度，且可良好地控制氣隙的深寬比。Based on the above, in the method of fabricating the memory of the present invention, a nitride layer is formed on the dielectric liner, and the nitride layer can be used to protect the dielectric liner during the formation of the air gap. The nitride layer and the dielectric liner are utilized to prevent the through-silicon dielectric layer from being damaged during the formation of the air gap. Therefore, even if the feature size of the memory element is continuously reduced, the yield and reliability of the memory can be effectively improved, and the aspect ratio of the air gap can be well controlled.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A至圖1D為本發明一實施例的記憶體的製造流程剖面圖。圖1E至圖1H為接續圖1D的記憶體的製造流程立體圖。 1A to 1D are cross-sectional views showing a manufacturing process of a memory according to an embodiment of the present invention. 1E to 1H are perspective views showing a manufacturing process of the memory of FIG. 1D.
請參照圖1A，在基底100上形成多個電荷儲存結構102，其中相鄰兩個電荷儲存結構102之間具有溝渠104，且溝渠104延伸至基底100中。基底100例如是半導體基底，如矽基底等。 Referring to FIG. 1A, a plurality of charge storage structures 102 are formed on a substrate 100, wherein trenches 104 are formed between adjacent two charge storage structures 102, and the trenches 104 extend into the substrate 100. The substrate 100 is, for example, a semiconductor substrate such as a germanium substrate or the like.
電荷儲存結構102可包括電荷儲存層102a與穿遂介電層102b，且更可包括圖案化硬罩幕層102c。相鄰兩個電荷儲存結構102之間具有溝渠104，且溝渠104延伸至基底100中。電荷儲存層102a設置在基底100上。穿遂介電層102b設置於電荷儲存層102a與基底100之間。圖案化硬罩幕層102c設置於電荷儲存層102a上。電荷儲存層102a例如是浮置閘極。電荷儲存層102a的材料例如是摻雜多晶矽。穿遂介電層102b的材料例如是氧化矽。圖案化硬罩幕層102c的材料例如是氮化矽。 The charge storage structure 102 can include a charge storage layer 102a and a passthrough dielectric layer 102b, and can further include a patterned hard mask layer 102c. A trench 104 is defined between adjacent two charge storage structures 102, and the trench 104 extends into the substrate 100. The charge storage layer 102a is disposed on the substrate 100. The through dielectric layer 102b is disposed between the charge storage layer 102a and the substrate 100. The patterned hard mask layer 102c is disposed on the charge storage layer 102a. The charge storage layer 102a is, for example, a floating gate. The material of the charge storage layer 102a is, for example, doped polysilicon. The material that penetrates the dielectric layer 102b is, for example, yttrium oxide. The material of the patterned hard mask layer 102c is, for example, tantalum nitride.
舉例來說，電荷儲存結構102的形成方法例如是先在基底100上形成穿遂介電材料層(未繪示)、電荷儲存材料層(未繪示)與硬罩幕層(未繪示)，再對穿遂介電材料層、電荷儲存材料層與硬 罩幕層進行圖案化製程。穿遂介電材料層的形成方法例如是熱氧化法。電荷儲存材料層與硬罩幕層的形成方法例如是化學氣相沉積法。 For example, the method for forming the charge storage structure 102 is to form a layer of a dielectric material (not shown), a layer of charge storage material (not shown), and a hard mask layer (not shown) on the substrate 100. And then through the layer of dielectric material, the layer of charge storage material and hard The mask layer is patterned. The method of forming the dielectric material layer is, for example, a thermal oxidation method. The method of forming the charge storage material layer and the hard mask layer is, for example, a chemical vapor deposition method.
在溝渠104的表面形成介電襯層106。介電襯層106的材料例如是氧化矽。介電襯層106的形成方法例如是熱氧化法。在採用熱氧化法形成介電襯層106時，介電襯層106在高溫下經密實化(densify)而使得其結構緻密。 A dielectric liner 106 is formed on the surface of the trench 104. The material of the dielectric liner 106 is, for example, ruthenium oxide. The method of forming the dielectric liner 106 is, for example, a thermal oxidation method. When the dielectric liner 106 is formed by thermal oxidation, the dielectric liner 106 is densified at a high temperature to make its structure dense.
可選擇性地在溝渠104中形成保護層108，且保護層108的頂面高於穿隧介電層102b的頂面。保護層108可用以在後續製程中調整介電襯層106的高度。保護層108的材料例如是光阻材料，如有機聚合物等。保護層108的形成方法例如是先以旋塗法形成填滿溝渠104的保護材料層(未繪示)，再對保護材料層進行回蝕刻製程。 A protective layer 108 can be selectively formed in the trench 104, and the top surface of the protective layer 108 is higher than the top surface of the tunnel dielectric layer 102b. The protective layer 108 can be used to adjust the height of the dielectric liner 106 in subsequent processes. The material of the protective layer 108 is, for example, a photoresist material such as an organic polymer or the like. For example, the protective layer 108 is formed by a spin coating method to form a protective material layer (not shown) that fills the trench 104, and then the protective material layer is subjected to an etch back process.
請參照圖1B，可以保護層108為罩幕，移除部分介電襯層106，以暴露出部分電荷儲存層102a。部分介電襯層106的移除方法例如是乾蝕刻法。 Referring to FIG. 1B, the protective layer 108 can be a mask, and a portion of the dielectric liner 106 is removed to expose a portion of the charge storage layer 102a. A method of removing a portion of the dielectric liner 106 is, for example, a dry etching method.
請參照圖1C，在移除部分介電襯層106之後，可移除保護層108。保護層108的移除方法例如是乾蝕刻法。 Referring to FIG. 1C, after removing a portion of the dielectric liner 106, the protective layer 108 can be removed. The removal method of the protective layer 108 is, for example, a dry etching method.
在介電襯層106上形成氮化物層110。由於氮化物層110在後續形成氣隙的製程中具有良好的耐蝕刻特性，所以可在後續形成氣隙的製程中保護介電襯層106，而可利用氮化物層110與介電襯層106來防止電荷儲存層102a下方的穿隧介電層102b在形成氣隙的過程中受到傷害。氮化物層110的材料例如是氮化矽或氧氮化矽。氮化物層110的形成方法例如是對介電襯層106進行氮化製程。氮化製程例如是電漿氮化製程、氣體氮化製程、離子氮化製程或真空氮化製程。A nitride layer 110 is formed over the dielectric liner 106. Since the nitride layer 110 has good etching resistance in the subsequent process of forming an air gap, the dielectric liner 106 can be protected in the subsequent process of forming an air gap, and the nitride layer 110 and the dielectric liner 106 can be utilized. The tunneling dielectric layer 102b under the charge storage layer 102a is prevented from being damaged during the formation of the air gap. The material of the nitride layer 110 is, for example, tantalum nitride or hafnium oxynitride. The method of forming the nitride layer 110 is, for example, a nitridation process of the dielectric liner 106. The nitridation process is, for example, a plasma nitridation process, a gas nitridation process, an ion nitridation process, or a vacuum nitridation process.
在溝渠104中填入介電層112。介電層112的頂面可低於電荷儲存層102a的頂面。介電層112的材料例如是氧化矽。介電層112的形成方法例如是先以化學氣相沉積法形成填滿溝渠104的介電材料層(未繪示)，再對介電材料層進行化學機械研磨製程與回蝕刻製程。在另一實施例中，介電層112的頂面與電荷儲存層102a的頂面亦可具有同樣高度。A dielectric layer 112 is filled in the trench 104. The top surface of the dielectric layer 112 may be lower than the top surface of the charge storage layer 102a. The material of the dielectric layer 112 is, for example, ruthenium oxide. The dielectric layer 112 is formed by, for example, forming a dielectric material layer (not shown) filled with the trench 104 by chemical vapor deposition, and then performing a chemical mechanical polishing process and an etch back process on the dielectric material layer. In another embodiment, the top surface of the dielectric layer 112 and the top surface of the charge storage layer 102a may also have the same height.
可移除圖案化硬罩幕層102c。圖案化硬罩幕層102c的移除方法例如是乾式蝕刻法或濕式蝕刻法。The patterned hard mask layer 102c can be removed. The method of removing the patterned hard mask layer 102c is, for example, a dry etching method or a wet etching method.
請參照圖1D，在電荷儲存結構102與介電層112上形成介電層114，其中介電層114可作為多晶矽層間介電層(inter-poly dielectric，IPD)使用。介電層114例如是氧化矽/氮化矽/氧化矽(oxide-nitride-oxide，ONO)複合層或氧化矽層。ONO複合層可為三層或是更多層。介電層114的形成方法例如是化學氣相沉積法。Referring to FIG. 1D, a dielectric layer 114 is formed on the charge storage structure 102 and the dielectric layer 112. The dielectric layer 114 can be used as an inter-poly dielectric (IPD). The dielectric layer 114 is, for example, a cerium oxide/nitride-oxide (ONO) composite layer or a ruthenium oxide layer. The ONO composite layer can be three or more layers. The method of forming the dielectric layer 114 is, for example, a chemical vapor deposition method.
在介電層114上形成導體層116，可用以作為控制閘極。導體層116可填入電荷儲存結構102之間的溝渠104中，以增加控制導體層116與電荷儲存層102a之間的耦合面積，進而提升閘極耦合比(gate coupling ratio，GCR)。由此可知，所屬技術領域具有通常知識者可藉由控制介電襯層106與介電層112的高度，來調整導體層116與電荷儲存層102a之間的耦合面積。導體層116的材料例如是摻雜多晶矽。導體層116的形成方法例如是化學氣相沉積法。A conductor layer 116 is formed over the dielectric layer 114 and can be used as a control gate. The conductor layer 116 can be filled in the trench 104 between the charge storage structures 102 to increase the coupling area between the control conductor layer 116 and the charge storage layer 102a, thereby increasing the gate coupling ratio (GCR). It can be seen that those skilled in the art can adjust the coupling area between the conductor layer 116 and the charge storage layer 102a by controlling the height of the dielectric liner 106 and the dielectric layer 112. The material of the conductor layer 116 is, for example, doped polysilicon. The method of forming the conductor layer 116 is, for example, a chemical vapor deposition method.
請參照圖1E，可在導體層116上形成圖案化硬罩幕層118。圖案化硬罩幕層118可為單層結構或多層結構。圖案化硬罩幕層118的材料例如是氮化矽、氧化矽、氮氧化矽或其組合。圖案化硬罩幕層118的形成方法例如是先形成硬罩幕層(未繪示)，再對硬罩幕層進行圖案化製程。Referring to FIG. 1E, a patterned hard mask layer 118 can be formed on the conductor layer 116. The patterned hard mask layer 118 can be a single layer structure or a multilayer structure. The material of the patterned hard mask layer 118 is, for example, tantalum nitride, hafnium oxide, hafnium oxynitride or a combination thereof. The method of forming the patterned hard mask layer 118 is, for example, first forming a hard mask layer (not shown), and then patterning the hard mask layer.
可藉由圖案化硬罩幕層118作為罩幕，對導體層116進行圖案化製程，而形成多條字元線WL。此外，在上述圖案化製程更包括移除位於相鄰兩條字元線WL之間的介電層114與至少部分電荷儲存結構102，且更可移除位於相鄰兩條字元線WL之間的部分介電襯層106、部分氮化物層110與部分介電層112，而在相鄰兩條字元線之間形成溝渠120。The conductor layer 116 can be patterned by patterning the hard mask layer 118 as a mask to form a plurality of word lines WL. In addition, the above-described patterning process further includes removing the dielectric layer 114 and the at least part of the charge storage structure 102 between the adjacent two word lines WL, and further removing the adjacent two word lines WL. A portion of the dielectric liner 106, a portion of the nitride layer 110 and a portion of the dielectric layer 112 are formed, and a trench 120 is formed between adjacent two word lines.
請參照圖1F，移除填入溝渠104中的介電層112，而在相鄰兩個電荷儲存結構102之間的介電層114下方形成氣隙AG1。氣隙AG1可延伸至基底100中。字元線WL的延伸方向例如是與氣隙AG1的延伸方向相交。移除介電層112的方法例如是濕蝕刻法。在移除介電層112的蝕刻製程中，介電層112的蝕刻速率例如是大於介電襯層106、氮化物層110、介電層114與穿隧介電層102b的蝕刻速率，因此在移除介電層112時，不會過度傷害到上述膜層。此外，在移除介電層112的過程中，由於氮化物層110具有良好的耐蝕刻特性，因此氮化物層110可用以保護介電襯層106，而可利用氮化物層110與介電襯層106來防止電荷儲存層102a下方的穿隧介電層102b在形成氣隙AG1的過程中受到傷害，因此可有效提升記憶體的良率及可靠度。Referring to FIG. 1F, the dielectric layer 112 filled in the trench 104 is removed, and an air gap AG1 is formed under the dielectric layer 114 between the adjacent two charge storage structures 102. The air gap AG1 can extend into the substrate 100. The extending direction of the word line WL is, for example, intersecting the extending direction of the air gap AG1. The method of removing the dielectric layer 112 is, for example, a wet etching method. In the etching process of removing the dielectric layer 112, the etching rate of the dielectric layer 112 is, for example, greater than the etching rate of the dielectric liner 106, the nitride layer 110, the dielectric layer 114, and the tunneling dielectric layer 102b, and thus When the dielectric layer 112 is removed, the above film layer is not excessively damaged. In addition, in the process of removing the dielectric layer 112, since the nitride layer 110 has good etching resistance, the nitride layer 110 can be used to protect the dielectric liner 106, and the nitride layer 110 and the dielectric liner can be utilized. The layer 106 prevents the tunneling dielectric layer 102b under the charge storage layer 102a from being damaged during the formation of the air gap AG1, thereby effectively improving the yield and reliability of the memory.
請參照圖1G，在形成氣隙AG1之後，可對氮化物層110進行氧化製程，而將氮化物層110層轉變成氧化物層122，而能夠有效地降低漏電流，進而使得記憶體具有良好的可靠度。此外，進行氧化製程的同時，會在圖案化硬罩幕層118、字元線WL與電荷儲存結構102的側壁上形成氧化物層124。氧化物層122、124的材料例如是氧化矽。氧化製程例如是電漿氧化製程或熱氧化製程。Referring to FIG. 1G, after the air gap AG1 is formed, the nitride layer 110 can be subjected to an oxidation process, and the nitride layer 110 layer can be converted into the oxide layer 122, thereby effectively reducing leakage current, thereby making the memory good. Reliability. In addition, an oxide layer 124 is formed on the sidewalls of the patterned hard mask layer 118, the word line WL, and the charge storage structure 102 while the oxidation process is being performed. The material of the oxide layers 122, 124 is, for example, ruthenium oxide. The oxidation process is, for example, a plasma oxidation process or a thermal oxidation process.
請參照圖1H，可在字元線WL上形成覆蓋層126，且覆蓋層126在溝渠120的頂部進行封口，而形成氣隙AG2。氣隙AG2的延伸方向例如是與氣隙AG1的延伸方向相交。此外，覆蓋層126亦可能會形成在氣隙AG1中，而使得氣隙AG1的尺寸略為縮小。覆蓋層126的材料可選擇階梯性覆蓋能力較低的材料，而可在溝渠120的頂部進行封口，以形成氣隙AG2。覆蓋層126的材料例如是氧化矽。覆蓋層126的形成方法例如是化學氣相沉積法。Referring to FIG. 1H, a capping layer 126 may be formed on the word line WL, and the capping layer 126 is sealed at the top of the trench 120 to form an air gap AG2. The extending direction of the air gap AG2 is, for example, intersecting the extending direction of the air gap AG1. In addition, the cover layer 126 may also be formed in the air gap AG1 such that the size of the air gap AG1 is slightly reduced. The material of the cover layer 126 may be selected from a material having a lower step coverage capability, and may be sealed at the top of the trench 120 to form an air gap AG2. The material of the cover layer 126 is, for example, ruthenium oxide. The formation method of the cover layer 126 is, for example, a chemical vapor deposition method.
基於上述實施例可知，由於會在介電襯層106上形成氮化物層110，且氮化物層110在形成氣隙AG1的過程中可用以保護介電襯層106，而可藉由氮化物層110與介電襯層106來防止穿遂介電層102b在形成氣隙AG1的過程受到傷害。因此，即使記憶體元件的特徵尺寸不斷縮小，仍可有效地提升記憶體的良率及可靠度，且可良好地控制氣隙AG1的深寬比。Based on the above embodiments, since the nitride layer 110 is formed on the dielectric liner 106, and the nitride layer 110 can be used to protect the dielectric liner 106 during the formation of the air gap AG1, the nitride layer can be protected by the nitride layer. 110 and dielectric liner 106 prevent the dielectric layer 102b from being damaged during the process of forming the air gap AG1. Therefore, even if the feature size of the memory element is continuously reduced, the yield and reliability of the memory can be effectively improved, and the aspect ratio of the air gap AG1 can be well controlled.
綜上所述，在上述實施例的記憶體的製造方法中，由於在形成氣隙的過程中，穿遂介電層可受到氮化物層與介電襯層的保護而具有較佳的品質，因此可有效地提升記憶體的良率及可靠度，且可良好地控制氣隙的深寬比。In summary, in the method of fabricating the memory of the above embodiment, since the through dielectric layer can be protected by the nitride layer and the dielectric liner in the process of forming the air gap, the quality is better. Therefore, the yield and reliability of the memory can be effectively improved, and the aspect ratio of the air gap can be well controlled.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧基底100‧‧‧Base
102‧‧‧電荷儲存結構102‧‧‧Charge storage structure
102a‧‧‧電荷儲存層102a‧‧‧Charge storage layer
102b‧‧‧穿遂介電層102b‧‧‧through dielectric layer
102c、118‧‧‧圖案化硬罩幕層102c, 118‧‧‧ patterned hard mask layer
104、120‧‧‧溝渠104, 120‧‧‧ Ditch
106‧‧‧介電襯層106‧‧‧Dielectric lining
108‧‧‧保護層108‧‧‧Protective layer
110‧‧‧氮化物層110‧‧‧ nitride layer
112、114‧‧‧介電層 112, 114‧‧‧ dielectric layer
116‧‧‧導體層 116‧‧‧Conductor layer
122、124‧‧‧氧化物層 122, 124‧‧‧ oxide layer
126‧‧‧覆蓋層 126‧‧‧ Coverage
AG1、AG2‧‧‧氣隙 AG1, AG2‧‧‧ air gap
WL‧‧‧字元線 WL‧‧‧ character line
圖1A至圖1D為本發明一實施例的記憶體的製造流程剖面圖。 1A to 1D are cross-sectional views showing a manufacturing process of a memory according to an embodiment of the present invention.
圖1E至圖1H為接續圖1D的記憶體的製造流程立體圖。 1E to 1H are perspective views showing a manufacturing process of the memory of FIG. 1D.
100‧‧‧基底 100‧‧‧Base
102‧‧‧電荷儲存結構 102‧‧‧Charge storage structure
102a‧‧‧電荷儲存層 102a‧‧‧Charge storage layer
102b‧‧‧穿遂介電層 102b‧‧‧through dielectric layer
106‧‧‧介電襯層 106‧‧‧Dielectric lining
110‧‧‧氮化物層 110‧‧‧ nitride layer
114‧‧‧介電層 114‧‧‧Dielectric layer
118‧‧‧圖案化硬罩幕層 118‧‧‧ patterned hard mask layer
120‧‧‧溝渠 120‧‧‧ditch
AG1‧‧‧氣隙 AG1‧‧‧ air gap
WL‧‧‧字元線 WL‧‧‧ character line
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