TWI574746B - Pretreatment methods and memory media - Google Patents

Pretreatment methods and memory media Download PDF

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Publication number
TWI574746B
TWI574746B TW103140060A TW103140060A TWI574746B TW I574746 B TWI574746 B TW I574746B TW 103140060 A TW103140060 A TW 103140060A TW 103140060 A TW103140060 A TW 103140060A TW I574746 B TWI574746 B TW I574746B
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Taiwan
Prior art keywords
bonding layer
substrate
treatment
coupling agent
concave portion
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TW103140060A
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English (en)
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TW201532682A (zh
Inventor
Takashi Tanaka
Yuichiro Inatomi
Kazutoshi IWAI
Mitsuaki Iwashita
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Tokyo Electron Ltd
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    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
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    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
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    • C23C18/18Pretreatment of the material to be coated
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    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
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    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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Description

鍍層之前處理方法及記憶媒體
本發明係有關一種對基板在利用電鍍把被形成的凹部埋入前進行下底處理之前處理之方法。
近年,LSI等半導體裝置,必須對應於實裝面積的省空間化或處理速度的改善等課題,而被要求更進一層高密度化。實現高密度化之技術之一例,習知為藉由層積複數配線基板來製作三次元LSI等多層基板之多層配線技術。
多層配線技術,一般上,為了確保配線基板間的導通,會在配線基板設置貫通配線基板同時被埋入銅等導電性材料的貫通導孔(TSV(Through Silicon Via))。供製作被埋入導電性材料的TSV用之技術之一例,習知為無電解電鍍法。
在利用無電解電鍍將金屬膜成膜之場合,其課題在於下底與金屬膜之緊貼性提升。因此,從以前起,利用矽烷耦合劑或者鈦耦合劑等之耦合劑在下底之上形成自己組織化單分子膜(SAM),介著自己組織化單分子膜 使鈀粒子等觸媒金屬結合在下底(參照例如專利文獻1)。
一般而言,鈦耦合劑是以TiOx為主成分,因而,金屬觸媒粒子的吸附性能佳。因此,能夠藉由採用鈦耦合劑,使金屬膜的緊貼性跟採用矽烷耦合劑之場合相比是提升的。但是,鈦耦合劑是不能用真空蒸鍍,因而,要對TSV等高深寬比的深孔施以處理或是非常困難,或是需要非常長時間。
另一方面,矽烷耦合劑是可以利用真空蒸鍍處理使之附著在基板,因而,覆蓋度佳、在TSV等高深寬比的深的凹部內側表面也可以附著。但是,緊貼性較低,因而,特別是凹部外側的膜,由於銅電鍍處理中發生的膜應力或CMP(化學機械研磨)造成剝離之疑慮是有的。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2002-302773號公報
本發明在於提供一種即使通孔等凹部為高深寬比,也可以在該凹部內側表面及凹部外側的基板表面形成具有足夠緊貼性的、均一的鍍層之前處理方法。
本發明係提供一種鍍層之前處理方法,具備:準備具有凹部的基板之步驟;使用第1耦合劑,在前述基板的至少凹部內側的表面形成第1結合層之第1結合層形成步驟;與在前述第1結合層形成步驟之後,使用第2耦合劑,在前述基板的至少凹部外側的表面形成第2結合層之第2結合層形成步驟。
本發明進而提供一種收容有供鍍層處理系統執行上述鍍層之前處理方法用的電腦程式之記憶媒體。
根據本發明,例如,能夠在第1結合層形成步驟藉由採用覆蓋率佳的第1耦合劑在凹部內側的表面形成均一的結合層;能夠在第2結合層形成步驟藉由採用緊貼性佳的第2耦合劑在凹部外側的基板的表面形成被強固地固定之結合層。亦即,可以藉由因應場所之不同而被要求不同的性質來分別使用不同的耦合劑,而在基板全體形成具有足夠的緊貼性、且均一的鍍層。而且,耦合劑的分別使用係可以不必使用遮蔽等特別的手段來進行。
2‧‧‧基板
2a‧‧‧凹部
21‧‧‧結合層
21、21a‧‧‧第1結合層(矽烷系結合層)
21、21b‧‧‧第2結合層(鈦系結合層)
22‧‧‧含觸媒粒子膜
23‧‧‧阻擋層
24‧‧‧銅晶種層
25‧‧‧銅電鍍層
圖1係供說明矽烷耦合處理及鈦耦合處理用之、凹部 附近之基板剖面圖。
圖2係供說明TSV形成步驟用之凹部附近之基板剖面圖。
圖3係概略地圖示在鍍層之前處理所使用之裝置構成。
圖4係顯示供實施包含鍍層之前處理之一連串處理用之鍍層處理系統之一例之概略平面圖。
以下,參照圖面,說明供在基板被形成的凹部(成為貫通導孔(TSV)的凹部)埋入銅(Cu)用之一連串步驟。這一連串步驟係包含關於發明之一實施型態之鍍層前處理方法之各步驟。
事先準備已形成要成為TSV的凹部(孔)2a的基板(矽基板)2。凹部2a,例如,可以用光刻技術,並利用習知的乾蝕刻製程、例如ICP-RIE(Inductively Coupled Plasma Reactive Ion Etching,感應耦合式乾蝕刻系統)來形成。
以下,針對鍍層之前處理進行說明。
[親水化處理]
首先,對基板2施以親水化處理。親水化處理,是可以利用UV(紫外線)照射處理、電漿氧化處理、SPM處理(Piranha Clean)等任意之習知方法來實施。利用這親 水化處理,使基板表面成為後述之耦合劑容易結合之狀態。在利用SPM處理來進行親水化處理之場合下,在SPM處理之後施以利用DIW(純水)之沖淨處理。
[矽烷耦合處理]
其次,進行矽烷耦合處理,使矽烷耦合劑吸附在包含凹部2a內側表面的基板表面並形成矽烷系結合層21a(參照圖1(a))。「矽烷系結合層」,係一種由矽烷耦合劑而來的自己組織化單分子膜(SAM)所構成之層,是介在該層的下底(在此為矽)與上層(後述的觸媒粒子含有層22)之間來強化兩者的結合之層。
本實施型態方面,係利用真空蒸鍍處理來進行矽烷耦合處理。真空蒸鍍處理,可以使用具有例如圖3(a)概略地顯示的構成的真空蒸鍍裝置30來進行。此場合下,在設置於被設定成真空(減壓)氛圍的處理室31內之載置台32上載置基板2,利用設在載置台32內部的加熱器33把基板2加熱到例如100℃左右。於此狀態下,將貯留在箱槽34內的液態矽烷耦合劑利用加熱器35加熱使之汽化、乘載在由載送氣體供給源36供給之載送氣體(carrier gas)而供給到處理室31內。
矽烷耦合處理,也可以是利用液處理來進行。液處理,可以採用使用後述之鈦耦合處理所用的旋轉器(旋轉式液處理裝置)之旋塗式(SPIN-ON)處理、把基板浸漬在矽烷耦合劑浴之浸漬處理。又,在利用液處理 進行矽烷耦合處理之場合下,必須在移行到下一個鈦耦合處理之前另外進行烘烤(bake)處理。
在凹部2a的深寬比(Aspect Ratio)高之場合(例如以本實施型態之方式讓凹部2a為高深寬比的TSV之場合)下,因為要使液處理的矽烷耦合劑到達至凹部2a的底的部分是不可能或困難的,或者必須有生產技術上無法支持的長時間,所以,最好是利用真空蒸鍍處理來進行矽烷耦合處理。因此,本實施型態方面係利用真空蒸鍍處理來進行矽烷耦合處理。
矽烷耦合處理結束時點的狀態則顯示在圖1(a)。由矽烷耦合劑而來的膜亦即矽烷系結合層21a係附著在凹部2a內側的表面全體、以及凹部2a外側的基板2的表面(上面)全體。
[鈦耦合處理]
其次,進行鈦耦合處理,使鈦耦合劑吸附在包含凹部內側表面的基板表面並形成鈦系結合層21b(參照圖1(b))。「鈦系結合層」,係一種由鈦耦合劑而來的自己組織化單分子膜所構成之層,是介在該層的下底與上層之間來強化兩者的結合之層。
鈦耦合處理係可以利用液處理來進行。液處理,可以採用將基板浸漬在鈦耦合劑浴之浸漬處理,或者用圖3(b)概略地顯示構成的旋轉器(旋轉式液處理裝置)40之旋塗式處理等。本實施型態方面,係利用旋塗 式處理來進行鈦耦合處理。
旋塗式處理,係如圖3(b)所示,可以藉由利用旋轉夾盤41使基板2保持水平姿勢並在鉛直軸線周圍旋轉、向該旋轉的基板2的表面中央部從噴嘴42將鈦耦合劑吐出來進行。被供給到基板2的表面中央部之液狀鈦耦合劑係利用離心力而向基板周緣部擴大,藉此,在基板的表面形成由鈦耦合劑而來的膜、亦即鈦系結合層21b。此處理可以於常溫的空氣中來進行。
理由係詳述於後,但,本實施型態方面,由於不想鈦耦合劑進到凹部2a的深處,所以可以藉由控制旋轉數等來抑制鈦耦合劑之往凹部2a內之旋塗式處理,是比浸漬處理還佳。
鈦耦合處理結束後,會在凹部2a的內部及其周邊,以圖1(b)概略地顯示之樣態,形成矽烷系結合層21a及鈦系結合層21b。先被形成的矽烷系結合層21a之中的鈦耦合劑作用的部分係變成鈦系結合層21b。針對此點詳述於後。
[燒成處理]
鈦耦合處理結束後,才進行鈦耦合劑的燒成處理。此燒成處理,可以是藉由在低氧氛圍例如氮氣氛圍下加熱基板來進行。具體而言,例如,使用具有圖3(c)概略地顯示的構成之加熱裝置(烘烤裝置)50,將基板2載置於設置在氮氣氛圍下的處理室51內之載置台52上,利用設 置在載置台52內部的加熱器53把基板2加熱到例如100℃左右。利用此燒成處理,完成鈦系結合層21b。
參照圖2,說明這以後的步驟。圖2方面,為了簡略化圖面,並不區別矽烷系結合層21a與鈦系結合層21b,而表記為單一的結合層21。圖2(a)係顯示上述燒成處理結束時點的狀態。
[含觸媒粒子膜形成處理]
其次,把作為金屬觸媒粒子的鈀奈米粒子(Pd-NPs)、與覆蓋鈀奈米粒子的作為分散劑的聚乙烯吡咯烷酮(PVP)分散到溶媒中而形成之鈀奈米膠狀溶液、亦即觸媒粒子溶液供給到基板,進行含觸媒粒子膜形成處理。
含觸媒粒子膜形成處理,例如,可以藉由使用具有圖3(b)概略地顯示的構成之旋轉器40,利用旋轉夾盤41將基板2保持在水平姿勢並使之在鉛直軸線周圍旋轉,向此旋轉的基板的表面中央部從噴嘴將觸媒粒子溶液吐出來進行。藉此,如圖2(b)所示方式,在凹部2a內側的表面及凹部2a外側的基板表面,在結合層21上,形成含有金屬觸媒粒子之含觸媒粒子膜22。
[加熱處理]
含觸媒粒子膜形成處理結束後,才進行加熱處理。加熱處理,可以藉由在真空(減壓)氛圍或氮氣氛圍下加熱基板2來進行。具體而言,例如,可以藉由採用具有例如 圖3(c)概略地顯示的構成之加熱裝置50,在做成真空(減壓)氛圍的處理室51內(不供給氮氣、而僅抽真空),將基板2載置在載置台52上,將基板2以100℃~280℃左右的溫度加熱,來進行加熱處理。藉由進行加熱處理,形成含觸媒粒子膜22強固地結合在下底的結合層21之狀態。
藉以上所述結束鍍層之前處理。
[阻擋層形成處理]
第2加熱處理結束後,才以圖2(c)所示方式,利用習知的無電解電鍍技術,形成鈷-鎢系的(包含鈷及鎢之物)阻擋層23。此時,觸媒粒子係作用為無電解電鍍的觸媒。
[晶種層形成處理]
阻擋層形成處理結束後,才以圖2(d)所示方式,利用習知的無電解電鍍技術,在阻擋層23上形成銅晶種層(Cu seed layer)24。
[埋入處理]
晶種層形成處理結束後,才利用習知的電解電鍍技術,如圖2(e)所示,在銅晶種層24上形成銅電鍍層25,利用該銅電鍍層25把凹部2a完全地埋入。
埋入處理結束後,利用CMP來刨削基板2的 背面,做成讓銅電鍍層25從背面露出來。依照上述,讓一連串的TSV的埋入處理結束。
以下,說明本實施型態之、二階段耦合處理之優點。
於先前技術已簡單提到過,由於鈦系結合層是以TiOx為主成分,鈀奈米粒子等觸媒金屬粒子之吸附性能高,從而,在使下底(本例為矽)與上層(本例為後述之含觸媒金屬粒子層)結合之能力上,跟矽烷系結合層相比是較為優秀的。
另一方面,鈦耦合劑,由於無法利用真空蒸鍍處理使之在基板的表面良好地吸附,所以,進行液處理是必要的。但是,鈦耦合劑之液處理有以下之問題。
(1)液處理方面,要使鈦耦合劑侵入到高深寬比的凹部2a深處的部分是不可能的、或者雖可能但必須要生產技術上無法支持之長時間處理。
(2)用液處理進行的鈦耦合處理,作為其後處理,必須進行燒成處理。該等之處理不充分進行的話,鈦系結合層的品質會降低,且無法使良好的含觸媒粒子膜22附著在鈦系結合層21b上。
(3)鈦耦合劑,即使用IPA(異丙醇)等有機溶劑稀釋了仍容易發生加水分解反應,而在比較短時間下劣化。從而,液處理必須在比較短時間下進行。
考慮上述情事,結論是,對於凹部的內部,不採用鈦耦合處理,而採用可使用本質上覆蓋度佳的成膜 方法之真空蒸鍍處理之矽烷耦合處理為較佳。
於是,本實施型態方面,首先,利用蒸鍍處理先進行矽烷耦合處理,使矽烷耦合劑到達凹部2a底的部分,而在凹部2a內側的表面及凹部2a外側的表面之全體,如圖1(a)所示形成矽烷系結合層21a。接著,之後,做成利用液處理來進行鈦耦合處理。
對著矽烷系結合層進行鈦耦合處理時,鈦耦合劑會作用成打消矽烷系結合層的性質,形成猶如從最初開始就進行鈦耦合處理之狀態。又,此特性,在不使用遮蔽等特別的手段、而進行隨場所之不同分別使用不同的耦合劑方面,是非常有幫助的。
在此,鈦耦合處理,由於是利用液處理、特別是旋塗式處理來進行的,所以,只要是處理時間不十分長,鈦耦合劑幾乎不會深入深寬比高的凹部2a的內部。作為一例,鈦耦合劑,從凹部2a的入口起最多不過進到10~30μm左右的深度為止。
從而,如圖1(b)所示,在從凹部2a的深度方向中央部到底部為止的範圍的表面會留下矽烷系結合層21a,而在凹部2a內側的入口附近及凹部2a外側的基板2的表面則形成鈦系結合層21b。
鍍層的緊貼性會特別成為問題的是在凹部2a的入口邊緣部的附近領域。這是在該領域鍍膜會發生高的內部應力,而且,在進行後面步驟的CMP(化學機械研磨)時容易產生應力集中的緣故。另一方面,在凹部2a 的內部,並不要求上述領域那樣的緊貼性,而重視形成無缺陷、均一的鍍層。
根據本實施型態,如圖1(b)所示,藉由在必須容忍應力的領域形成高結合力的鈦系結合層21a、這以外的部分則形成可以高覆蓋度成膜的矽烷系結合層21b,來完全滿足上述要求。
此外,由於鈦耦合劑不進入凹部2a深處,所以也有能夠容易地進行後面步驟的燒成處理之優點。
此外,鈦耦合劑進不到凹部2a深處也沒關係,這是意味能夠在非常短時間下來進行液處理。這在以前述方式處理於短時間下容易劣化的鈦耦合劑方面是較佳的。此外,如果短時間的處理是可以的,則能夠削減進行旋塗式處理之場合下鈦耦合劑之消耗量。在例如基板2為12吋晶圓之場合,鈦耦合劑的消耗量為每1枚基板10ml左右來完成。
根據上述實施型態,可以藉由組合利用2種類耦合劑之各自的優點,來形成高品質的鍍層。此外,在2種類耦合劑的分別使用上,沒有遮蔽等特別的手段之必要。
在上述實施型態,2種類耦合劑為矽烷耦合劑與鈦耦合劑,但是,並不受限定於此,組合使用其他種類的耦合劑亦可。
在上述實施型態,觸媒粒子溶液所含的金屬觸媒雖是鈀(Pd),但並不受限於此,也可以是例如金 (Au)、白金(Pt)、釕(Ru)。
在上述實施型態,觸媒粒子溶液所含的分散劑雖是聚乙烯吡咯烷酮(PVP),但並不受限於此,也可以是例如聚丙烯酸(PAA)、聚乙烯亞胺(PEI)、四甲銨(TMA)、檸檬酸。
在上述實施型態,係在低氧濃度氛圍或真空氛圍下進行加熱步驟,但在大氣(空氣)氛圍下進行也是可以的。這場合,與在低氧濃度氛圍或真空氛圍下進行加熱處理之場合相比,前者有緊貼性降低之傾向,但是,如果緊貼性降低的水準是可以容許的,從處理成本減低的觀點而言則採用大氣(空氣)氛圍下的加熱處理亦可。
在上述實施型態,阻擋層23為鈷-鎢系之物,但並不受限於此,也可以是形成由其他習知的適當的阻擋層材料、例如鎳-鎢系(包含鎳及鎢之物)材料所構成的阻擋層。此外,阻擋層,也可以如關於本件申請人的先前申請之日本專利特開2013-194306號記載之方式形成二層。
在上述實施型態,晶種層24及電鍍層25為銅(Cu),但也可以是鎢(W)、鈷(Co)、鎳(Ni)或者其合金。阻擋層23,是可以因應晶種層24及電鍍層25的材質之不同而斟酌變更。
在上述實施型態,凹部2a為TSV,但並不受限於此,凹部也可以是通常的通孔、凹溝等。
上述一連串的處理,亦即親水化處理、矽烷 耦合處理、鈦耦合處理、燒成處理、含觸媒粒子膜形成處理、加熱處理、阻擋層形成處理、晶種層形成處理及埋入處理,係能夠利用例如圖4概略地顯示之鍍層處理系統來執行。
在圖4所示之鍍層處理系統100,設置在搬出入工作站200之基板搬送裝置13,是從被載置在載子載置部11之載子C將基板2取出、將取出的基板2載置到遞送部14。設置在處理工作站300之處理單元16,被構成得以執行上述一連串的處理之至少任一處理。亦即,若干處理單元16係圖3所示之裝置30、40、50。被載置在遞送部14之基板2,係利用處理工作站300的基板搬送裝置17而從遞送部14被取出,並依序被搬入對應於上述處理之處理單元16,於各處理單元16被施以指定的處理。一連串的處理結束之後,基板2從處理單元16被搬出、載置到遞送部14。接著,被載置在遞送部14之處理完成的基板2,則利用基板搬送裝置13而返回載子載置部11的載子C。
基板處理系統100係具備控制裝置400。控制裝置400,係例如電腦,具備控制部401與記憶部402。記憶部402,係收納控制在基板處理系統100被執行的各種處理之程式。控制部401係藉由讀出並執行被記憶在記憶部402之程式來控制基板處理系統100的動作。亦即,控制裝置400,係為了實施鍍層相關之上述一連串的處理,而控制各處理單元16的動作、與由基板搬送裝置 13、17所進行的基板2的搬送動作。
又,這樣的程式,或是被記錄在可以利用電腦來讀取的記憶媒體之程式,亦或是從該記憶媒體被安裝到控制裝置4的記憶部19之程式。作為可以利用電腦來讀取的記憶媒體,係有例如硬碟(HD)、軟碟(FD)、光碟(CD)、磁碟(MO)、記憶卡等。
2‧‧‧基板(矽基板)
2a‧‧‧凹部(孔)
21、21a‧‧‧第1結合層(矽烷系結合層)
21b‧‧‧第2結合層(鈦系結合層)

Claims (6)

  1. 一種鍍層之前處理方法,其特徵係具備:準備具有凹部的基板之步驟;使用第1耦合劑,在前述基板的至少凹部內側的表面形成第1結合層之第1結合層形成步驟;與在前述第1結合層形成步驟之後,使用第2耦合劑,在前述基板的至少凹部外側的表面形成第2結合層之第2結合層形成步驟。
  2. 如申請專利範圍第1項記載之鍍層之前處理方法,其中前述第1耦合劑為矽烷耦合劑;前述第2耦合劑為鈦耦合劑。
  3. 如申請專利範圍第1或2項記載之鍍層之前處理方法,其中前述第1結合層形成步驟係利用真空蒸鍍處理來進行;前述第2結合層形成步驟係利用液處理來進行。
  4. 如申請專利範圍第3項記載之鍍層之前處理方法,其中前述液處理係藉由邊使基板以水平姿勢在鉛直軸線周圍旋轉、邊對基板供給液體狀態的第2耦合劑來進行。
  5. 如申請專利範圍第1或2項記載之鍍層之前處理方法,其中進而具備在前述第2結合層形成步驟之後在前述第1結合層及前述第2結合層之上使金屬觸媒粒子附著之步驟。
  6. 一種記憶媒體收納有供鍍層處理系統執行鍍層之前處理方法用之電腦程式之記憶媒體,其特徵係前述前處理方法具備:準備具有凹部的基板之步驟;使用第1耦合劑,在前述基板的至少凹部內側的表面形成第1結合層之第1結合層形成步驟;與在前述第1結合層形成步驟之後,使用第2耦合劑,在前述基板的至少凹部外側的表面形成第2結合層之第2結合層形成步驟。
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