TWI573203B - Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices - Google Patents
Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Description
本申請案之主題標的與以下申請案之主題標的相關：2011年3月31日提出之美國專利申請案13/077,365號，其名稱為「形成包含由一共同底材承載之兩個或更多已處理半導體結構之鍵結半導體結構之方法及應用此等方法所形成之半導體結構 The subject matter of the present application is related to the subject matter of the following application: U.S. Patent Application Serial No. 13/077,365, filed on March 31, 2011, entitled Method for processing bonded semiconductor structures of semiconductor structures and semiconductor structures formed by using the same
本發明與製作半導體元件期間形成及利用居間結構之方法，及應用此等方法所製作之結構及元件有關。 The present invention relates to methods of forming and utilizing intervening structures during fabrication of semiconductor devices, and structures and components fabricated using such methods.
製作含有積體電路之半導體元件，像是電子信號處理器、記憶元件及感光元件(例如發光二極體(LED)、雷射二極體、光電池、光檢測器等等)時，經常需要在兩個元件間(例如兩個積體電路元件間)、一元件與一結構間，或兩個結構間使用本發明所屬技術領域所稱之「居間結構(interposer)」。居間結構被設置成介於兩個元件及/或結構間，可用於在該兩個元件及/或結構間提供結構上及電性上之互連。 When manufacturing semiconductor components including integrated circuits, such as electronic signal processors, memory devices, and photosensitive devices (such as light-emitting diodes (LEDs), laser diodes, photovoltaic cells, photodetectors, etc.), it is often necessary to An "interposer" as referred to in the technical field of the present invention is used between two elements (for example, between two integrated circuit elements), between one element and one structure, or between two structures. The intervening structure is disposed between two elements and/or structures and can be used to provide structural and electrical interconnections between the two elements and/or structures.
在某些情況下，居間結構可用於重新分佈一電性連接之圖案。舉例而言，一積體電路元件可具有排成第一圖案之電性接觸部件陣列，而該積體電路元件所要耦合之另一元件或結構可具有排成不同之第二圖案之電性接觸部件陣列。這樣，該積體電路元件便無法只藉由緊靠及鍵結至該另一元件或結構，而在該積體電路元件之電性接觸部件與該另一元件或結構之電性接觸部件間建立電性連接。 In some cases, the intervening structure can be used to redistribute the pattern of an electrical connection. For example, an integrated circuit component can have an array of electrical contact features arranged in a first pattern, and another component or structure to which the integrated circuit component is to be coupled can have electrical contacts arranged in a second, different pattern. An array of parts. Thus, the integrated circuit component cannot be held between the electrical contact member of the integrated circuit component and the electrical contact component of the other component or structure by merely abutting and bonding to the other component or structure. Establish an electrical connection.
為利於電性互連，可製作一居間結構，該居間結構在其第一面包含排成第一圖案之第一組電性接觸部件，並在相反之第二面包含排成另一圖案之第二組電性接觸部件，其中第一圖案為該積體電路元件之電性接觸部件圖案之鏡像，另一圖案為該另一元件或結構之電性接觸部件圖案之鏡像。該居間結構可包含以下所列之一種或多種：導電通孔，其在垂直於該居間結構之主要平面之縱向上穿過該居間結構之至少一部分；導電跡線，其在平行於該居間結構之主要平面之橫向上橫越該居間結構；及導電接觸墊，其定義出欲與該積體電路元件及該另一元件或結構建立電性接觸之位置。該些導電通孔及跡線可用於將該居間結構之第一面上之接觸墊之圖案，在該居間結構之相反第二面「重分佈」為一不同之接觸墊圖案。在此組構下，該居間結構之第一面上之接觸墊可在結構上及電性上耦合至該積體電路元件之電性接觸部件，該居間結構之相反第二面上之接觸墊則可在結構上及電性上耦合至該另一元件或結構之電性接觸部件，從而透過該居間結構在該積體電路元件與該另一元件或結構間提供一電性互連。 To facilitate electrical interconnection, an intervening structure can be fabricated that includes a first set of electrical contact features arranged in a first pattern on a first side thereof and a second pattern on a second opposite surface. A second set of electrical contact members, wherein the first pattern is a mirror image of the electrical contact member pattern of the integrated circuit component and the other pattern is a mirror image of the electrical contact member pattern of the other component or structure. The intervening structure can comprise one or more of the following: a conductive via that passes through at least a portion of the intervening structure in a longitudinal direction perpendicular to a major plane of the intervening structure; a conductive trace that is parallel to the intervening structure The primary plane traverses the intervening structure laterally; and the electrically conductive contact pad defines a location to be in electrical contact with the integrated circuit component and the other component or structure. The conductive vias and traces can be used to "redistribute" the pattern of contact pads on the first side of the intervening structure to a different contact pad pattern on the opposite second side of the intervening structure. In this configuration, the contact pads on the first side of the intervening structure are structurally and electrically coupled to the electrical contact members of the integrated circuit component, and the contact pads on the opposite second side of the intervening structure The electrical contact member can be structurally and electrically coupled to the other component or structure to provide an electrical interconnection between the integrated circuit component and the other component or structure through the intervening structure.
為使居間結構能夠用一般的半導體製造加工設備處理及操作，居間結構通常相對厚。舉例而言，居間結構可具有200微米(200 μm)或更厚之平均層厚度。 In order for the intervening structure to be handled and handled by conventional semiconductor fabrication processing equipment, the intervening structure is typically relatively thick. For example, the intervening structure can have an average layer thickness of 200 microns (200 μm) or more.
半導體元件之部件持續縮減至更小尺寸。由於穿透居間結構所形成之導電貫孔之平均截面尺寸(例如平均直徑)減少，該些導電貫孔之高寬比(aspect ratio)因而增加。一導電貫孔之高寬比被定義為：該導電貫孔之長度(垂直於該居間結構之主要平面之縱向尺寸)除以該導電貫孔之平均截面尺寸。舉 例而言，若一導電貫孔具有之長度為200微米(200 μm)，平均截面尺寸為40微米(40 μm)，則該導電貫孔所具有之高寬比為5(亦即200/40=5)。 The components of the semiconductor component continue to shrink to smaller sizes. As the average cross-sectional dimension (e.g., average diameter) of the conductive vias formed by the interpenetrating structures is reduced, the aspect ratio of the conductive vias is thereby increased. The aspect ratio of a conductive via is defined as the length of the conductive via (perpendicular to the longitudinal dimension of the major plane of the intervening structure) divided by the average cross-sectional dimension of the conductive via. Lift For example, if a conductive via has a length of 200 micrometers (200 μm) and an average cross-sectional dimension of 40 micrometers (40 μm), the conductive via has an aspect ratio of 5 (ie, 200/40). =5).
形成具有高高寬比之導電貫孔並不容易。要在居間結構中形成導電貫孔，首先需形成穿透居間結構之洞孔，接著需利用一種或多種電鍍製程(例如在一無電電鍍製程後接著一電解電鍍製程)以導電金屬填充該些洞孔。由於所沉積之金屬必須有良好之階梯覆蓋能力且無空隙，因此具有高高寬比之洞孔在電鍍製程中不易以金屬填充。舉例而言，在接近居間結構中間之洞孔區域完全填滿前，靠近居間結構之相反主要表面之洞孔區域便可能已被金屬堵塞，因而使金屬無法進一步在洞孔內沉積，造成所產生之導電貫孔內有空隙。此等空隙可能使得導電貫孔無法操作。再者，較大的導電貫孔需要使用較多金屬，這會增加成本及金屬沉積製程之時間。較大導電貫孔還會在居間結構上佔據較多面積，使得在該居間結構之給定面積內可形成之導電貫孔數目受到限制，進而局限諸如居間結構等半導體元件之整體操作頻寬。 It is not easy to form a conductive via having a high aspect ratio. To form a conductive via in the intervening structure, first a hole is formed through the intervening structure, and then the holes are filled with a conductive metal using one or more electroplating processes (eg, an electroless plating process followed by an electrolytic plating process). hole. Since the deposited metal must have good step coverage and no voids, the holes having a high aspect ratio are not easily filled with metal during the electroplating process. For example, before the hole area near the middle of the intermediate structure is completely filled, the hole area near the opposite main surface of the intermediate structure may have been blocked by the metal, so that the metal cannot be further deposited in the hole, resulting in the generation There is a gap in the conductive through hole. These voids may make the conductive vias inoperable. Furthermore, larger conductive vias require more metal to be used, which increases the cost and time of the metal deposition process. Larger conductive vias also occupy more area on the intervening structure, such that the number of conductive vias that can be formed within a given area of the intervening structure is limited, thereby limiting the overall operating bandwidth of semiconductor components such as intervening structures.
本概要之提供旨在以簡要形式介紹一系列概念。該些概念將在本發明示範性實施例中進一步詳述。本概要之用意並非指出所主張專利標的之主要特點或基本特點，亦非用於限制所主張專利標的之範圍。 The purpose of this summary is to present a series of concepts in a concise form. These concepts are further detailed in the exemplary embodiments of the invention. This summary is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.
在一些實施例中，本發明包括製作含有居間結構之半導體元件之方法。根據此等方法，形成導電貫孔使之穿透一可回收底材上之一材料層。在就該材料層而言相反於該可回收底材之一面，將一載體底材鍵結於該材料層上方，並使該可回收底材從該材料層分離以回收該可回收底材。在就該材料層 而言相反於該載體底材之一面，將多個電接點形成於該材料層上方，該些電接點在電性上與該些導電貫孔有連通。 In some embodiments, the invention includes a method of fabricating a semiconductor component having an intervening structure. According to such methods, a conductive via is formed to penetrate a layer of material on a recyclable substrate. In the case of the material layer opposite to one side of the recyclable substrate, a carrier substrate is bonded over the layer of material and the recyclable substrate is separated from the layer of material to recover the recyclable substrate. In the layer of material In contrast to one side of the carrier substrate, a plurality of electrical contacts are formed over the layer of material, the electrical contacts being electrically connected to the conductive vias.
製作含有居間結構之半導體元件之其他方法包括，使一可分離界面形成於一半導體層與一可回收底材之間。該可分離界面包含該半導體層與該可回收底材間受到控制之一機械強度。然後，形成導電貫孔使之穿透該可回收底材上之半導體層。在就該半導體層而言相反於該可回收底材之一面，將一載體底材鍵結於該半導體層上方，並使該可回收底材從該半導體層分離以回收該可回收底材。之後，可在就該半導體層而言相反於該載體底材之一面，將電性上與該些導電貫孔有連通之電接點形成於該半導體層上方。 Other methods of fabricating a semiconductor component having an intervening structure include forming a separable interface between a semiconductor layer and a recyclable substrate. The detachable interface comprises a mechanical strength that is controlled between the semiconductor layer and the recyclable substrate. A conductive via is then formed to penetrate the semiconductor layer on the recyclable substrate. A carrier substrate is bonded over the semiconductor layer opposite the one of the recyclable substrate for the semiconductor layer, and the recyclable substrate is separated from the semiconductor layer to recover the recyclable substrate. Thereafter, an electrical contact electrically connected to the conductive vias may be formed over the semiconductor layer opposite to one side of the carrier substrate for the semiconductor layer.
本發明之進一步實施例包含應用本說明書所述方法所形成之中間半導體結構和元件及完全製作之半導體結構和元件。 Further embodiments of the invention include intermediate semiconductor structures and elements formed using the methods described herein, as well as fully fabricated semiconductor structures and elements.
舉例而言，在一些實施例中，製作半導體元件期間所形成之中間結構包含鍵結在一可回收底材上方之一半導體層及穿透該半導體層之導電貫孔，其中該可回收底材具有一可分離界面，該可分離界面在該半導體層與該可回收底材間有受到控制之一機械強度。在就該半導體層而言相反於該可回收底材之一面，可將一載體底材鍵結於該半導體層上方。 For example, in some embodiments, the intermediate structure formed during fabrication of the semiconductor device includes a semiconductor layer bonded over a recyclable substrate and a conductive via extending through the semiconductor layer, wherein the recyclable substrate There is a separable interface that is controlled by a mechanical strength between the semiconductor layer and the recyclable substrate. A carrier substrate can be bonded over the semiconductor layer in relation to the semiconductor layer opposite one side of the recyclable substrate.
本說明書所提出之闡釋，其用意並非對任何特定半導體材料、結構、元件或方法之實際意見，而僅是用來描述本發明實施例之理想化陳述。本說明書之任何標題不應視為限制本發明實施例之範圍，本發明之範圍乃是由以下申請專利範圍及其法律均等範圍所界定。在任何特定標題下所敘述之概念通 常亦適用於整份說明書之其他部分。本說明書引用了若干參考資料，但相對於本發明所主張之專利標的，所引用之參考資料不論本說明書如何描述其特點，均不予承認為習知技術。 The illustrations set forth in this specification are not intended to be an actual description of any particular semiconductor material, structure, component or method, but are merely intended to describe an idealized representation of an embodiment of the invention. The title of the present specification is not to be construed as limiting the scope of the embodiments of the present invention. The concept described under any particular heading Often applied to the rest of the specification. The specification refers to a number of references, but the referenced materials are not recognized as conventional techniques, regardless of how they are described in the specification.
製作包含本說明書所述居間結構之半導體元件之方法可提供相對薄之一居間結構，其包含具有相對低之高寬比之導電貫孔。如下文所進一步討論，該些方法大致包含形成穿透一底材上之一材料層之多個導電貫孔，該底材可為一可回收底材。在就該材料層而言相反於該可回收底材之一面，將一載體底材鍵結於該材料層上方，之後，使該可回收底材從該材料層分離以回收該可回收底材。接著，在就該材料層而言相反於該載體底材之一面，將電性上與該些導電貫孔有連通之多個電接點形成於該材料層上方。 A method of fabricating a semiconductor component comprising the intervening structure described herein can provide a relatively thin intervening structure comprising a conductive via having a relatively low aspect ratio. As discussed further below, the methods generally include forming a plurality of conductive vias that penetrate a layer of material on a substrate, which may be a recyclable substrate. In the case of the material layer opposite to one side of the recyclable substrate, a carrier substrate is bonded over the layer of material, after which the recyclable substrate is separated from the layer of material to recover the recyclable substrate . Next, a plurality of electrical contacts electrically connected to the conductive vias are formed over the material layer opposite to one side of the carrier substrate for the material layer.
圖1呈現一結構100，其包含一可回收底材102。該可回收底材102上面設置一材料層104。在一些實施例中，一可分離界面106可形成或以其他方式提供於該材料層104與該可回收底材102之間。該可分離界面106可在該材料層104與該可回收底材102間提供機械強度受到控制之一鍵結，且在下文所討論之進一步處理後，該可分離界面106可用於將該可回收底材102從該材料層104分離。 FIG. 1 presents a structure 100 that includes a recyclable substrate 102. A layer of material 104 is disposed over the recyclable substrate 102. In some embodiments, a separable interface 106 can be formed or otherwise provided between the layer of material 104 and the recyclable substrate 102. The detachable interface 106 can provide a mechanical strength bond between the material layer 104 and the recyclable substrate 102, and the detachable interface 106 can be used to recycle the material after being further processed as discussed below. Substrate 102 is separated from the layer of material 104.
在一些實施例中，該材料層104可包含一層半導體材料。換言之，該材料層104可包含一半導體層。作為非限制性質之範例，該材料層104可包含矽、鍺、碳化矽、鑽石及一種III-V族半導體材料當中至少一者。在一些實施例中，該材料層104實質上可由矽構成，且構成該材料層之矽可為多晶或單晶。 In some embodiments, the material layer 104 can comprise a layer of semiconductor material. In other words, the material layer 104 can comprise a semiconductor layer. As an example of non-limiting properties, the material layer 104 can comprise at least one of tantalum, niobium, tantalum carbide, diamond, and a III-V semiconductor material. In some embodiments, the material layer 104 can be substantially composed of tantalum, and the layer constituting the material layer can be polycrystalline or single crystal.
該可回收底材102可包含一種半導體材料(例如矽(採用生產等級(prime grade)或機械等級(mechanical grade)以達到較低之擁有成本)、鍺、一種III-V族半導體材料等等)或一種陶瓷材料，譬如一種氧化物(例如氧化鋁、氧化矽、氧化鋯等等)、一種氮化物(例如氮化矽)或一種碳化物(例如碳化矽)。 The recyclable substrate 102 can comprise a semiconductor material (eg, ruthenium (using prime grade or mechanical grade to achieve lower cost of ownership), niobium, a III-V semiconductor material, etc.) Or a ceramic material such as an oxide (such as alumina, yttria, zirconia, etc.), a nitride (such as tantalum nitride) or a carbide (such as tantalum carbide).
介於該可回收底材102與該材料層104間之可分離界面106可以諸如下列任何專利公開案所揭露之方式形成：2004年11月11日以Aspar等人之名公開之美國專利申請公開案2004/0222500號、2007年5月31日以Martinez等人之名公開之美國專利申請公開案2007/0122926號，以及2010年2月11日以Faure等人之名公開之國際專利申請公開案WO 2010/015878 A2號。 The detachable interface 106 between the recyclable substrate 102 and the material layer 104 can be formed, for example, in the manner disclosed in any of the following patent publications: U.S. Patent Application Publication No. US Patent Application Publication No. 2007/0122926, published on May 31, 2007, in the name of Martinez et al., and International Patent Application Publication No. 2007/0122926, filed on Feb. 11, 2010, in the name of Faure et al. WO 2010/015878 A2.
在一些實施例中，該可分離界面106可包含該材料層104與該可回收底材102間之直接分子鍵結。在其他實施例中，如圖1所示者，該可分離界面106可包含設置在該材料層104與該可回收底材102間之一種中間材料107。此種中間材料107可包含一種半導體材料、一種介電材料或一種陶瓷材料(例如上文所述之任何一種)當中的一者或多者。在其他實施例中，該中間材料107可包含一種金屬。在進一步之實施例中，該中間材料107可包括含有兩種或更多種此等材料之多層結構。 In some embodiments, the detachable interface 106 can comprise a direct molecular bond between the material layer 104 and the recyclable substrate 102. In other embodiments, as shown in FIG. 1, the detachable interface 106 can include an intermediate material 107 disposed between the layer of material 104 and the recyclable substrate 102. Such intermediate material 107 can comprise one or more of a semiconductor material, a dielectric material, or a ceramic material, such as any of those described above. In other embodiments, the intermediate material 107 can comprise a metal. In further embodiments, the intermediate material 107 can comprise a multilayer structure comprising two or more such materials.
作為非限制性質之一範例，在該材料層104鍵結於該可回收底材102上方前，該可分離界面106之機械強度可透過控制該材料層104及該可回收底材102之相對面之粗度及親水性當中至少一者而加以操縱，如美國專利申請公開案2004/0222500號所述。舉例而言，若相對面當中一者或兩者包含SiO2，則該SiO2表面可用氫氟酸加以蝕刻，以控制其表面粗度。其他化學處理亦可 視所要蝕刻材料之性質而採用。舉例而言，磷酸(H3PO4)可用於蝕刻及粗化氮化矽(Si3N4)，而氫氧化銨(NH4OH)、過氧化氫(H2O2)與水(H2O)之溶液則可用於蝕刻及粗化矽。在其他技術中，受到選擇性控制之熱處理可用於控制該材料層104與該可回收底材102間之分子鍵結之機械強度。 As an example of a non-limiting property, the mechanical strength of the separable interface 106 can be controlled by controlling the material layer 104 and the opposite side of the recyclable substrate 102 before the material layer 104 is bonded over the recyclable substrate 102. At least one of the thickness and the hydrophilicity is manipulated as described in U.S. Patent Application Publication No. 2004/0222500. For example, if one or both of the opposing faces comprise SiO 2 , the surface of the SiO 2 may be etched with hydrofluoric acid to control its surface roughness. Other chemical treatments may also be employed depending on the nature of the material to be etched. For example, phosphoric acid (H 3 PO 4 ) can be used to etch and roughen tantalum nitride (Si 3 N 4 ), while ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H) A solution of 2 O) can be used to etch and roughen the crucible. In other techniques, a selectively controlled heat treatment can be used to control the mechanical strength of the molecular bonds between the material layer 104 and the recyclable substrate 102.
因此，在一些實施例中，空隙108可存在於該可分離界面106。該些空隙108可因相鄰鍵結表面間之初始表面粗度所致，且該些空隙108可隨機分佈於該可分離界面106。在其他實施例中，該些空隙108可在鍵結前便形成於該些相鄰鍵結表面其中一者或兩者，且該些空隙108可分佈於該可分離界面106中預定及選定之位置。該些空隙108之數目及尺寸可用於選擇性地控制該材料層104與該可回收底材102間之鍵結之機械強度。 Thus, in some embodiments, voids 108 may be present at the detachable interface 106. The voids 108 may be due to an initial surface roughness between adjacent bond surfaces, and the voids 108 may be randomly distributed at the separable interface 106. In other embodiments, the voids 108 may be formed on one or both of the adjacent bond surfaces before bonding, and the voids 108 may be distributed in the detachable interface 106 to be predetermined and selected. position. The number and size of the voids 108 can be used to selectively control the mechanical strength of the bond between the material layer 104 and the recyclable substrate 102.
在實施例中，若該材料層104包含一種半導體材料，且該可分離界面106包含一種中間材料107，其含有一電絕緣材料者，則圖1之結構100可包含本發明所屬技術領域中稱為「絕緣體上半導體(SeOI)」類型之底材，像是絕緣體上矽(SOI)底材或絕緣體上鍺(GeOI)底材。在此等實施例中，該可回收底材102構成該SeOI類型底材之基底，該中間材料107則構成該材料層104與該基底間之一絕緣層。 In an embodiment, if the material layer 104 comprises a semiconductor material, and the separable interface 106 comprises an intermediate material 107 containing an electrically insulating material, the structure 100 of FIG. 1 may be included in the technical field of the present invention. It is a "semiconductor-on-insulator (SeOI)" type substrate, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In such embodiments, the recyclable substrate 102 constitutes a substrate for the SeOI type substrate, and the intermediate material 107 constitutes an insulating layer between the material layer 104 and the substrate.
在一些實施例中，該可回收底材102可被選定成包含一種材料，其所展現之熱膨脹係數與該材料層104所展現之熱膨脹係數高度匹配。舉例而言，該可回收底材102所展現之熱膨脹係數可在該材料層104所展現之熱膨脹係數之大約10%以內、在該材料層104所展現之熱膨脹係數之大約5%以內，或甚至在該材料層104所展現之熱膨脹係數之大約2.5%以內。當該結構100之溫度在後續製程期間有所變化時，該可回收底材102及該材料層104之熱 膨脹係數之高度匹配可使該可分離界面106附近之熱應力減少或降至最低，且可防止該材料層104意外過早從該可分離界面106分離。 In some embodiments, the recyclable substrate 102 can be selected to comprise a material that exhibits a coefficient of thermal expansion that is highly matched to the coefficient of thermal expansion exhibited by the layer of material 104. For example, the recyclable substrate 102 exhibits a coefficient of thermal expansion that is within about 10% of the coefficient of thermal expansion exhibited by the layer of material 104, within about 5% of the coefficient of thermal expansion exhibited by the layer of material 104, or even Within about 2.5% of the coefficient of thermal expansion exhibited by the layer of material 104. When the temperature of the structure 100 changes during subsequent processes, the recyclable substrate 102 and the heat of the material layer 104 The high degree of expansion of the coefficient of expansion reduces or minimizes thermal stresses near the detachable interface 106 and prevents the material layer 104 from being accidentally prematurely separated from the detachable interface 106.
該可回收底材102可較該材料層104厚。作為非限制性質之範例，該材料層104可具有一平均層厚度T，其大約為200微米(200 μm)或更薄、大約50微米(50 μm)或更薄、大約1微米(1 μm)或更薄，或甚至大約100奈米(100 nm)或更薄。在一些實施例中，該平均層厚度T可介於大約15奈米(15 nm)及大約100微米(100 μm)之間。在一些實施例中，該可回收底材102可具有一平均層厚度，其大約為200微米(200 μm)或更厚、大約500微米(500 μm)或更厚，或甚至大約700微米(700 μm)或更厚。在該可分離界面106包含一中間材料107之實施例中，該中間材料107可較該材料層104薄，且該中間材料107可具有一平均層厚度，其大約為，舉例而言，100奈米(100 nm)或更薄、大約50奈米(50 nm)或更薄，或甚至大約25奈米(25 nm)或更薄。 The recyclable substrate 102 can be thicker than the layer of material 104. As an example of non-limiting properties, the material layer 104 can have an average layer thickness T of about 200 microns (200 μm) or less, about 50 microns (50 μm) or less, about 1 micron (1 μm). Or thinner, or even about 100 nanometers (100 nm) or thinner. In some embodiments, the average layer thickness T can be between about 15 nanometers (15 nm) and about 100 micrometers (100 μm). In some embodiments, the recyclable substrate 102 can have an average layer thickness of about 200 microns (200 μm) or more, about 500 microns (500 μm) or more, or even about 700 microns (700). Μm) or thicker. In embodiments where the separable interface 106 comprises an intermediate material 107, the intermediate material 107 can be thinner than the material layer 104, and the intermediate material 107 can have an average layer thickness, which is approximately, for example, 100 nm. Rice (100 nm) or thinner, about 50 nm (50 nm) or thinner, or even about 25 nm (25 nm) or thinner.
具有如此薄之平均層厚度T之材料層104，可利用諸如本發明所屬技術領域稱為SMART-CUT®製程者提供於該可回收底材102上方。該SMART-CUT®製程描述於，舉例而言，美國專利RE39,484號(2007年2月6日核發予Bruel)、美國專利6,303,468號(2001年10月16日核發予Aspar等人)、美國專利6,335,258號(2002年1月1日核發予Aspar等人)、美國專利6,756,286號(2004年6月29日核發予Moriceau等人)、美國專利6,809,044號(2004年10月26日核發予Aspar等人)，以及美國專利6,946,365號(2005年9月20日核發予Aspar等人)。 The material layer 104 having such a thin average layer thickness T can be provided over the recyclable substrate 102 using a process known as the SMART-CUT® process in the art to which the present invention pertains. The SMART-CUT® process is described, for example, in US Patent RE 39,484 (issued to Bruel on February 6, 2007), US Patent 6,303,468 (issued to Aspar et al. on October 16, 2001), USA Patent No. 6,335,258 (issued to Aspar et al. on January 1, 2002), US Patent 6,756,286 (issued to Moriceau et al. on June 29, 2004), and US Patent 6,809,044 (issued to Aspar et al. on October 26, 2004). (Man), and U.S. Patent No. 6,946,365 (issued to Aspar et al. on September 20, 2005).
簡言之，該SMART-CUT®製程包含將離子植入相對厚之一材料層，以在該材料層內形成大致平坦之一弱化離子植入平面。該相對厚材料層可鍵結於該可回收底材102上方。接著可使該相對厚材料層沿著當中之弱化離子植入平面裂開，留下具有所需平均層厚度T之材料層104鍵結於該可回收底材102上方。或者，可在該SMART-CUT®製程後，將額外之半導體材料(其可具有多晶或非晶質之微結構)沉積在該移轉材料層104上面，以提供具有所需平均層厚度T之材料層104。 Briefly, the SMART-CUT® process involves implanting ions into a relatively thick layer of material to form a substantially flat one of the weakened ion implantation planes within the layer of material. The relatively thick layer of material can be bonded over the recyclable substrate 102. The relatively thick layer of material can then be cleaved along the weakened ion implantation plane therein, leaving a layer of material 104 having the desired average layer thickness T bonded over the recyclable substrate 102. Alternatively, additional semiconductor material (which may have a polycrystalline or amorphous microstructure) may be deposited over the layer of shifting material 104 after the SMART-CUT® process to provide the desired average layer thickness T. Material layer 104.
在額外實施例中，具有如此薄之平均層厚度T之材料層104，可經由以下方式提供於該可回收底材102上方：先將相對厚之一材料層鍵結於該可回收底材102上方，接著利用一磨削製程、一研磨製程及一蝕刻製程(例如使用一化學機械研磨(CMP)製程)當中的一種或多種，將該材料層薄化至該平均層厚度T。此種鍵結及薄化製程適於提供平均層厚度T大約為150微米(150 μm)或更厚之材料層104，而SMART-CUT®製程則適於提供平均層厚度T大約為1.5微米(1.5 μm)或更厚之材料層104。 In an additional embodiment, the material layer 104 having such a thin average layer thickness T can be provided over the recyclable substrate 102 by first bonding a relatively thick layer of material to the recyclable substrate 102. Above, the material layer is then thinned to the average layer thickness T using one or more of a grinding process, a polishing process, and an etching process (eg, using a chemical mechanical polishing (CMP) process). Such bonding and thinning processes are suitable for providing a material layer 104 having an average layer thickness T of about 150 microns (150 μm) or more, while the SMART-CUT® process is suitable for providing an average layer thickness T of about 1.5 microns ( A layer of material 104 of 1.5 μm or more.
參照圖2，多個導電貫孔110可在該材料層104位於該可回收底材102上時形成並穿透該材料層104，以產生圖2之結構112。該些導電貫孔110可利用本發明所屬技術領域中已知之技術形成。 Referring to FIG. 2, a plurality of conductive vias 110 can be formed and penetrate the material layer 104 as the material layer 104 is positioned on the recyclable substrate 102 to produce the structure 112 of FIG. The conductive vias 110 can be formed using techniques known in the art to which the present invention pertains.
舉例而言，可將一有圖案光罩提供於該材料層104之一曝露主要表面114上方。該光罩層可以包含多個孔隙，該些孔隙可在該材料層104中欲形成該些導電貫孔110之處貫穿該有圖案光罩層。一非等向性蝕刻製程，例如乾式反應離子蝕刻(RIE)製程，可用於穿過貫穿該光罩層之孔隙而在該材料層 104蝕刻出穿過該材料層104之洞孔，而該光罩層可阻隔該材料層104之其他部分不受蝕刻劑影響及防止此等部分被移除。 For example, a patterned reticle can be provided over one of the layers of material 104 exposed above the major surface 114. The mask layer can include a plurality of apertures that extend through the patterned mask layer where the conductive vias 110 are to be formed in the layer of material 104. An anisotropic etching process, such as a dry reactive ion etching (RIE) process, can be used to pass through the pores of the mask layer in the layer of material 104 etches through the holes of the material layer 104, and the mask layer blocks other portions of the material layer 104 from etchants and prevents such portions from being removed.
穿透該材料層104之洞孔形成後，便可將一介電材料(例如一種氧化物)沉積在該些洞孔104內以提供絕緣，之後，可用導電材料，例如一種金屬，填充該些洞孔104，以在該些洞孔內形成導電貫孔110。舉例而言，該金屬可包含銅、鋁、銀、鎢、鈦、鎳等等當中的一種或多種。在一些實施例中，該些導電貫孔110可包含多個金屬層，且其中兩層或更多層可具有不同組成。舉例而言，一第一無電電鍍製程可用於將相對薄之一金屬種子層沉積在該些洞孔內之材料層104之表面上。此等製程可提供相對緻密之一金屬薄層，其具有良好之階梯覆蓋性，因此可使至少實質上連續之一金屬層得以沉積在該些洞孔內所有表面上。沉積此種種子層後，便可利用另一電鍍製程，譬如一電解電鍍製程，以相對較高之速率將額外之金屬沉積在該種子層上，直到該些洞孔至少實質上被金屬填滿，以形成該些導電貫孔110。在額外實施例中亦可使用其他沉積製程，例如物理氣相沉積(PVD)製程及/或化學氣相沉積(CVD)製程，將導電材料沉積於該些洞孔內。 After the holes penetrating the material layer 104 are formed, a dielectric material (for example, an oxide) may be deposited in the holes 104 to provide insulation, and then the conductive material, such as a metal, may be used to fill the holes. The holes 104 are formed to form conductive through holes 110 in the holes. For example, the metal may comprise one or more of copper, aluminum, silver, tungsten, titanium, nickel, and the like. In some embodiments, the conductive vias 110 may comprise a plurality of metal layers, and wherein two or more layers may have different compositions. For example, a first electroless plating process can be used to deposit a relatively thin one metal seed layer on the surface of the material layer 104 within the holes. These processes provide a relatively dense layer of metal that has good step coverage so that at least substantially one continuous metal layer can be deposited on all surfaces within the holes. After depositing such a seed layer, another electroplating process, such as an electrolytic plating process, can be used to deposit additional metal on the seed layer at a relatively high rate until the holes are at least substantially filled with metal. To form the conductive vias 110. Other deposition processes, such as physical vapor deposition (PVD) processes and/or chemical vapor deposition (CVD) processes, may also be used in additional embodiments to deposit conductive material into the holes.
如圖2所示，該些導電貫孔110可從該曝露主要表面114延伸至該可分離界面106，穿透整個該材料層104。因此，在該材料層104含有矽之實施例中，該些導電貫孔110可包含本發明所屬技術領域稱為「穿透晶圓通孔(TWVs)」或「穿透矽通孔(TSVs)」者。 As shown in FIG. 2, the conductive vias 110 may extend from the exposed major surface 114 to the separable interface 106 to penetrate the entire material layer 104. Therefore, in the embodiment in which the material layer 104 contains germanium, the conductive vias 110 may include "through-wafer vias (TWVs)" or "through-through vias (TSVs) in the technical field of the present invention. By.
在一些實施例中，所形成之導電貫孔110可具有大約2.5或更低之高寬比，或甚至大約1.6或更低之高寬比。藉由形成該些導電貫孔110使其具有 相對低之高寬比，可使本說明書先前所討論因形成高高寬比之導電貫孔所造成之相關問題獲得改善。 In some embodiments, the formed conductive vias 110 can have an aspect ratio of about 2.5 or less, or even an aspect ratio of about 1.6 or less. Forming the conductive vias 110 to have The relatively low aspect ratio allows for improved problems associated with the formation of high aspect ratio conductive vias as discussed earlier in this specification.
此外，本說明書所述方法之實施例可以不涉及該材料層104之任何顯著薄化，在此等情況下，該些導電貫孔110係在該些導電貫孔110形成於該材料層104中之後形成。 In addition, embodiments of the method of the present specification may not involve any significant thinning of the material layer 104. In these cases, the conductive vias 110 are formed in the material layer 104 in the conductive vias 110. Formed afterwards.
參照圖3，形成該些導電貫孔110後，便可在就該材料層104而言相反於該可回收底材102之一面，將選擇性質之一重分佈層118形成於該材料層104上方，以產生圖3之結構120。該些導電貫孔110之位置及圖案可不需與所要耦合之另一結構或元件之電性接觸部件互補。這樣，該重分佈層118便可用於重新分佈該電接點圖案。該重分佈層118可包含縱向延伸之導電通孔122、橫向延伸之導電跡線124及導電接觸墊126當中的一種或多種。該些導電通孔122及跡線124可用於將該材料層104中該些導電貫孔110之圖案，在就該重分佈層118而言相反於該材料層104之一面上重新分佈為一不同圖案。該重分佈層118可利用本發明所屬技術領域已知之技術，在一逐層微影製程中形成。 Referring to FIG. 3, after the conductive vias 110 are formed, one of the selective properties of the redistribution layer 118 may be formed over the material layer 104 in terms of the material layer 104 opposite to one side of the recyclable substrate 102. To create the structure 120 of FIG. The locations and patterns of the conductive vias 110 need not be complementary to the electrical contact features of another structure or component to be coupled. Thus, the redistribution layer 118 can be used to redistribute the electrical contact pattern. The redistribution layer 118 can include one or more of a longitudinally extending conductive via 122, a laterally extending conductive trace 124, and a conductive contact pad 126. The conductive vias 122 and the traces 124 can be used to redistribute the pattern of the conductive vias 110 in the material layer 104 to a different side of the material layer 104 than the redistribution layer 118. pattern. The redistribution layer 118 can be formed in a layer-by-layer lithography process using techniques known in the art to which the present invention pertains.
如圖4所示，在就該材料層104而言相反於該可回收底材102之一面，可將一載體底材130暫時鍵結於該材料層104上方，以形成圖4之結構132。該載體底材130可為大致平坦，且可包含若干材料中的任一種。舉例而言，該載體底材130可包含上文討論該可回收底材102時所述及之材料中的任一種。該載體底材130所具有之平均層厚度，足以使該結構132能夠在後續製程中以半導體製造設備加以處理及操作。舉例而言，該載體底材130所具有之平均層厚度可為大約200微米(200 μm)或更厚、大約500微米(500 μ m)或更厚，或甚至大約700微米(700 μm)或更厚。該載體底材130可利用一直接分子鍵結製程鍵結在該材料層104上方，或者，可在欲鍵結之表面間利用一黏著劑或其他鍵結材料，將該載體底材130鍵結在該材料層104上方。 As shown in FIG. 4, a carrier substrate 130 can be temporarily bonded over the material layer 104 in relation to one side of the material layer 104 opposite the recyclable substrate 102 to form the structure 132 of FIG. The carrier substrate 130 can be substantially flat and can comprise any of a number of materials. For example, the carrier substrate 130 can comprise any of the materials described above when the recyclable substrate 102 is discussed. The carrier substrate 130 has an average layer thickness sufficient to enable the structure 132 to be processed and handled by semiconductor fabrication equipment in subsequent processes. For example, the carrier substrate 130 can have an average layer thickness of about 200 microns (200 μm) or more, about 500 microns (500 μ). m) or thicker, or even about 700 microns (700 μm) or thicker. The carrier substrate 130 can be bonded to the material layer 104 by a direct molecular bonding process, or the carrier substrate 130 can be bonded by an adhesive or other bonding material between the surfaces to be bonded. Above the material layer 104.
在實施例中，若在就該材料層104而言相反於該可回收底材102之一面，有一重分佈層118形成於該材料層104上方，則該載體底材130可鍵結至該材料層104上方之重分佈層118。若在實施例中並未形成此種重分佈層118，則該載體底材130可鍵結至該材料層118。 In an embodiment, if a redistribution layer 118 is formed over the material layer 104 in relation to the material layer 104 opposite to one side of the recyclable substrate 102, the carrier substrate 130 can be bonded to the material. A redistribution layer 118 above layer 104. If such a redistribution layer 118 is not formed in an embodiment, the carrier substrate 130 can be bonded to the material layer 118.
參照圖5，將該載體底材130鍵結於該材料層104上方後(如參照圖4所述者)，便可使該可回收底材102從該材料層104分離，以回收該可回收底材102及形成圖5所示之結構138。特定而言，該可回收底材102可沿著該可分離界面106從該材料層104分離。如有需要，該可回收底材102之後可重複使用。換言之，該可回收底材102可循環使用。循環使用該可回收底材102可減少廢料及製造成本。 Referring to FIG. 5, after the carrier substrate 130 is bonded over the material layer 104 (as described with reference to FIG. 4), the recyclable substrate 102 can be separated from the material layer 104 to recover the recyclable material. The substrate 102 and the structure 138 shown in FIG. In particular, the recyclable substrate 102 can be separated from the material layer 104 along the separable interface 106. The recyclable substrate 102 can then be reused if desired. In other words, the recyclable substrate 102 can be recycled. Recycling the recyclable substrate 102 reduces waste and manufacturing costs.
將該可回收底材102從該材料層104分離，可利用諸如前述2007年5月31日以Martinez等人之名公開之美國專利申請公開案2007/0122926號所述之設備及方法。如該公開案所述，固定之一定位件可用於固定圖4之結構132，且含有刀片之一切割裝置可以引發傳遞至整個該可分離界面106之一切割波之方式接觸該結構132。在一些實施例中，可於圖4之結構132之側邊表面形成一切口，該切割裝置之刀片可施力***該切口，以沿著該可回收底材102與該材料層104間之可分離界面106引發該切割波。 The apparatus and method described in U.S. Patent Application Publication No. 2007/0122926, the entire disclosure of which is incorporated herein by reference. As described in this publication, a fixed one of the positioning members can be used to secure the structure 132 of FIG. 4, and one of the cutting devices including the blade can initiate contact with the structure 132 in a manner that initiates a cutting wave that is transmitted throughout the separable interface 106. In some embodiments, a slit can be formed on the side surface of the structure 132 of FIG. 4, and the blade of the cutting device can be forcefully inserted into the slit to be along the recyclable substrate 102 and the material layer 104. The separation interface 106 initiates the cutting wave.
如圖5所示，將該可回收底材102從該材料層104分離後，該結構138之一斷裂表面140可能會相對粗糙，而且，在一些實施例中，該結構138之斷裂表面140可能包含殘餘之中間材料107。因此，該斷裂表面140可視需要加以清潔及/或平滑化。舉例而言，可利用一蝕刻製程、一磨削製程及一研磨製程(例如使用一化學機械研磨(CMP)製程)當中的一種或多種，使該斷裂表面140變得平滑。在該斷裂表面140經過平滑處理後，便可使用一標準清潔製程將殘留在其上之任何非所需材料去除。 As shown in FIG. 5, after the recyclable substrate 102 is separated from the material layer 104, one of the fracture surfaces 140 of the structure 138 may be relatively rough, and, in some embodiments, the fracture surface 140 of the structure 138 may A residual intermediate material 107 is included. Thus, the fracture surface 140 can be cleaned and/or smoothed as desired. For example, the fracture surface 140 can be smoothed using one or more of an etching process, a grinding process, and a polishing process (eg, using a chemical mechanical polishing (CMP) process). After the fracture surface 140 has been smoothed, any undesired material remaining thereon can be removed using a standard cleaning process.
如圖6所示，在就該材料層104而言相反於該載體底材130之一面，可將選擇性質之一重分佈層144形成於該材料層104上方，以產生圖6之結構146。如前文所討論，該些導電貫孔110之位置及圖案可不需與所要耦合之另一結構或元件之電性接觸部件互補。因此，該重分佈層144可像該重分佈層118一樣，用於重新分佈該電接點圖案。該重分佈層144可包含縱向延伸之導電通孔150、橫向延伸之導電跡線152及導電接觸墊154當中的一種或多種。該些導電通孔150及跡線152可用於將該材料層104中該些導電貫孔110之圖案，在就該重分佈層144而言相反於該材料層104之一面上重新分佈為一不同圖案。該重分佈層144可利用本發明所屬技術領域已知之技術，在一逐層微影製程中形成。 As shown in FIG. 6, one of the selective properties of redistribution layer 144 may be formed over the material layer 104 in relation to one side of the carrier substrate 130 with respect to the material layer 104 to produce the structure 146 of FIG. As discussed above, the locations and patterns of the conductive vias 110 need not be complementary to the electrical contact features of another structure or component to be coupled. Thus, the redistribution layer 144 can be used to redistribute the electrical contact pattern as the redistribution layer 118. The redistribution layer 144 can include one or more of a longitudinally extending conductive via 150, a laterally extending conductive trace 152, and a conductive contact pad 154. The conductive vias 150 and traces 152 can be used to redistribute the pattern of the conductive vias 110 in the material layer 104 to a different side of the material layer 104 than the redistribution layer 144. pattern. The redistribution layer 144 can be formed in a layer-by-layer lithography process using techniques known in the art to which the present invention pertains.
參照圖7，在就該材料層104而言相反於該載體底材130之一面，可將多個電接點160形成於該材料層104上方，以產生圖7之結構162。該些電接點160在電性上與該些導電貫孔110有連通。在該結構162包含該選擇性質重分佈層144之實施例中，該些電接點160係透過該重分佈層144中該些導電通孔150、跡線152及接觸墊154在電性上與該些導電貫孔110有連通。 在該結構162不包含該選擇性質重分佈層144之實施例中，該些電接點160可直接形成於該些導電貫孔110上，以建立與該些導電貫孔110之直接電性連通。 Referring to FIG. 7, a plurality of electrical contacts 160 may be formed over the material layer 104 in relation to one side of the carrier substrate 130 with respect to the material layer 104 to produce the structure 162 of FIG. The electrical contacts 160 are electrically connected to the conductive vias 110. In the embodiment where the structure 162 includes the selective property redistribution layer 144, the electrical contacts 160 are electrically connected to the conductive vias 150, the traces 152 and the contact pads 154 in the redistribution layer 144. The conductive vias 110 are in communication. In the embodiment in which the structure 162 does not include the selective property redistribution layer 144, the electrical contacts 160 may be directly formed on the conductive vias 110 to establish direct electrical connection with the conductive vias 110. .
不同類型之電接點160為本發明所屬技術領域所已知，且可為本發明實施例所採用。作為非限制性質之一範例，該些電接點160可包含形成於該材料層104上方之導電凸塊。如本發明所屬技術領域已知，一介電材料164可提供於該材料層104上方，且在該介電材料164中欲形成該些導電凸塊之處，可形成多個孔隙並使之穿過該介電材料164。接著，可利用所謂之「凸塊下冶金(under-bump metallurgy)」製程，將一層或多層導電金屬166沉積於該些孔隙內。然後便可在穿過該介電材料164之該些孔隙內之導電金屬166上形成該些導電凸塊。 Different types of electrical contacts 160 are known in the art to which the present invention pertains and may be employed in embodiments of the present invention. As an example of non-limiting properties, the electrical contacts 160 can include conductive bumps formed over the material layer 104. As is known in the art, a dielectric material 164 can be provided over the material layer 104, and where the conductive bumps are to be formed in the dielectric material 164, a plurality of voids can be formed and worn. The dielectric material 164 is passed through. Next, one or more layers of conductive metal 166 may be deposited in the pores using a so-called "under-bump metallurgy" process. The conductive bumps can then be formed on the conductive metal 166 in the voids through the dielectric material 164.
這樣，如上所述，一居間結構170便告形成，該居間結構170包含被該些導電貫孔110(例如穿透晶圓通孔(TWVs))所穿透之材料層104。該居間結構170亦可在該材料層104之一第一面包含一選擇性質重分佈層118，及/或在該材料層104之一相反第二面包含一選擇性質重分佈層144。在圖7之情形下，亦即該居間結構170維持暫時鍵結至該載體底材130時，在就該材料層104相反於該載體底材130之一面，該居間結構170可包含該材料層104上方之電接點160。將該載體底材130從該居間結構170分離後，便可接著在該材料層104之另一面將額外之電接點形成於該居間結構170上，如下文進一步所討論。 Thus, as described above, an intervening structure 170 is formed that includes a layer of material 104 that is penetrated by the conductive vias 110 (eg, through-wafer vias (TWVs)). The intervening structure 170 can also include a selective property redistribution layer 118 on a first side of the material layer 104 and/or a selective property redistribution layer 144 on an opposite second side of the material layer 104. In the case of FIG. 7, that is, when the intervening structure 170 is temporarily bonded to the carrier substrate 130, the intervening structure 170 may comprise the material layer insofar as the material layer 104 is opposite to one side of the carrier substrate 130. Electrical contacts 160 above 104. After the carrier substrate 130 is separated from the intervening structure 170, additional electrical contacts can then be formed on the other side of the material layer 104 on the intervening structure 170, as discussed further below.
參照圖8，將該載體底材130從該材料層104移除前，可使一第一結構或元件(例如一積體電路元件172)之導電部件171在結構上及電性上耦合 至該居間結構170之電接點160，以形成圖8之結構174。該積體電路元件172可被選定成包含一電子信號處理器、一記憶元件及一感光元件(例如發光二極體(LED)、雷射二極體、光電池、光檢測器等等)當中的一種或多種。 Referring to FIG. 8, the conductive member 171 of a first structure or component (e.g., an integrated circuit component 172) can be structurally and electrically coupled before the carrier substrate 130 is removed from the material layer 104. The electrical contacts 160 to the intervening structure 170 are formed to form the structure 174 of FIG. The integrated circuit component 172 can be selected to include an electronic signal processor, a memory component, and a photosensitive component (eg, a light emitting diode (LED), a laser diode, a photocell, a photodetector, etc.) One or more.
如圖9所示，接著可使該載體底材130從該材料層104分離，以形成圖9之結構176，其包含該居間結構170及該積體電路元件172。移除該載體底材130後，可使圖9之結構176在結構上及電性上耦合至另一結構或元件182之導電部件180，以形成圖10之結構184。該另一結構或元件182可包含，舉例而言，另一積體電路元件(像是前文所述及之積體電路元件當中任何一者)、一印刷電路板等等。這樣，電性接觸便在該居間結構170之材料層104之導電貫孔110與該結構或元件182之導電部件180間建立起來。此外，透過該居間結構170之材料層104之導電貫孔110(該居間結構170係插置在該積體電路元件172與該結構或元件182間)電性接觸亦會在該積體電路元件172與該結構或元件182建立。 As shown in FIG. 9, the carrier substrate 130 can then be separated from the material layer 104 to form the structure 176 of FIG. 9, which includes the intervening structure 170 and the integrated circuit component 172. After the carrier substrate 130 is removed, the structure 176 of FIG. 9 can be structurally and electrically coupled to the conductive features 180 of another structure or component 182 to form the structure 184 of FIG. The other structure or component 182 can comprise, for example, another integrated circuit component (such as any of the integrated circuit components described above), a printed circuit board, and the like. Thus, electrical contact is established between the conductive vias 110 of the material layer 104 of the intervening structure 170 and the conductive features 180 of the structure or component 182. In addition, the conductive vias 110 of the material layer 104 of the intervening structure 170 (the intervening structure 170 is interposed between the integrated circuit component 172 and the structure or component 182) are also in electrical contact with the integrated circuit component. 172 is established with the structure or component 182.
本發明所屬技術領域中已知之各種技術皆可用於使圖9之結構176在結構上及電性上耦合至該結構或元件182之導電部件180。作為非限制性質之一範例，導電凸塊186可形成於該些導電部件180上，或形成於該居間結構170之互補導電部件上，像是該些導電貫孔110之曝露端(若該居間結構未包含該選擇性質重分佈層144)，或形成於該選擇性質重分佈層144之導電墊154。作為非限制性質之一範例，該些導電凸塊186可利用諸如上文討論該些電接點160時所述及之技術形成於該材料層104上方。在額外實施例中，導電凸塊可形成於該結構或元件182之導電部件180上。 Various techniques known in the art to which the present invention pertains can be used to structurally and electrically couple the structure 176 of FIG. 9 to the conductive component 180 of the structure or component 182. As an example of the non-limiting property, the conductive bumps 186 may be formed on the conductive members 180 or formed on the complementary conductive members of the intermediate structure 170, such as the exposed ends of the conductive vias 110. The structure does not include the selective property redistribution layer 144) or the conductive pads 154 formed on the selective property redistribution layer 144. As an example of a non-limiting property, the conductive bumps 186 can be formed over the material layer 104 using techniques such as those discussed above for the electrical contacts 160. In an additional embodiment, conductive bumps may be formed on conductive features 180 of the structure or component 182.
利用本發明書所述技術可製作出許多居間結構170，該些居間結構所具有之導電貫孔110係製作成普遍、通用之一圖案，即使該些居間結構170係為了搭配具有各種各樣接觸部件圖案之若干不同結構及元件使用亦無妨。該些重分佈層118、144則可針對該些居間結構170之不同子集以不同方式組構及製作，以按不同結構及元件所需客製化該些不同子集。 By using the techniques described in the present invention, a plurality of intervening structures 170 can be fabricated. The interposing structures have conductive vias 110 that are made in a common, universal pattern, even if the intervening structures 170 have various contacts for matching. It is also possible to use several different structures and components of the component pattern. The redistribution layers 118, 144 can be organized and fabricated in different ways for different subsets of the intervening structures 170 to customize the different subsets as needed for different structures and components.
茲將本發明其他非限制性質實施例敘述如下： Other non-limiting examples of the invention are described below:
實施例1：一種製作含有一居間結構之半導體元件之方法，該方法包括：形成穿透一可回收底材上一材料層之多個導電貫孔；在就該材料層而言相反於該可回收底材之一面，將一載體底材鍵結於該材料層上方；使該可回收底材從該材料層分離以回收該可回收底材；以及在就該材料層而言相反於該載體底材之一面，將多個電接點形成於該材料層上方，該些電接點在電性上與該些導電貫孔有連通。 Embodiment 1 : A method of fabricating a semiconductor device having an intervening structure, the method comprising: forming a plurality of conductive vias penetrating a layer of material on a recyclable substrate; Retrieving one side of the substrate, bonding a carrier substrate over the layer of material; separating the recyclable substrate from the layer of material to recover the recyclable substrate; and in contrast to the carrier in terms of the layer of material One surface of the substrate is formed with a plurality of electrical contacts formed above the material layer, and the electrical contacts are electrically connected to the conductive vias.
實施例2：如實施例1之方法，其更包括選定該材料層使之具有大約100微米(100 μm)或更薄之平均層厚度。 Embodiment 2: The method of Embodiment 1, further comprising selecting the layer of material to have an average layer thickness of about 100 microns (100 μm) or less.
實施例3：如實施例2之方法，其更包括選定該材料層使其平均層厚度介於大約15奈米(15 nm)與大約100微米(100 μm)之間。 Embodiment 3: The method of Embodiment 2, further comprising selecting the layer of material to have an average layer thickness between about 15 nanometers (15 nm) and about 100 microns (100 μm).
實施例4：如實施例1至3中任一例之方法，其更包括選定該材料層使之包含一種半導體材料。 Embodiment 4. The method of any of embodiments 1 to 3, further comprising selecting the layer of material to comprise a semiconductor material.
實施例5：如實施例4之方法，其更包括選定該材料層使之包含矽、鍺及一種III-V族半導體材料當中至少一者。 Embodiment 5: The method of Embodiment 4, further comprising selecting the layer of material to comprise at least one of ruthenium, osmium, and a Group III-V semiconductor material.
實施例6：如實施例5之方法，其更包括選定該材料層使之包含矽。 Embodiment 6: The method of Embodiment 5, further comprising selecting the layer of material to include ruthenium.
實施例7：如實施例1至6中任一例之方法，其中形成穿透該可回收底材上之材料層之多個導電貫孔包含形成該些導電貫孔使之穿透一絕緣體上半導體(SeOI)結構之一半導體材料層，該SeOI結構包含一基底，該基底包含該可回收底材及介於該基底與該半導體材料層間之一絕緣層。 The method of any one of embodiments 1 to 6, wherein forming a plurality of conductive vias penetrating the material layer on the recyclable substrate comprises forming the conductive vias to penetrate a semiconductor-on-insulator (SeOI) A semiconductor material layer, the SeOI structure comprising a substrate comprising the recyclable substrate and an insulating layer interposed between the substrate and the semiconductor material layer.
實施例8：如實施例7之方法，其中該基底包含一種材料，該材料所展現之熱膨脹係數與該半導體材料層所展現之熱膨脹係數高度匹配。 Embodiment 8: The method of Embodiment 7, wherein the substrate comprises a material exhibiting a coefficient of thermal expansion that is highly matched to a coefficient of thermal expansion exhibited by the layer of semiconductor material.
實施例9：如實施例7或實施例8之方法，其中使該可回收底材從該材料層分離以回收該可回收底材包含使該半導體材料層沿著該絕緣層從該基底分離。 Embodiment 9. The method of Embodiment 7 or Embodiment 8, wherein separating the recyclable substrate from the layer of material to recover the recyclable substrate comprises separating the layer of semiconductor material from the substrate along the insulating layer.
實施例10：如實施例1至9中任一例之方法，其更包括形成該些導電貫孔使之具有大約2.5或更低之高寬比。 The method of any one of embodiments 1 to 9, further comprising forming the conductive vias to have an aspect ratio of about 2.5 or less.
實施例11：如實施例10之方法，其更包括形成該些導電貫孔使之具有大約1.6或更低之高寬比。 Embodiment 11: The method of Embodiment 10, further comprising forming the conductive vias to have an aspect ratio of about 1.6 or less.
實施例12：如實施例1至11中任一例之方法，其更包括在使該可回收底材從該材料層分離以回收該可回收底材前，於該可回收底材及該材料層間形成一可分離界面，該可分離界面包含該可回收底材與該材料層間機械強度受到控制之一鍵結。 The method of any one of embodiments 1 to 11, further comprising, between separating the recyclable substrate from the layer of material to recover the recyclable substrate, between the recyclable substrate and the layer of material A separable interface is formed, the separable interface comprising a bond between the recyclable substrate and the mechanical strength of the layer of material being controlled.
實施例13：如實施例1至12中任一例之方法，其更包括在就該材料層而言相反於該可回收底材之一面將該載體底材鍵結於該材料層上方前，於就該材料層而言相反於該可回收底材之一面，將一重分佈層形成於該材料層上方。 The method of any one of embodiments 1 to 12, further comprising, prior to bonding the carrier substrate to the layer of material on the side of the material layer opposite to the recyclable substrate, In the case of the material layer, opposite to one side of the recyclable substrate, a redistribution layer is formed over the material layer.
實施例14：如實施例13之方法，其更包括在就該材料層而言相反於該載體底材之一面將多個電接點形成於該材料層上方前，於就該材料層而言相反於該載體底材之一面，將另一重分佈層形成於該材料層上方，該些電接點係透過該另一重分佈層在電性上與該些導電貫孔有連通。 Embodiment 14: The method of Embodiment 13, further comprising, prior to forming the plurality of electrical contacts on the one side of the carrier substrate opposite the material layer, in the case of the material layer Conversely to one side of the carrier substrate, another redistribution layer is formed over the layer of material, the electrical contacts being electrically connected to the conductive vias through the other redistribution layer.
實施例15：如實施例1至12中任一例之方法，其更包括在就該材料層而言相反於該載體底材之一面將多個電接點形成於該材料層上方前，於就該材料層而言相反於該載體底材之一面，將另一重分佈層形成於該材料層上方，該些電接點係透過該另一重分佈層在電性上與該些導電貫孔有連通。 The method of any one of embodiments 1 to 12, further comprising, prior to forming a plurality of electrical contacts on the side of the material layer opposite to the carrier substrate, in the case of the material layer, The material layer is opposite to one side of the carrier substrate, and another redistribution layer is formed over the material layer, and the electrical contacts are electrically connected to the conductive vias through the other redistribution layer .
實施例16：如實施例1至15中任一例之方法，其中在就該材料層而言相反於該載體底材之一面將多個電接點形成於該材料層上方包含將多個導電凸塊形成於該材料層上方。 The method of any one of embodiments 1 to 15, wherein a plurality of electrical contacts are formed over the material layer in relation to the one side of the carrier substrate for the material layer to comprise a plurality of conductive bumps A block is formed over the layer of material.
實施例17：如實施例1至16中任一例之方法，其更包括使一積體電路元件之導電部件在結構上及電性上耦合至該些電接點。 The method of any one of embodiments 1 to 16, further comprising structurally and electrically coupling the electrically conductive members of an integrated circuit component to the electrical contacts.
實施例18：如實施例17之方法，其更包括選定該積體電路元件使之包含一電子信號處理器、一記憶元件及一感光元件當中至少一者。 Embodiment 18: The method of Embodiment 17, further comprising selecting the integrated circuit component to include at least one of an electronic signal processor, a memory component, and a photosensitive component.
實施例19：如實施例17或實施例18之方法，其更包括在就該材料層而言相反於該積體電路元件之一面，於該些導電貫孔及一結構或元件之導電部件間建立電性接觸，該材料層及該些導電貫孔係插置在該積體電路元件與該另一結構或元件之間。 Embodiment 19: The method of Embodiment 17 or Embodiment 18, further comprising, in relation to the material layer, opposite one of the integrated circuit components, between the conductive vias and a conductive component of a structure or component An electrical contact is established, the layer of material and the conductive vias being interposed between the integrated circuit component and the other structure or component.
實施例20：如實施例1至19中任一例之方法，其更包括使該載體底材從該材料層分離。 The method of any one of embodiments 1 to 19, further comprising separating the carrier substrate from the layer of material.
實施例21：製作一半導體元件期間所形成之一中間結構，該中間結構包括：一半導體層，其被鍵結在一可回收底材上方，該可回收底材具有一可分離界面，該可分離界面在該可回收底材與該材料層間有受到控制之一機械強度：多個導電貫孔，其穿透該半導體層；以及一載體底材，其在就該半導體層而言相反於該可回收底材之一面被鍵結在該半導體層上方。 Embodiment 21: an intermediate structure formed during fabrication of a semiconductor device, the intermediate structure comprising: a semiconductor layer bonded over a recyclable substrate having a separable interface, the recyclable substrate having a separable interface The separation interface has a mechanical strength controlled between the recyclable substrate and the material layer: a plurality of conductive vias penetrating the semiconductor layer; and a carrier substrate opposite to the semiconductor layer One side of the recyclable substrate is bonded over the semiconductor layer.
實施例22：如實施例21之中間結構，其中該半導體層所具有之平均層厚度介於大約15奈米(15 nm)與大約100微米(100 μm)之間。 Embodiment 22: The intermediate structure of Embodiment 21, wherein the semiconductor layer has an average layer thickness of between about 15 nanometers (15 nm) and about 100 microns (100 μm).
實施例23：如實施例21或實施例22之中間結構，其中該半導體層包含矽。 Embodiment 23: The intermediate structure of Embodiment 21 or Embodiment 22, wherein the semiconductor layer comprises ruthenium.
實施例24：如實施例21至23中任一例之中間結構，其中該些導電貫孔具有大約2.5或更低之高寬比。 Embodiment 24: The intermediate structure of any one of embodiments 21 to 23, wherein the conductive vias have an aspect ratio of about 2.5 or less.
實施例25：如實施例21至24中任一例之中間結構，其更包括該半導體層上方之一重分佈層，該重分佈層介於該載體底材與該半導體層之間。 Embodiment 25. The intermediate structure of any one of embodiments 21 to 24, further comprising a redistribution layer over the semiconductor layer, the redistribution layer being interposed between the carrier substrate and the semiconductor layer.
實施例26：一種製作含有一居間結構之半導體元件之方法，該方法包括：在一半導體層與一可回收底材間形成一可分離界面，該可分離界面包含該半導體層與該可回收底材間受到控制之一機械強度；形成穿透該可回收底材上之半導體層之多個導電貫孔；在就該半導體層而言相反於該可回收底材之一面，將一載體底材鍵結於該半導體層上方；使該可回收底材從該半導體層分離以回收該可回收底材；以及在就該半導體層而言相反於該載體底材之一面，將多個電接點形成於該半導體層上方，該些電接點在電性上與該些導電貫孔有連通。 Embodiment 26: A method of fabricating a semiconductor device comprising an intervening structure, the method comprising: forming a separable interface between a semiconductor layer and a recyclable substrate, the separable interface comprising the semiconductor layer and the recyclable bottom Between the materials being controlled by a mechanical strength; forming a plurality of conductive vias penetrating the semiconductor layer on the recyclable substrate; and in the case of the semiconductor layer opposite to one side of the recyclable substrate, a carrier substrate Bonding over the semiconductor layer; separating the recyclable substrate from the semiconductor layer to recover the recyclable substrate; and, in relation to the semiconductor layer, opposite the carrier substrate, a plurality of electrical contacts Formed above the semiconductor layer, the electrical contacts are electrically connected to the conductive vias.
實施例27：如實施例26之方法，其更包括選定該半導體層使其具有之平均層厚度介於大約15奈米(15 nm)與大約100微米(100 μm)之間。 Embodiment 27. The method of Embodiment 26, further comprising selecting the semiconductor layer to have an average layer thickness of between about 15 nanometers (15 nm) and about 100 microns (100 μm).
實施例28：如實施例26或實施例27之方法，其更包括選定該半導體層使之包含矽。 Embodiment 28: The method of Embodiment 26 or Embodiment 27, further comprising selecting the semiconductor layer to include germanium.
實施例29：如實施例26至28中任一例之方法，其更包括形成該些導電貫孔使之具有大約2.5或更低之高寬比。 The method of any one of embodiments 26 to 28, further comprising forming the conductive vias to have an aspect ratio of about 2.5 or less.
實施例30：如實施例29之方法，其更包括形成該些導電貫孔使之具有大約1.6或更低之高寬比。 Embodiment 30: The method of Embodiment 29, further comprising forming the conductive vias to have an aspect ratio of about 1.6 or less.
實施例31：如實施例26至30中任一例之方法，其更包括在就該半導體層而言相反於該可回收底材之一面將該載體底材鍵結於該半導體層上方前，於就該半導體層而言相反於該可回收底材之一面，將一重分佈層形成於該半導體層上方。 The method of any one of embodiments 26 to 30, further comprising, prior to bonding the carrier substrate to the semiconductor layer opposite to the one of the recyclable substrate for the semiconductor layer, A redistribution layer is formed over the semiconductor layer in relation to the semiconductor layer opposite to one side of the recyclable substrate.
實施例32：如實施例26至31中任一例之方法，其更包括在就該半導體層而言相反於該載體底材之一面將多個電接點形成於該半導體層上方前，於就該半導體層而言相反於該載體底材之一面，將一重分佈層形成於該半導體層上方，該些電接點係透過該重分佈層在電性上與該些導電貫孔有連通。 The method of any one of embodiments 26 to 31, further comprising, prior to forming the plurality of electrical contacts on the semiconductor layer opposite to the one of the carrier substrate, on the semiconductor layer, The semiconductor layer is opposite to one side of the carrier substrate, and a redistribution layer is formed over the semiconductor layer, and the electrical contacts are electrically connected to the conductive vias through the redistribution layer.
實施例33：如實施例26至32中任一例之方法，其更包括：使一積體電路元件之導電部件在結構上及電性上耦合至該些電接點；以及使該載體底材從該半導體層分離。 The method of any one of embodiments 26 to 32, further comprising: electrically and electrically coupling a conductive member of an integrated circuit component to the electrical contacts; and causing the carrier substrate Separated from the semiconductor layer.
實施例34：如實施例33之方法，其更包括選定該積體電路元件使之包含一電子信號處理器、一記憶元件及一感光元件當中至少一者。 Embodiment 34: The method of Embodiment 33, further comprising selecting the integrated circuit component to include at least one of an electronic signal processor, a memory component, and a light sensor component.
實施例35：如實施例33或實施例34之方法，其更包括在就該半導體層而言相反於該積體電路元件之一面，於該些導電貫孔及另一結構或元件之導電部件間建立電性接觸，該半導體層及該些導電貫孔係插置在該積體電路元件與該另一結構或元件之間。 Embodiment 35: The method of Embodiment 33 or Embodiment 34, further comprising: a conductive member opposite to the one of the integrated circuit components for the semiconductor layer, and the conductive via and the other structure or component Electrical contact is established, and the semiconductor layer and the conductive vias are interposed between the integrated circuit component and the other structure or component.
上述該些示範性實施例並不會限制本發明之範圍，因該些實施例僅為本發明實施例之範例，本發明乃是由所附之申請專利範圍及其法律均等範圍所定義。任何均等之實施例均屬本發明之範圍。事實上，對於本發明所屬技術領域具有通常知識者而言，除本說明書所示及所述者外，對於本發明之各種修改，例如替換所述元件之有用組合，都會因本說明書之敘述而變得顯而易見。換言之，本說明書所述任一示範性實施例之一項或多項特點，可以與本說明書所述另一示範性實施例之一項或多項特點結合，而成為本發明之額外實施例。此等修改及額外實施例亦落在所附之申請專利範圍內。 The above-described exemplary embodiments are not intended to limit the scope of the invention, and the embodiments are only examples of the embodiments of the invention, which are defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of the invention. In fact, various modifications of the invention, such as a substitute for a useful combination of the elements, in addition to those shown and described herein, will be apparent from the description of the specification. It became obvious. In other words, one or more of the features of any one of the exemplary embodiments described herein may be combined with one or more features of another exemplary embodiment described herein as an additional embodiment of the invention. Such modifications and additional embodiments are also within the scope of the appended claims.
100‧‧‧結構 100‧‧‧ structure
102‧‧‧可回收底材 102‧‧‧Recyclable substrate
104‧‧‧材料層 104‧‧‧Material layer
106‧‧‧可分離界面 106‧‧‧ separable interface
107‧‧‧中間材料 107‧‧‧Intermediate materials
108‧‧‧空隙 108‧‧‧ gap
110‧‧‧導電貫孔 110‧‧‧ Conductive through hole
112‧‧‧結構 112‧‧‧ structure
114‧‧‧曝露主要表面 114‧‧‧Exposed main surface
118‧‧‧重分佈層 118‧‧‧ redistribution layer
120‧‧‧結構 120‧‧‧ structure
122‧‧‧導電通孔 122‧‧‧ conductive through holes
124‧‧‧導電跡線 124‧‧‧conductive traces
126‧‧‧導電接觸墊 126‧‧‧Electrical contact pads
130‧‧‧載體底材 130‧‧‧ Carrier substrate
132‧‧‧結構 132‧‧‧ structure
138‧‧‧結構 138‧‧‧ structure
140‧‧‧斷裂表面 140‧‧‧Fracture surface
144‧‧‧重分佈層 144‧‧‧ redistribution layer
146‧‧‧結構 146‧‧‧ structure
150‧‧‧導電通孔 150‧‧‧ conductive vias
152‧‧‧導電跡線 152‧‧‧conductive traces
154‧‧‧導電接觸墊 154‧‧‧Electrical contact pads
160‧‧‧電接點 160‧‧‧Electrical contacts
162‧‧‧結構 162‧‧‧structure
164‧‧‧介電材料 164‧‧‧ dielectric materials
166‧‧‧導電金屬 166‧‧‧Conductive metal
170‧‧‧居間結構 170‧‧ intervening structure
171‧‧‧導電部件 171‧‧‧Electrical parts
172‧‧‧積體電路元件 172‧‧‧Integrated circuit components
174‧‧‧結構 174‧‧‧structure
176‧‧‧結構 176‧‧‧structure
180‧‧‧導電部件 180‧‧‧Electrical parts
182‧‧‧結構或元件 182‧‧‧ Structure or component
184‧‧‧結構 184‧‧‧ structure
186‧‧‧導電凸塊 186‧‧‧Electrical bumps
雖然本說明書以申請專利範圍作結，且該些申請專利範圍明確指出及主張可認為是本發明實施例者，但配合所附圖式閱讀本發明實施例某些範例之敘述，將更容易確知本發明實施例之優點，在所附圖式中：圖1為一材料層之簡化截面圖，該材料層係用於在一可回收底材上形成一居間結構，在該材料層與該可回收底材間具有一可分離界面；圖2為一簡化截面圖，其概要呈現多個導電貫孔形成並穿透圖1所示結構之材料層，以構成該居間結構之至少一部分；圖3為一簡化截面圖，其概要呈現在就該材料層而言相反於該可回收底材之一面，一重分佈層形成於圖2所示之居間結構之材料層上方； 圖4為一簡化截面圖，其概要呈現在就該材料層而言相反於該可回收底材之一面，一載體底材暫時鍵結於圖3所示之居間結構之材料層上方；圖5為一簡化截面圖，其概要呈現該居間結構之材料層沿著該居間結構與該可回收底材間之可分離界面，從圖4所示之可回收底材分離；圖6為一簡化截面圖，其概要呈現在就該材料層而言相反於該載體底材之一面，另一重分佈層形成於圖5所示之居間結構之材料層上方；圖7為一簡化截面圖，其概要呈現在就該材料層而言相反於該載體底材之一面，多個電接點形成於圖6所示之居間結構之材料層上方；圖8為一簡化截面圖，其概要呈現在就該居間結構而言相反於該載體底材之一面，一積體電路元件在結構上及電性上耦合至圖7所示之結構；圖9呈現該載體底材從圖8之結構移除；以及圖10呈現在就該居間結構而言相反於該積體電路元件之一面，另一結構或元件在結構上及電性上耦合至該居間結構。 While the specification has been described in the specification of the invention, and the claims are intended to be construed as the embodiment of the invention, Advantages of the embodiments of the present invention, in the drawings: FIG. 1 is a simplified cross-sectional view of a material layer for forming an intervening structure on a recyclable substrate, There is a separable interface between the recovered substrates; FIG. 2 is a simplified cross-sectional view schematically showing a plurality of conductive vias formed through the material layer of the structure shown in FIG. 1 to form at least a portion of the intervening structure; FIG. a simplified cross-sectional view, the outline of which is opposite to one side of the recyclable substrate in terms of the material layer, and a redistribution layer formed over the material layer of the intervening structure shown in FIG. 2; Figure 4 is a simplified cross-sectional view schematically showing one side of the recyclable substrate in relation to the material layer, a carrier substrate temporarily bonded over the material layer of the intervening structure shown in Figure 3; Figure 5 In a simplified cross-sectional view, the outline of the material layer of the intervening structure is along the separable interface between the intervening structure and the recyclable substrate, separated from the recyclable substrate shown in FIG. 4; FIG. 6 is a simplified cross section. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a schematic cross-sectional view of a layer of a carrier material as shown in FIG. In the case of the material layer opposite to one side of the carrier substrate, a plurality of electrical contacts are formed over the material layer of the intervening structure shown in FIG. 6; FIG. 8 is a simplified cross-sectional view, the outline of which is presented in the intervening Structurally opposite to one side of the carrier substrate, an integrated circuit component is structurally and electrically coupled to the structure shown in FIG. 7; FIG. 9 shows the carrier substrate removed from the structure of FIG. 8; 10 is presented in terms of the intervening structure as opposed to the product The circuit elements on one side, the other structures or elements coupled to the intermediate structure and upper structure on electrically.
100‧‧‧結構 100‧‧‧ structure
102‧‧‧可回收底材 102‧‧‧Recyclable substrate
104‧‧‧材料層 104‧‧‧Material layer
106‧‧‧可分離界面 106‧‧‧ separable interface
107‧‧‧中間材料 107‧‧‧Intermediate materials
108‧‧‧空隙 108‧‧‧ gap
Claims (20)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/397,954 US8970045B2 (en) | 2011-03-31 | 2012-02-16 | Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices |
| FR1251871A FR2987494B1 (en) | 2012-02-29 | 2012-02-29 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES COMPRISING INTERPOSITION DEVICES WITH CONDUCTIVE INTERCONNECTION HOLES, AND RELATED STRUCTURES AND DEVICES |
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| Publication Number | Publication Date |
|---|---|
| TW201336000A TW201336000A (en) | 2013-09-01 |
| TWI573203B true TWI573203B (en) | 2017-03-01 |
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| TW101147266A TWI573203B (en) | 2012-02-16 | 2012-12-13 | Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices |
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| KR (2) | KR20130094750A (en) |
| CN (1) | CN103258782B (en) |
| TW (1) | TWI573203B (en) |
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| KR102206937B1 (en) * | 2017-11-03 | 2021-01-25 | 주식회사 네패스 | Interposer for semiconductor package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040056344A1 (en) * | 2001-11-22 | 2004-03-25 | Tsuyoshi Ogawa | Multi-chip circuit module and method for producing the same |
| US20060177173A1 (en) * | 2005-02-04 | 2006-08-10 | Sioptical, Inc. | Vertical stacking of multiple integrated circuits including SOI-based optical components |
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| CN100487898C (en) * | 2001-11-05 | 2009-05-13 | 佐伊科比株式会社 | Solid-state image sensor and its production method |
| JP4179186B2 (en) * | 2004-02-25 | 2008-11-12 | ソニー株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE |
| US7098070B2 (en) * | 2004-11-16 | 2006-08-29 | International Business Machines Corporation | Device and method for fabricating double-sided SOI wafer scale package with through via connections |
| CN101128761A (en) * | 2005-02-04 | 2008-02-20 | 斯欧普迪克尔股份有限公司 | Vertical stacking of multiple integrated circuits including SOI-based optical components |
| KR101152822B1 (en) * | 2009-07-31 | 2012-06-12 | 에스케이하이닉스 주식회사 | Fabricating method for wafer |
| JP5729932B2 (en) * | 2010-07-22 | 2015-06-03 | キヤノン株式会社 | Method of filling metal into substrate through hole |
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2012
- 2012-12-13 TW TW101147266A patent/TWI573203B/en active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040056344A1 (en) * | 2001-11-22 | 2004-03-25 | Tsuyoshi Ogawa | Multi-chip circuit module and method for producing the same |
| US20060177173A1 (en) * | 2005-02-04 | 2006-08-10 | Sioptical, Inc. | Vertical stacking of multiple integrated circuits including SOI-based optical components |
Also Published As
| Publication number | Publication date |
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| CN103258782B (en) | 2017-10-20 |
| KR20200083398A (en) | 2020-07-08 |
| TW201336000A (en) | 2013-09-01 |
| CN103258782A (en) | 2013-08-21 |
| KR102164539B1 (en) | 2020-10-12 |
| KR20130094750A (en) | 2013-08-26 |
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