TWI569279B - Memory protection device and method - Google Patents

Memory protection device and method Download PDF

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TWI569279B
TWI569279B TW104133858A TW104133858A TWI569279B TW I569279 B TWI569279 B TW I569279B TW 104133858 A TW104133858 A TW 104133858A TW 104133858 A TW104133858 A TW 104133858A TW I569279 B TWI569279 B TW I569279B
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memory
bit group
redundant bit
input data
column
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TW104133858A
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TW201714183A (en
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黃立仁
楊智仁
張雍昌
紀坤明
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財團法人工業技術研究院
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Priority to TW104133858A priority Critical patent/TWI569279B/en
Priority to CN201510759612.3A priority patent/CN106601298A/en
Priority to US14/952,912 priority patent/US10268547B2/en
Priority to DE102015226073.9A priority patent/DE102015226073B3/en
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Publication of TW201714183A publication Critical patent/TW201714183A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1417—Boot up procedures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0787—Storage of error reports, e.g. persistent data storage, storage using memory protection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Computer Hardware Design (AREA)

Description

記憶體保護裝置與方法 Memory protection device and method

本案是有關於一種記憶體保護裝置與方法。 This case is related to a memory protection device and method.

非揮發性記憶體(Non-volatile memory)在多種系統上愈來愈常見。因此，從航太領域到車用領域無不對如何能更妥善地保護非揮發性記憶體的內部資料進行研究。由文獻以及研究報告得知，來自因IC封裝材質產生的輻射線(Radiation)或是由外太空所傳來的宇宙射線(Cosmic ray)對於非揮發性記憶體的內部資料有可能會造成影響，甚至造成系統運作的不順暢或者錯誤。 Non-volatile memory is becoming more and more common in many systems. Therefore, from the aerospace field to the automotive field, there is no research on how to better protect the internal data of non-volatile memory. According to the literature and research reports, Radiation from IC packaging materials or Cosmic ray from outer space may affect the internal data of non-volatile memory. It even caused the system to operate unsmoothly or incorrectly.

故而，需要能有一種記憶體保護方法，能有效除錯(error correction)及/或偵錯(error detection)，以保護記憶體的內部資料。 Therefore, it is necessary to have a memory protection method that can effectively correct the error and/or error detection to protect the internal data of the memory.

本案係有關於一種記憶體保護裝置與方法，其能根據所輸入的資料，來選擇相對應的編碼方式。 The present invention relates to a memory protection device and method, which can select a corresponding coding mode according to the input data.

根據本案一實施例，提出一種記憶體保護裝置，用以保護一記憶體。該記憶體保護裝置包括：一過濾單元與一編碼單元。過濾單元搜尋一輸入資料，以依照該輸入資料之一位元組 成樣式，輸出一編碼選擇信號。編碼單元根據由該過濾單元所輸出的該編碼選擇信號，從複數種編碼方式中選擇針對該輸入資料所要採用的一或多個編碼方式。 According to an embodiment of the present invention, a memory protection device is provided for protecting a memory. The memory protection device comprises: a filtering unit and a coding unit. The filtering unit searches for an input data to follow a byte of the input data In the style, an encoding selection signal is output. The encoding unit selects one or more encoding modes to be used for the input data from the plurality of encoding modes according to the encoding selection signal output by the filtering unit.

根據本案另一實施例，提出一種記憶體保護方法， 用以保護一記憶體，包括：搜尋一輸入資料，以依照該輸入資料之一位元組成樣式，輸出一編碼選擇信號；以及根據由該過濾單元所輸出的該編碼選擇信號，從複數種編碼方式中選擇針對該輸入資料所要採用的一或多個編碼方式。 According to another embodiment of the present disclosure, a memory protection method is proposed. For protecting a memory, comprising: searching for an input data, outputting an encoding selection signal according to a bit composition pattern of the input data; and selecting a plurality of encodings according to the encoding selection signal output by the filtering unit In the mode, one or more encoding methods to be used for the input data are selected.

為了對本案之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式，作詳細說明如下： In order to better understand the above and other aspects of the present invention, the following specific embodiments, together with the drawings, are described in detail below:

50‧‧‧記憶體 50‧‧‧ memory

100‧‧‧記憶體保護裝置 100‧‧‧ memory protection device

110‧‧‧過濾單元 110‧‧‧Filter unit

120‧‧‧編碼單元 120‧‧‧ coding unit

130‧‧‧開機檢查單元 130‧‧‧Power inspection unit

210‧‧‧第一冗餘位元群組 210‧‧‧First redundant bit group

220、230‧‧‧第二冗餘位元群組 220, 230‧‧‧Second redundant bit group

240‧‧‧填補位元群組 240‧‧‧ Filling the bit group

250‧‧‧第三冗餘位元群組 250‧‧‧ Third redundant bit group

310-360‧‧‧錯誤 310-360‧‧‧Error

400‧‧‧記憶體保護裝置 400‧‧‧ memory protection device

410‧‧‧過濾單元 410‧‧‧Filter unit

420‧‧‧編碼單元 420‧‧‧ coding unit

430‧‧‧開機檢查單元 430‧‧‧Power inspection unit

440‧‧‧冗餘位元排列單元 440‧‧‧Redundant bit arrangement unit

450‧‧‧記憶體控制單元 450‧‧‧Memory Control Unit

IN‧‧‧輸入資料 IN‧‧‧ Input data

EN_SEL‧‧‧編碼選擇信號 EN_SEL‧‧‧ code selection signal

ER‧‧‧錯誤訊號 ER‧‧‧ error signal

第1圖顯示根據本案一實施例之記憶體保護裝置之功能方塊圖。 1 is a functional block diagram of a memory protection device according to an embodiment of the present invention.

第2A圖至第2F圖顯示本案實施例之編碼。 Figures 2A through 2F show the encoding of the embodiment of the present invention.

第3A圖至第3C圖分別顯示本案一實施例之偵錯及/或除錯結果。 Figures 3A through 3C show the debug and/or debug results of an embodiment of the present invention, respectively.

第4圖顯示根據本案另一實施例的記憶體保護裝置之功能方塊圖。 Fig. 4 is a block diagram showing the function of a memory protection device according to another embodiment of the present invention.

第5圖顯示根據本案另一實施例的記憶體保護方法之流程圖。 Fig. 5 is a flow chart showing a memory protection method according to another embodiment of the present invention.

本說明書的技術用語係參照本技術領域之習慣用 語，如本說明書對部分用語有加以說明或定義，該部分用語之解釋係以本說明書之說明或定義為準。對於該領域習見的技術或原理，若不涉及本揭露之技術特徵，將不予贅述。本揭露之各個實施例分別具有一或多個技術特徵。在可能實施的前提下，本技術領域具有通常知識者可選擇性地實施任一實施例中部分或全部的技術特徵，或者選擇性地將這些實施例中部分或全部的技術特徵加以組合。 The technical terms of this specification refer to the customary use in the technical field. For the purpose of this specification, some terms are explained or defined. The interpretation of the terms is based on the description or definition of this specification. The technical or principle of the prior art will not be described again if it does not involve the technical features of the disclosure. Various embodiments of the present disclosure each have one or more of the technical features. Those skilled in the art can selectively implement some or all of the technical features of any embodiment, or selectively combine some or all of the technical features of these embodiments, where possible.

現請參考第1圖，其顯示根據本案一實施例之記憶 體保護裝置之功能方塊圖。如第1圖所示，本案一實施例之記憶體保護裝置100可偵錯(error detection)及/或除錯(error correction)，以保護記憶體50的內部資料。在此以記憶體50為非揮發性記憶體為例做說明，但當知本案並不受限於此。 Referring now to Figure 1, there is shown a memory according to an embodiment of the present invention. Functional block diagram of the body protection device. As shown in FIG. 1, the memory protection device 100 of one embodiment of the present invention can detect error detection and/or error correction to protect the internal data of the memory 50. Here, the description is made by taking the memory 50 as a non-volatile memory as an example, but it is known that the present case is not limited thereto.

記憶體保護裝置100至少包括：過濾單元110、編 碼單元120與開機檢查單元130。 The memory protection device 100 includes at least: a filtering unit 110, The code unit 120 and the power-on checking unit 130.

過濾單元110搜尋輸入資料IN，以依照所搜尋到的 輸入資料的位元組成樣式(pattern)，輸出相對應的編碼選擇信號EN_SEL給編碼單元120。輸入資料的位元組成樣式的定義將於底下說明之。 The filtering unit 110 searches for the input data IN to follow the searched The bit of the input material constitutes a pattern, and the corresponding code selection signal EN_SEL is output to the encoding unit 120. The definition of the bit composition style of the input data will be explained below.

編碼單元120根據由過濾單元110所輸出的編碼選 擇信號EN_SEL，從多種編碼方式中選擇針對該輸入資料IN所要採用的編碼方式。在對一筆輸入資料編碼時，可以採用一或多種不同編碼方式來進行編碼。 The encoding unit 120 selects according to the encoding output by the filtering unit 110. The signal EN_SEL is selected to select the encoding method to be used for the input data IN from a plurality of encoding modes. When encoding an input data, one or more different encoding methods may be used for encoding.

開機檢查單元130，在開機時，於電子裝置(未示出) 的處理器(未示出)存取記憶體50之前，執行開機檢查。如果檢查到錯誤的話，開機檢查單元130發出錯誤信號ER。如果檢查結果為正確的話，開機檢查單元130通知處理器，以讓處理器開始存取記憶體50。開機檢查的細節將於底下說明之。 The booting check unit 130, when turned on, is in an electronic device (not shown) A boot check is performed before the processor (not shown) accesses the memory 50. The boot check unit 130 issues an error signal ER if an error is detected. If the check result is correct, the power-on checking unit 130 notifies the processor to let the processor start accessing the memory 50. The details of the power-on check will be explained below.

現將說明本案實施例如何進行編碼，請參考第2A 圖至第2F圖。 Now how to encode the embodiment of this case, please refer to section 2A Figure to Figure 2F.

第2A圖顯示輸入資料IN之一例。在此以輸入資料 IN為32*17為例做說明，但當知本案並不受限於此。 Fig. 2A shows an example of the input data IN. Enter data here IN is 32*17 as an example, but it is not limited to this case.

第2B圖顯示，對輸入資料IN進行第一編碼，以得 到第一冗餘位元群組210。在此，對輸入資料IN進行第一編碼例如但不受限於，以偶同位檢查(even parity check)為例做說明。詳細地說，對輸入資料的各直行0-31分別進行偶同位檢查，以得到對應於各直行的各別1個檢查位元(parity bit)，這些檢查位元即為第一冗餘位元群組210。第一冗餘位元群組210寫入至記憶體的列17之中。以直行0為例，由於直行0具有15個“1”，所以，直行0的檢查位元為“1”(被寫入至列17的位址0)。其餘可依此類推。 Figure 2B shows that the first encoding of the input data IN is obtained. To the first redundant bit group 210. Here, the first encoding of the input data IN is, for example, but not limited to, an example of an even parity check is taken as an example. In detail, each of the straight lines 0-31 of the input data is subjected to an even parity check to obtain a respective parity bit corresponding to each straight line, and the check bits are the first redundant bit. Group 210. The first redundant bit group 210 is written into the column 17 of the memory. Taking straight line 0 as an example, since straight line 0 has 15 "1"s, the check bit of straight line 0 is "1" (written to address 0 of column 17). The rest can be deduced by analogy.

第2C圖顯示，對輸入資料IN進行第二編碼，以得 到第二冗餘位元群組220。在此，對輸入資料IN進行第二編碼例如但不受限於，以偶同位檢查及/或錯誤檢查碼(ECC，error correction code)為例做說明。對輸入資料的各橫列0-16分別進行 搜尋，以了解各橫列的位元組成樣式，來決定要對各橫列採用各自編碼方式(此操作乃是由第1圖的過濾單元110所進行)。以橫列0為例，橫列0包括1個位元1與31個位元0。過濾單元110決定橫列0的位元0的比率超過臨界值(例如但不受限於，為50%)，所以，過濾單元110會發出編碼選擇信號EN_SEL給編碼單元120，告知編碼單元120要對橫列0進行7位元ECC編碼(編碼結果為1010011，其位元成本較高)。再以橫列1為例，橫列1包括32個位元1與0個位元0。過濾單元110決定橫列1的位元0的比率低於臨界值。過濾單元110會發出編碼選擇信號EN_SEL給編碼單元120，告知編碼單元120要對橫列0進行偶同位檢查編碼(編碼結果為0，其位元成本較低)。輸入資料IN的第二編碼結果為第二冗餘位元群組220。行C0-C6乃是用於暫時顯示編碼結果。也就是說，在本案實施例中，對該輸入資料IN的各列，所用的編碼方式可以相同或不同，由各列的位元組成樣式來決定。 Figure 2C shows that the input data IN is second encoded to obtain Go to the second redundant bit group 220. Here, the second encoding of the input data IN is, for example, but not limited to, an example of an even parity check and/or an error correction code (ECC). Perform each row 0-16 of the input data separately Search to understand the bit composition of each row to determine the respective encoding mode for each row (this operation is performed by the filtering unit 110 of Fig. 1). Taking row 0 as an example, row 0 includes 1 bit 1 and 31 bits 0. The filtering unit 110 determines that the ratio of the bit 0 of the row 0 exceeds a critical value (for example, but not limited to, 50%), so the filtering unit 110 issues an encoding selection signal EN_SEL to the encoding unit 120, informing the encoding unit 120 that The 7-bit ECC encoding is performed on the row 0 (the encoding result is 1010011, and the bit cost is high). Taking the column 1 as an example, the column 1 includes 32 bits 1 and 0 bits 0. Filter unit 110 determines that the ratio of bit 0 of row 1 is below a critical value. The filtering unit 110 sends an encoding selection signal EN_SEL to the encoding unit 120, informing the encoding unit 120 to perform even parity checking encoding on the row 0 (the encoding result is 0, and the bit cost is low). The second encoded result of the input data IN is the second redundant bit group 220. Lines C0-C6 are used to temporarily display the result of the encoding. That is to say, in the embodiment of the present invention, the coding modes used for the columns of the input data IN may be the same or different, and are determined by the bit composition pattern of each column.

在本案其他可能實施例中，尚可以有其他不同種編 碼方式。例如，臨界值可以設成25%與75%。如果橫列的位元0的比率介於0-25%的話，則對該橫列進行偶同位檢查編碼；如果橫列的位元0的比率介於25-75%的話，則對該橫列進行檢驗和(checksum)編碼；以及，如果橫列的位元0的比率介於75%-100%的話，則對該橫列進行ECC編碼。雖然上例以決定位元0的比率為例做說明，但當知本案其他可能實施例中，也可以決定位元1 的比率，來決定對該列資料的編碼方式，此亦在本案精神範圍內。 In other possible embodiments of the case, there are other different types of Code method. For example, the threshold can be set to 25% and 75%. If the ratio of the bit 0 of the row is between 0-25%, then the rank is checked by the parity check; if the ratio of the rank 0 of the rank is between 25-75%, then the rank is A checksum encoding is performed; and, if the ratio of the bit 0 of the row is between 75% and 100%, the course is ECC encoded. Although the above example takes the ratio of the bit 0 as an example, it can be determined that in other possible embodiments of the present case, the bit 1 can also be determined. The ratio is used to determine the way in which the information is coded. This is also within the spirit of the case.

也就是說，在本案一實施例中，針對橫列的位元組 成樣式(亦即，其位元0的比率)，決定要對該橫列所採用的編碼方式。本案一實施例採用多種混合編碼方式的原因在於，經研究顯示，在記憶體之中，位元0與位元1的錯誤發生率有所不同，且彼此不對稱。也就是說，位元0錯誤地變成位元1的錯誤率(受外界(例如輻射線)影響，位元0被錯誤地儲存成位元1)較容易發生，而位元1錯誤地變成位元0的錯誤則較不易發生。因此，在本案實施例中，於進行編碼之前，先針對輸入內容進行搜尋(掃描)，判別要被編碼的資料是否容易被外界影響(亦即，判別資料受外界影響的程度，如果資料的位元0愈多個的話，則該列資料受外界影響程度愈高；相反地，如果資料的位元1愈多個的話，則該列資料受外界影響程度愈低)。如果判別出要被編碼的資料容易被外界影響(也就是說，要被編碼的橫列包括比較多的位元0)的話，則在編碼時，利用較多的位元來保護之(例如7位元ECC編碼，其位元成本較高)，自然地，其保護成本較高。相反地，如果判別出要被編碼的資料比較不容易被外界影響(也就是說，要被編碼的橫列包括比較少的位元0)的話，則在編碼時，利用較少的位元來保護之(例如1位元偶同位檢查，其位元成本較低)，但其保護成本較低。本案實施例在編碼保護能力與保護成本之間取得平衡。 That is to say, in an embodiment of the present case, the byte for the horizontal column The pattern (i.e., the ratio of its bit 0) determines the encoding used for the column. The reason why a hybrid encoding method is adopted in one embodiment of the present invention is that, in research, in the memory, the error occurrence rates of bit 0 and bit 1 are different and are asymmetrical to each other. That is to say, bit 0 erroneously becomes the error rate of bit 1 (affected by the outside world (for example, radiation), bit 0 is incorrectly stored as bit 1), and bit 1 is erroneously changed. The error of 0 is less likely to occur. Therefore, in the embodiment of the present invention, before the encoding is performed, the input content is searched (scanned) to determine whether the data to be encoded is easily affected by the outside world (that is, the degree to which the data is affected by the outside world, if the data bit is If there are more than 0 yuan, the higher the degree of influence of the data on the list; on the contrary, if there are more bits 1 of the data, the lesser the data is affected by the outside world. If it is discriminated that the data to be encoded is easily affected by the outside world (that is, the row to be encoded includes a relatively large number of bits 0), then more bits are used to protect it during encoding (for example, 7) Bit ECC coding, which has a higher bit cost), naturally, its protection cost is higher. Conversely, if it is discriminated that the data to be encoded is less susceptible to external influences (that is, the row to be encoded includes fewer bits 0), then fewer bits are used in encoding. Protection (for example, 1-bit parity parity check, its bit cost is lower), but its protection cost is lower. The embodiment of the present invention strikes a balance between coding protection capability and protection cost.

在本案另一可能實施例中，則可以根據輸入資料的 各列資料來得到該列資料的權重，再依據權重來產生編碼選擇信號(決定編碼方式)。例如，如果一列資料中，所有位元全為1的話，則權重設為0；在該列資料中，位元0的個數超過16(亦即超過一半)的話，則權重設為大於或等於16；在該列資料中，所有位元全為0的話，則權重設為32。雖然上例以決定該列資料的位元0的權重為例做說明，但當知本案其他可能實施例也可以決定該列資料的位元1的權重，此亦在本案精神範圍內。 In another possible embodiment of the present case, it may be based on input data. Each column of data obtains the weight of the column of data, and then generates a code selection signal according to the weight (determines the coding mode). For example, if all the bits in a column of data are all 1, the weight is set to 0; in the column data, if the number of bit 0 exceeds 16 (that is, more than half), the weight is set to be greater than or equal to 16; In the column data, if all the bits are 0, the weight is set to 32. Although the above example takes the weight of the bit 0 which determines the data of the column as an example, it can be determined that other possible embodiments of the present case can also determine the weight of the bit 1 of the listed data, which is also within the spirit of the present case.

根據所設的權重，來選擇相對應的編碼方式。例如 但不受限於，權重小於等於3的話，則採用1位元同位元檢查(1-bit parity check)。權重大於等於4但小於8的話，則採用2位元同位元檢查(2-bit parity check)。權重大於等於8但小於16的話，則採用4位元ECC。權重大於等於16的話，則採用5位元ECC。 亦即，位元組成樣式包括位元0及/或1的權重。 According to the set weight, the corresponding coding method is selected. E.g However, it is not limited to, if the weight is less than or equal to 3, a 1-bit parity check is used. If the weight is greater than or equal to 4 but less than 8, then a 2-bit parity check is used. If the weight is greater than or equal to 8 but less than 16, then 4-bit ECC is used. If the weight is greater than or equal to 16, then the 5-bit ECC is used. That is, the bit composition pattern includes the weights of the bits 0 and/or 1.

另外，雖然在上述說明中，先做直行編碼，再做橫 列編碼，但本案並不受限於此。在本案其他可能實施例中，也可先做橫列編碼，再做直行編碼，此皆在本案精神範圍內。 In addition, although in the above description, first do straight code, then cross Column coding, but the case is not limited to this. In other possible embodiments of the present case, it is also possible to do the horizontal coding first and then the straight line coding, which are all within the spirit of the case.

在第2D圖中，將暫時顯示於行C0-C6內的第二冗 餘位元群組220真正寫入至記憶體的列18至列19之中，成為第二冗餘位元群組230。詳細地說，對列0的編碼結果1010011寫入至列18的位址0-6之內，對列1的編碼結果0寫入至列18的位址7之內，其餘可依此類推。 In the 2D diagram, the second redundancy will be temporarily displayed in lines C0-C6. The remaining bit group 220 is actually written into the columns 18 to 19 of the memory to become the second redundant bit group 230. In detail, the encoding result 1010011 of column 0 is written into the address 0-6 of the column 18, and the encoding result 0 of the column 1 is written into the address 7 of the column 18, and the rest can be deduced by analogy.

如果列19未被第二冗餘位元群組220/230填滿的 話，則在本案實施例中，可以適當地填入0或1於列19的空白位址，如第2E圖的填補位元群組240所示。 If column 19 is not filled by the second redundant bit group 220/230 In this case, in the embodiment of the present invention, a blank address of 0 or 1 in column 19 may be appropriately filled, as shown in the padding group 240 of FIG. 2E.

在本案其他可能實施例中，亦可以對列17-19進行 編碼，並將編碼結果寫入至記憶體之中。 In other possible embodiments of the present case, columns 17-19 can also be performed. Encode and write the encoded result to the memory.

於第2F圖中，對第一冗餘位元群組210、第二冗餘 位元群組230及/或該填補位元群組240進行編碼(例如但不受限於，偶同位檢查)以得到第三冗餘位元群組250，並將第三冗餘位元群組250寫入至列20之中。詳細地說，對直行0的位址20-位址22(分別是111)進行偶同位檢查編碼以得到編碼結果(位元1)，並將此位元1寫入至列20的位址0。其餘可依此類推。亦即，在本案實施例中，除了對輸入資料的橫列與直行分別進行編碼以進行保護外，更對編碼後結果再次進行編碼。 In the 2F figure, the first redundant bit group 210, the second redundancy The bit group 230 and/or the padding bit group 240 is encoded (eg, but not limited to, even parity check) to obtain a third redundant bit group 250, and the third redundant bit group Group 250 is written into column 20. In detail, the address 20-bit address 22 of the straight line 0 (111 is respectively 111) is subjected to even parity check coding to obtain a coding result (bit 1), and this bit 1 is written to the address 0 of the column 20. . The rest can be deduced by analogy. That is to say, in the embodiment of the present invention, in addition to encoding the row and the straight line of the input data for protection, the encoded result is encoded again.

第3A圖至第3C圖分別顯示本案一實施例之偵錯及 /或除錯結果。第3A圖顯示本案一實施例之單一錯誤偵錯及除錯(single error detection and correction)。第3B圖顯示本案一實施例之多錯誤偵錯及除錯(multiple error detection and correction)。第3C圖顯示本案一實施例之多錯誤偵錯但無法除錯(multiple error detection and not correction)。 3A to 3C respectively show the debugging of an embodiment of the present invention and / or debug results. Figure 3A shows a single error detection and correction in an embodiment of the present invention. Figure 3B shows multiple error detection and correction in one embodiment of the present invention. Figure 3C shows multiple error detection and not correction in one embodiment of the present invention.

在第3A圖中，C代表由所讀出的資料進行運算而 得，而S則代表存於記憶體中的冗餘位元。比較C值與S值，即可發現是否發生同位元檢查錯誤(parity check error)。如果資料當中存在1個錯誤310，藉由應用本案實施例後，可利用橫列的C 值與S值與直行的C值與S值來找出該錯誤310，並校正之。 In Figure 3A, C represents the operation of the data read. Yes, and S represents the redundant bits stored in the memory. Comparing the C value with the S value, you can see if a parity check error has occurred. If there is one error 310 in the data, by applying the embodiment of the present case, the horizontal C can be utilized. The value and the S value and the straight C value and the S value are used to find the error 310 and correct it.

相同地，如第3B圖所示，如果資料當中存在多個 錯誤320-340，藉由應用本案實施例後，可利用橫列的C值與S值與直行的C值與S值來找出錯誤320-340，並校正之。 Similarly, as shown in Figure 3B, if there are multiple data in the data Errors 320-340, by applying the embodiment of the present invention, can use the C value and the S value of the course and the C value and the S value of the straight line to find the error 320-340 and correct it.

相同地，如第3B圖所示，如果資料當中存在多個 錯誤320-340，藉由應用本案實施例後，可利用橫列的C值與S值與直行的C值與S值來找出錯誤320-340，並校正之。如果多個錯誤不在同一列也不在同一行的話，則本案一實施例可以偵錯並除錯之。 Similarly, as shown in Figure 3B, if there are multiple data in the data Errors 320-340, by applying the embodiment of the present invention, can use the C value and the S value of the course and the C value and the S value of the straight line to find the error 320-340 and correct it. If multiple errors are not in the same column or in the same row, then an embodiment of the present invention can detect and debug.

如第3C圖所示，如果資料當中存在多個錯誤350 或360，藉由應用本案實施例後，可利用橫列的C值與S值與直行的C值與S值來找出錯誤350與360，但無法校正之。以錯誤350為例，應用本案實施例後，可以找到發生錯誤的位置，但無法校正之。 As shown in Figure 3C, if there are multiple errors in the data 350 Or 360, by applying the embodiment of the present invention, the C value and the S value of the course and the C value and the S value of the straight line can be used to find the errors 350 and 360, but cannot be corrected. Taking the error 350 as an example, after applying the embodiment of the present case, the location where the error occurred can be found, but it cannot be corrected.

第3A圖至第3C圖也一樣可以應用至第一冗餘位元 群組210、第二冗餘位元群組230、填補位元群組240及/或第三冗餘位元群組250的偵錯及/或除錯，其細節在此不詳述。 Figures 3A through 3C can also be applied to the first redundant bit. The debugging and/or debugging of the group 210, the second redundant bit group 230, the padding bit group 240, and/or the third redundant bit group 250 are not detailed herein.

現請參考第4圖，其顯示根據本案另一實施例的記 憶體保護裝置之功能方塊圖。如第4圖所示，記憶體保護裝置400包括：過濾單元410、編碼單元420、開機檢查單元430、冗餘位元排列單元440與記憶體控制單元450。過濾單元410、編碼單元420與開機檢查單元430可相同或相似於第1圖的過濾單元 110、編碼單元120與開機檢查單元130，其細節在此省略。 Please refer to FIG. 4, which shows a record according to another embodiment of the present invention. Functional block diagram of the memory protection device. As shown in FIG. 4, the memory protection device 400 includes a filtering unit 410, an encoding unit 420, a power-on checking unit 430, a redundancy bit array unit 440, and a memory control unit 450. The filtering unit 410, the encoding unit 420, and the power-on checking unit 430 may be the same as or similar to the filtering unit of FIG. 110, the encoding unit 120 and the booting check unit 130, the details of which are omitted here.

當過濾單元410接收到輸入資料IN時，過濾單元 410搜尋/掃描輸入資料IN的位元組成樣式，以輸出編碼選擇信號EN_SEL給編碼單元420。編碼單元420根據編碼選擇信號EN_SEL，從多個編碼方式中選擇適合的一或多個編碼方式來對輸入資料IN進行編碼。 When the filtering unit 410 receives the input data IN, the filtering unit 410 searches/scans the bit composition of the input data IN to form a code selection signal EN_SEL to the encoding unit 420. The encoding unit 420 encodes the input material IN by selecting an appropriate one or more encoding modes from the plurality of encoding modes according to the encoding selection signal EN_SEL.

冗餘位元排列單元440收集編碼單元420的編碼結 果(如上圖中的第一冗餘位元群組210、第二冗餘位元群組230、填補位元群組240，及/或第三冗餘位元群組250)，並排列成符合記憶體50的資料寬度，及產生相對應的位址。 The redundancy bit arrangement unit 440 collects the coding knot of the coding unit 420. (such as the first redundant bit group 210, the second redundant bit group 230, the padding bit group 240, and/or the third redundant bit group 250) in the above figure, and arranged The data width of the memory 50 is matched, and the corresponding address is generated.

記憶體控制單元450將輸入資料IN寫入至記憶體 50，並將冗餘位元排列單元440所對齊好的編碼結果(如上圖中的第一冗餘位元群組210、第二冗餘位元群組230、填補位元群組240，及/或第三冗餘位元群組250)，依據其相對應位址來寫入至記憶體50。 The memory control unit 450 writes the input data IN to the memory 50, and the encoded result of the redundant bit arrangement unit 440 is aligned (the first redundant bit group 210, the second redundant bit group 230, the padding bit group 240 in the above figure, and / or the third redundant bit group 250) is written to the memory 50 according to its corresponding address.

於開機時，開機檢查單元430從記憶體50中讀出輸 入資料IN及其相應的編碼結果；開機檢查單元430令過濾單元410、編碼單元420與冗餘位元排列單元440進行其相關操作，並將操作結果回報給開機檢查單元430；開機檢查單元430比對由記憶體50所讀出的輸入資料IN及其相應的編碼結果，以及過濾單元410、編碼單元420與冗餘位元排列單元440的操作結果，以檢查是否有發生錯誤。如果有發生錯誤的話，開機檢查單元430 發出錯誤信號ER(例如發生處理器(未示出))。如果檢查結果為正確的話，開機檢查單元430讓處理器存取記憶體50。 When the power is turned on, the power-on checking unit 430 reads out the memory from the memory 50. The data entry IN and its corresponding coded result; the boot check unit 430 causes the filter unit 410, the encoding unit 420 and the redundant bit array unit 440 to perform related operations thereof, and returns the operation result to the boot check unit 430; the boot check unit 430 The input data IN read by the memory 50 and its corresponding encoding result, and the operation results of the filtering unit 410, the encoding unit 420, and the redundancy bit array unit 440 are compared to check whether an error has occurred. If there is an error, the boot check unit 430 An error signal ER is issued (eg, a processor (not shown) is generated). The boot check unit 430 causes the processor to access the memory 50 if the check result is correct.

此外，在本案其他可能實施例中，記憶體保護裝置可以更包括：多個資料緩衝器，用以暫存待寫入的輸入資料IN。 In addition, in other possible embodiments of the present disclosure, the memory protection device may further include: a plurality of data buffers for temporarily storing the input data IN to be written.

現將說明本案一實施例的開機檢查流程。於開機檢查時，讀出存於記憶體中的第三冗餘位元群組250，以檢查第一冗餘位元群組210與第二冗餘位元群組220/230是否有錯誤存在。如果有誤的話，則校正之。如果發現錯誤，但無法校正的話，則代表開機檢查未通過，開機檢查單元130/430發出錯誤信號ER。 The boot check process of an embodiment of the present invention will now be described. At the power-on check, the third redundant bit group 250 stored in the memory is read to check whether the first redundant bit group 210 and the second redundant bit group 220/230 have errors. . If it is wrong, correct it. If an error is found but cannot be corrected, it means that the power-on check failed, and the power-on check unit 130/430 issues an error signal ER.

如果檢查結果無誤的話，則讀出第二冗餘位元群組220/230，以檢查記憶體50。發現錯誤的話，則校正之。如果發現錯誤但無法校正的話，則代表開機檢查未通過，開機檢查單元130/430發出錯誤信號ER。 If the result of the check is correct, the second redundant bit group 220/230 is read to check the memory 50. If you find an error, correct it. If an error is found but cannot be corrected, it means that the power-on check failed, and the power-on check unit 130/430 issues an error signal ER.

如果沒有發現記憶體50存在錯誤的話，讀出第一冗餘位元群組210，以檢查記憶體50，發現錯誤的話，則校正之。如果發現錯誤但無法校正的話，則代表開機檢查未通過，開機檢查單元130/430發出錯誤信號ER。 If the memory 50 is not found to be erroneous, the first redundant bit group 210 is read to check the memory 50, and if an error is found, it is corrected. If an error is found but cannot be corrected, it means that the power-on check failed, and the power-on check unit 130/430 issues an error signal ER.

當然，第二冗餘位元群組220/230與第一冗餘位元群組210的讀出順序可不限定之。如果檢查都沒有錯誤存在的話，代表通過開機檢查。 Of course, the readout order of the second redundant bit group 220/230 and the first redundant bit group 210 may not be limited. If there are no errors in the check, the representative checks through the boot.

現請參考第5圖，其顯示根據本案另一實施例的記憶體保護方法之流程圖。如第5圖所示，於步驟510中，搜尋一 輸入資料，以依照該輸入資料之一位元組成樣式，輸出一編碼選擇信號。步驟510之細節可如上所述，於此不重複。 Referring now to Figure 5, there is shown a flow chart of a method of memory protection in accordance with another embodiment of the present invention. As shown in FIG. 5, in step 510, a search is performed. The data is input to output an encoding selection signal according to a bit composition of the input data. The details of step 510 can be as described above and will not be repeated here.

於步驟520中，根據由該過濾單元所輸出的該編碼 選擇信號，從複數種編碼方式中選擇針對該輸入資料所要採用的一或多個編碼方式。步驟520之細節可如上所述，於此不重複。 In step 520, according to the encoding output by the filtering unit The selection signal selects one or more encoding modes to be used for the input data from a plurality of encoding modes. The details of step 520 can be as described above and will not be repeated here.

於本案其他實施例中，更提出一種記憶體解碼實現 方式。此記憶體解碼實現方式可用於解碼由本案上述實施例所編碼出的內容。記憶體解碼的細節於此省略。 In other embodiments of the present invention, a memory decoding implementation is proposed. the way. This memory decoding implementation can be used to decode the content encoded by the above embodiments of the present invention. The details of the memory decoding are omitted here.

由上述描述可知，在本案實施例中，依據(1)輸入資 料所包括的位元0的比率，及/或(2)輸入資料的位元0或1的權重，及/或(3)輸入資料受外界影響的程度，可以選擇相應的編碼方法(亦即，決定所產生的冗餘位元的位元數)，以達到編碼保護存效性與編碼成本之間的平衡。亦即，在本案一實施例中，位元組成樣式包括：位元0及/或位元1的比率，及/或，位元0及/或位元1的權重，及/或各列資料受外界影響的程度。 It can be seen from the above description that in the embodiment of the present invention, according to (1) input capital The ratio of the bit 0 included in the material, and/or (2) the weight of the bit 0 or 1 of the input data, and/or (3) the extent to which the input data is affected by the outside world, the corresponding coding method may be selected (ie The number of bits of the redundant bits generated is determined to achieve a balance between code protection and cost. That is, in an embodiment of the present invention, the bit composition pattern includes: a ratio of bit 0 and/or bit 1, and/or a weight of bit 0 and/or bit 1, and/or data of each column. The extent of external influence.

綜上所述，雖然本案已以實施例揭露如上，然其並非用以限定本案。本案所屬技術領域中具有通常知識者，在不脫離本案之精神和範圍內，當可作各種之更動與潤飾。因此，本案之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field of the present invention can make various changes and refinements without departing from the spirit and scope of the present case. Therefore, the scope of protection of this case is subject to the definition of the scope of the patent application attached.

50‧‧‧記憶體 50‧‧‧ memory

100‧‧‧記憶體保護裝置 100‧‧‧ memory protection device

110‧‧‧過濾單元 110‧‧‧Filter unit

120‧‧‧編碼單元 120‧‧‧ coding unit

130‧‧‧開機檢查單元 130‧‧‧Power inspection unit

IN‧‧‧輸入資料 IN‧‧‧ Input data

EN_SEL‧‧‧編碼選擇信號 EN_SEL‧‧‧ code selection signal

ER‧‧‧錯誤訊號 ER‧‧‧ error signal

Claims (14)

一種記憶體保護裝置，用以保護一記憶體，該記憶體保護裝置包括：一過濾單元，搜尋一輸入資料，以依照該輸入資料之一位元組成樣式，輸出一編碼選擇信號；以及一編碼單元，根據由該過濾單元所輸出的該編碼選擇信號，從複數種編碼方式中選擇針對該輸入資料所要採用的一或多個編碼方式；其中，該編碼單元對該輸入資料之各行進行一第一編碼，以得到一第一冗餘位元群組，並將該第一冗餘位元群組寫入至該記憶體；該編碼單元對該輸入資料之各列進行一第二編碼，以得到一第二冗餘位元群組，並將該第二冗餘位元群組寫入至該記憶體，其中，該第二編碼取決於各列之各別位元組成樣式；當將該第二冗餘位元群組寫入至該記憶體時，如果該第二冗餘位元群組未填滿一列的話，則填入一填補位元群組於該列之中，以填滿該列；以及對該第一冗餘位元群組、該第二冗餘位元群組及/或該填補位元群組進行編碼以得到一第三冗餘位元群組，並將該第三冗餘位元群組寫入至該記憶體。 A memory protection device for protecting a memory, the memory protection device comprising: a filtering unit for searching an input data to output a code selection signal according to a bit pattern of the input data; and an encoding And selecting, according to the code selection signal output by the filtering unit, one or more coding modes to be used for the input data from a plurality of coding modes; wherein the coding unit performs a first row on the input data An encoding to obtain a first redundant bit group, and writing the first redundant bit group to the memory; the encoding unit performs a second encoding on each column of the input data to Obtaining a second redundant bit group, and writing the second redundant bit group to the memory, wherein the second encoding depends on each bit composition pattern of each column; When the second redundant bit group is written to the memory, if the second redundant bit group is not filled with a column, a padding bit group is filled in the column to fill up The column; and the first redundancy The bit group, the second redundant bit group, and/or the padding bit group are encoded to obtain a third redundant bit group, and the third redundant bit group is written To the memory. 如申請專利範圍第1項所述之記憶體保護裝置，其中，該過濾單元搜尋該輸入資料之各列資料，以依照該輸入資料 之各列資料之該各別位元組成樣式，輸出該編碼選擇信號；以及該編碼單元，根據由該過濾單元所輸出的該編碼選擇信號，從該些編碼方式中選擇針對該輸入資料之各列資料所要採用的該各別編碼方式，其中，對該輸入資料之各列資料所採用的該各別編碼方式彼此相同或不同。 The memory protection device of claim 1, wherein the filtering unit searches for each column of the input data to follow the input data. Each of the individual bits of the data of each column forms a pattern, and outputs the code selection signal; and the coding unit selects, according to the code selection signal output by the filter unit, the input data for each of the input data The respective encoding methods to be used for the data, wherein the respective encoding methods used for each column of the input data are the same or different from each other. 如申請專利範圍第1項所述之記憶體保護裝置，其中，該輸入資料之各列資料之該各別位元組成樣式包括：各列資料之位元0及/或位元1的比率，及/或，位元0及/或位元1的權重，及/或各列資料受外界影響的程度。 The memory protection device of claim 1, wherein the individual bit composition of each column of the input data comprises: a ratio of bit 0 and/or bit 1 of each column of data. And/or the weight of bit 0 and/or bit 1, and/or the extent to which each column of data is affected by the outside world. 如申請專利範圍第1項所述之記憶體保護裝置，其中，如果該輸入資料之各列資料之該各別位元組成樣式高於一臨界值的話，該編碼單元選擇一第一編碼方式；以及如果該輸入資料之各列資料之該各別位元組成樣式低於該臨界值的話，該編碼單元選擇一第二編碼方式，其中，該第一編碼方式與該第二編碼方式之位元成本不同。 The memory protection device of claim 1, wherein the coding unit selects a first coding mode if the respective bit composition patterns of the data of the input data are higher than a threshold value; And if the individual bit composition pattern of each column of the input data is lower than the threshold, the coding unit selects a second coding mode, wherein the first coding mode and the second coding mode bit The cost is different. 如申請專利範圍第1項所述之記憶體保護裝置，更包括：一開機檢查單元，在開機時，執行一開機檢查，從該記憶體讀出，並令該過濾單元與該編碼單元操作，以比較從該記憶體之一讀出資料，及該過濾單元與該編碼單元的一操作結果，以檢查該記憶體是否發生錯誤。 The memory protection device of claim 1, further comprising: a booting inspection unit, performing a power-on check when booting, reading from the memory, and operating the filtering unit and the encoding unit, The data is read from one of the memories, and an operation result of the filtering unit and the encoding unit is checked to check whether the memory has an error. 如申請專利範圍第5項所述之記憶體保護裝置，其中，該開機檢查單元，在開機時， 讀出存於該記憶體中的該第三冗餘位元群組，以檢查該第一冗餘位元群組與該第二冗餘位元群組是否有錯誤存在，如果有誤的話，則校正之，如果發現錯誤但無法校正的話，則代表開機檢查未通過；如果檢查該第一冗餘位元群組與該第二冗餘位元群組無錯誤的話，則從該記憶體讀出該第二冗餘位元群組，以檢查該記憶體，如果發現該記憶體存在錯誤的話，則校正之，如果發現錯誤但無法校正的話，則代表開機檢查未通過；以及如果沒有發現該記憶體存在錯誤的話，讀出該第一冗餘位元群組，以檢查該記憶體，如果發現該記憶體存在錯誤的話，則校正之，如果發現錯誤但無法校正的話，則代表開機檢查未通過。 The memory protection device of claim 5, wherein the power-on inspection unit is turned on, Reading the third redundant bit group stored in the memory to check whether the first redundant bit group and the second redundant bit group have errors, if any, Then correct, if an error is found but cannot be corrected, it means that the power-on check fails; if the first redundant bit group and the second redundant bit group are checked, there is no error, then the memory is read from the memory. Excluding the second redundant bit group to check the memory, if the memory is found to be in error, correct it, if an error is found but cannot be corrected, the boot check fails; and if the memory is not found If there is an error in the memory, the first redundant bit group is read to check the memory. If the memory is found to be in error, it is corrected. If an error is found but cannot be corrected, it means that the boot check is not performed. by. 如申請專利範圍第1項所述之記憶體保護裝置，更包括：一冗餘位元排列單元，收集該第一冗餘位元群組、第二冗餘位元群組、該填補位元群組及/或該第三冗餘位元群組，並排列成符合該記憶體的資料寬度，及產生相對應的複數個位址；以及一記憶體控制單元，將該輸入資料寫入至該記憶體，並依據該些位址，將該冗餘位元排列單元所對齊好的該第一冗餘位元群組、第二冗餘位元群組、該填補位元群組及/或該第三冗餘位元群組寫入至該記憶體。 The memory protection device of claim 1, further comprising: a redundant bit arrangement unit, collecting the first redundant bit group, the second redundant bit group, and the padding bit a group and/or the third redundant bit group, arranged to conform to a data width of the memory, and generating a corresponding plurality of addresses; and a memory control unit to write the input data to The memory, and according to the addresses, the first redundant bit group, the second redundant bit group, the padding bit group and/or aligned by the redundant bit arrangement unit Or the third redundant bit group is written to the memory. 一種記憶體保護方法，用以保護一記憶體，包括：搜尋一輸入資料，以依照該輸入資料之一位元組成樣式，輸出一編碼選擇信號；以及 根據由該過濾單元所輸出的該編碼選擇信號，從複數種編碼方式中選擇針對該輸入資料所要採用的一或多個編碼方式；其中，對該輸入資料之各行進行一第一編碼，以得到一第一冗餘位元群組，並將該第一冗餘位元群組寫入至該記憶體；對該輸入資料之各列進行一第二編碼，以得到一第二冗餘位元群組，並將該第二冗餘位元群組寫入至該記憶體，其中，該第二編碼取決於各列之各別位元組成樣式；當將該第二冗餘位元群組寫入至該記憶體時，如果該第二冗餘位元群組未填滿一列的話，則填入一填補位元群組於該列之中，以填滿該列；以及對該第一冗餘位元群組、該第二冗餘位元群組及/或該填補位元群組進行編碼以得到一第三冗餘位元群組，並將該第三冗餘位元群組寫入至該記憶體。 A memory protection method for protecting a memory, comprising: searching for an input data, and outputting an encoding selection signal according to a bit composition pattern of the input data; Determining, according to the code selection signal outputted by the filtering unit, one or more encoding modes to be used for the input data from a plurality of encoding modes; wherein, performing a first encoding on each row of the input data to obtain a first redundant bit group, and writing the first redundant bit group to the memory; performing a second encoding on each column of the input data to obtain a second redundant bit Grouping, and writing the second redundant bit group to the memory, wherein the second encoding depends on each bit composition pattern of each column; when the second redundant bit group is When writing to the memory, if the second redundant bit group is not filled with a column, a padding bit group is filled in the column to fill the column; and the first Redundant bit group, the second redundant bit group and/or the padding bit group are encoded to obtain a third redundant bit group, and the third redundant bit group is obtained Write to this memory. 如申請專利範圍第8項所述之記憶體保護方法，其中，搜尋該輸入資料之各列資料，以依照該輸入資料之各列資料之該各別位元組成樣式，輸出該編碼選擇信號；以及根據由該過濾單元所輸出的該編碼選擇信號，從該些編碼方式中選擇針對該輸入資料之各列資料所要採用的該各別編碼方式，其中，對該輸入資料之各列資料所採用的該各別編碼方式彼此相同或不同。 The memory protection method of claim 8, wherein the data of each column of the input data is searched for, and the code selection signal is output according to the individual bit composition of each column of the input data; And selecting, according to the code selection signal outputted by the filtering unit, the respective coding modes to be used for each column of data of the input data, wherein the data of each column of the input data is used The respective encoding methods are the same or different from each other. 如申請專利範圍第8項所述之記憶體保護方法，其中， 該輸入資料之各列資料之該各別位元組成樣式包括：各列資料之位元0及/或位元1的比率，及/或，位元0及/或位元1的權重，及/或各列資料受外界影響的程度。 The memory protection method of claim 8, wherein The individual bit composition of each column of the input data includes: the ratio of bit 0 and/or bit 1 of each column of data, and/or the weight of bit 0 and/or bit 1, and / or the extent to which each column of information is affected by the outside world. 如申請專利範圍第8項所述之記憶體保護方法，其中，如果該輸入資料之各列資料之該各別位元組成樣式高於一臨界值的話，選擇一第一編碼方式；以及如果該輸入資料之各列資料之該各別位元組成樣式低於該臨界值的話，選擇一第二編碼方式，其中，該第一編碼方式與該第二編碼方式之位元成本不同。 The memory protection method of claim 8, wherein if the individual bit composition of each column of the input data is higher than a threshold, a first encoding mode is selected; and if If the individual bit composition pattern of each column of the input data is lower than the threshold value, a second encoding mode is selected, wherein the first encoding mode is different from the bit cost of the second encoding mode. 如申請專利範圍第8項所述之記憶體保護方法，更包括：在開機時，執行一開機檢查，從該記憶體讀出，並再次執行該搜尋該輸入資料之該步驟及選擇該或該些編碼方式之該步驟，以比較從該記憶體之一讀出資料，及再次執行該搜尋該輸入資料之該步驟及選擇該或該些編碼方式之該步驟的一操作結果，以檢查該記憶體是否發生錯誤。 The memory protection method of claim 8, further comprising: performing a power-on check at the time of power-on, reading from the memory, and performing the step of searching for the input data again and selecting the or the The step of encoding the method to compare the reading of the data from the memory, and performing the step of searching the input data again and selecting an operation result of the step of selecting the encoding mode to check the memory Whether the body has an error. 如申請專利範圍第12項所述之記憶體保護方法，其中，在開機時，讀出存於該記憶體中的該第三冗餘位元群組，以檢查該第一冗餘位元群組與該第二冗餘位元群組是否有錯誤存在，如果有誤的話，則校正之，如果發現錯誤但無法校正的話，則代表開機檢查未通過；如果檢查該第一冗餘位元群組與該第二冗餘位元群組無錯 誤的話，則從該記憶體讀出該第二冗餘位元群組，以檢查該記憶體，如果發現該記憶體存在錯誤的話，則校正之，如果發現錯誤但無法校正的話，則代表開機檢查未通過；以及如果沒有發現該記憶體存在錯誤的話，讀出該第一冗餘位元群組，以檢查該記憶體，如果發現該記憶體存在錯誤的話，則校正之，如果發現錯誤但無法校正的話，則代表開機檢查未通過。 The memory protection method of claim 12, wherein, at power-on, the third redundant bit group stored in the memory is read to check the first redundant bit group. Whether there is an error in the group and the second redundant bit group, if it is wrong, it is corrected, if an error is found but cannot be corrected, it means that the power-on check fails; if the first redundant bit group is checked Group and the second redundant bit group are correct If it is wrong, the second redundant bit group is read from the memory to check the memory. If the memory is found to be in error, it is corrected. If an error is found but cannot be corrected, it means booting. The check fails; and if the memory is not found to be in error, the first redundant bit group is read to check the memory, and if the memory is found to be in error, it is corrected, if an error is found, If it cannot be corrected, it means that the power-on check failed. 如申請專利範圍第8項所述之記憶體保護方法，更包括：收集該第一冗餘位元群組、第二冗餘位元群組、該填補位元群組及/或該第三冗餘位元群組，並排列成符合該記憶體的資料寬度，及產生相對應的複數個位址；以及將該輸入資料寫入至該記憶體，並依據該些位址，將該冗餘位元排列單元所對齊好的該第一冗餘位元群組、第二冗餘位元群組、該填補位元群組及/或該第三冗餘位元群組寫入至該記憶體。 The memory protection method of claim 8, further comprising: collecting the first redundant bit group, the second redundant bit group, the padding bit group, and/or the third Redundant bit groups, arranged to conform to the data width of the memory, and generate corresponding multiple addresses; and writing the input data to the memory, and according to the addresses, the redundancy The first redundant bit group, the second redundant bit group, the padding bit group, and/or the third redundant bit group aligned to the remaining bit alignment unit are written to the Memory.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4525780A (en) * 1981-05-22 1985-06-25 Data General Corporation Data processing system having a memory using object-based information and a protection scheme for determining access rights to such information
US20110219208A1 (en) * 2010-01-08 2011-09-08 International Business Machines Corporation Multi-petascale highly efficient parallel supercomputer
US20120313817A1 (en) * 2003-09-02 2012-12-13 Csr Technology Inc. Signal processing system for satellite positioning signals
WO2013074341A1 (en) * 2011-11-15 2013-05-23 Global Supercomputing Corporation Method and system for converting a single-threaded software program into an application-specific supercomputer
US8799559B2 (en) * 2011-10-24 2014-08-05 Sandisk Technologies Inc. Endurance enhancement coding of compressible data in flash memories

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260783A (en) * 1991-02-21 1993-11-09 Gte Laboratories Incorporated Layered DCT video coder for packet switched ATM networks
US6651213B2 (en) * 2001-03-19 2003-11-18 International Business Machines Corporation Programmable multi-level track layout method and system for optimizing ECC redundancy in data storage devices
US6804799B2 (en) 2001-06-26 2004-10-12 Advanced Micro Devices, Inc. Using type bits to track storage of ECC and predecode bits in a level two cache
US6961890B2 (en) 2001-08-16 2005-11-01 Hewlett-Packard Development Company, L.P. Dynamic variable-length error correction code
US7188296B1 (en) * 2003-10-30 2007-03-06 Sun Microsystems, Inc. ECC for component failures using Galois fields
SG130962A1 (en) * 2005-09-16 2007-04-26 St Microelectronics Asia A method and system for adaptive pre-filtering for digital video signals
US7801308B1 (en) * 2006-07-17 2010-09-21 Integrated Device Technology, Inc. Secure key encoding for content protection
US7984360B2 (en) * 2006-12-31 2011-07-19 Ramot At Tel Aviv University Ltd. Avoiding errors in a flash memory by using substitution transformations
CN101599305B (en) 2008-06-04 2013-03-27 威刚科技股份有限公司 Storage system with data repair function and data repair method thereof
US20100311432A1 (en) * 2009-06-05 2010-12-09 Broadcom Corporation Cluster parsing for signaling within multiple user, multiple access, and/or mimo wireless communications
US8301948B2 (en) * 2009-08-10 2012-10-30 Hitachi Global Storage Technologies Netherlands B.V. Storage device with adaptive error-correcting code for improved areal efficiency
US8661315B2 (en) * 2009-10-07 2014-02-25 Mediatek Inc. Efuse devices, correction methods thereof, and methods for operating efuse devices
WO2011073940A1 (en) * 2009-12-17 2011-06-23 International Business Machines Corporation Data management in solid state storage systems
WO2011083439A1 (en) * 2010-01-08 2011-07-14 Nokia Corporation An apparatus, a method and a computer program for video coding
US9081062B1 (en) 2010-08-27 2015-07-14 Altera Corporation Memory error detection and correction circuitry
US8510636B2 (en) 2011-04-01 2013-08-13 Intel Corporation Dynamic read channel calibration for non-volatile memory devices
US8615690B2 (en) * 2011-05-05 2013-12-24 Mediatek Inc. Controller of memory device and method for operating the same
US8589762B2 (en) 2011-07-05 2013-11-19 International Business Machines Corporation Adaptive multi-bit error correction in endurance limited memories
US8793467B2 (en) * 2011-09-30 2014-07-29 Pure Storage, Inc. Variable length encoding in a storage system
US8527544B1 (en) * 2011-08-11 2013-09-03 Pure Storage Inc. Garbage collection in a storage system
JP5525498B2 (en) 2011-09-13 2014-06-18 株式会社東芝 Error detection device
US8874995B2 (en) * 2012-02-02 2014-10-28 International Business Machines Corporation Partial-maximum distance separable (PMDS) erasure correcting codes for storage arrays
US8862967B2 (en) 2012-03-15 2014-10-14 Sandisk Technologies Inc. Statistical distribution based variable-bit error correction coding
US8806294B2 (en) 2012-04-20 2014-08-12 Freescale Semiconductor, Inc. Error detection within a memory
TWI497515B (en) 2012-07-10 2015-08-21 Silicon Motion Inc Flash memory controllers and flash memory debug methods
US8910018B2 (en) 2012-07-17 2014-12-09 Macronix International Co., Ltd. Memory with dynamic error detection and correction
TWI482014B (en) 2012-08-10 2015-04-21 Macronix Int Co Ltd Memory with dynamic error detection and correction
US8898544B2 (en) 2012-12-11 2014-11-25 International Business Machines Corporation DRAM error detection, evaluation, and correction

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4525780A (en) * 1981-05-22 1985-06-25 Data General Corporation Data processing system having a memory using object-based information and a protection scheme for determining access rights to such information
US20120313817A1 (en) * 2003-09-02 2012-12-13 Csr Technology Inc. Signal processing system for satellite positioning signals
US20110219208A1 (en) * 2010-01-08 2011-09-08 International Business Machines Corporation Multi-petascale highly efficient parallel supercomputer
US8799559B2 (en) * 2011-10-24 2014-08-05 Sandisk Technologies Inc. Endurance enhancement coding of compressible data in flash memories
WO2013074341A1 (en) * 2011-11-15 2013-05-23 Global Supercomputing Corporation Method and system for converting a single-threaded software program into an application-specific supercomputer

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