TWI565036B - Reduced size semiconductor device and method for manufacture thereof - Google Patents
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本發明之範例實施例大致上是有關於一種半導體裝置，且特別是有關於避免字元線干擾的一種尺寸減小的半導體裝置。Exemplary embodiments of the present invention are generally directed to a semiconductor device, and more particularly to a reduced size semiconductor device that avoids word line interference.
半導體裝置可典型地分為需要電源以維持資料之儲存的揮發性半導體裝置，或即使移除電源仍可保留資料的非揮發性半導體裝置。非揮發性半導體裝置的一範例係快閃記憶體裝置，其大致上包括以列與欄排列的記憶胞(memory cell)的一陣列。各個記憶胞包括具有閘極、汲極、源極以及被定義於汲極與源極之間的通道的一電晶體結構。各個記憶胞係位於字元線與位元線之間的交集處，在該處，閘極係連接至字元線，汲極係連接至位元線，且源極係連接至源極線，接著連接至共同接地(common ground)。傳統之快閃記憶胞的閘極大致上包括雙閘極結構，雙閘極結構包括一控制閘極以及一浮接的閘極，其中浮接的閘極係夾置於兩個介電層之間，以捕捉載子(例如電子)，以寫入記憶胞。A semiconductor device can be typically classified into a volatile semiconductor device that requires a power source to maintain the storage of data, or a non-volatile semiconductor device that retains data even if the power source is removed. An example of a non-volatile semiconductor device is a flash memory device that generally includes an array of memory cells arranged in columns and columns. Each memory cell includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. Each memory cell is located at an intersection between the word line and the bit line, where the gate is connected to the word line, the drain is connected to the bit line, and the source is connected to the source line. Then connect to the common ground. The gate of the conventional flash memory cell generally comprises a double gate structure, the double gate structure comprises a control gate and a floating gate, wherein the floating gate is sandwiched between two dielectric layers. To capture a carrier (such as an electron) to write to a memory cell.
快閃記憶體裝置可接著被分為NOR或NAND快閃記憶體裝置。雖然NOR快閃記憶體具有它的好處，NAND快閃記憶體典型地提供較快的寫入以及抹除速度，大部分係因為其之串聯結構(serialized structure)，藉此可於記憶胞的串列上實施寫入以及抹除運作。The flash memory device can then be divided into NOR or NAND flash memory devices. While NOR flash memory has its benefits, NAND flash memory typically provides faster write and erase speeds, mostly because of its serialized structure, which allows for stringing of memory cells. Write and erase operations are performed on the column.
儘管現存的NAND快閃記憶體具有這些優點，半導體工業越來越朝向更小且更具性能的電子裝置發展。為了在減小這類裝置的尺寸的同時維持或改進它們各自的性能，裝置內之元件的尺寸以及這些元件之間的距離必須被減小。Despite the advantages of existing NAND flash memory, the semiconductor industry is increasingly moving toward smaller and more performance electronic devices. In order to maintain or improve their respective performance while reducing the size of such devices, the dimensions of the components within the device and the distance between these components must be reduced.
關於NAND快閃記憶體裝置，問題產生於維持記憶胞的性能與各自的功能阻止了尺寸的減小。舉例來說，所選電晶體與觸點(contact)之傳統串列高度已逐漸地成為減小記憶胞尺寸之規模的障礙。因為減小字元線與源極線之間的距離造成洩漏的擔憂，已證明不易到達這些尺寸。關於這方面，來自接地選擇線(ground select line, GSL)的閘極引發汲極漏(Gate-Induced Drain Leakage, GIDL)電流可以造成對於鄰近高臨界電壓之記憶胞的熱電子(hot electron, hot-E)干擾。因此，邊緣字元線經常經歷此干擾。With regard to NAND flash memory devices, the problem arises from maintaining memory cell performance and respective functions preventing size reduction. For example, the traditional tandem height of selected transistors and contacts has gradually become an obstacle to reducing the size of memory cells. Because of the concern of reducing the distance between the word line and the source line, it has proven difficult to reach these dimensions. In this regard, the Gate-Induced Drain Leakage (GIDL) current from the ground select line (GSL) can cause hot electrons to the memory cells adjacent to the high threshold voltage. -E) Interference. Therefore, edge word lines often experience this interference.
因此，本發明所屬技術領域對於減小NAND快閃記憶體裝置之尺寸，而同時降低熱電子邊緣字元線干擾之可能性仍然有需求。Accordingly, there is still a need in the art to reduce the size of NAND flash memory devices while reducing the likelihood of hot electron edge word line interference.
依照本發明之實施例，提供能夠同時減小晶片的尺寸以及避免邊緣字元線熱電子干擾的一種非揮發性半導體裝置。如在此所述，自包括多個區塊的串列移除接地選擇線(GSLs)能夠減小晶片的尺寸，且能夠降低易受熱電子干擾之邊緣字元線的數目。並且，於一些實施例中，本發明之實施例使用空間(space)和/或虛設(dummy)字元線以防止於一區塊中實施的運作干擾鄰近區塊的字元線。因此，用以寫入、抹除或讀取記憶胞功能的運作係良好的，邊緣字元線的干擾係減輕，並可以實質上減小晶片的尺寸。In accordance with an embodiment of the present invention, a non-volatile semiconductor device capable of simultaneously reducing the size of a wafer and avoiding thermal electronic interference of edge word lines is provided. As described herein, removing ground select lines (GSLs) from a series comprising a plurality of blocks can reduce the size of the wafer and can reduce the number of edge word lines susceptible to thermal electron interference. Also, in some embodiments, embodiments of the present invention use space and/or dummy word lines to prevent operations performed in one block from interfering with word lines of neighboring blocks. Therefore, the operation for writing, erasing, or reading the memory cell function is good, the interference of the edge word line is reduced, and the size of the wafer can be substantially reduced.
於第一範例實施例中，提供一非揮發性半導體裝置，其包括一基板以及多個區塊，此多個區塊形成一串列，其中各個區塊係位於基板上且包括配置於基板上的多條字元線。各個區塊係位於基板上且包括多條配置於基板上的字元線。串列包括一單一的接地選擇線，配置於多個區塊之一側，且單一的串列選擇線係配置於多個區塊的另一側。非揮發性半導體裝置可包括快閃記憶體，且特別是可包括NAND快閃記憶體。In a first exemplary embodiment, a non-volatile semiconductor device is provided, including a substrate and a plurality of blocks, the plurality of blocks forming a series, wherein each of the blocks is on the substrate and includes being disposed on the substrate Multiple word lines. Each block is located on the substrate and includes a plurality of word lines disposed on the substrate. The series includes a single ground selection line disposed on one side of the plurality of blocks, and a single serial selection line is disposed on the other side of the plurality of blocks. Non-volatile semiconductor devices can include flash memory, and in particular can include NAND flash memory.
於一些實施例中，此多個區塊的字元線定義將串列中之各個區塊自串列中之相鄰區塊分離的間隙。關於這方面，可於串列的區塊之間的間隙中配置一或多條虛設字元線。於一實施例中，虛設字元線係浮接的(floating)虛設字元線。於另一實施例中，虛設字元線具有偏壓。於又一實施例中，虛設字元線係接地連接。於其他實施例中，虛設字元線可包括多條字元線。In some embodiments, the word lines of the plurality of blocks define a gap separating the individual blocks in the string from adjacent blocks in the string. In this regard, one or more dummy word lines can be placed in the gap between the aligned blocks. In one embodiment, the dummy word line is a floating dummy word line. In another embodiment, the dummy word line has a bias voltage. In yet another embodiment, the dummy word lines are grounded. In other embodiments, the dummy word line can include a plurality of word lines.
於另一範例實施例中，提供一種非揮發性半導體裝置的製造方法。此方法包括提供一基板，以及設置多個區塊於基板上，以形成一串列，其中此多個區塊的各個區塊包括配置於基板上的多條字元線。此方法更包括形成與串列關聯的一單一的接地選擇線，其中此一單一的接地選擇線係配置於此多個區塊的一側，並形成與串列關聯的一單一的串列選擇線，其中此一單一的串列選擇線係配置於此多個區塊的另一側。可於此多個區塊之相對的側上配置接地選擇線以及串列選擇線。In another exemplary embodiment, a method of fabricating a non-volatile semiconductor device is provided. The method includes providing a substrate and disposing a plurality of blocks on the substrate to form a series, wherein each of the plurality of blocks includes a plurality of word lines disposed on the substrate. The method further includes forming a single ground select line associated with the string, wherein the single ground select line is disposed on one side of the plurality of blocks and forms a single string selection associated with the series A line, wherein the single serial selection line is configured on the other side of the plurality of blocks. A ground selection line and a tandem selection line may be disposed on opposite sides of the plurality of blocks.
於此方法的一些實施例中，設置多個區塊於基板上的步驟包括：以此多個區塊之字元線定義將串列中之各個區塊自串列中之相鄰區塊分離的間隙。關於這方面，此方法可包括於分離多個區塊之兩個區塊的間隙中設置虛設字元線。為此，於一實施例中，虛設字元線係浮接的虛設字元線。於另一實施例中，虛設字元線具有偏壓。於又一實施例中，虛設字元線係接地連接。於其他實施例中，虛設字元線包括多條字元線。In some embodiments of the method, the step of setting a plurality of blocks on the substrate comprises: separating the respective blocks in the series from adjacent blocks in the series by the word line definition of the plurality of blocks Clearance. In this regard, the method can include setting a dummy word line in a gap separating two of the plurality of blocks. To this end, in one embodiment, the dummy word line is a floating dummy word line. In another embodiment, the dummy word line has a bias voltage. In yet another embodiment, the dummy word lines are grounded. In other embodiments, the dummy word line includes a plurality of word lines.
於又另一實施例中，提供一種非揮發性半導體裝置的操作方法。關於這方面，非揮發性半導體裝置的操作方法可包括自形成串列之多個區塊中選擇一第一區塊，並於所選的區塊上實施一運作。In yet another embodiment, a method of operating a non-volatile semiconductor device is provided. In this regard, a method of operating a non-volatile semiconductor device can include selecting a first block from a plurality of blocks forming a series and performing an operation on the selected block.
在一個這樣的實施例中，運作包括抹除運作，其中偏壓係施加至所選區塊的多條字元線上，以抹除儲存於所選區塊之複數個記憶胞中的資料，偏壓並不施加至虛設字元線。In one such embodiment, the operation includes an erase operation in which a bias voltage is applied to a plurality of word lines of the selected block to erase data stored in a plurality of memory cells of the selected block, biased and Not applied to the dummy word line.
於另一這樣的實施例中，運作包括寫入運作，其中偏壓係施加至所選區塊的多條字元線上，以寫入所選區塊之複數個記憶胞中，偏壓並不施加至虛設字元線。In another such embodiment, the operation includes a write operation in which a bias voltage is applied to a plurality of word lines of the selected block to write into a plurality of memory cells of the selected block, and the bias voltage is not applied to Dummy word line.
於又另一這樣的實施例中，運作包括讀取運作，施加一導通電壓(pass voltage)至虛設字元線。In yet another such embodiment, the operation includes a read operation, applying a pass voltage to the dummy word line.
上述總結的提供僅是為了概括一些範例實施例的目的，以提供對於本發明一些方面的基本理解。因此，可以理解的是，上述實施例僅為範例，不應以任何方式被解釋為限縮本發明之範圍或精神。可以理解的是，本發明之範圍除了在此概括的那些實施例，尚包括許多潛在的實施例，下文中將會進一步敘述其中某些實施例。The above summary is provided merely to summarize the purpose of some example embodiments to provide a basic understanding of some aspects of the invention. Therefore, it is to be understood that the above-described embodiments are merely exemplary and are not to be construed as limiting the scope or spirit of the invention. It is to be understood that the scope of the invention includes many potential embodiments in addition to those embodiments set forth herein, and some of the embodiments are further described below.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下，其中圖式可能不是依其實際比例加以繪製：For a better understanding of the above and other aspects of the present invention, the preferred embodiments of the present invention are described in detail herein below,
102‧‧‧字元線
102d‧‧‧虛設字元線
102e‧‧‧邊緣字元線
104‧‧‧位元線
106‧‧‧源極線
108‧‧‧串列選擇線
110‧‧‧接地選擇線
112‧‧‧高度
202‧‧‧間隙
302‧‧‧高度
402、502、602、BLKn、BLKn+1‧‧‧區塊
702、704、706、708‧‧‧運作102‧‧‧ character line
102d‧‧‧dummy word line
102e‧‧‧Edge word line
104‧‧‧ bit line
106‧‧‧Source line
108‧‧‧Sequence selection line
110‧‧‧ Grounding selection line
112‧‧‧ Height
202‧‧‧ gap
302‧‧‧ Height
402, 502, 602, BLK n , BLK n+1 ‧‧‧ blocks
702, 704, 706, 708‧‧‧ operations
第1圖繪示傳統的快閃記憶體裝置的上視圖。
第2圖繪示依照本發明範例實施例之允許降低串列高度之半導體裝置的修改的上視圖。
第3圖繪示依照本發明範例實施例之尺寸減小的半導體裝置的上視圖。
第4-6圖繪示依照本發明範例實施例之可使用尺寸減小的半導體裝置實施的示範性運作。
第7圖繪示製造依照本發明範例實施例之半導體裝置的運作流程圖。
Figure 1 is a top view of a conventional flash memory device.
2 is a top view of a modification of a semiconductor device that allows for reduced string height in accordance with an exemplary embodiment of the present invention.
3 is a top view of a semiconductor device of reduced size in accordance with an exemplary embodiment of the present invention.
4-6 illustrate exemplary operations that may be implemented using a reduced size semiconductor device in accordance with an exemplary embodiment of the present invention.
FIG. 7 is a flow chart showing the operation of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention.
配合所附圖式，將更充分地於下文中描述本發明之一些實施例，圖式中顯示本發明的一些實施例，但並非所有實施例。事實上，可以許多不同的形式體現這些發明，並不應被解釋為限於在此所闡述的實施例；更確切地說，這些實施例的提供是用以使得本公開符合適用的法律要求。本公開中類似的元件符號指類似的元件。Some embodiments of the invention are described more fully hereinafter with reference to the accompanying drawings. In fact, these inventions may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, the embodiments are provided to make the disclosure comply with applicable legal requirements. Like reference numerals in the present disclosure refer to like elements.
如在此所使用的，「非揮發性記憶體」指即使自記憶體移除電性的提供仍能夠儲存資訊的半導體裝置。非揮發性記憶體包括但不限於遮罩唯讀記憶體(Mask Read-Only Memory)、可程式唯讀記憶體(Programmable Read-Only Memory)、可抹除可程式唯讀記憶體(Erasable Programmable Read-Only Memory)、電子式可抹除可程式唯讀記憶體(Electrically Erasable Programmable Read-Only Memory)以及快閃記憶體。As used herein, "non-volatile memory" refers to a semiconductor device that is capable of storing information even if electrical supply is removed from the memory. Non-volatile memory includes, but is not limited to, Mask Read-Only Memory, Programmable Read-Only Memory, Erasable Programmable Read -Only Memory), Electronically Erasable Programmable Read-Only Memory and Flash Memory.
如在此所使用的，「基板」可包括任何在下方的在其上可形成裝置、電路、磊晶層或半導體的材料。大致上，基板可用以定義位於半導體裝置下方或甚至形成半導體裝置的基底層的層。基板可包括矽、摻雜矽、鍺、矽鍺、半導體化合物或其他半導體材料的其中之一或任何組合。As used herein, a "substrate" can include any material below that can form a device, circuit, epitaxial layer, or semiconductor thereon. In general, a substrate can be used to define a layer underlying a semiconductor device or even forming a base layer of a semiconductor device. The substrate can include one or any combination of germanium, germanium, germanium, antimony, semiconductor compounds, or other semiconductor materials.
現在請參照第1圖，其繪示傳統的非揮發性半導體裝置。第1圖的半導體裝置包括多個區塊(雖然以類似的配置可附加額外的區塊至半導體，於此實施例中顯示兩個區塊BLKn 以及BLKn+1 )。各個區塊包括多條字元線102，與多條位元線104相交。記憶胞係位於各個交點，記憶胞包括閘極、汲極、源極以及被定義在介於汲極與源極之間的通道。如前面所述，各個記憶胞的閘極係連接至字元線，汲極係連接至位元線，且源極係連接至設置於相鄰區塊BLKn 與BLKn+1 之間的源極線106，區塊BLKn 與BLKn+1 係連接至共同接地。如進一步於第1圖中所示者，各個區塊具有對應的串列選擇線108以及接地選擇線110。Referring now to Figure 1, a conventional non-volatile semiconductor device is illustrated. The semiconductor device of FIG. 1 comprises a plurality of first blocks (although a similar configuration can be attached to additional blocks of the semiconductor, display and two blocks BLK n BLK n + 1 Example thereto). Each block includes a plurality of word lines 102 that intersect the plurality of bit lines 104. The memory cell is located at each intersection, and the memory cell includes a gate, a drain, a source, and a channel defined between the drain and the source. As described above, the gate of each memory cell is connected to the word line, the drain is connected to the bit line, and the source is connected to the source disposed between the adjacent blocks BLK n and BLK n+1 . The pole line 106, the block BLK n and the BLK n+1 are connected to a common ground. As further shown in FIG. 1, each block has a corresponding tandem select line 108 and a ground select line 110.
使用此傳統的半導體構造，兩個區塊的串列具有對應的高度112。然而，為了減小整體晶片的尺寸，各個區塊的組成元件必須減小尺寸和/或處於彼此較靠近的關係。然而，如前面所述，把字元線與串列選擇線以及接地選擇線設置於較靠近的位置，使得邊緣字元線之熱電子干擾的可能性較大。關於這方面，因為邊緣字元線102e以及串列選擇線與接地選擇線各自的通道電壓之間的電位差，可能產生影響邊緣字元線的橫向電場。特別是，此電場可在邊緣字元線102e產生熱電子，熱電子可能被注入與沿著邊緣字元線之記憶胞關聯的資料層。邊緣字元線102e可能因此被不適當地寫入。與此類似，把區塊設置於較靠近彼此的位置，寫入以及抹除運作亦可能將附隨的干擾引導至相鄰區塊的邊緣字元線102e。因此，存在對於能夠減小晶片的尺寸且同時避免這些干擾問題之串列配置的需求。Using this conventional semiconductor construction, the series of two blocks has a corresponding height 112. However, in order to reduce the size of the overall wafer, the constituent elements of the respective blocks must be reduced in size and/or in a relatively close relationship to each other. However, as described above, the word line and the string selection line and the ground selection line are disposed at a relatively close position, so that the possibility of thermal electron interference of the edge word line is large. In this regard, because of the potential difference between the edge word line 102e and the channel voltage of the series select line and the ground select line, a lateral electric field that affects the edge word line may be generated. In particular, this electric field can generate hot electrons at the edge word line 102e, which may be injected into the data layer associated with the memory cells along the edge word line. Edge word line 102e may therefore be improperly written. Similarly, placing the blocks closer to each other, the write and erase operations may also direct the accompanying interference to the edge word line 102e of the adjacent block. Therefore, there is a need for a tandem configuration that can reduce the size of the wafer while avoiding these interference problems.
第2圖繪示依照本發明範例實施例之能夠降低串列高度之半導體裝置的修改的上視圖。第2圖亦描述兩個區塊BLKn 以及BLKn+1 ，但是它們的配置已經與第1圖所示的那些配置方式不同。關於這方面，第2圖繪示源極線106已被移至相鄰區塊的一側，且僅提供單一的串列選擇線108以及單一的接地選擇線110。如此一來，使用相同串列高度112提供相連區塊之間的間隙202。提供這樣大的間隙202降低對於這些區塊中的一個區塊之由實施於其他區塊的寫入或抹除運作所造成的干擾的可能性。此外，因為僅使用單一的串列選擇線108以及單一的接地選擇線110，所以僅有一條邊緣字元線120e與串列選擇線108關聯，且僅有一條邊緣字元線120e與接地選擇線110關聯。因此，儘管第1圖所示之傳統半導體裝置包括四條易受熱電子干擾的邊緣字元線120e，第2圖中所示之修改的半導體裝置僅包括兩條邊緣字元線120e。因此，除了於相鄰區塊之間提供大的間隙，第2圖的半導體裝置具有較少之易受熱電子干擾的字元線。應該注意的是，雖然第2圖繪示串列僅具有兩個區塊BLKn 以及BLKn+1 ，可加入任何數目之額外的區塊至串列。2 is a top view of a modification of a semiconductor device capable of reducing the string height in accordance with an exemplary embodiment of the present invention. Figure 2 also depicts the two blocks BLK n and BLK n+1 , but their configuration has been different from those shown in Figure 1. In this regard, FIG. 2 illustrates that source line 106 has been moved to one side of an adjacent block and only a single string select line 108 and a single ground select line 110 are provided. As such, the same tandem height 112 is used to provide a gap 202 between the connected blocks. Providing such a large gap 202 reduces the likelihood of interference from one of these blocks caused by write or erase operations performed on other blocks. Moreover, because only a single string select line 108 and a single ground select line 110 are used, only one edge word line 120e is associated with the string select line 108, and there is only one edge word line 120e and ground select line 110 associations. Therefore, although the conventional semiconductor device shown in Fig. 1 includes four edge word lines 120e susceptible to thermal electron interference, the modified semiconductor device shown in Fig. 2 includes only two edge word lines 120e. Therefore, in addition to providing a large gap between adjacent blocks, the semiconductor device of Fig. 2 has fewer word lines susceptible to thermal electron interference. It should be noted that although Figure 2 illustrates that the string has only two blocks BLK n and BLK n+1 , any number of additional blocks may be added to the string.
現在請參照第3圖，其繪示依照本發明範例實施例之尺寸減小的半導體裝置的上視圖。第3圖中所示之半導體裝置顯示對於第2圖中所示之裝置的進一步修改。第3圖的半導體裝置移動相鄰區塊更靠近在一起，並使用一或多條虛設字元線102d分離它們，而不是簡單地於串列的相鄰區塊之間製造間隙202。雖然第3圖中繪示兩條虛設字元線，於一些實施例中，可有更多或更少條於串列中分離相鄰區塊的虛設字元線102d。雖然於此圖式中相鄰區塊係較靠近在一起，虛設字元線102d阻止一個區塊中藉由實施運作於其相鄰區塊上所造成的干擾。Referring now to FIG. 3, a top view of a reduced size semiconductor device in accordance with an exemplary embodiment of the present invention is shown. The semiconductor device shown in Fig. 3 shows a further modification to the device shown in Fig. 2. The semiconductor device of Figure 3 moves adjacent blocks closer together and separates them using one or more dummy word lines 102d, rather than simply creating a gap 202 between adjacent blocks of the series. Although two dummy word lines are depicted in FIG. 3, in some embodiments, there may be more or fewer dummy word lines 102d separating adjacent blocks in the series. Although adjacent blocks are closer together in this figure, the dummy word line 102d prevents interference caused by operating in its neighboring blocks in one block.
於一實施例中，虛設字元線係浮接的，且虛設字元線之阻抗以及相鄰區塊之間的距離產生足夠的緩衝以減輕電位干擾。於另一實施例中，提供具有偏壓的虛設字元線，此一偏壓可干擾任何可能在運作過程中促使熱電子干擾的橫向電場。於又另一實施例中，虛設字元線係接地連接，這在熱電子能夠自一個區塊移動通過虛設字元線102d至其相鄰區塊之前，自電路移除熱電子。如上所述，虛設字元線可包括多條字元線。In one embodiment, the dummy word lines are floating, and the impedance of the dummy word lines and the distance between adjacent blocks generate sufficient buffer to mitigate potential interference. In another embodiment, a dummy word line having a bias voltage is provided that can interfere with any lateral electric field that may cause thermal electron interference during operation. In yet another embodiment, the dummy word lines are grounded, which removes hot electrons from the circuit before the hot electrons can move from one block through the dummy word line 102d to its neighboring blocks. As described above, the dummy word line can include a plurality of word lines.
在各個例子中，雖然移動相鄰區塊更靠近在一起，一或多條虛設字元線102d的存在允許完全的寫入、抹除以及讀取功能。因此，如第3圖中所示，因為兩個區塊串列高度自如第1圖以及第2圖中所示之半導體裝置中的高度112減少至降低的串列高度302，晶片尺寸可以顯著的幅度減小。In various examples, the presence of one or more dummy word lines 102d allows for full write, erase, and read functions, although moving adjacent blocks are closer together. Therefore, as shown in FIG. 3, since the height of the two block series is reduced from the height 112 in the semiconductor device shown in FIGS. 1 and 2 to the reduced tandem height 302, the wafer size can be remarkable. The amplitude is reduced.
應該注意的是，雖然第3圖繪示串列僅具有兩個區塊BLKn 以及BLKn+1 ，可加入任何數目之額外的區塊至串列。尤其是，當與第1圖中所示之傳統的裝置比較時，提供至如第3圖所示配置的串列的各個額外區塊產生更大程度的效率，這是因為當隨著各個額外區塊加入多條字元線時，沒有新的串列選擇線108或接地選擇線110加入，因此對於加入至半導體裝置的各個區塊，相較於依照第1圖或第2圖配置之裝置的整體串列高度，具有如第3圖所示之配置的裝置的整體串列高度以較小的幅度增加。It should be noted that although Figure 3 illustrates that the string has only two blocks BLK n and BLK n+1 , any number of additional blocks may be added to the string. In particular, when compared with the conventional apparatus shown in Fig. 1, each of the additional blocks supplied to the series as shown in Fig. 3 produces a greater degree of efficiency because when each additional When a block is added to a plurality of word lines, no new serial select line 108 or ground select line 110 is added, so that for each block added to the semiconductor device, compared to the device configured according to FIG. 1 or FIG. The overall tandem height, the overall tandem height of the device having the configuration as shown in Figure 3, increases by a small margin.
第4-6圖繪示依照本發明範例實施例之可使用尺寸減小的半導體裝置實施的範例運作。4-6 illustrate example operations that may be implemented using a reduced size semiconductor device in accordance with an exemplary embodiment of the present invention.
第4圖繪示其中使用虛設字元線102d以避免一個區塊中由實施抹除運作於所選相鄰區塊上所造成的干擾的一實施例。關於這方面，選擇區塊402來抹除。此運作可施加偏壓至所選區塊的記憶胞。尤其是，即使當偏壓施加至所選區塊，虛設字元線與串列之未被選擇的區塊浮接。Figure 4 illustrates an embodiment in which dummy word line 102d is used to avoid interference caused by the implementation of erase operations on selected neighboring blocks in a block. In this regard, block 402 is selected for erasure. This operation can apply a bias voltage to the memory cells of the selected block. In particular, even when a bias voltage is applied to the selected block, the dummy word line is floated with the unselected block of the series.
第5圖繪示其中使用虛設字元線102d與實施於所選相鄰區塊上的寫入運作關聯的一實施例。關於這方面，選擇區塊502來寫入。尤其是，虛設字元線102d不需要與記憶胞關聯，並且因此可不會被寫入。Figure 5 illustrates an embodiment in which a dummy word line 102d is used in association with a write operation implemented on a selected adjacent block. In this regard, block 502 is selected for writing. In particular, the dummy word line 102d need not be associated with a memory cell and therefore may not be written.
第6圖繪示其中在實施讀取運作於所選相鄰區塊上的過程中使用虛設字元線102d的一實施例。於此範例中，選擇區塊602以被讀取。此運作可施加導通電壓至串列之未被選擇的字元線。關於這方面，藉由建立較低的電壓至被檢查的字元線以及建立導通電壓至所有其他字元線，讀取運作辨識一記憶胞是否含有被捕捉的電子。因此，除了所有未被選擇的字元線之外，導通電壓還施加至虛設字元線。Figure 6 illustrates an embodiment in which a dummy word line 102d is used in performing a read operation on a selected adjacent block. In this example, block 602 is selected to be read. This operation can apply a turn-on voltage to the unselected word lines of the series. In this regard, by establishing a lower voltage to the word line being inspected and establishing a turn-on voltage to all other word lines, the read operation identifies whether a memory cell contains captured electrons. Thus, in addition to all unselected word lines, the turn-on voltage is applied to the dummy word lines.
現在請參照第7圖，其繪示製造依照本發明範例實施例之半導體裝置的運作流程圖。於運作702中，提供一基板。於運作704中，設置多個區塊於基板上，以形成一串列，其中此多個區塊的各個區塊包括配置於基板上的多條字元線。此多條字元線中的一些可包括位於包括剩餘字元線的區塊之間的虛設字元線。於一些實施例中，虛設字元線與剩餘的字元線之間不需有任何差異，然而於其他實施例中，虛設字元線可連接至共同接地或電壓源。於運作706中，形成與串列關聯的一單一的接地選擇線，其中此一單一的接地選擇線係配置於多個區塊的一側。最後，於運作708中，形成與串列關聯的一單一的串列選擇線，其中此一單一的串列選擇線係配置於多個區塊的另一側。Referring now to FIG. 7, a flowchart of the operation of fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention is shown. In operation 702, a substrate is provided. In operation 704, a plurality of blocks are disposed on the substrate to form a series, wherein each of the plurality of blocks includes a plurality of word lines disposed on the substrate. Some of the plurality of word lines may include dummy word lines between the blocks including the remaining word lines. In some embodiments, there is no need to make any difference between the dummy word line and the remaining word lines, however in other embodiments, the dummy word lines can be connected to a common ground or voltage source. In operation 706, a single ground select line associated with the string is formed, wherein the single ground select line is disposed on one side of the plurality of blocks. Finally, in operation 708, a single string select line associated with the string is formed, wherein the single string select line is disposed on the other side of the plurality of blocks.
因此，如此所述，提供非揮發性半導體裝置、其製造方法以及其操作方法，能夠減小晶片的尺寸並且避免邊緣字元線的熱電子干擾。此外，即使具有實質上尺寸減小的晶片，用以寫入、抹除或讀取記憶胞功能的運作係良好的。如前面所述，位於相鄰區塊之間的虛設字元線的數目不是固定的，且於不同的實施例中可包括不同數目的虛設字元線。關於這方面，於一些實施例中沒有使用虛設線路，而間隙202可為足夠的。再者，雖然為了簡化，於串列中僅繪示兩個相鄰區塊，如本申請的所有方面，可使用任何數目的區塊與本發明之實施例連結。於一些實施例中，虛設字元線可包括任何適宜的技術，並且不限於任何特定的材料和/或結構。最後，雖然本發明的一些實施例包括NAND快閃記憶體裝置，本發明之實施例亦意欲用於其他非揮發性半導體裝置，如NOR快閃記憶體或其類似物。Therefore, as described above, the provision of the non-volatile semiconductor device, the method of manufacturing the same, and the method of operating the same can reduce the size of the wafer and avoid thermal electronic interference of the edge word lines. Moreover, even with a substantially reduced size wafer, the operation to write, erase or read the memory cell function is good. As previously mentioned, the number of dummy word lines located between adjacent blocks is not fixed, and different numbers of dummy word lines may be included in different embodiments. In this regard, dummy lines are not used in some embodiments, and gap 202 may be sufficient. Moreover, although only two adjacent blocks are shown in the series for simplicity, as in all aspects of the present application, any number of blocks may be used in conjunction with embodiments of the present invention. In some embodiments, the dummy word lines can include any suitable technique and are not limited to any particular material and/or structure. Finally, while some embodiments of the invention include NAND flash memory devices, embodiments of the invention are also intended for use with other non-volatile semiconductor devices, such as NOR flash memory or the like.
本發明所屬技術領域具有通常知識者將想到本文所闡述之本發明的許多修改以及其他實施例，這些發明涉及具有前述之描述以及所附圖示之教示的益處。因此，應當理解本發明不限於公開的特定實施例，修改和其他實施例應被包括在所附申請專利範圍的範圍內。此外，儘管文中的前述敘述以及所附圖示敘述範例實施例中元件和/或功能的特定示範性組合，應當理解的是，在不脫離所述申請專利範圍之範圍內，可藉由替代實施例提供元件和/或功能的不同組合。關於這方面，舉例來說，與上文明確敘述不同的元件和/或功能的組合亦被認為可被列在所附申請專利範圍中。儘管在此使用特定的用語，它們僅係用於通用以及描述性的意義，並非用於限制之目的。Many modifications and other embodiments of the inventions set forth herein will be apparent to those skilled in the <RTIgt; Therefore, the invention is to be understood as not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, although the foregoing description of the specification and the accompanying drawings are intended to illustrate a particular exemplary combination of the elements and/or functions in the example embodiments, it should be understood that Examples provide different combinations of components and/or functions. In this regard, for example, combinations of elements and/or functions that are distinct from the above are also considered to be included in the scope of the appended claims. Although specific terms are used herein, they are used in a generic and descriptive sense and not for the purpose of limitation.
102d‧‧‧虛設字元線 102d‧‧‧dummy word line
112‧‧‧高度 112‧‧‧ Height
302‧‧‧高度 302‧‧‧ Height
BLKn、BLKn+1‧‧‧區塊 BLK n , BLK n+1 ‧‧‧ blocks
Claims (10)
一基板；
複數個區塊，形成一串列，其中各個區塊係設置於該基板上，且各個區塊包括配置於該基板上的複數條字元線；
一單一的接地選擇線，與該串列關聯，其中該單一的接地選擇線係配置於該些區塊的一側；以及
一單一的串列選擇線，與該串列關聯，其中該單一的串列選擇線係配置於該些區塊的另一側。A non-volatile semiconductor device comprising:
a substrate;
a plurality of blocks forming a series of columns, wherein each of the blocks is disposed on the substrate, and each of the blocks includes a plurality of word lines disposed on the substrate;
a single ground select line associated with the string, wherein the single ground select line is disposed on one side of the blocks; and a single string select line associated with the string, wherein the single The serial selection line is disposed on the other side of the blocks.
提供一基板；
設置複數個區塊於該基板上，以形成一串列，其中該些區塊中的各個區塊包括配置於該基板上的複數條字元線；
形成與該串列關聯的一單一的接地選擇線，其中該單一的接地選擇線係配置於該些區塊的一側；以及
形成與該串列關聯的一單一的串列選擇線，其中該單一的串列選擇線係配置於該些區塊的另一側。A method of manufacturing a non-volatile semiconductor device, comprising:
Providing a substrate;
Setting a plurality of blocks on the substrate to form a series, wherein each of the blocks includes a plurality of word lines disposed on the substrate;
Forming a single ground select line associated with the string, wherein the single ground select line is disposed on one side of the blocks; and forming a single string select line associated with the string, wherein the A single serial selection line is placed on the other side of the blocks.
選擇形成該串列之該些區塊中之該第一區塊；以及
實施一運作於所選的該第一區塊。A method of operating a non-volatile semiconductor device as described in claim 3, comprising:
Selecting the first block of the blocks forming the string; and implementing a first block operating in the selected one.
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| TW201142856A (en) * | 2010-02-09 | 2011-12-01 | Samsung Electronics Co Ltd | Nonvolatile memory devices, operating methods thereof and memory systems including the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201142856A (en) * | 2010-02-09 | 2011-12-01 | Samsung Electronics Co Ltd | Nonvolatile memory devices, operating methods thereof and memory systems including the same |
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